drivers/usb/dwc2/hcd_intr.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * This file contains the interrupt handlers for Host mode
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/io.h>
  47 #include <linux/slab.h>
  48 #include <linux/usb.h>
  49
  50 #include <linux/usb/hcd.h>
  51 #include <linux/usb/ch11.h>
  52
  53 #include "core.h"
  54 #include "hcd.h"
  55
  56 /*
  57  * If we get this many NAKs on a split transaction we'll slow down
  58  * retransmission.  A 1 here means delay after the first NAK.
  59  */
  60 #define DWC2_NAKS_BEFORE_DELAY          3
  61
  62 /* This function is for debug only */
  63 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  64 {
  65         u16 curr_frame_number = hsotg->frame_number;
  66         u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
  67
  68         if (expected != curr_frame_number)
  69                 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
  70                               expected, curr_frame_number);
  71
  72 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  73         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  74                 if (expected != curr_frame_number) {
  75                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  76                                         curr_frame_number;
  77                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  78                                         hsotg->last_frame_num;
  79                         hsotg->frame_num_idx++;
  80                 }
  81         } else if (!hsotg->dumped_frame_num_array) {
  82                 int i;
  83
  84                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  85                 dev_info(hsotg->dev, "-----     ----------\n");
  86                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  87                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  88                                  hsotg->frame_num_array[i],
  89                                  hsotg->last_frame_num_array[i]);
  90                 }
  91                 hsotg->dumped_frame_num_array = 1;
  92         }
  93 #endif
  94         hsotg->last_frame_num = curr_frame_number;
  95 }
  96
  97 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  98                                     struct dwc2_host_chan *chan,
  99                                     struct dwc2_qtd *qtd)
 100 {
 101         struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
 102         struct urb *usb_urb;
 103
 104         if (!chan->qh)
 105                 return;
 106
 107         if (chan->qh->dev_speed == USB_SPEED_HIGH)
 108                 return;
 109
 110         if (!qtd->urb)
 111                 return;
 112
 113         usb_urb = qtd->urb->priv;
 114         if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 115                 return;
 116
 117         /*
 118          * The root hub doesn't really have a TT, but Linux thinks it
 119          * does because how could you have a "high speed hub" that
 120          * directly talks directly to low speed devices without a TT?
 121          * It's all lies.  Lies, I tell you.
 122          */
 123         if (usb_urb->dev->tt->hub == root_hub)
 124                 return;
 125
 126         if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 127                 chan->qh->tt_buffer_dirty = 1;
 128                 if (usb_hub_clear_tt_buffer(usb_urb))
 129                         /* Clear failed; let's hope things work anyway */
 130                         chan->qh->tt_buffer_dirty = 0;
 131         }
 132 }
 133
 134 /*
 135  * Handles the start-of-frame interrupt in host mode. Non-periodic
 136  * transactions may be queued to the DWC_otg controller for the current
 137  * (micro)frame. Periodic transactions may be queued to the controller
 138  * for the next (micro)frame.
 139  */
 140 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 141 {
 142         struct list_head *qh_entry;
 143         struct dwc2_qh *qh;
 144         enum dwc2_transaction_type tr_type;
 145
 146         /* Clear interrupt */
 147         dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 148
 149 #ifdef DEBUG_SOF
 150         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 151 #endif
 152
 153         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 154
 155         dwc2_track_missed_sofs(hsotg);
 156
 157         /* Determine whether any periodic QHs should be executed */
 158         qh_entry = hsotg->periodic_sched_inactive.next;
 159         while (qh_entry != &hsotg->periodic_sched_inactive) {
 160                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 161                 qh_entry = qh_entry->next;
 162                 if (dwc2_frame_num_le(qh->next_active_frame,
 163                                       hsotg->frame_number)) {
 164                         dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
 165                                       qh, hsotg->frame_number,
 166                                       qh->next_active_frame);
 167
 168                         /*
 169                          * Move QH to the ready list to be executed next
 170                          * (micro)frame
 171                          */
 172                         list_move_tail(&qh->qh_list_entry,
 173                                        &hsotg->periodic_sched_ready);
 174                 }
 175         }
 176         tr_type = dwc2_hcd_select_transactions(hsotg);
 177         if (tr_type != DWC2_TRANSACTION_NONE)
 178                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 179 }
 180
 181 /*
 182  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 183  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 184  * memory if the DWC_otg controller is operating in Slave mode.
 185  */
 186 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 187 {
 188         u32 grxsts, chnum, bcnt, dpid, pktsts;
 189         struct dwc2_host_chan *chan;
 190
 191         if (dbg_perio())
 192                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 193
 194         grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
 195         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 196         chan = hsotg->hc_ptr_array[chnum];
 197         if (!chan) {
 198                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 199                 return;
 200         }
 201
 202         bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 203         dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 204         pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 205
 206         /* Packet Status */
 207         if (dbg_perio()) {
 208                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 209                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 210                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 211                          chan->data_pid_start);
 212                 dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 213         }
 214
 215         switch (pktsts) {
 216         case GRXSTS_PKTSTS_HCHIN:
 217                 /* Read the data into the host buffer */
 218                 if (bcnt > 0) {
 219                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 220
 221                         /* Update the HC fields for the next packet received */
 222                         chan->xfer_count += bcnt;
 223                         chan->xfer_buf += bcnt;
 224                 }
 225                 break;
 226         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 227         case GRXSTS_PKTSTS_DATATOGGLEERR:
 228         case GRXSTS_PKTSTS_HCHHALTED:
 229                 /* Handled in interrupt, just ignore data */
 230                 break;
 231         default:
 232                 dev_err(hsotg->dev,
 233                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 234                 break;
 235         }
 236 }
 237
 238 /*
 239  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 240  * data packets may be written to the FIFO for OUT transfers. More requests
 241  * may be written to the non-periodic request queue for IN transfers. This
 242  * interrupt is enabled only in Slave mode.
 243  */
 244 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 245 {
 246         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 247         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 248 }
 249
 250 /*
 251  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 252  * packets may be written to the FIFO for OUT transfers. More requests may be
 253  * written to the periodic request queue for IN transfers. This interrupt is
 254  * enabled only in Slave mode.
 255  */
 256 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 257 {
 258         if (dbg_perio())
 259                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 260         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 261 }
 262
 263 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 264                               u32 *hprt0_modify)
 265 {
 266         struct dwc2_core_params *params = &hsotg->params;
 267         int do_reset = 0;
 268         u32 usbcfg;
 269         u32 prtspd;
 270         u32 hcfg;
 271         u32 fslspclksel;
 272         u32 hfir;
 273
 274         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 275
 276         /* Every time when port enables calculate HFIR.FrInterval */
 277         hfir = dwc2_readl(hsotg->regs + HFIR);
 278         hfir &= ~HFIR_FRINT_MASK;
 279         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 280                 HFIR_FRINT_MASK;
 281         dwc2_writel(hfir, hsotg->regs + HFIR);
 282
 283         /* Check if we need to adjust the PHY clock speed for low power */
 284         if (!params->host_support_fs_ls_low_power) {
 285                 /* Port has been enabled, set the reset change flag */
 286                 hsotg->flags.b.port_reset_change = 1;
 287                 return;
 288         }
 289
 290         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 291         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 292
 293         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 294                 /* Low power */
 295                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 296                         /* Set PHY low power clock select for FS/LS devices */
 297                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 298                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 299                         do_reset = 1;
 300                 }
 301
 302                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 303                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 304                               HCFG_FSLSPCLKSEL_SHIFT;
 305
 306                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 307                     params->host_ls_low_power_phy_clk) {
 308                         /* 6 MHZ */
 309                         dev_vdbg(hsotg->dev,
 310                                  "FS_PHY programming HCFG to 6 MHz\n");
 311                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 312                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 313                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 314                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 315                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 316                                 do_reset = 1;
 317                         }
 318                 } else {
 319                         /* 48 MHZ */
 320                         dev_vdbg(hsotg->dev,
 321                                  "FS_PHY programming HCFG to 48 MHz\n");
 322                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 323                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 324                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 325                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 326                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 327                                 do_reset = 1;
 328                         }
 329                 }
 330         } else {
 331                 /* Not low power */
 332                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 333                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 334                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 335                         do_reset = 1;
 336                 }
 337         }
 338
 339         if (do_reset) {
 340                 *hprt0_modify |= HPRT0_RST;
 341                 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
 342                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 343                                    msecs_to_jiffies(60));
 344         } else {
 345                 /* Port has been enabled, set the reset change flag */
 346                 hsotg->flags.b.port_reset_change = 1;
 347         }
 348 }
 349
 350 /*
 351  * There are multiple conditions that can cause a port interrupt. This function
 352  * determines which interrupt conditions have occurred and handles them
 353  * appropriately.
 354  */
 355 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 356 {
 357         u32 hprt0;
 358         u32 hprt0_modify;
 359
 360         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 361
 362         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 363         hprt0_modify = hprt0;
 364
 365         /*
 366          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 367          * GINTSTS
 368          */
 369         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 370                           HPRT0_OVRCURRCHG);
 371
 372         /*
 373          * Port Connect Detected
 374          * Set flag and clear if detected
 375          */
 376         if (hprt0 & HPRT0_CONNDET) {
 377                 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
 378
 379                 dev_vdbg(hsotg->dev,
 380                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 381                          hprt0);
 382                 dwc2_hcd_connect(hsotg);
 383
 384                 /*
 385                  * The Hub driver asserts a reset when it sees port connect
 386                  * status change flag
 387                  */
 388         }
 389
 390         /*
 391          * Port Enable Changed
 392          * Clear if detected - Set internal flag if disabled
 393          */
 394         if (hprt0 & HPRT0_ENACHG) {
 395                 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
 396                 dev_vdbg(hsotg->dev,
 397                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 398                          hprt0, !!(hprt0 & HPRT0_ENA));
 399                 if (hprt0 & HPRT0_ENA) {
 400                         hsotg->new_connection = true;
 401                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 402                 } else {
 403                         hsotg->flags.b.port_enable_change = 1;
 404                         if (hsotg->params.dma_desc_fs_enable) {
 405                                 u32 hcfg;
 406
 407                                 hsotg->params.dma_desc_enable = false;
 408                                 hsotg->new_connection = false;
 409                                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 410                                 hcfg &= ~HCFG_DESCDMA;
 411                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 412                         }
 413                 }
 414         }
 415
 416         /* Overcurrent Change Interrupt */
 417         if (hprt0 & HPRT0_OVRCURRCHG) {
 418                 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
 419                             hsotg->regs + HPRT0);
 420                 dev_vdbg(hsotg->dev,
 421                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 422                          hprt0);
 423                 hsotg->flags.b.port_over_current_change = 1;
 424         }
 425 }
 426
 427 /*
 428  * Gets the actual length of a transfer after the transfer halts. halt_status
 429  * holds the reason for the halt.
 430  *
 431  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 432  * is set to 1 upon return if less than the requested number of bytes were
 433  * transferred. short_read may also be NULL on entry, in which case it remains
 434  * unchanged.
 435  */
 436 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 437                                        struct dwc2_host_chan *chan, int chnum,
 438                                        struct dwc2_qtd *qtd,
 439                                        enum dwc2_halt_status halt_status,
 440                                        int *short_read)
 441 {
 442         u32 hctsiz, count, length;
 443
 444         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 445
 446         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 447                 if (chan->ep_is_in) {
 448                         count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 449                                 TSIZ_XFERSIZE_SHIFT;
 450                         length = chan->xfer_len - count;
 451                         if (short_read)
 452                                 *short_read = (count != 0);
 453                 } else if (chan->qh->do_split) {
 454                         length = qtd->ssplit_out_xfer_count;
 455                 } else {
 456                         length = chan->xfer_len;
 457                 }
 458         } else {
 459                 /*
 460                  * Must use the hctsiz.pktcnt field to determine how much data
 461                  * has been transferred. This field reflects the number of
 462                  * packets that have been transferred via the USB. This is
 463                  * always an integral number of packets if the transfer was
 464                  * halted before its normal completion. (Can't use the
 465                  * hctsiz.xfersize field because that reflects the number of
 466                  * bytes transferred via the AHB, not the USB).
 467                  */
 468                 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 469                 length = (chan->start_pkt_count - count) * chan->max_packet;
 470         }
 471
 472         return length;
 473 }
 474
 475 /**
 476  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 477  * Complete interrupt on the host channel. Updates the actual_length field
 478  * of the URB based on the number of bytes transferred via the host channel.
 479  * Sets the URB status if the data transfer is finished.
 480  *
 481  * @hsotg: Programming view of the DWC_otg controller
 482  * @chan: Programming view of host channel
 483  * @chnum: Channel number
 484  * @urb: Processing URB
 485  * @qtd: Queue transfer descriptor
 486  *
 487  * Return: 1 if the data transfer specified by the URB is completely finished,
 488  * 0 otherwise
 489  */
 490 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 491                                  struct dwc2_host_chan *chan, int chnum,
 492                                  struct dwc2_hcd_urb *urb,
 493                                  struct dwc2_qtd *qtd)
 494 {
 495         u32 hctsiz;
 496         int xfer_done = 0;
 497         int short_read = 0;
 498         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 499                                                       DWC2_HC_XFER_COMPLETE,
 500                                                       &short_read);
 501
 502         if (urb->actual_length + xfer_length > urb->length) {
 503                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 504                 xfer_length = urb->length - urb->actual_length;
 505         }
 506
 507         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 508                  urb->actual_length, xfer_length);
 509         urb->actual_length += xfer_length;
 510
 511         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 512             (urb->flags & URB_SEND_ZERO_PACKET) &&
 513             urb->actual_length >= urb->length &&
 514             !(urb->length % chan->max_packet)) {
 515                 xfer_done = 0;
 516         } else if (short_read || urb->actual_length >= urb->length) {
 517                 xfer_done = 1;
 518                 urb->status = 0;
 519         }
 520
 521         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 522         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 523                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 524         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 525         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 526                  (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 527         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 528         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 529         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 530                  xfer_done);
 531
 532         return xfer_done;
 533 }
 534
 535 /*
 536  * Save the starting data toggle for the next transfer. The data toggle is
 537  * saved in the QH for non-control transfers and it's saved in the QTD for
 538  * control transfers.
 539  */
 540 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 541                                struct dwc2_host_chan *chan, int chnum,
 542                                struct dwc2_qtd *qtd)
 543 {
 544         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 545         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 546
 547         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 548                 if (WARN(!chan || !chan->qh,
 549                          "chan->qh must be specified for non-control eps\n"))
 550                         return;
 551
 552                 if (pid == TSIZ_SC_MC_PID_DATA0)
 553                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 554                 else
 555                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 556         } else {
 557                 if (WARN(!qtd,
 558                          "qtd must be specified for control eps\n"))
 559                         return;
 560
 561                 if (pid == TSIZ_SC_MC_PID_DATA0)
 562                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 563                 else
 564                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 565         }
 566 }
 567
 568 /**
 569  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 570  * the transfer is stopped for any reason. The fields of the current entry in
 571  * the frame descriptor array are set based on the transfer state and the input
 572  * halt_status. Completes the Isochronous URB if all the URB frames have been
 573  * completed.
 574  *
 575  * @hsotg: Programming view of the DWC_otg controller
 576  * @chan: Programming view of host channel
 577  * @chnum: Channel number
 578  * @halt_status: Reason for halting a host channel
 579  * @qtd: Queue transfer descriptor
 580  *
 581  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 582  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 583  */
 584 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 585                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 586                 int chnum, struct dwc2_qtd *qtd,
 587                 enum dwc2_halt_status halt_status)
 588 {
 589         struct dwc2_hcd_iso_packet_desc *frame_desc;
 590         struct dwc2_hcd_urb *urb = qtd->urb;
 591
 592         if (!urb)
 593                 return DWC2_HC_XFER_NO_HALT_STATUS;
 594
 595         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 596
 597         switch (halt_status) {
 598         case DWC2_HC_XFER_COMPLETE:
 599                 frame_desc->status = 0;
 600                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 601                                         chan, chnum, qtd, halt_status, NULL);
 602                 break;
 603         case DWC2_HC_XFER_FRAME_OVERRUN:
 604                 urb->error_count++;
 605                 if (chan->ep_is_in)
 606                         frame_desc->status = -ENOSR;
 607                 else
 608                         frame_desc->status = -ECOMM;
 609                 frame_desc->actual_length = 0;
 610                 break;
 611         case DWC2_HC_XFER_BABBLE_ERR:
 612                 urb->error_count++;
 613                 frame_desc->status = -EOVERFLOW;
 614                 /* Don't need to update actual_length in this case */
 615                 break;
 616         case DWC2_HC_XFER_XACT_ERR:
 617                 urb->error_count++;
 618                 frame_desc->status = -EPROTO;
 619                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 620                                         chan, chnum, qtd, halt_status, NULL);
 621
 622                 /* Skip whole frame */
 623                 if (chan->qh->do_split &&
 624                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 625                     hsotg->params.host_dma) {
 626                         qtd->complete_split = 0;
 627                         qtd->isoc_split_offset = 0;
 628                 }
 629
 630                 break;
 631         default:
 632                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 633                         halt_status);
 634                 break;
 635         }
 636
 637         if (++qtd->isoc_frame_index == urb->packet_count) {
 638                 /*
 639                  * urb->status is not used for isoc transfers. The individual
 640                  * frame_desc statuses are used instead.
 641                  */
 642                 dwc2_host_complete(hsotg, qtd, 0);
 643                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 644         } else {
 645                 halt_status = DWC2_HC_XFER_COMPLETE;
 646         }
 647
 648         return halt_status;
 649 }
 650
 651 /*
 652  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 653  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 654  * still linked to the QH, the QH is added to the end of the inactive
 655  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 656  * schedule if no more QTDs are linked to the QH.
 657  */
 658 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 659                                int free_qtd)
 660 {
 661         int continue_split = 0;
 662         struct dwc2_qtd *qtd;
 663
 664         if (dbg_qh(qh))
 665                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 666                          hsotg, qh, free_qtd);
 667
 668         if (list_empty(&qh->qtd_list)) {
 669                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 670                 goto no_qtd;
 671         }
 672
 673         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 674
 675         if (qtd->complete_split)
 676                 continue_split = 1;
 677         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 678                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 679                 continue_split = 1;
 680
 681         if (free_qtd) {
 682                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 683                 continue_split = 0;
 684         }
 685
 686 no_qtd:
 687         qh->channel = NULL;
 688         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 689 }
 690
 691 /**
 692  * dwc2_release_channel() - Releases a host channel for use by other transfers
 693  *
 694  * @hsotg:       The HCD state structure
 695  * @chan:        The host channel to release
 696  * @qtd:         The QTD associated with the host channel. This QTD may be
 697  *               freed if the transfer is complete or an error has occurred.
 698  * @halt_status: Reason the channel is being released. This status
 699  *               determines the actions taken by this function.
 700  *
 701  * Also attempts to select and queue more transactions since at least one host
 702  * channel is available.
 703  */
 704 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 705                                  struct dwc2_host_chan *chan,
 706                                  struct dwc2_qtd *qtd,
 707                                  enum dwc2_halt_status halt_status)
 708 {
 709         enum dwc2_transaction_type tr_type;
 710         u32 haintmsk;
 711         int free_qtd = 0;
 712
 713         if (dbg_hc(chan))
 714                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 715                          __func__, chan->hc_num, halt_status);
 716
 717         switch (halt_status) {
 718         case DWC2_HC_XFER_URB_COMPLETE:
 719                 free_qtd = 1;
 720                 break;
 721         case DWC2_HC_XFER_AHB_ERR:
 722         case DWC2_HC_XFER_STALL:
 723         case DWC2_HC_XFER_BABBLE_ERR:
 724                 free_qtd = 1;
 725                 break;
 726         case DWC2_HC_XFER_XACT_ERR:
 727                 if (qtd && qtd->error_count >= 3) {
 728                         dev_vdbg(hsotg->dev,
 729                                  "  Complete URB with transaction error\n");
 730                         free_qtd = 1;
 731                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 732                 }
 733                 break;
 734         case DWC2_HC_XFER_URB_DEQUEUE:
 735                 /*
 736                  * The QTD has already been removed and the QH has been
 737                  * deactivated. Don't want to do anything except release the
 738                  * host channel and try to queue more transfers.
 739                  */
 740                 goto cleanup;
 741         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 742                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 743                 free_qtd = 1;
 744                 dwc2_host_complete(hsotg, qtd, -EIO);
 745                 break;
 746         case DWC2_HC_XFER_NO_HALT_STATUS:
 747         default:
 748                 break;
 749         }
 750
 751         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 752
 753 cleanup:
 754         /*
 755          * Release the host channel for use by other transfers. The cleanup
 756          * function clears the channel interrupt enables and conditions, so
 757          * there's no need to clear the Channel Halted interrupt separately.
 758          */
 759         if (!list_empty(&chan->hc_list_entry))
 760                 list_del(&chan->hc_list_entry);
 761         dwc2_hc_cleanup(hsotg, chan);
 762         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 763
 764         if (hsotg->params.uframe_sched) {
 765                 hsotg->available_host_channels++;
 766         } else {
 767                 switch (chan->ep_type) {
 768                 case USB_ENDPOINT_XFER_CONTROL:
 769                 case USB_ENDPOINT_XFER_BULK:
 770                         hsotg->non_periodic_channels--;
 771                         break;
 772                 default:
 773                         /*
 774                          * Don't release reservations for periodic channels
 775                          * here. That's done when a periodic transfer is
 776                          * descheduled (i.e. when the QH is removed from the
 777                          * periodic schedule).
 778                          */
 779                         break;
 780                 }
 781         }
 782
 783         haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 784         haintmsk &= ~(1 << chan->hc_num);
 785         dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
 786
 787         /* Try to queue more transfers now that there's a free channel */
 788         tr_type = dwc2_hcd_select_transactions(hsotg);
 789         if (tr_type != DWC2_TRANSACTION_NONE)
 790                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 791 }
 792
 793 /*
 794  * Halts a host channel. If the channel cannot be halted immediately because
 795  * the request queue is full, this function ensures that the FIFO empty
 796  * interrupt for the appropriate queue is enabled so that the halt request can
 797  * be queued when there is space in the request queue.
 798  *
 799  * This function may also be called in DMA mode. In that case, the channel is
 800  * simply released since the core always halts the channel automatically in
 801  * DMA mode.
 802  */
 803 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 804                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 805                               enum dwc2_halt_status halt_status)
 806 {
 807         if (dbg_hc(chan))
 808                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 809
 810         if (hsotg->params.host_dma) {
 811                 if (dbg_hc(chan))
 812                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 813                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 814                 return;
 815         }
 816
 817         /* Slave mode processing */
 818         dwc2_hc_halt(hsotg, chan, halt_status);
 819
 820         if (chan->halt_on_queue) {
 821                 u32 gintmsk;
 822
 823                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 824                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 825                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 826                         dev_vdbg(hsotg->dev, "control/bulk\n");
 827                         /*
 828                          * Make sure the Non-periodic Tx FIFO empty interrupt
 829                          * is enabled so that the non-periodic schedule will
 830                          * be processed
 831                          */
 832                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 833                         gintmsk |= GINTSTS_NPTXFEMP;
 834                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 835                 } else {
 836                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 837                         /*
 838                          * Move the QH from the periodic queued schedule to
 839                          * the periodic assigned schedule. This allows the
 840                          * halt to be queued when the periodic schedule is
 841                          * processed.
 842                          */
 843                         list_move_tail(&chan->qh->qh_list_entry,
 844                                        &hsotg->periodic_sched_assigned);
 845
 846                         /*
 847                          * Make sure the Periodic Tx FIFO Empty interrupt is
 848                          * enabled so that the periodic schedule will be
 849                          * processed
 850                          */
 851                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 852                         gintmsk |= GINTSTS_PTXFEMP;
 853                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 854                 }
 855         }
 856 }
 857
 858 /*
 859  * Performs common cleanup for non-periodic transfers after a Transfer
 860  * Complete interrupt. This function should be called after any endpoint type
 861  * specific handling is finished to release the host channel.
 862  */
 863 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 864                                             struct dwc2_host_chan *chan,
 865                                             int chnum, struct dwc2_qtd *qtd,
 866                                             enum dwc2_halt_status halt_status)
 867 {
 868         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 869
 870         qtd->error_count = 0;
 871
 872         if (chan->hcint & HCINTMSK_NYET) {
 873                 /*
 874                  * Got a NYET on the last transaction of the transfer. This
 875                  * means that the endpoint should be in the PING state at the
 876                  * beginning of the next transfer.
 877                  */
 878                 dev_vdbg(hsotg->dev, "got NYET\n");
 879                 chan->qh->ping_state = 1;
 880         }
 881
 882         /*
 883          * Always halt and release the host channel to make it available for
 884          * more transfers. There may still be more phases for a control
 885          * transfer or more data packets for a bulk transfer at this point,
 886          * but the host channel is still halted. A channel will be reassigned
 887          * to the transfer when the non-periodic schedule is processed after
 888          * the channel is released. This allows transactions to be queued
 889          * properly via dwc2_hcd_queue_transactions, which also enables the
 890          * Tx FIFO Empty interrupt if necessary.
 891          */
 892         if (chan->ep_is_in) {
 893                 /*
 894                  * IN transfers in Slave mode require an explicit disable to
 895                  * halt the channel. (In DMA mode, this call simply releases
 896                  * the channel.)
 897                  */
 898                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 899         } else {
 900                 /*
 901                  * The channel is automatically disabled by the core for OUT
 902                  * transfers in Slave mode
 903                  */
 904                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 905         }
 906 }
 907
 908 /*
 909  * Performs common cleanup for periodic transfers after a Transfer Complete
 910  * interrupt. This function should be called after any endpoint type specific
 911  * handling is finished to release the host channel.
 912  */
 913 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 914                                         struct dwc2_host_chan *chan, int chnum,
 915                                         struct dwc2_qtd *qtd,
 916                                         enum dwc2_halt_status halt_status)
 917 {
 918         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 919
 920         qtd->error_count = 0;
 921
 922         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 923                 /* Core halts channel in these cases */
 924                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 925         else
 926                 /* Flush any outstanding requests from the Tx queue */
 927                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 928 }
 929
 930 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 931                                        struct dwc2_host_chan *chan, int chnum,
 932                                        struct dwc2_qtd *qtd)
 933 {
 934         struct dwc2_hcd_iso_packet_desc *frame_desc;
 935         u32 len;
 936         u32 hctsiz;
 937         u32 pid;
 938
 939         if (!qtd->urb)
 940                 return 0;
 941
 942         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 943         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 944                                           DWC2_HC_XFER_COMPLETE, NULL);
 945         if (!len) {
 946                 qtd->complete_split = 0;
 947                 qtd->isoc_split_offset = 0;
 948                 return 0;
 949         }
 950
 951         frame_desc->actual_length += len;
 952
 953         qtd->isoc_split_offset += len;
 954
 955         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 956         pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 957
 958         if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
 959                 frame_desc->status = 0;
 960                 qtd->isoc_frame_index++;
 961                 qtd->complete_split = 0;
 962                 qtd->isoc_split_offset = 0;
 963         }
 964
 965         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 966                 dwc2_host_complete(hsotg, qtd, 0);
 967                 dwc2_release_channel(hsotg, chan, qtd,
 968                                      DWC2_HC_XFER_URB_COMPLETE);
 969         } else {
 970                 dwc2_release_channel(hsotg, chan, qtd,
 971                                      DWC2_HC_XFER_NO_HALT_STATUS);
 972         }
 973
 974         return 1;       /* Indicates that channel released */
 975 }
 976
 977 /*
 978  * Handles a host channel Transfer Complete interrupt. This handler may be
 979  * called in either DMA mode or Slave mode.
 980  */
 981 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 982                                   struct dwc2_host_chan *chan, int chnum,
 983                                   struct dwc2_qtd *qtd)
 984 {
 985         struct dwc2_hcd_urb *urb = qtd->urb;
 986         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 987         int pipe_type;
 988         int urb_xfer_done;
 989
 990         if (dbg_hc(chan))
 991                 dev_vdbg(hsotg->dev,
 992                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 993                          chnum);
 994
 995         if (!urb)
 996                 goto handle_xfercomp_done;
 997
 998         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 999
1000         if (hsotg->params.dma_desc_enable) {
1001                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
1002                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
1003                         /* Do not disable the interrupt, just clear it */
1004                         return;
1005                 goto handle_xfercomp_done;
1006         }
1007
1008         /* Handle xfer complete on CSPLIT */
1009         if (chan->qh->do_split) {
1010                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1011                     hsotg->params.host_dma) {
1012                         if (qtd->complete_split &&
1013                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1014                                                         qtd))
1015                                 goto handle_xfercomp_done;
1016                 } else {
1017                         qtd->complete_split = 0;
1018                 }
1019         }
1020
1021         /* Update the QTD and URB states */
1022         switch (pipe_type) {
1023         case USB_ENDPOINT_XFER_CONTROL:
1024                 switch (qtd->control_phase) {
1025                 case DWC2_CONTROL_SETUP:
1026                         if (urb->length > 0)
1027                                 qtd->control_phase = DWC2_CONTROL_DATA;
1028                         else
1029                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1030                         dev_vdbg(hsotg->dev,
1031                                  "  Control setup transaction done\n");
1032                         halt_status = DWC2_HC_XFER_COMPLETE;
1033                         break;
1034                 case DWC2_CONTROL_DATA:
1035                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1036                                                               chnum, urb, qtd);
1037                         if (urb_xfer_done) {
1038                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1039                                 dev_vdbg(hsotg->dev,
1040                                          "  Control data transfer done\n");
1041                         } else {
1042                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1043                                                           qtd);
1044                         }
1045                         halt_status = DWC2_HC_XFER_COMPLETE;
1046                         break;
1047                 case DWC2_CONTROL_STATUS:
1048                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1049                         if (urb->status == -EINPROGRESS)
1050                                 urb->status = 0;
1051                         dwc2_host_complete(hsotg, qtd, urb->status);
1052                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1053                         break;
1054                 }
1055
1056                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1057                                                 halt_status);
1058                 break;
1059         case USB_ENDPOINT_XFER_BULK:
1060                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1061                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1062                                                       qtd);
1063                 if (urb_xfer_done) {
1064                         dwc2_host_complete(hsotg, qtd, urb->status);
1065                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1066                 } else {
1067                         halt_status = DWC2_HC_XFER_COMPLETE;
1068                 }
1069
1070                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1071                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1072                                                 halt_status);
1073                 break;
1074         case USB_ENDPOINT_XFER_INT:
1075                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1076                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1077                                                       qtd);
1078
1079                 /*
1080                  * Interrupt URB is done on the first transfer complete
1081                  * interrupt
1082                  */
1083                 if (urb_xfer_done) {
1084                         dwc2_host_complete(hsotg, qtd, urb->status);
1085                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1086                 } else {
1087                         halt_status = DWC2_HC_XFER_COMPLETE;
1088                 }
1089
1090                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1091                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1092                                             halt_status);
1093                 break;
1094         case USB_ENDPOINT_XFER_ISOC:
1095                 if (dbg_perio())
1096                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1097                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1098                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1099                                                         chnum, qtd,
1100                                                         DWC2_HC_XFER_COMPLETE);
1101                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1102                                             halt_status);
1103                 break;
1104         }
1105
1106 handle_xfercomp_done:
1107         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1108 }
1109
1110 /*
1111  * Handles a host channel STALL interrupt. This handler may be called in
1112  * either DMA mode or Slave mode.
1113  */
1114 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1115                                struct dwc2_host_chan *chan, int chnum,
1116                                struct dwc2_qtd *qtd)
1117 {
1118         struct dwc2_hcd_urb *urb = qtd->urb;
1119         int pipe_type;
1120
1121         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1122                 chnum);
1123
1124         if (hsotg->params.dma_desc_enable) {
1125                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1126                                             DWC2_HC_XFER_STALL);
1127                 goto handle_stall_done;
1128         }
1129
1130         if (!urb)
1131                 goto handle_stall_halt;
1132
1133         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1134
1135         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1136                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1137
1138         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1139             pipe_type == USB_ENDPOINT_XFER_INT) {
1140                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1141                 /*
1142                  * USB protocol requires resetting the data toggle for bulk
1143                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1144                  * setup command is issued to the endpoint. Anticipate the
1145                  * CLEAR_FEATURE command since a STALL has occurred and reset
1146                  * the data toggle now.
1147                  */
1148                 chan->qh->data_toggle = 0;
1149         }
1150
1151 handle_stall_halt:
1152         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1153
1154 handle_stall_done:
1155         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1156 }
1157
1158 /*
1159  * Updates the state of the URB when a transfer has been stopped due to an
1160  * abnormal condition before the transfer completes. Modifies the
1161  * actual_length field of the URB to reflect the number of bytes that have
1162  * actually been transferred via the host channel.
1163  */
1164 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1165                                       struct dwc2_host_chan *chan, int chnum,
1166                                       struct dwc2_hcd_urb *urb,
1167                                       struct dwc2_qtd *qtd,
1168                                       enum dwc2_halt_status halt_status)
1169 {
1170         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1171                                                       qtd, halt_status, NULL);
1172         u32 hctsiz;
1173
1174         if (urb->actual_length + xfer_length > urb->length) {
1175                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1176                 xfer_length = urb->length - urb->actual_length;
1177         }
1178
1179         urb->actual_length += xfer_length;
1180
1181         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1182         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1183                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1184         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1185                  chan->start_pkt_count);
1186         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1187                  (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1188         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1189         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1190                  xfer_length);
1191         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1192                  urb->actual_length);
1193         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1194                  urb->length);
1195 }
1196
1197 /*
1198  * Handles a host channel NAK interrupt. This handler may be called in either
1199  * DMA mode or Slave mode.
1200  */
1201 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1202                              struct dwc2_host_chan *chan, int chnum,
1203                              struct dwc2_qtd *qtd)
1204 {
1205         if (!qtd) {
1206                 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1207                 return;
1208         }
1209
1210         if (!qtd->urb) {
1211                 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1212                 return;
1213         }
1214
1215         if (dbg_hc(chan))
1216                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1217                          chnum);
1218
1219         /*
1220          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1221          * interrupt. Re-start the SSPLIT transfer.
1222          *
1223          * Normally for non-periodic transfers we'll retry right away, but to
1224          * avoid interrupt storms we'll wait before retrying if we've got
1225          * several NAKs. If we didn't do this we'd retry directly from the
1226          * interrupt handler and could end up quickly getting another
1227          * interrupt (another NAK), which we'd retry.
1228          *
1229          * Note that in DMA mode software only gets involved to re-send NAKed
1230          * transfers for split transactions, so we only need to apply this
1231          * delaying logic when handling splits. In non-DMA mode presumably we
1232          * might want a similar delay if someone can demonstrate this problem
1233          * affects that code path too.
1234          */
1235         if (chan->do_split) {
1236                 if (chan->complete_split)
1237                         qtd->error_count = 0;
1238                 qtd->complete_split = 0;
1239                 qtd->num_naks++;
1240                 qtd->qh->want_wait = qtd->num_naks >= DWC2_NAKS_BEFORE_DELAY;
1241                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1242                 goto handle_nak_done;
1243         }
1244
1245         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1246         case USB_ENDPOINT_XFER_CONTROL:
1247         case USB_ENDPOINT_XFER_BULK:
1248                 if (hsotg->params.host_dma && chan->ep_is_in) {
1249                         /*
1250                          * NAK interrupts are enabled on bulk/control IN
1251                          * transfers in DMA mode for the sole purpose of
1252                          * resetting the error count after a transaction error
1253                          * occurs. The core will continue transferring data.
1254                          */
1255                         qtd->error_count = 0;
1256                         break;
1257                 }
1258
1259                 /*
1260                  * NAK interrupts normally occur during OUT transfers in DMA
1261                  * or Slave mode. For IN transfers, more requests will be
1262                  * queued as request queue space is available.
1263                  */
1264                 qtd->error_count = 0;
1265
1266                 if (!chan->qh->ping_state) {
1267                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1268                                                   qtd, DWC2_HC_XFER_NAK);
1269                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1270
1271                         if (chan->speed == USB_SPEED_HIGH)
1272                                 chan->qh->ping_state = 1;
1273                 }
1274
1275                 /*
1276                  * Halt the channel so the transfer can be re-started from
1277                  * the appropriate point or the PING protocol will
1278                  * start/continue
1279                  */
1280                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1281                 break;
1282         case USB_ENDPOINT_XFER_INT:
1283                 qtd->error_count = 0;
1284                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1285                 break;
1286         case USB_ENDPOINT_XFER_ISOC:
1287                 /* Should never get called for isochronous transfers */
1288                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1289                 break;
1290         }
1291
1292 handle_nak_done:
1293         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1294 }
1295
1296 /*
1297  * Handles a host channel ACK interrupt. This interrupt is enabled when
1298  * performing the PING protocol in Slave mode, when errors occur during
1299  * either Slave mode or DMA mode, and during Start Split transactions.
1300  */
1301 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1302                              struct dwc2_host_chan *chan, int chnum,
1303                              struct dwc2_qtd *qtd)
1304 {
1305         struct dwc2_hcd_iso_packet_desc *frame_desc;
1306
1307         if (dbg_hc(chan))
1308                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1309                          chnum);
1310
1311         if (chan->do_split) {
1312                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1313                 if (!chan->ep_is_in &&
1314                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1315                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1316
1317                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1318                         qtd->complete_split = 1;
1319                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1320                 } else {
1321                         /* ISOC OUT */
1322                         switch (chan->xact_pos) {
1323                         case DWC2_HCSPLT_XACTPOS_ALL:
1324                                 break;
1325                         case DWC2_HCSPLT_XACTPOS_END:
1326                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1327                                 qtd->isoc_split_offset = 0;
1328                                 break;
1329                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1330                         case DWC2_HCSPLT_XACTPOS_MID:
1331                                 /*
1332                                  * For BEGIN or MID, calculate the length for
1333                                  * the next microframe to determine the correct
1334                                  * SSPLIT token, either MID or END
1335                                  */
1336                                 frame_desc = &qtd->urb->iso_descs[
1337                                                 qtd->isoc_frame_index];
1338                                 qtd->isoc_split_offset += 188;
1339
1340                                 if (frame_desc->length - qtd->isoc_split_offset
1341                                                         <= 188)
1342                                         qtd->isoc_split_pos =
1343                                                         DWC2_HCSPLT_XACTPOS_END;
1344                                 else
1345                                         qtd->isoc_split_pos =
1346                                                         DWC2_HCSPLT_XACTPOS_MID;
1347                                 break;
1348                         }
1349                 }
1350         } else {
1351                 qtd->error_count = 0;
1352
1353                 if (chan->qh->ping_state) {
1354                         chan->qh->ping_state = 0;
1355                         /*
1356                          * Halt the channel so the transfer can be re-started
1357                          * from the appropriate point. This only happens in
1358                          * Slave mode. In DMA mode, the ping_state is cleared
1359                          * when the transfer is started because the core
1360                          * automatically executes the PING, then the transfer.
1361                          */
1362                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1363                 }
1364         }
1365
1366         /*
1367          * If the ACK occurred when _not_ in the PING state, let the channel
1368          * continue transferring data after clearing the error count
1369          */
1370         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1371 }
1372
1373 /*
1374  * Handles a host channel NYET interrupt. This interrupt should only occur on
1375  * Bulk and Control OUT endpoints and for complete split transactions. If a
1376  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1377  * handled in the xfercomp interrupt handler, not here. This handler may be
1378  * called in either DMA mode or Slave mode.
1379  */
1380 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1381                               struct dwc2_host_chan *chan, int chnum,
1382                               struct dwc2_qtd *qtd)
1383 {
1384         if (dbg_hc(chan))
1385                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1386                          chnum);
1387
1388         /*
1389          * NYET on CSPLIT
1390          * re-do the CSPLIT immediately on non-periodic
1391          */
1392         if (chan->do_split && chan->complete_split) {
1393                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1394                     hsotg->params.host_dma) {
1395                         qtd->complete_split = 0;
1396                         qtd->isoc_split_offset = 0;
1397                         qtd->isoc_frame_index++;
1398                         if (qtd->urb &&
1399                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1400                                 dwc2_host_complete(hsotg, qtd, 0);
1401                                 dwc2_release_channel(hsotg, chan, qtd,
1402                                                      DWC2_HC_XFER_URB_COMPLETE);
1403                         } else {
1404                                 dwc2_release_channel(hsotg, chan, qtd,
1405                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1406                         }
1407                         goto handle_nyet_done;
1408                 }
1409
1410                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1411                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1412                         struct dwc2_qh *qh = chan->qh;
1413                         bool past_end;
1414
1415                         if (!hsotg->params.uframe_sched) {
1416                                 int frnum = dwc2_hcd_get_frame_number(hsotg);
1417
1418                                 /* Don't have num_hs_transfers; simple logic */
1419                                 past_end = dwc2_full_frame_num(frnum) !=
1420                                      dwc2_full_frame_num(qh->next_active_frame);
1421                         } else {
1422                                 int end_frnum;
1423
1424                                 /*
1425                                  * Figure out the end frame based on
1426                                  * schedule.
1427                                  *
1428                                  * We don't want to go on trying again
1429                                  * and again forever. Let's stop when
1430                                  * we've done all the transfers that
1431                                  * were scheduled.
1432                                  *
1433                                  * We're going to be comparing
1434                                  * start_active_frame and
1435                                  * next_active_frame, both of which
1436                                  * are 1 before the time the packet
1437                                  * goes on the wire, so that cancels
1438                                  * out. Basically if had 1 transfer
1439                                  * and we saw 1 NYET then we're done.
1440                                  * We're getting a NYET here so if
1441                                  * next >= (start + num_transfers)
1442                                  * we're done. The complexity is that
1443                                  * for all but ISOC_OUT we skip one
1444                                  * slot.
1445                                  */
1446                                 end_frnum = dwc2_frame_num_inc(
1447                                         qh->start_active_frame,
1448                                         qh->num_hs_transfers);
1449
1450                                 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1451                                     qh->ep_is_in)
1452                                         end_frnum =
1453                                                dwc2_frame_num_inc(end_frnum, 1);
1454
1455                                 past_end = dwc2_frame_num_le(
1456                                         end_frnum, qh->next_active_frame);
1457                         }
1458
1459                         if (past_end) {
1460                                 /* Treat this as a transaction error. */
1461 #if 0
1462                                 /*
1463                                  * Todo: Fix system performance so this can
1464                                  * be treated as an error. Right now complete
1465                                  * splits cannot be scheduled precisely enough
1466                                  * due to other system activity, so this error
1467                                  * occurs regularly in Slave mode.
1468                                  */
1469                                 qtd->error_count++;
1470 #endif
1471                                 qtd->complete_split = 0;
1472                                 dwc2_halt_channel(hsotg, chan, qtd,
1473                                                   DWC2_HC_XFER_XACT_ERR);
1474                                 /* Todo: add support for isoc release */
1475                                 goto handle_nyet_done;
1476                         }
1477                 }
1478
1479                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1480                 goto handle_nyet_done;
1481         }
1482
1483         chan->qh->ping_state = 1;
1484         qtd->error_count = 0;
1485
1486         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1487                                   DWC2_HC_XFER_NYET);
1488         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1489
1490         /*
1491          * Halt the channel and re-start the transfer so the PING protocol
1492          * will start
1493          */
1494         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1495
1496 handle_nyet_done:
1497         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1498 }
1499
1500 /*
1501  * Handles a host channel babble interrupt. This handler may be called in
1502  * either DMA mode or Slave mode.
1503  */
1504 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1505                                 struct dwc2_host_chan *chan, int chnum,
1506                                 struct dwc2_qtd *qtd)
1507 {
1508         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1509                 chnum);
1510
1511         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1512
1513         if (hsotg->params.dma_desc_enable) {
1514                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1515                                             DWC2_HC_XFER_BABBLE_ERR);
1516                 goto disable_int;
1517         }
1518
1519         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1520                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1521                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1522         } else {
1523                 enum dwc2_halt_status halt_status;
1524
1525                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1526                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1527                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1528         }
1529
1530 disable_int:
1531         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1532 }
1533
1534 /*
1535  * Handles a host channel AHB error interrupt. This handler is only called in
1536  * DMA mode.
1537  */
1538 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1539                                 struct dwc2_host_chan *chan, int chnum,
1540                                 struct dwc2_qtd *qtd)
1541 {
1542         struct dwc2_hcd_urb *urb = qtd->urb;
1543         char *pipetype, *speed;
1544         u32 hcchar;
1545         u32 hcsplt;
1546         u32 hctsiz;
1547         u32 hc_dma;
1548
1549         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1550                 chnum);
1551
1552         if (!urb)
1553                 goto handle_ahberr_halt;
1554
1555         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1556
1557         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1558         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1559         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1560         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1561
1562         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1563         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1564         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1565         dev_err(hsotg->dev, "  Device address: %d\n",
1566                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1567         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1568                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1569                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1570
1571         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1572         case USB_ENDPOINT_XFER_CONTROL:
1573                 pipetype = "CONTROL";
1574                 break;
1575         case USB_ENDPOINT_XFER_BULK:
1576                 pipetype = "BULK";
1577                 break;
1578         case USB_ENDPOINT_XFER_INT:
1579                 pipetype = "INTERRUPT";
1580                 break;
1581         case USB_ENDPOINT_XFER_ISOC:
1582                 pipetype = "ISOCHRONOUS";
1583                 break;
1584         default:
1585                 pipetype = "UNKNOWN";
1586                 break;
1587         }
1588
1589         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1590
1591         switch (chan->speed) {
1592         case USB_SPEED_HIGH:
1593                 speed = "HIGH";
1594                 break;
1595         case USB_SPEED_FULL:
1596                 speed = "FULL";
1597                 break;
1598         case USB_SPEED_LOW:
1599                 speed = "LOW";
1600                 break;
1601         default:
1602                 speed = "UNKNOWN";
1603                 break;
1604         }
1605
1606         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1607
1608         dev_err(hsotg->dev, "  Max packet size: %d\n",
1609                 dwc2_hcd_get_mps(&urb->pipe_info));
1610         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1611         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1612                 urb->buf, (unsigned long)urb->dma);
1613         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1614                 urb->setup_packet, (unsigned long)urb->setup_dma);
1615         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1616
1617         /* Core halts the channel for Descriptor DMA mode */
1618         if (hsotg->params.dma_desc_enable) {
1619                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1620                                             DWC2_HC_XFER_AHB_ERR);
1621                 goto handle_ahberr_done;
1622         }
1623
1624         dwc2_host_complete(hsotg, qtd, -EIO);
1625
1626 handle_ahberr_halt:
1627         /*
1628          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1629          * write to the HCCHARn register in DMA mode to force the halt.
1630          */
1631         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1632
1633 handle_ahberr_done:
1634         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1635 }
1636
1637 /*
1638  * Handles a host channel transaction error interrupt. This handler may be
1639  * called in either DMA mode or Slave mode.
1640  */
1641 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1642                                  struct dwc2_host_chan *chan, int chnum,
1643                                  struct dwc2_qtd *qtd)
1644 {
1645         dev_dbg(hsotg->dev,
1646                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1647
1648         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1649
1650         if (hsotg->params.dma_desc_enable) {
1651                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1652                                             DWC2_HC_XFER_XACT_ERR);
1653                 goto handle_xacterr_done;
1654         }
1655
1656         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1657         case USB_ENDPOINT_XFER_CONTROL:
1658         case USB_ENDPOINT_XFER_BULK:
1659                 qtd->error_count++;
1660                 if (!chan->qh->ping_state) {
1661                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1662                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1663                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1664                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1665                                 chan->qh->ping_state = 1;
1666                 }
1667
1668                 /*
1669                  * Halt the channel so the transfer can be re-started from
1670                  * the appropriate point or the PING protocol will start
1671                  */
1672                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1673                 break;
1674         case USB_ENDPOINT_XFER_INT:
1675                 qtd->error_count++;
1676                 if (chan->do_split && chan->complete_split)
1677                         qtd->complete_split = 0;
1678                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1679                 break;
1680         case USB_ENDPOINT_XFER_ISOC:
1681                 {
1682                         enum dwc2_halt_status halt_status;
1683
1684                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1685                                          chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1686                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1687                 }
1688                 break;
1689         }
1690
1691 handle_xacterr_done:
1692         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1693 }
1694
1695 /*
1696  * Handles a host channel frame overrun interrupt. This handler may be called
1697  * in either DMA mode or Slave mode.
1698  */
1699 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1700                                   struct dwc2_host_chan *chan, int chnum,
1701                                   struct dwc2_qtd *qtd)
1702 {
1703         enum dwc2_halt_status halt_status;
1704
1705         if (dbg_hc(chan))
1706                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1707                         chnum);
1708
1709         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1710
1711         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1712         case USB_ENDPOINT_XFER_CONTROL:
1713         case USB_ENDPOINT_XFER_BULK:
1714                 break;
1715         case USB_ENDPOINT_XFER_INT:
1716                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1717                 break;
1718         case USB_ENDPOINT_XFER_ISOC:
1719                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1720                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1721                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1722                 break;
1723         }
1724
1725         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1726 }
1727
1728 /*
1729  * Handles a host channel data toggle error interrupt. This handler may be
1730  * called in either DMA mode or Slave mode.
1731  */
1732 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1733                                     struct dwc2_host_chan *chan, int chnum,
1734                                     struct dwc2_qtd *qtd)
1735 {
1736         dev_dbg(hsotg->dev,
1737                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1738
1739         if (chan->ep_is_in)
1740                 qtd->error_count = 0;
1741         else
1742                 dev_err(hsotg->dev,
1743                         "Data Toggle Error on OUT transfer, channel %d\n",
1744                         chnum);
1745
1746         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1747         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1748 }
1749
1750 /*
1751  * For debug only. It checks that a valid halt status is set and that
1752  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1753  * taken and a warning is issued.
1754  *
1755  * Return: true if halt status is ok, false otherwise
1756  */
1757 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1758                                 struct dwc2_host_chan *chan, int chnum,
1759                                 struct dwc2_qtd *qtd)
1760 {
1761 #ifdef DEBUG
1762         u32 hcchar;
1763         u32 hctsiz;
1764         u32 hcintmsk;
1765         u32 hcsplt;
1766
1767         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1768                 /*
1769                  * This code is here only as a check. This condition should
1770                  * never happen. Ignore the halt if it does occur.
1771                  */
1772                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1773                 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1774                 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1775                 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1776                 dev_dbg(hsotg->dev,
1777                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1778                          __func__);
1779                 dev_dbg(hsotg->dev,
1780                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1781                         chnum, hcchar, hctsiz);
1782                 dev_dbg(hsotg->dev,
1783                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1784                         chan->hcint, hcintmsk, hcsplt);
1785                 if (qtd)
1786                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1787                                 qtd->complete_split);
1788                 dev_warn(hsotg->dev,
1789                          "%s: no halt status, channel %d, ignoring interrupt\n",
1790                          __func__, chnum);
1791                 return false;
1792         }
1793
1794         /*
1795          * This code is here only as a check. hcchar.chdis should never be set
1796          * when the halt interrupt occurs. Halt the channel again if it does
1797          * occur.
1798          */
1799         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1800         if (hcchar & HCCHAR_CHDIS) {
1801                 dev_warn(hsotg->dev,
1802                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1803                          __func__, hcchar);
1804                 chan->halt_pending = 0;
1805                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1806                 return false;
1807         }
1808 #endif
1809
1810         return true;
1811 }
1812
1813 /*
1814  * Handles a host Channel Halted interrupt in DMA mode. This handler
1815  * determines the reason the channel halted and proceeds accordingly.
1816  */
1817 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1818                                     struct dwc2_host_chan *chan, int chnum,
1819                                     struct dwc2_qtd *qtd)
1820 {
1821         u32 hcintmsk;
1822         int out_nak_enh = 0;
1823
1824         if (dbg_hc(chan))
1825                 dev_vdbg(hsotg->dev,
1826                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1827                          chnum);
1828
1829         /*
1830          * For core with OUT NAK enhancement, the flow for high-speed
1831          * CONTROL/BULK OUT is handled a little differently
1832          */
1833         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1834                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1835                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1836                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1837                         out_nak_enh = 1;
1838                 }
1839         }
1840
1841         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1842             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1843              !hsotg->params.dma_desc_enable)) {
1844                 if (hsotg->params.dma_desc_enable)
1845                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1846                                                     chan->halt_status);
1847                 else
1848                         /*
1849                          * Just release the channel. A dequeue can happen on a
1850                          * transfer timeout. In the case of an AHB Error, the
1851                          * channel was forced to halt because there's no way to
1852                          * gracefully recover.
1853                          */
1854                         dwc2_release_channel(hsotg, chan, qtd,
1855                                              chan->halt_status);
1856                 return;
1857         }
1858
1859         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1860
1861         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1862                 /*
1863                  * Todo: This is here because of a possible hardware bug. Spec
1864                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1865                  * interrupt w/ACK bit set should occur, but I only see the
1866                  * XFERCOMP bit, even with it masked out. This is a workaround
1867                  * for that behavior. Should fix this when hardware is fixed.
1868                  */
1869                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1870                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1871                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1872         } else if (chan->hcint & HCINTMSK_STALL) {
1873                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1874         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1875                    !hsotg->params.dma_desc_enable) {
1876                 if (out_nak_enh) {
1877                         if (chan->hcint &
1878                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1879                                 dev_vdbg(hsotg->dev,
1880                                          "XactErr with NYET/NAK/ACK\n");
1881                                 qtd->error_count = 0;
1882                         } else {
1883                                 dev_vdbg(hsotg->dev,
1884                                          "XactErr without NYET/NAK/ACK\n");
1885                         }
1886                 }
1887
1888                 /*
1889                  * Must handle xacterr before nak or ack. Could get a xacterr
1890                  * at the same time as either of these on a BULK/CONTROL OUT
1891                  * that started with a PING. The xacterr takes precedence.
1892                  */
1893                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1894         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1895                    hsotg->params.dma_desc_enable) {
1896                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1897         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1898                    hsotg->params.dma_desc_enable) {
1899                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1900         } else if (chan->hcint & HCINTMSK_BBLERR) {
1901                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1902         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1903                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1904         } else if (!out_nak_enh) {
1905                 if (chan->hcint & HCINTMSK_NYET) {
1906                         /*
1907                          * Must handle nyet before nak or ack. Could get a nyet
1908                          * at the same time as either of those on a BULK/CONTROL
1909                          * OUT that started with a PING. The nyet takes
1910                          * precedence.
1911                          */
1912                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1913                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1914                            !(hcintmsk & HCINTMSK_NAK)) {
1915                         /*
1916                          * If nak is not masked, it's because a non-split IN
1917                          * transfer is in an error state. In that case, the nak
1918                          * is handled by the nak interrupt handler, not here.
1919                          * Handle nak here for BULK/CONTROL OUT transfers, which
1920                          * halt on a NAK to allow rewinding the buffer pointer.
1921                          */
1922                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1923                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1924                            !(hcintmsk & HCINTMSK_ACK)) {
1925                         /*
1926                          * If ack is not masked, it's because a non-split IN
1927                          * transfer is in an error state. In that case, the ack
1928                          * is handled by the ack interrupt handler, not here.
1929                          * Handle ack here for split transfers. Start splits
1930                          * halt on ACK.
1931                          */
1932                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1933                 } else {
1934                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1935                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1936                                 /*
1937                                  * A periodic transfer halted with no other
1938                                  * channel interrupts set. Assume it was halted
1939                                  * by the core because it could not be completed
1940                                  * in its scheduled (micro)frame.
1941                                  */
1942                                 dev_dbg(hsotg->dev,
1943                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1944                                         __func__, chnum);
1945                                 dwc2_halt_channel(hsotg, chan, qtd,
1946                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1947                         } else {
1948                                 dev_err(hsotg->dev,
1949                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1950                                         __func__, chnum);
1951                                 dev_err(hsotg->dev,
1952                                         "hcint 0x%08x, intsts 0x%08x\n",
1953                                         chan->hcint,
1954                                         dwc2_readl(hsotg->regs + GINTSTS));
1955                                 goto error;
1956                         }
1957                 }
1958         } else {
1959                 dev_info(hsotg->dev,
1960                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1961                          chan->hcint);
1962 error:
1963                 /* Failthrough: use 3-strikes rule */
1964                 qtd->error_count++;
1965                 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1966                                           qtd, DWC2_HC_XFER_XACT_ERR);
1967                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1968                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1969         }
1970 }
1971
1972 /*
1973  * Handles a host channel Channel Halted interrupt
1974  *
1975  * In slave mode, this handler is called only when the driver specifically
1976  * requests a halt. This occurs during handling other host channel interrupts
1977  * (e.g. nak, xacterr, stall, nyet, etc.).
1978  *
1979  * In DMA mode, this is the interrupt that occurs when the core has finished
1980  * processing a transfer on a channel. Other host channel interrupts (except
1981  * ahberr) are disabled in DMA mode.
1982  */
1983 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1984                                 struct dwc2_host_chan *chan, int chnum,
1985                                 struct dwc2_qtd *qtd)
1986 {
1987         if (dbg_hc(chan))
1988                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1989                          chnum);
1990
1991         if (hsotg->params.host_dma) {
1992                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1993         } else {
1994                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1995                         return;
1996                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1997         }
1998 }
1999
2000 /*
2001  * Check if the given qtd is still the top of the list (and thus valid).
2002  *
2003  * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
2004  * the qtd from the top of the list, this will return false (otherwise true).
2005  */
2006 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
2007 {
2008         struct dwc2_qtd *cur_head;
2009
2010         if (!qh)
2011                 return false;
2012
2013         cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
2014                                     qtd_list_entry);
2015         return (cur_head == qtd);
2016 }
2017
2018 /* Handles interrupt for a specific Host Channel */
2019 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2020 {
2021         struct dwc2_qtd *qtd;
2022         struct dwc2_host_chan *chan;
2023         u32 hcint, hcintmsk;
2024
2025         chan = hsotg->hc_ptr_array[chnum];
2026
2027         hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
2028         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
2029         if (!chan) {
2030                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2031                 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2032                 return;
2033         }
2034
2035         if (dbg_hc(chan)) {
2036                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2037                          chnum);
2038                 dev_vdbg(hsotg->dev,
2039                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2040                          hcint, hcintmsk, hcint & hcintmsk);
2041         }
2042
2043         dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2044
2045         /*
2046          * If we got an interrupt after someone called
2047          * dwc2_hcd_endpoint_disable() we don't want to crash below
2048          */
2049         if (!chan->qh) {
2050                 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2051                 return;
2052         }
2053
2054         chan->hcint = hcint;
2055         hcint &= hcintmsk;
2056
2057         /*
2058          * If the channel was halted due to a dequeue, the qtd list might
2059          * be empty or at least the first entry will not be the active qtd.
2060          * In this case, take a shortcut and just release the channel.
2061          */
2062         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2063                 /*
2064                  * If the channel was halted, this should be the only
2065                  * interrupt unmasked
2066                  */
2067                 WARN_ON(hcint != HCINTMSK_CHHLTD);
2068                 if (hsotg->params.dma_desc_enable)
2069                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2070                                                     chan->halt_status);
2071                 else
2072                         dwc2_release_channel(hsotg, chan, NULL,
2073                                              chan->halt_status);
2074                 return;
2075         }
2076
2077         if (list_empty(&chan->qh->qtd_list)) {
2078                 /*
2079                  * TODO: Will this ever happen with the
2080                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
2081                  */
2082                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2083                         chnum);
2084                 dev_dbg(hsotg->dev,
2085                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2086                         chan->hcint, hcintmsk, hcint);
2087                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2088                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2089                 chan->hcint = 0;
2090                 return;
2091         }
2092
2093         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2094                                qtd_list_entry);
2095
2096         if (!hsotg->params.host_dma) {
2097                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2098                         hcint &= ~HCINTMSK_CHHLTD;
2099         }
2100
2101         if (hcint & HCINTMSK_XFERCOMPL) {
2102                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2103                 /*
2104                  * If NYET occurred at same time as Xfer Complete, the NYET is
2105                  * handled by the Xfer Complete interrupt handler. Don't want
2106                  * to call the NYET interrupt handler in this case.
2107                  */
2108                 hcint &= ~HCINTMSK_NYET;
2109         }
2110
2111         if (hcint & HCINTMSK_CHHLTD) {
2112                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2113                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2114                         goto exit;
2115         }
2116         if (hcint & HCINTMSK_AHBERR) {
2117                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2118                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2119                         goto exit;
2120         }
2121         if (hcint & HCINTMSK_STALL) {
2122                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2123                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2124                         goto exit;
2125         }
2126         if (hcint & HCINTMSK_NAK) {
2127                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2128                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2129                         goto exit;
2130         }
2131         if (hcint & HCINTMSK_ACK) {
2132                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2133                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2134                         goto exit;
2135         }
2136         if (hcint & HCINTMSK_NYET) {
2137                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2138                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2139                         goto exit;
2140         }
2141         if (hcint & HCINTMSK_XACTERR) {
2142                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2143                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2144                         goto exit;
2145         }
2146         if (hcint & HCINTMSK_BBLERR) {
2147                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2148                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2149                         goto exit;
2150         }
2151         if (hcint & HCINTMSK_FRMOVRUN) {
2152                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2153                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2154                         goto exit;
2155         }
2156         if (hcint & HCINTMSK_DATATGLERR) {
2157                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2158                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2159                         goto exit;
2160         }
2161
2162 exit:
2163         chan->hcint = 0;
2164 }
2165
2166 /*
2167  * This interrupt indicates that one or more host channels has a pending
2168  * interrupt. There are multiple conditions that can cause each host channel
2169  * interrupt. This function determines which conditions have occurred for each
2170  * host channel interrupt and handles them appropriately.
2171  */
2172 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2173 {
2174         u32 haint;
2175         int i;
2176         struct dwc2_host_chan *chan, *chan_tmp;
2177
2178         haint = dwc2_readl(hsotg->regs + HAINT);
2179         if (dbg_perio()) {
2180                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2181
2182                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2183         }
2184
2185         /*
2186          * According to USB 2.0 spec section 11.18.8, a host must
2187          * issue complete-split transactions in a microframe for a
2188          * set of full-/low-speed endpoints in the same relative
2189          * order as the start-splits were issued in a microframe for.
2190          */
2191         list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2192                                  split_order_list_entry) {
2193                 int hc_num = chan->hc_num;
2194
2195                 if (haint & (1 << hc_num)) {
2196                         dwc2_hc_n_intr(hsotg, hc_num);
2197                         haint &= ~(1 << hc_num);
2198                 }
2199         }
2200
2201         for (i = 0; i < hsotg->params.host_channels; i++) {
2202                 if (haint & (1 << i))
2203                         dwc2_hc_n_intr(hsotg, i);
2204         }
2205 }
2206
2207 /* This function handles interrupts for the HCD */
2208 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2209 {
2210         u32 gintsts, dbg_gintsts;
2211         irqreturn_t retval = IRQ_NONE;
2212
2213         if (!dwc2_is_controller_alive(hsotg)) {
2214                 dev_warn(hsotg->dev, "Controller is dead\n");
2215                 return retval;
2216         }
2217
2218         spin_lock(&hsotg->lock);
2219
2220         /* Check if HOST Mode */
2221         if (dwc2_is_host_mode(hsotg)) {
2222                 gintsts = dwc2_read_core_intr(hsotg);
2223                 if (!gintsts) {
2224                         spin_unlock(&hsotg->lock);
2225                         return retval;
2226                 }
2227
2228                 retval = IRQ_HANDLED;
2229
2230                 dbg_gintsts = gintsts;
2231 #ifndef DEBUG_SOF
2232                 dbg_gintsts &= ~GINTSTS_SOF;
2233 #endif
2234                 if (!dbg_perio())
2235                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2236                                          GINTSTS_PTXFEMP);
2237
2238                 /* Only print if there are any non-suppressed interrupts left */
2239                 if (dbg_gintsts)
2240                         dev_vdbg(hsotg->dev,
2241                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2242                                  gintsts);
2243
2244                 if (gintsts & GINTSTS_SOF)
2245                         dwc2_sof_intr(hsotg);
2246                 if (gintsts & GINTSTS_RXFLVL)
2247                         dwc2_rx_fifo_level_intr(hsotg);
2248                 if (gintsts & GINTSTS_NPTXFEMP)
2249                         dwc2_np_tx_fifo_empty_intr(hsotg);
2250                 if (gintsts & GINTSTS_PRTINT)
2251                         dwc2_port_intr(hsotg);
2252                 if (gintsts & GINTSTS_HCHINT)
2253                         dwc2_hc_intr(hsotg);
2254                 if (gintsts & GINTSTS_PTXFEMP)
2255                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2256
2257                 if (dbg_gintsts) {
2258                         dev_vdbg(hsotg->dev,
2259                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2260                         dev_vdbg(hsotg->dev,
2261                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2262                                  dwc2_readl(hsotg->regs + GINTSTS),
2263                                  dwc2_readl(hsotg->regs + GINTMSK));
2264                 }
2265         }
2266
2267         spin_unlock(&hsotg->lock);
2268
2269         return retval;
2270 }