1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
34 /* conversion functions */
35 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
37 return container_of(req, struct dwc2_hsotg_req, req);
40 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
42 return container_of(ep, struct dwc2_hsotg_ep, ep);
45 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
47 return container_of(gadget, struct dwc2_hsotg, gadget);
50 static inline void dwc2_set_bit(void __iomem *ptr, u32 val)
52 dwc2_writel(dwc2_readl(ptr) | val, ptr);
55 static inline void dwc2_clear_bit(void __iomem *ptr, u32 val)
57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
60 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
61 u32 ep_index, u32 dir_in)
64 return hsotg->eps_in[ep_index];
66 return hsotg->eps_out[ep_index];
69 /* forward declaration of functions */
70 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
76 * Return true if we're using DMA.
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
89 * g_using_dma is set depending on dts flag.
91 static inline bool using_dma(struct dwc2_hsotg *hsotg)
93 return hsotg->params.g_dma;
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
100 * Return true if we're using descriptor DMA.
102 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
104 return hsotg->params.g_dma_desc;
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
111 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
112 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
114 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116 hs_ep->target_frame += hs_ep->interval;
117 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
118 hs_ep->frame_overrun = true;
119 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
121 hs_ep->frame_overrun = false;
126 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
127 * @hsotg: The device state
128 * @ints: A bitmask of the interrupts to enable
130 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
132 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
135 new_gsintmsk = gsintmsk | ints;
137 if (new_gsintmsk != gsintmsk) {
138 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
139 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
144 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
145 * @hsotg: The device state
146 * @ints: A bitmask of the interrupts to enable
148 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
150 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
153 new_gsintmsk = gsintmsk & ~ints;
155 if (new_gsintmsk != gsintmsk)
156 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
160 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
161 * @hsotg: The device state
162 * @ep: The endpoint index
163 * @dir_in: True if direction is in.
164 * @en: The enable value, true to enable
166 * Set or clear the mask for an individual endpoint's interrupt
169 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
170 unsigned int ep, unsigned int dir_in,
180 local_irq_save(flags);
181 daint = dwc2_readl(hsotg->regs + DAINTMSK);
186 dwc2_writel(daint, hsotg->regs + DAINTMSK);
187 local_irq_restore(flags);
191 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
193 * @hsotg: Programming view of the DWC_otg controller
195 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
197 if (hsotg->hw_params.en_multiple_tx_fifo)
198 /* In dedicated FIFO mode we need count of IN EPs */
199 return hsotg->hw_params.num_dev_in_eps;
201 /* In shared FIFO mode we need count of Periodic IN EPs */
202 return hsotg->hw_params.num_dev_perio_in_ep;
206 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
207 * device mode TX FIFOs
209 * @hsotg: Programming view of the DWC_otg controller
211 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
217 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
218 hsotg->params.g_np_tx_fifo_size);
220 /* Get Endpoint Info Control block size in DWORDs. */
221 tx_addr_max = hsotg->hw_params.total_fifo_size;
223 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
224 if (tx_addr_max <= addr)
227 return tx_addr_max - addr;
231 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
234 * @hsotg: Programming view of the DWC_otg controller
236 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
241 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
243 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
246 return tx_fifo_depth;
248 return tx_fifo_depth / tx_fifo_count;
252 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
253 * @hsotg: The device instance.
255 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
262 u32 *txfsz = hsotg->params.g_tx_fifo_size;
264 /* Reset fifo map if not correctly cleared during previous session */
265 WARN_ON(hsotg->fifo_map);
268 /* set RX/NPTX FIFO sizes */
269 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
270 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
271 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
272 hsotg->regs + GNPTXFSIZ);
275 * arange all the rest of the TX FIFOs, as some versions of this
276 * block have overlapping default addresses. This also ensures
277 * that if the settings have been changed, then they are set to
281 /* start at the end of the GNPTXFSIZ, rounded up */
282 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
285 * Configure fifos sizes from provided configuration and assign
286 * them to endpoints dynamically according to maxpacket size value of
289 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
293 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
294 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
295 "insufficient fifo memory");
298 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
299 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
302 dwc2_writel(hsotg->hw_params.total_fifo_size |
303 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
304 hsotg->regs + GDFIFOCFG);
306 * according to p428 of the design guide, we need to ensure that
307 * all fifos are flushed before continuing
310 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
311 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
313 /* wait until the fifos are both flushed */
316 val = dwc2_readl(hsotg->regs + GRSTCTL);
318 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
321 if (--timeout == 0) {
323 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
331 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
335 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
336 * @ep: USB endpoint to allocate request for.
337 * @flags: Allocation flags
339 * Allocate a new USB request structure appropriate for the specified endpoint
341 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
344 struct dwc2_hsotg_req *req;
346 req = kzalloc(sizeof(*req), flags);
350 INIT_LIST_HEAD(&req->queue);
356 * is_ep_periodic - return true if the endpoint is in periodic mode.
357 * @hs_ep: The endpoint to query.
359 * Returns true if the endpoint is in periodic mode, meaning it is being
360 * used for an Interrupt or ISO transfer.
362 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
364 return hs_ep->periodic;
368 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
369 * @hsotg: The device state.
370 * @hs_ep: The endpoint for the request
371 * @hs_req: The request being processed.
373 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
374 * of a request to ensure the buffer is ready for access by the caller.
376 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
377 struct dwc2_hsotg_ep *hs_ep,
378 struct dwc2_hsotg_req *hs_req)
380 struct usb_request *req = &hs_req->req;
382 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
386 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
387 * for Control endpoint
388 * @hsotg: The device state.
390 * This function will allocate 4 descriptor chains for EP 0: 2 for
391 * Setup stage, per one for IN and OUT data/status transactions.
393 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
395 hsotg->setup_desc[0] =
396 dmam_alloc_coherent(hsotg->dev,
397 sizeof(struct dwc2_dma_desc),
398 &hsotg->setup_desc_dma[0],
400 if (!hsotg->setup_desc[0])
403 hsotg->setup_desc[1] =
404 dmam_alloc_coherent(hsotg->dev,
405 sizeof(struct dwc2_dma_desc),
406 &hsotg->setup_desc_dma[1],
408 if (!hsotg->setup_desc[1])
411 hsotg->ctrl_in_desc =
412 dmam_alloc_coherent(hsotg->dev,
413 sizeof(struct dwc2_dma_desc),
414 &hsotg->ctrl_in_desc_dma,
416 if (!hsotg->ctrl_in_desc)
419 hsotg->ctrl_out_desc =
420 dmam_alloc_coherent(hsotg->dev,
421 sizeof(struct dwc2_dma_desc),
422 &hsotg->ctrl_out_desc_dma,
424 if (!hsotg->ctrl_out_desc)
434 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
435 * @hsotg: The controller state.
436 * @hs_ep: The endpoint we're going to write for.
437 * @hs_req: The request to write data for.
439 * This is called when the TxFIFO has some space in it to hold a new
440 * transmission and we have something to give it. The actual setup of
441 * the data size is done elsewhere, so all we have to do is to actually
444 * The return value is zero if there is more space (or nothing was done)
445 * otherwise -ENOSPC is returned if the FIFO space was used up.
447 * This routine is only needed for PIO
449 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
450 struct dwc2_hsotg_ep *hs_ep,
451 struct dwc2_hsotg_req *hs_req)
453 bool periodic = is_ep_periodic(hs_ep);
454 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
455 int buf_pos = hs_req->req.actual;
456 int to_write = hs_ep->size_loaded;
462 to_write -= (buf_pos - hs_ep->last_load);
464 /* if there's nothing to write, get out early */
468 if (periodic && !hsotg->dedicated_fifos) {
469 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
474 * work out how much data was loaded so we can calculate
475 * how much data is left in the fifo.
478 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
481 * if shared fifo, we cannot write anything until the
482 * previous data has been completely sent.
484 if (hs_ep->fifo_load != 0) {
485 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
489 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
491 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
493 /* how much of the data has moved */
494 size_done = hs_ep->size_loaded - size_left;
496 /* how much data is left in the fifo */
497 can_write = hs_ep->fifo_load - size_done;
498 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
499 __func__, can_write);
501 can_write = hs_ep->fifo_size - can_write;
502 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
503 __func__, can_write);
505 if (can_write <= 0) {
506 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
509 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
510 can_write = dwc2_readl(hsotg->regs +
511 DTXFSTS(hs_ep->fifo_index));
516 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
518 "%s: no queue slots available (0x%08x)\n",
521 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
525 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
526 can_write *= 4; /* fifo size is in 32bit quantities. */
529 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
531 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
532 __func__, gnptxsts, can_write, to_write, max_transfer);
535 * limit to 512 bytes of data, it seems at least on the non-periodic
536 * FIFO, requests of >512 cause the endpoint to get stuck with a
537 * fragment of the end of the transfer in it.
539 if (can_write > 512 && !periodic)
543 * limit the write to one max-packet size worth of data, but allow
544 * the transfer to return that it did not run out of fifo space
547 if (to_write > max_transfer) {
548 to_write = max_transfer;
550 /* it's needed only when we do not use dedicated fifos */
551 if (!hsotg->dedicated_fifos)
552 dwc2_hsotg_en_gsint(hsotg,
553 periodic ? GINTSTS_PTXFEMP :
557 /* see if we can write data */
559 if (to_write > can_write) {
560 to_write = can_write;
561 pkt_round = to_write % max_transfer;
564 * Round the write down to an
565 * exact number of packets.
567 * Note, we do not currently check to see if we can ever
568 * write a full packet or not to the FIFO.
572 to_write -= pkt_round;
575 * enable correct FIFO interrupt to alert us when there
579 /* it's needed only when we do not use dedicated fifos */
580 if (!hsotg->dedicated_fifos)
581 dwc2_hsotg_en_gsint(hsotg,
582 periodic ? GINTSTS_PTXFEMP :
586 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
587 to_write, hs_req->req.length, can_write, buf_pos);
592 hs_req->req.actual = buf_pos + to_write;
593 hs_ep->total_data += to_write;
596 hs_ep->fifo_load += to_write;
598 to_write = DIV_ROUND_UP(to_write, 4);
599 data = hs_req->req.buf + buf_pos;
601 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
603 return (to_write >= can_write) ? -ENOSPC : 0;
607 * get_ep_limit - get the maximum data legnth for this endpoint
608 * @hs_ep: The endpoint
610 * Return the maximum data that can be queued in one go on a given endpoint
611 * so that transfers that are too long can be split.
613 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
615 int index = hs_ep->index;
616 unsigned int maxsize;
620 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
621 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
625 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
630 /* we made the constant loading easier above by using +1 */
635 * constrain by packet count if maxpkts*pktsize is greater
636 * than the length register size.
639 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
640 maxsize = maxpkt * hs_ep->ep.maxpacket;
646 * dwc2_hsotg_read_frameno - read current frame number
647 * @hsotg: The device instance
649 * Return the current frame number
651 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
655 dsts = dwc2_readl(hsotg->regs + DSTS);
656 dsts &= DSTS_SOFFN_MASK;
657 dsts >>= DSTS_SOFFN_SHIFT;
663 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
664 * DMA descriptor chain prepared for specific endpoint
665 * @hs_ep: The endpoint
667 * Return the maximum data that can be queued in one go on a given endpoint
668 * depending on its descriptor chain capacity so that transfers that
669 * are too long can be split.
671 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
673 int is_isoc = hs_ep->isochronous;
674 unsigned int maxsize;
677 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
678 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
680 maxsize = DEV_DMA_NBYTES_LIMIT;
682 /* Above size of one descriptor was chosen, multiple it */
683 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
689 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
690 * @hs_ep: The endpoint
691 * @mask: RX/TX bytes mask to be defined
693 * Returns maximum data payload for one descriptor after analyzing endpoint
695 * DMA descriptor transfer bytes limit depends on EP type:
697 * Isochronous - descriptor rx/tx bytes bitfield limit,
698 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
699 * have concatenations from various descriptors within one packet.
701 * Selects corresponding mask for RX/TX bytes as well.
703 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
705 u32 mps = hs_ep->ep.maxpacket;
706 int dir_in = hs_ep->dir_in;
709 if (!hs_ep->index && !dir_in) {
711 *mask = DEV_DMA_NBYTES_MASK;
712 } else if (hs_ep->isochronous) {
714 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
715 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
717 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
718 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
721 desc_size = DEV_DMA_NBYTES_LIMIT;
722 *mask = DEV_DMA_NBYTES_MASK;
724 /* Round down desc_size to be mps multiple */
725 desc_size -= desc_size % mps;
732 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
733 * @hs_ep: The endpoint
734 * @dma_buff: DMA address to use
735 * @len: Length of the transfer
737 * This function will iterate over descriptor chain and fill its entries
738 * with corresponding information based on transfer data.
740 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
744 struct dwc2_hsotg *hsotg = hs_ep->parent;
745 int dir_in = hs_ep->dir_in;
746 struct dwc2_dma_desc *desc = hs_ep->desc_list;
747 u32 mps = hs_ep->ep.maxpacket;
753 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
755 hs_ep->desc_count = (len / maxsize) +
756 ((len % maxsize) ? 1 : 0);
758 hs_ep->desc_count = 1;
760 for (i = 0; i < hs_ep->desc_count; ++i) {
762 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
763 << DEV_DMA_BUFF_STS_SHIFT);
766 if (!hs_ep->index && !dir_in)
767 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
769 desc->status |= (maxsize <<
770 DEV_DMA_NBYTES_SHIFT & mask);
771 desc->buf = dma_buff + offset;
776 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
779 desc->status |= (len % mps) ? DEV_DMA_SHORT :
780 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
782 dev_err(hsotg->dev, "wrong len %d\n", len);
785 len << DEV_DMA_NBYTES_SHIFT & mask;
786 desc->buf = dma_buff + offset;
789 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
790 desc->status |= (DEV_DMA_BUFF_STS_HREADY
791 << DEV_DMA_BUFF_STS_SHIFT);
797 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
798 * @hs_ep: The isochronous endpoint.
799 * @dma_buff: usb requests dma buffer.
800 * @len: usb request transfer length.
802 * Fills next free descriptor with the data of the arrived usb request,
803 * frame info, sets Last and IOC bits increments next_desc. If filled
804 * descriptor is not the first one, removes L bit from the previous descriptor
807 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
808 dma_addr_t dma_buff, unsigned int len)
810 struct dwc2_dma_desc *desc;
811 struct dwc2_hsotg *hsotg = hs_ep->parent;
817 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
819 index = hs_ep->next_desc;
820 desc = &hs_ep->desc_list[index];
822 /* Check if descriptor chain full */
823 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
824 DEV_DMA_BUFF_STS_HREADY) {
825 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
829 /* Clear L bit of previous desc if more than one entries in the chain */
830 if (hs_ep->next_desc)
831 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
833 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
834 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
837 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
839 desc->buf = dma_buff;
840 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
841 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
845 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
848 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
849 DEV_DMA_ISOC_PID_MASK) |
850 ((len % hs_ep->ep.maxpacket) ?
852 ((hs_ep->target_frame <<
853 DEV_DMA_ISOC_FRNUM_SHIFT) &
854 DEV_DMA_ISOC_FRNUM_MASK);
857 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
858 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
860 /* Increment frame number by interval for IN */
862 dwc2_gadget_incr_frame_num(hs_ep);
864 /* Update index of last configured entry in the chain */
866 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC)
867 hs_ep->next_desc = 0;
873 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
874 * @hs_ep: The isochronous endpoint.
876 * Prepare descriptor chain for isochronous endpoints. Afterwards
877 * write DMA address to HW and enable the endpoint.
879 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
881 struct dwc2_hsotg *hsotg = hs_ep->parent;
882 struct dwc2_hsotg_req *hs_req, *treq;
883 int index = hs_ep->index;
889 struct dwc2_dma_desc *desc;
891 if (list_empty(&hs_ep->queue)) {
892 hs_ep->target_frame = TARGET_FRAME_INITIAL;
893 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
897 /* Initialize descriptor chain by Host Busy status */
898 for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) {
899 desc = &hs_ep->desc_list[i];
901 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
902 << DEV_DMA_BUFF_STS_SHIFT);
905 hs_ep->next_desc = 0;
906 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
907 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
913 hs_ep->compl_desc = 0;
914 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
915 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
917 /* write descriptor chain address to control register */
918 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
920 ctrl = dwc2_readl(hsotg->regs + depctl);
921 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
922 dwc2_writel(ctrl, hsotg->regs + depctl);
926 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
927 * @hsotg: The controller state.
928 * @hs_ep: The endpoint to process a request for
929 * @hs_req: The request to start.
930 * @continuing: True if we are doing more for the current request.
932 * Start the given request running by setting the endpoint registers
933 * appropriately, and writing any data to the FIFOs.
935 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
936 struct dwc2_hsotg_ep *hs_ep,
937 struct dwc2_hsotg_req *hs_req,
940 struct usb_request *ureq = &hs_req->req;
941 int index = hs_ep->index;
942 int dir_in = hs_ep->dir_in;
948 unsigned int packets;
950 unsigned int dma_reg;
953 if (hs_ep->req && !continuing) {
954 dev_err(hsotg->dev, "%s: active request\n", __func__);
957 } else if (hs_ep->req != hs_req && continuing) {
959 "%s: continue different req\n", __func__);
965 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
966 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
967 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
969 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
970 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
971 hs_ep->dir_in ? "in" : "out");
973 /* If endpoint is stalled, we will restart request later */
974 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
976 if (index && ctrl & DXEPCTL_STALL) {
977 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
981 length = ureq->length - ureq->actual;
982 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
983 ureq->length, ureq->actual);
985 if (!using_desc_dma(hsotg))
986 maxreq = get_ep_limit(hs_ep);
988 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
990 if (length > maxreq) {
991 int round = maxreq % hs_ep->ep.maxpacket;
993 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
994 __func__, length, maxreq, round);
996 /* round down to multiple of packets */
1004 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1006 packets = 1; /* send one packet if length is zero. */
1008 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1009 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1013 if (dir_in && index != 0)
1014 if (hs_ep->isochronous)
1015 epsize = DXEPTSIZ_MC(packets);
1017 epsize = DXEPTSIZ_MC(1);
1022 * zero length packet should be programmed on its own and should not
1023 * be counted in DIEPTSIZ.PktCnt with other packets.
1025 if (dir_in && ureq->zero && !continuing) {
1026 /* Test if zlp is actually required. */
1027 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1028 !(ureq->length % hs_ep->ep.maxpacket))
1029 hs_ep->send_zlp = 1;
1032 epsize |= DXEPTSIZ_PKTCNT(packets);
1033 epsize |= DXEPTSIZ_XFERSIZE(length);
1035 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1036 __func__, packets, length, ureq->length, epsize, epsize_reg);
1038 /* store the request as the current one we're doing */
1039 hs_ep->req = hs_req;
1041 if (using_desc_dma(hsotg)) {
1043 u32 mps = hs_ep->ep.maxpacket;
1045 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1049 else if (length % mps)
1050 length += (mps - (length % mps));
1054 * If more data to send, adjust DMA for EP0 out data stage.
1055 * ureq->dma stays unchanged, hence increment it by already
1056 * passed passed data count before starting new transaction.
1058 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1060 offset = ureq->actual;
1062 /* Fill DDMA chain entries */
1063 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1066 /* write descriptor chain address to control register */
1067 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1069 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1070 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1072 /* write size / packets */
1073 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1075 if (using_dma(hsotg) && !continuing && (length != 0)) {
1077 * write DMA address to control register, buffer
1078 * already synced by dwc2_hsotg_ep_queue().
1081 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1083 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1084 __func__, &ureq->dma, dma_reg);
1088 if (hs_ep->isochronous && hs_ep->interval == 1) {
1089 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1090 dwc2_gadget_incr_frame_num(hs_ep);
1092 if (hs_ep->target_frame & 0x1)
1093 ctrl |= DXEPCTL_SETODDFR;
1095 ctrl |= DXEPCTL_SETEVENFR;
1098 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1100 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1102 /* For Setup request do not clear NAK */
1103 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1104 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1106 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1107 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1110 * set these, it seems that DMA support increments past the end
1111 * of the packet buffer so we need to calculate the length from
1114 hs_ep->size_loaded = length;
1115 hs_ep->last_load = ureq->actual;
1117 if (dir_in && !using_dma(hsotg)) {
1118 /* set these anyway, we may need them for non-periodic in */
1119 hs_ep->fifo_load = 0;
1121 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1125 * Note, trying to clear the NAK here causes problems with transmit
1126 * on the S3C6400 ending up with the TXFIFO becoming full.
1129 /* check ep is enabled */
1130 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1132 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1133 index, dwc2_readl(hsotg->regs + epctrl_reg));
1135 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1136 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1138 /* enable ep interrupts */
1139 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1143 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1144 * @hsotg: The device state.
1145 * @hs_ep: The endpoint the request is on.
1146 * @req: The request being processed.
1148 * We've been asked to queue a request, so ensure that the memory buffer
1149 * is correctly setup for DMA. If we've been passed an extant DMA address
1150 * then ensure the buffer has been synced to memory. If our buffer has no
1151 * DMA memory, then we map the memory and mark our request to allow us to
1152 * cleanup on completion.
1154 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1155 struct dwc2_hsotg_ep *hs_ep,
1156 struct usb_request *req)
1160 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1167 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1168 __func__, req->buf, req->length);
1173 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1174 struct dwc2_hsotg_ep *hs_ep,
1175 struct dwc2_hsotg_req *hs_req)
1177 void *req_buf = hs_req->req.buf;
1179 /* If dma is not being used or buffer is aligned */
1180 if (!using_dma(hsotg) || !((long)req_buf & 3))
1183 WARN_ON(hs_req->saved_req_buf);
1185 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1186 hs_ep->ep.name, req_buf, hs_req->req.length);
1188 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1189 if (!hs_req->req.buf) {
1190 hs_req->req.buf = req_buf;
1192 "%s: unable to allocate memory for bounce buffer\n",
1197 /* Save actual buffer */
1198 hs_req->saved_req_buf = req_buf;
1201 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1206 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1207 struct dwc2_hsotg_ep *hs_ep,
1208 struct dwc2_hsotg_req *hs_req)
1210 /* If dma is not being used or buffer was aligned */
1211 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1214 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1215 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1217 /* Copy data from bounce buffer on successful out transfer */
1218 if (!hs_ep->dir_in && !hs_req->req.status)
1219 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1220 hs_req->req.actual);
1222 /* Free bounce buffer */
1223 kfree(hs_req->req.buf);
1225 hs_req->req.buf = hs_req->saved_req_buf;
1226 hs_req->saved_req_buf = NULL;
1230 * dwc2_gadget_target_frame_elapsed - Checks target frame
1231 * @hs_ep: The driver endpoint to check
1233 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1234 * corresponding transfer.
1236 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1238 struct dwc2_hsotg *hsotg = hs_ep->parent;
1239 u32 target_frame = hs_ep->target_frame;
1240 u32 current_frame = hsotg->frame_number;
1241 bool frame_overrun = hs_ep->frame_overrun;
1243 if (!frame_overrun && current_frame >= target_frame)
1246 if (frame_overrun && current_frame >= target_frame &&
1247 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1254 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1255 * @hsotg: The driver state
1256 * @hs_ep: the ep descriptor chain is for
1258 * Called to update EP0 structure's pointers depend on stage of
1261 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1262 struct dwc2_hsotg_ep *hs_ep)
1264 switch (hsotg->ep0_state) {
1265 case DWC2_EP0_SETUP:
1266 case DWC2_EP0_STATUS_OUT:
1267 hs_ep->desc_list = hsotg->setup_desc[0];
1268 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1270 case DWC2_EP0_DATA_IN:
1271 case DWC2_EP0_STATUS_IN:
1272 hs_ep->desc_list = hsotg->ctrl_in_desc;
1273 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1275 case DWC2_EP0_DATA_OUT:
1276 hs_ep->desc_list = hsotg->ctrl_out_desc;
1277 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1280 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1288 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1291 struct dwc2_hsotg_req *hs_req = our_req(req);
1292 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1293 struct dwc2_hsotg *hs = hs_ep->parent;
1300 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1301 ep->name, req, req->length, req->buf, req->no_interrupt,
1302 req->zero, req->short_not_ok);
1304 /* Prevent new request submission when controller is suspended */
1305 if (hs->lx_state != DWC2_L0) {
1306 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1311 /* initialise status of the request */
1312 INIT_LIST_HEAD(&hs_req->queue);
1314 req->status = -EINPROGRESS;
1316 /* In DDMA mode for ISOC's don't queue request if length greater
1317 * than descriptor limits.
1319 if (using_desc_dma(hs) && hs_ep->isochronous) {
1320 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1321 if (hs_ep->dir_in && req->length > maxsize) {
1322 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1323 req->length, maxsize);
1327 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1328 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1329 req->length, hs_ep->ep.maxpacket);
1334 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1338 /* if we're using DMA, sync the buffers as necessary */
1339 if (using_dma(hs)) {
1340 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1344 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1345 if (using_desc_dma(hs) && !hs_ep->index) {
1346 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1351 first = list_empty(&hs_ep->queue);
1352 list_add_tail(&hs_req->queue, &hs_ep->queue);
1355 * Handle DDMA isochronous transfers separately - just add new entry
1356 * to the descriptor chain.
1357 * Transfer will be started once SW gets either one of NAK or
1358 * OutTknEpDis interrupts.
1360 if (using_desc_dma(hs) && hs_ep->isochronous) {
1361 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1362 dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1363 hs_req->req.length);
1369 if (!hs_ep->isochronous) {
1370 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1374 /* Update current frame number value. */
1375 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1376 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1377 dwc2_gadget_incr_frame_num(hs_ep);
1378 /* Update current frame number value once more as it
1381 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1384 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1385 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1390 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1393 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1394 struct dwc2_hsotg *hs = hs_ep->parent;
1395 unsigned long flags = 0;
1398 spin_lock_irqsave(&hs->lock, flags);
1399 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1400 spin_unlock_irqrestore(&hs->lock, flags);
1405 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1406 struct usb_request *req)
1408 struct dwc2_hsotg_req *hs_req = our_req(req);
1414 * dwc2_hsotg_complete_oursetup - setup completion callback
1415 * @ep: The endpoint the request was on.
1416 * @req: The request completed.
1418 * Called on completion of any requests the driver itself
1419 * submitted that need cleaning up.
1421 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1422 struct usb_request *req)
1424 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1425 struct dwc2_hsotg *hsotg = hs_ep->parent;
1427 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1429 dwc2_hsotg_ep_free_request(ep, req);
1433 * ep_from_windex - convert control wIndex value to endpoint
1434 * @hsotg: The driver state.
1435 * @windex: The control request wIndex field (in host order).
1437 * Convert the given wIndex into a pointer to an driver endpoint
1438 * structure, or return NULL if it is not a valid endpoint.
1440 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1443 struct dwc2_hsotg_ep *ep;
1444 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1445 int idx = windex & 0x7F;
1447 if (windex >= 0x100)
1450 if (idx > hsotg->num_of_eps)
1453 ep = index_to_ep(hsotg, idx, dir);
1455 if (idx && ep->dir_in != dir)
1462 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1463 * @hsotg: The driver state.
1464 * @testmode: requested usb test mode
1465 * Enable usb Test Mode requested by the Host.
1467 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1469 int dctl = dwc2_readl(hsotg->regs + DCTL);
1471 dctl &= ~DCTL_TSTCTL_MASK;
1478 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1483 dwc2_writel(dctl, hsotg->regs + DCTL);
1488 * dwc2_hsotg_send_reply - send reply to control request
1489 * @hsotg: The device state
1491 * @buff: Buffer for request
1492 * @length: Length of reply.
1494 * Create a request and queue it on the given endpoint. This is useful as
1495 * an internal method of sending replies to certain control requests, etc.
1497 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1498 struct dwc2_hsotg_ep *ep,
1502 struct usb_request *req;
1505 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1507 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1508 hsotg->ep0_reply = req;
1510 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1514 req->buf = hsotg->ep0_buff;
1515 req->length = length;
1517 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1521 req->complete = dwc2_hsotg_complete_oursetup;
1524 memcpy(req->buf, buff, length);
1526 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1528 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1536 * dwc2_hsotg_process_req_status - process request GET_STATUS
1537 * @hsotg: The device state
1538 * @ctrl: USB control request
1540 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1541 struct usb_ctrlrequest *ctrl)
1543 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1544 struct dwc2_hsotg_ep *ep;
1548 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1551 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1555 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1556 case USB_RECIP_DEVICE:
1558 * bit 0 => self powered
1559 * bit 1 => remote wakeup
1561 reply = cpu_to_le16(0);
1564 case USB_RECIP_INTERFACE:
1565 /* currently, the data result should be zero */
1566 reply = cpu_to_le16(0);
1569 case USB_RECIP_ENDPOINT:
1570 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1574 reply = cpu_to_le16(ep->halted ? 1 : 0);
1581 if (le16_to_cpu(ctrl->wLength) != 2)
1584 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1586 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1593 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1596 * get_ep_head - return the first request on the endpoint
1597 * @hs_ep: The controller endpoint to get
1599 * Get the first request on the endpoint.
1601 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1603 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1608 * dwc2_gadget_start_next_request - Starts next request from ep queue
1609 * @hs_ep: Endpoint structure
1611 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1612 * in its handler. Hence we need to unmask it here to be able to do
1613 * resynchronization.
1615 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1618 struct dwc2_hsotg *hsotg = hs_ep->parent;
1619 int dir_in = hs_ep->dir_in;
1620 struct dwc2_hsotg_req *hs_req;
1621 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1623 if (!list_empty(&hs_ep->queue)) {
1624 hs_req = get_ep_head(hs_ep);
1625 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1628 if (!hs_ep->isochronous)
1632 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1635 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1637 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1638 mask |= DOEPMSK_OUTTKNEPDISMSK;
1639 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1644 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1645 * @hsotg: The device state
1646 * @ctrl: USB control request
1648 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1649 struct usb_ctrlrequest *ctrl)
1651 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1652 struct dwc2_hsotg_req *hs_req;
1653 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1654 struct dwc2_hsotg_ep *ep;
1661 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1662 __func__, set ? "SET" : "CLEAR");
1664 wValue = le16_to_cpu(ctrl->wValue);
1665 wIndex = le16_to_cpu(ctrl->wIndex);
1666 recip = ctrl->bRequestType & USB_RECIP_MASK;
1669 case USB_RECIP_DEVICE:
1671 case USB_DEVICE_REMOTE_WAKEUP:
1672 hsotg->remote_wakeup_allowed = 1;
1675 case USB_DEVICE_TEST_MODE:
1676 if ((wIndex & 0xff) != 0)
1681 hsotg->test_mode = wIndex >> 8;
1682 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1685 "%s: failed to send reply\n", __func__);
1694 case USB_RECIP_ENDPOINT:
1695 ep = ep_from_windex(hsotg, wIndex);
1697 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1703 case USB_ENDPOINT_HALT:
1704 halted = ep->halted;
1706 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1708 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1711 "%s: failed to send reply\n", __func__);
1716 * we have to complete all requests for ep if it was
1717 * halted, and the halt was cleared by CLEAR_FEATURE
1720 if (!set && halted) {
1722 * If we have request in progress,
1728 list_del_init(&hs_req->queue);
1729 if (hs_req->req.complete) {
1730 spin_unlock(&hsotg->lock);
1731 usb_gadget_giveback_request(
1732 &ep->ep, &hs_req->req);
1733 spin_lock(&hsotg->lock);
1737 /* If we have pending request, then start it */
1739 dwc2_gadget_start_next_request(ep);
1754 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1757 * dwc2_hsotg_stall_ep0 - stall ep0
1758 * @hsotg: The device state
1760 * Set stall for ep0 as response for setup request.
1762 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1764 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1768 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1769 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1772 * DxEPCTL_Stall will be cleared by EP once it has
1773 * taken effect, so no need to clear later.
1776 ctrl = dwc2_readl(hsotg->regs + reg);
1777 ctrl |= DXEPCTL_STALL;
1778 ctrl |= DXEPCTL_CNAK;
1779 dwc2_writel(ctrl, hsotg->regs + reg);
1782 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1783 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1786 * complete won't be called, so we enqueue
1787 * setup request here
1789 dwc2_hsotg_enqueue_setup(hsotg);
1793 * dwc2_hsotg_process_control - process a control request
1794 * @hsotg: The device state
1795 * @ctrl: The control request received
1797 * The controller has received the SETUP phase of a control request, and
1798 * needs to work out what to do next (and whether to pass it on to the
1801 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1802 struct usb_ctrlrequest *ctrl)
1804 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1809 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1810 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1811 ctrl->wIndex, ctrl->wLength);
1813 if (ctrl->wLength == 0) {
1815 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1816 } else if (ctrl->bRequestType & USB_DIR_IN) {
1818 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1821 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1824 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1825 switch (ctrl->bRequest) {
1826 case USB_REQ_SET_ADDRESS:
1827 hsotg->connected = 1;
1828 dcfg = dwc2_readl(hsotg->regs + DCFG);
1829 dcfg &= ~DCFG_DEVADDR_MASK;
1830 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1831 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1832 dwc2_writel(dcfg, hsotg->regs + DCFG);
1834 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1836 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1839 case USB_REQ_GET_STATUS:
1840 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1843 case USB_REQ_CLEAR_FEATURE:
1844 case USB_REQ_SET_FEATURE:
1845 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1850 /* as a fallback, try delivering it to the driver to deal with */
1852 if (ret == 0 && hsotg->driver) {
1853 spin_unlock(&hsotg->lock);
1854 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1855 spin_lock(&hsotg->lock);
1857 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1861 * the request is either unhandlable, or is not formatted correctly
1862 * so respond with a STALL for the status stage to indicate failure.
1866 dwc2_hsotg_stall_ep0(hsotg);
1870 * dwc2_hsotg_complete_setup - completion of a setup transfer
1871 * @ep: The endpoint the request was on.
1872 * @req: The request completed.
1874 * Called on completion of any requests the driver itself submitted for
1877 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1878 struct usb_request *req)
1880 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1881 struct dwc2_hsotg *hsotg = hs_ep->parent;
1883 if (req->status < 0) {
1884 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1888 spin_lock(&hsotg->lock);
1889 if (req->actual == 0)
1890 dwc2_hsotg_enqueue_setup(hsotg);
1892 dwc2_hsotg_process_control(hsotg, req->buf);
1893 spin_unlock(&hsotg->lock);
1897 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1898 * @hsotg: The device state.
1900 * Enqueue a request on EP0 if necessary to received any SETUP packets
1901 * received from the host.
1903 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1905 struct usb_request *req = hsotg->ctrl_req;
1906 struct dwc2_hsotg_req *hs_req = our_req(req);
1909 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1913 req->buf = hsotg->ctrl_buff;
1914 req->complete = dwc2_hsotg_complete_setup;
1916 if (!list_empty(&hs_req->queue)) {
1917 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1921 hsotg->eps_out[0]->dir_in = 0;
1922 hsotg->eps_out[0]->send_zlp = 0;
1923 hsotg->ep0_state = DWC2_EP0_SETUP;
1925 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1927 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1929 * Don't think there's much we can do other than watch the
1935 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1936 struct dwc2_hsotg_ep *hs_ep)
1939 u8 index = hs_ep->index;
1940 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1941 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1944 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1947 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1949 if (using_desc_dma(hsotg)) {
1950 /* Not specific buffer needed for ep0 ZLP */
1951 dma_addr_t dma = hs_ep->desc_list_dma;
1954 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1956 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1958 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1959 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1963 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1964 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1965 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1966 ctrl |= DXEPCTL_USBACTEP;
1967 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1971 * dwc2_hsotg_complete_request - complete a request given to us
1972 * @hsotg: The device state.
1973 * @hs_ep: The endpoint the request was on.
1974 * @hs_req: The request to complete.
1975 * @result: The result code (0 => Ok, otherwise errno)
1977 * The given request has finished, so call the necessary completion
1978 * if it has one and then look to see if we can start a new request
1981 * Note, expects the ep to already be locked as appropriate.
1983 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1984 struct dwc2_hsotg_ep *hs_ep,
1985 struct dwc2_hsotg_req *hs_req,
1989 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1993 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1994 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1997 * only replace the status if we've not already set an error
1998 * from a previous transaction
2001 if (hs_req->req.status == -EINPROGRESS)
2002 hs_req->req.status = result;
2004 if (using_dma(hsotg))
2005 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2007 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2010 list_del_init(&hs_req->queue);
2013 * call the complete request with the locks off, just in case the
2014 * request tries to queue more work for this endpoint.
2017 if (hs_req->req.complete) {
2018 spin_unlock(&hsotg->lock);
2019 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2020 spin_lock(&hsotg->lock);
2023 /* In DDMA don't need to proceed to starting of next ISOC request */
2024 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2028 * Look to see if there is anything else to do. Note, the completion
2029 * of the previous request may have caused a new request to be started
2030 * so be careful when doing this.
2033 if (!hs_ep->req && result >= 0)
2034 dwc2_gadget_start_next_request(hs_ep);
2038 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2039 * @hs_ep: The endpoint the request was on.
2041 * Get first request from the ep queue, determine descriptor on which complete
2042 * happened. SW discovers which descriptor currently in use by HW, adjusts
2043 * dma_address and calculates index of completed descriptor based on the value
2044 * of DEPDMA register. Update actual length of request, giveback to gadget.
2046 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2048 struct dwc2_hsotg *hsotg = hs_ep->parent;
2049 struct dwc2_hsotg_req *hs_req;
2050 struct usb_request *ureq;
2054 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2056 /* Process only descriptors with buffer status set to DMA done */
2057 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2058 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2060 hs_req = get_ep_head(hs_ep);
2062 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2065 ureq = &hs_req->req;
2067 /* Check completion status */
2068 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2070 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2071 DEV_DMA_ISOC_RX_NBYTES_MASK;
2072 ureq->actual = ureq->length - ((desc_sts & mask) >>
2073 DEV_DMA_ISOC_NBYTES_SHIFT);
2075 /* Adjust actual len for ISOC Out if len is
2078 if (!hs_ep->dir_in && ureq->length & 0x3)
2079 ureq->actual += 4 - (ureq->length & 0x3);
2082 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2084 hs_ep->compl_desc++;
2085 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1))
2086 hs_ep->compl_desc = 0;
2087 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2092 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2093 * @hs_ep: The isochronous endpoint.
2095 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2096 * interrupt. Reset target frame and next_desc to allow to start
2097 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2098 * interrupt for OUT direction.
2100 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2102 struct dwc2_hsotg *hsotg = hs_ep->parent;
2105 dwc2_flush_rx_fifo(hsotg);
2106 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2108 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2109 hs_ep->next_desc = 0;
2110 hs_ep->compl_desc = 0;
2114 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2115 * @hsotg: The device state.
2116 * @ep_idx: The endpoint index for the data
2117 * @size: The size of data in the fifo, in bytes
2119 * The FIFO status shows there is data to read from the FIFO for a given
2120 * endpoint, so sort out whether we need to read the data into a request
2121 * that has been made for that endpoint.
2123 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2125 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2126 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2127 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2133 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2137 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2138 __func__, size, ep_idx, epctl);
2140 /* dump the data from the FIFO, we've nothing we can do */
2141 for (ptr = 0; ptr < size; ptr += 4)
2142 (void)dwc2_readl(fifo);
2148 read_ptr = hs_req->req.actual;
2149 max_req = hs_req->req.length - read_ptr;
2151 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2152 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2154 if (to_read > max_req) {
2156 * more data appeared than we where willing
2157 * to deal with in this request.
2160 /* currently we don't deal this */
2164 hs_ep->total_data += to_read;
2165 hs_req->req.actual += to_read;
2166 to_read = DIV_ROUND_UP(to_read, 4);
2169 * note, we might over-write the buffer end by 3 bytes depending on
2170 * alignment of the data.
2172 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2176 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2177 * @hsotg: The device instance
2178 * @dir_in: If IN zlp
2180 * Generate a zero-length IN packet request for terminating a SETUP
2183 * Note, since we don't write any data to the TxFIFO, then it is
2184 * currently believed that we do not need to wait for any space in
2187 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2189 /* eps_out[0] is used in both directions */
2190 hsotg->eps_out[0]->dir_in = dir_in;
2191 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2193 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2196 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2201 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2202 if (ctrl & DXEPCTL_EOFRNUM)
2203 ctrl |= DXEPCTL_SETEVENFR;
2205 ctrl |= DXEPCTL_SETODDFR;
2206 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2210 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2211 * @hs_ep - The endpoint on which transfer went
2213 * Iterate over endpoints descriptor chain and get info on bytes remained
2214 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2216 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2218 struct dwc2_hsotg *hsotg = hs_ep->parent;
2219 unsigned int bytes_rem = 0;
2220 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2227 for (i = 0; i < hs_ep->desc_count; ++i) {
2228 status = desc->status;
2229 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2231 if (status & DEV_DMA_STS_MASK)
2232 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2233 i, status & DEV_DMA_STS_MASK);
2240 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2241 * @hsotg: The device instance
2242 * @epnum: The endpoint received from
2244 * The RXFIFO has delivered an OutDone event, which means that the data
2245 * transfer for an OUT endpoint has been completed, either by a short
2246 * packet or by the finish of a transfer.
2248 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2250 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2251 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2252 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2253 struct usb_request *req = &hs_req->req;
2254 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2258 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2262 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2263 dev_dbg(hsotg->dev, "zlp packet received\n");
2264 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2265 dwc2_hsotg_enqueue_setup(hsotg);
2269 if (using_desc_dma(hsotg))
2270 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2272 if (using_dma(hsotg)) {
2273 unsigned int size_done;
2276 * Calculate the size of the transfer by checking how much
2277 * is left in the endpoint size register and then working it
2278 * out from the amount we loaded for the transfer.
2280 * We need to do this as DMA pointers are always 32bit aligned
2281 * so may overshoot/undershoot the transfer.
2284 size_done = hs_ep->size_loaded - size_left;
2285 size_done += hs_ep->last_load;
2287 req->actual = size_done;
2290 /* if there is more request to do, schedule new transfer */
2291 if (req->actual < req->length && size_left == 0) {
2292 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2296 if (req->actual < req->length && req->short_not_ok) {
2297 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2298 __func__, req->actual, req->length);
2301 * todo - what should we return here? there's no one else
2302 * even bothering to check the status.
2306 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2307 if (!using_desc_dma(hsotg) && epnum == 0 &&
2308 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2309 /* Move to STATUS IN */
2310 dwc2_hsotg_ep0_zlp(hsotg, true);
2315 * Slave mode OUT transfers do not go through XferComplete so
2316 * adjust the ISOC parity here.
2318 if (!using_dma(hsotg)) {
2319 if (hs_ep->isochronous && hs_ep->interval == 1)
2320 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2321 else if (hs_ep->isochronous && hs_ep->interval > 1)
2322 dwc2_gadget_incr_frame_num(hs_ep);
2325 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2329 * dwc2_hsotg_handle_rx - RX FIFO has data
2330 * @hsotg: The device instance
2332 * The IRQ handler has detected that the RX FIFO has some data in it
2333 * that requires processing, so find out what is in there and do the
2336 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2337 * chunks, so if you have x packets received on an endpoint you'll get x
2338 * FIFO events delivered, each with a packet's worth of data in it.
2340 * When using DMA, we should not be processing events from the RXFIFO
2341 * as the actual data should be sent to the memory directly and we turn
2342 * on the completion interrupts to get notifications of transfer completion.
2344 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2346 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2347 u32 epnum, status, size;
2349 WARN_ON(using_dma(hsotg));
2351 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2352 status = grxstsr & GRXSTS_PKTSTS_MASK;
2354 size = grxstsr & GRXSTS_BYTECNT_MASK;
2355 size >>= GRXSTS_BYTECNT_SHIFT;
2357 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2358 __func__, grxstsr, size, epnum);
2360 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2361 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2362 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2365 case GRXSTS_PKTSTS_OUTDONE:
2366 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2367 dwc2_hsotg_read_frameno(hsotg));
2369 if (!using_dma(hsotg))
2370 dwc2_hsotg_handle_outdone(hsotg, epnum);
2373 case GRXSTS_PKTSTS_SETUPDONE:
2375 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2376 dwc2_hsotg_read_frameno(hsotg),
2377 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2379 * Call dwc2_hsotg_handle_outdone here if it was not called from
2380 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2381 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2383 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2384 dwc2_hsotg_handle_outdone(hsotg, epnum);
2387 case GRXSTS_PKTSTS_OUTRX:
2388 dwc2_hsotg_rx_data(hsotg, epnum, size);
2391 case GRXSTS_PKTSTS_SETUPRX:
2393 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2394 dwc2_hsotg_read_frameno(hsotg),
2395 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2397 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2399 dwc2_hsotg_rx_data(hsotg, epnum, size);
2403 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2406 dwc2_hsotg_dump(hsotg);
2412 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2413 * @mps: The maximum packet size in bytes.
2415 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2419 return D0EPCTL_MPS_64;
2421 return D0EPCTL_MPS_32;
2423 return D0EPCTL_MPS_16;
2425 return D0EPCTL_MPS_8;
2428 /* bad max packet size, warn and return invalid result */
2434 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2435 * @hsotg: The driver state.
2436 * @ep: The index number of the endpoint
2437 * @mps: The maximum packet size in bytes
2438 * @mc: The multicount value
2439 * @dir_in: True if direction is in.
2441 * Configure the maximum packet size for the given endpoint, updating
2442 * the hardware control registers to reflect this.
2444 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2445 unsigned int ep, unsigned int mps,
2446 unsigned int mc, unsigned int dir_in)
2448 struct dwc2_hsotg_ep *hs_ep;
2449 void __iomem *regs = hsotg->regs;
2452 hs_ep = index_to_ep(hsotg, ep, dir_in);
2457 u32 mps_bytes = mps;
2459 /* EP0 is a special case */
2460 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2463 hs_ep->ep.maxpacket = mps_bytes;
2471 hs_ep->ep.maxpacket = mps;
2475 reg = dwc2_readl(regs + DIEPCTL(ep));
2476 reg &= ~DXEPCTL_MPS_MASK;
2478 dwc2_writel(reg, regs + DIEPCTL(ep));
2480 reg = dwc2_readl(regs + DOEPCTL(ep));
2481 reg &= ~DXEPCTL_MPS_MASK;
2483 dwc2_writel(reg, regs + DOEPCTL(ep));
2489 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2493 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2494 * @hsotg: The driver state
2495 * @idx: The index for the endpoint (0..15)
2497 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2499 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2500 hsotg->regs + GRSTCTL);
2502 /* wait until the fifo is flushed */
2503 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2504 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2509 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2510 * @hsotg: The driver state
2511 * @hs_ep: The driver endpoint to check.
2513 * Check to see if there is a request that has data to send, and if so
2514 * make an attempt to write data into the FIFO.
2516 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2517 struct dwc2_hsotg_ep *hs_ep)
2519 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2521 if (!hs_ep->dir_in || !hs_req) {
2523 * if request is not enqueued, we disable interrupts
2524 * for endpoints, excepting ep0
2526 if (hs_ep->index != 0)
2527 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2532 if (hs_req->req.actual < hs_req->req.length) {
2533 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2535 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2542 * dwc2_hsotg_complete_in - complete IN transfer
2543 * @hsotg: The device state.
2544 * @hs_ep: The endpoint that has just completed.
2546 * An IN transfer has been completed, update the transfer's state and then
2547 * call the relevant completion routines.
2549 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2550 struct dwc2_hsotg_ep *hs_ep)
2552 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2553 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2554 int size_left, size_done;
2557 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2561 /* Finish ZLP handling for IN EP0 transactions */
2562 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2563 dev_dbg(hsotg->dev, "zlp packet sent\n");
2566 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2567 * changed to IN. Change back to complete OUT transfer request
2571 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2572 if (hsotg->test_mode) {
2575 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2577 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2579 dwc2_hsotg_stall_ep0(hsotg);
2583 dwc2_hsotg_enqueue_setup(hsotg);
2588 * Calculate the size of the transfer by checking how much is left
2589 * in the endpoint size register and then working it out from
2590 * the amount we loaded for the transfer.
2592 * We do this even for DMA, as the transfer may have incremented
2593 * past the end of the buffer (DMA transfers are always 32bit
2596 if (using_desc_dma(hsotg)) {
2597 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2599 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2602 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2605 size_done = hs_ep->size_loaded - size_left;
2606 size_done += hs_ep->last_load;
2608 if (hs_req->req.actual != size_done)
2609 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2610 __func__, hs_req->req.actual, size_done);
2612 hs_req->req.actual = size_done;
2613 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2614 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2616 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2617 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2618 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2622 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2623 if (hs_ep->send_zlp) {
2624 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2625 hs_ep->send_zlp = 0;
2626 /* transfer will be completed on next complete interrupt */
2630 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2631 /* Move to STATUS OUT */
2632 dwc2_hsotg_ep0_zlp(hsotg, false);
2636 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2640 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2641 * @hsotg: The device state.
2642 * @idx: Index of ep.
2643 * @dir_in: Endpoint direction 1-in 0-out.
2645 * Reads for endpoint with given index and direction, by masking
2646 * epint_reg with coresponding mask.
2648 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2649 unsigned int idx, int dir_in)
2651 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2652 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2657 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2658 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2659 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2660 mask |= DXEPINT_SETUP_RCVD;
2662 ints = dwc2_readl(hsotg->regs + epint_reg);
2668 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2669 * @hs_ep: The endpoint on which interrupt is asserted.
2671 * This interrupt indicates that the endpoint has been disabled per the
2672 * application's request.
2674 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2675 * in case of ISOC completes current request.
2677 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2678 * request starts it.
2680 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2682 struct dwc2_hsotg *hsotg = hs_ep->parent;
2683 struct dwc2_hsotg_req *hs_req;
2684 unsigned char idx = hs_ep->index;
2685 int dir_in = hs_ep->dir_in;
2686 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2687 int dctl = dwc2_readl(hsotg->regs + DCTL);
2689 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2692 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2694 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2696 if (hs_ep->isochronous) {
2697 dwc2_hsotg_complete_in(hsotg, hs_ep);
2701 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2702 int dctl = dwc2_readl(hsotg->regs + DCTL);
2704 dctl |= DCTL_CGNPINNAK;
2705 dwc2_writel(dctl, hsotg->regs + DCTL);
2710 if (dctl & DCTL_GOUTNAKSTS) {
2711 dctl |= DCTL_CGOUTNAK;
2712 dwc2_writel(dctl, hsotg->regs + DCTL);
2715 if (!hs_ep->isochronous)
2718 if (list_empty(&hs_ep->queue)) {
2719 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2725 hs_req = get_ep_head(hs_ep);
2727 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2729 dwc2_gadget_incr_frame_num(hs_ep);
2730 /* Update current frame number value. */
2731 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2732 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2734 dwc2_gadget_start_next_request(hs_ep);
2738 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2739 * @ep: The endpoint on which interrupt is asserted.
2741 * This is starting point for ISOC-OUT transfer, synchronization done with
2742 * first out token received from host while corresponding EP is disabled.
2744 * Device does not know initial frame in which out token will come. For this
2745 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2746 * getting this interrupt SW starts calculation for next transfer frame.
2748 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2750 struct dwc2_hsotg *hsotg = ep->parent;
2751 int dir_in = ep->dir_in;
2755 if (dir_in || !ep->isochronous)
2759 * Store frame in which irq was asserted here, as
2760 * it can change while completing request below.
2762 tmp = dwc2_hsotg_read_frameno(hsotg);
2764 if (using_desc_dma(hsotg)) {
2765 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2766 /* Start first ISO Out */
2767 ep->target_frame = tmp;
2768 dwc2_gadget_start_isoc_ddma(ep);
2773 if (ep->interval > 1 &&
2774 ep->target_frame == TARGET_FRAME_INITIAL) {
2778 dsts = dwc2_readl(hsotg->regs + DSTS);
2779 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2780 dwc2_gadget_incr_frame_num(ep);
2782 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2783 if (ep->target_frame & 0x1)
2784 ctrl |= DXEPCTL_SETODDFR;
2786 ctrl |= DXEPCTL_SETEVENFR;
2788 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2791 dwc2_gadget_start_next_request(ep);
2792 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2793 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2794 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2798 * dwc2_gadget_handle_nak - handle NAK interrupt
2799 * @hs_ep: The endpoint on which interrupt is asserted.
2801 * This is starting point for ISOC-IN transfer, synchronization done with
2802 * first IN token received from host while corresponding EP is disabled.
2804 * Device does not know when first one token will arrive from host. On first
2805 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2806 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2807 * sent in response to that as there was no data in FIFO. SW is basing on this
2808 * interrupt to obtain frame in which token has come and then based on the
2809 * interval calculates next frame for transfer.
2811 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2813 struct dwc2_hsotg *hsotg = hs_ep->parent;
2814 int dir_in = hs_ep->dir_in;
2817 if (!dir_in || !hs_ep->isochronous)
2820 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2822 tmp = dwc2_hsotg_read_frameno(hsotg);
2823 if (using_desc_dma(hsotg)) {
2824 hs_ep->target_frame = tmp;
2825 dwc2_gadget_incr_frame_num(hs_ep);
2826 dwc2_gadget_start_isoc_ddma(hs_ep);
2830 hs_ep->target_frame = tmp;
2831 if (hs_ep->interval > 1) {
2832 u32 ctrl = dwc2_readl(hsotg->regs +
2833 DIEPCTL(hs_ep->index));
2834 if (hs_ep->target_frame & 0x1)
2835 ctrl |= DXEPCTL_SETODDFR;
2837 ctrl |= DXEPCTL_SETEVENFR;
2839 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2842 dwc2_hsotg_complete_request(hsotg, hs_ep,
2843 get_ep_head(hs_ep), 0);
2846 if (!using_desc_dma(hsotg))
2847 dwc2_gadget_incr_frame_num(hs_ep);
2851 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2852 * @hsotg: The driver state
2853 * @idx: The index for the endpoint (0..15)
2854 * @dir_in: Set if this is an IN endpoint
2856 * Process and clear any interrupt pending for an individual endpoint
2858 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2861 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2862 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2863 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2864 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2868 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2869 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2871 /* Clear endpoint interrupts */
2872 dwc2_writel(ints, hsotg->regs + epint_reg);
2875 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2876 __func__, idx, dir_in ? "in" : "out");
2880 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2881 __func__, idx, dir_in ? "in" : "out", ints);
2883 /* Don't process XferCompl interrupt if it is a setup packet */
2884 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2885 ints &= ~DXEPINT_XFERCOMPL;
2888 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2889 * stage and xfercomplete was generated without SETUP phase done
2890 * interrupt. SW should parse received setup packet only after host's
2891 * exit from setup phase of control transfer.
2893 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2894 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2895 ints &= ~DXEPINT_XFERCOMPL;
2897 if (ints & DXEPINT_XFERCOMPL) {
2899 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2900 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2901 dwc2_readl(hsotg->regs + epsiz_reg));
2903 /* In DDMA handle isochronous requests separately */
2904 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2905 /* XferCompl set along with BNA */
2906 if (!(ints & DXEPINT_BNAINTR))
2907 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2908 } else if (dir_in) {
2910 * We get OutDone from the FIFO, so we only
2911 * need to look at completing IN requests here
2912 * if operating slave mode
2914 if (hs_ep->isochronous && hs_ep->interval > 1)
2915 dwc2_gadget_incr_frame_num(hs_ep);
2917 dwc2_hsotg_complete_in(hsotg, hs_ep);
2918 if (ints & DXEPINT_NAKINTRPT)
2919 ints &= ~DXEPINT_NAKINTRPT;
2921 if (idx == 0 && !hs_ep->req)
2922 dwc2_hsotg_enqueue_setup(hsotg);
2923 } else if (using_dma(hsotg)) {
2925 * We're using DMA, we need to fire an OutDone here
2926 * as we ignore the RXFIFO.
2928 if (hs_ep->isochronous && hs_ep->interval > 1)
2929 dwc2_gadget_incr_frame_num(hs_ep);
2931 dwc2_hsotg_handle_outdone(hsotg, idx);
2935 if (ints & DXEPINT_EPDISBLD)
2936 dwc2_gadget_handle_ep_disabled(hs_ep);
2938 if (ints & DXEPINT_OUTTKNEPDIS)
2939 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2941 if (ints & DXEPINT_NAKINTRPT)
2942 dwc2_gadget_handle_nak(hs_ep);
2944 if (ints & DXEPINT_AHBERR)
2945 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2947 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2948 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2950 if (using_dma(hsotg) && idx == 0) {
2952 * this is the notification we've received a
2953 * setup packet. In non-DMA mode we'd get this
2954 * from the RXFIFO, instead we need to process
2961 dwc2_hsotg_handle_outdone(hsotg, 0);
2965 if (ints & DXEPINT_STSPHSERCVD) {
2966 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2968 /* Safety check EP0 state when STSPHSERCVD asserted */
2969 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2970 /* Move to STATUS IN for DDMA */
2971 if (using_desc_dma(hsotg))
2972 dwc2_hsotg_ep0_zlp(hsotg, true);
2977 if (ints & DXEPINT_BACK2BACKSETUP)
2978 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2980 if (ints & DXEPINT_BNAINTR) {
2981 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2982 if (hs_ep->isochronous)
2983 dwc2_gadget_handle_isoc_bna(hs_ep);
2986 if (dir_in && !hs_ep->isochronous) {
2987 /* not sure if this is important, but we'll clear it anyway */
2988 if (ints & DXEPINT_INTKNTXFEMP) {
2989 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2993 /* this probably means something bad is happening */
2994 if (ints & DXEPINT_INTKNEPMIS) {
2995 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2999 /* FIFO has space or is empty (see GAHBCFG) */
3000 if (hsotg->dedicated_fifos &&
3001 ints & DXEPINT_TXFEMP) {
3002 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3004 if (!using_dma(hsotg))
3005 dwc2_hsotg_trytx(hsotg, hs_ep);
3011 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3012 * @hsotg: The device state.
3014 * Handle updating the device settings after the enumeration phase has
3017 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3019 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
3020 int ep0_mps = 0, ep_mps = 8;
3023 * This should signal the finish of the enumeration phase
3024 * of the USB handshaking, so we should now know what rate
3028 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3031 * note, since we're limited by the size of transfer on EP0, and
3032 * it seems IN transfers must be a even number of packets we do
3033 * not advertise a 64byte MPS on EP0.
3036 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3037 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3038 case DSTS_ENUMSPD_FS:
3039 case DSTS_ENUMSPD_FS48:
3040 hsotg->gadget.speed = USB_SPEED_FULL;
3041 ep0_mps = EP0_MPS_LIMIT;
3045 case DSTS_ENUMSPD_HS:
3046 hsotg->gadget.speed = USB_SPEED_HIGH;
3047 ep0_mps = EP0_MPS_LIMIT;
3051 case DSTS_ENUMSPD_LS:
3052 hsotg->gadget.speed = USB_SPEED_LOW;
3056 * note, we don't actually support LS in this driver at the
3057 * moment, and the documentation seems to imply that it isn't
3058 * supported by the PHYs on some of the devices.
3062 dev_info(hsotg->dev, "new device is %s\n",
3063 usb_speed_string(hsotg->gadget.speed));
3066 * we should now know the maximum packet size for an
3067 * endpoint, so set the endpoints to a default value.
3072 /* Initialize ep0 for both in and out directions */
3073 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3074 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3075 for (i = 1; i < hsotg->num_of_eps; i++) {
3076 if (hsotg->eps_in[i])
3077 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3079 if (hsotg->eps_out[i])
3080 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3085 /* ensure after enumeration our EP0 is active */
3087 dwc2_hsotg_enqueue_setup(hsotg);
3089 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3090 dwc2_readl(hsotg->regs + DIEPCTL0),
3091 dwc2_readl(hsotg->regs + DOEPCTL0));
3095 * kill_all_requests - remove all requests from the endpoint's queue
3096 * @hsotg: The device state.
3097 * @ep: The endpoint the requests may be on.
3098 * @result: The result code to use.
3100 * Go through the requests on the given endpoint and mark them
3101 * completed with the given result code.
3103 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3104 struct dwc2_hsotg_ep *ep,
3107 struct dwc2_hsotg_req *req, *treq;
3112 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3113 dwc2_hsotg_complete_request(hsotg, ep, req,
3116 if (!hsotg->dedicated_fifos)
3118 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3119 if (size < ep->fifo_size)
3120 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3124 * dwc2_hsotg_disconnect - disconnect service
3125 * @hsotg: The device state.
3127 * The device has been disconnected. Remove all current
3128 * transactions and signal the gadget driver that this
3131 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3135 if (!hsotg->connected)
3138 hsotg->connected = 0;
3139 hsotg->test_mode = 0;
3141 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3142 if (hsotg->eps_in[ep])
3143 kill_all_requests(hsotg, hsotg->eps_in[ep],
3145 if (hsotg->eps_out[ep])
3146 kill_all_requests(hsotg, hsotg->eps_out[ep],
3150 call_gadget(hsotg, disconnect);
3151 hsotg->lx_state = DWC2_L3;
3153 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3157 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3158 * @hsotg: The device state:
3159 * @periodic: True if this is a periodic FIFO interrupt
3161 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3163 struct dwc2_hsotg_ep *ep;
3166 /* look through for any more data to transmit */
3167 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3168 ep = index_to_ep(hsotg, epno, 1);
3176 if ((periodic && !ep->periodic) ||
3177 (!periodic && ep->periodic))
3180 ret = dwc2_hsotg_trytx(hsotg, ep);
3186 /* IRQ flags which will trigger a retry around the IRQ loop */
3187 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3192 * dwc2_hsotg_core_init - issue softreset to the core
3193 * @hsotg: The device state
3194 * @is_usb_reset: Usb resetting flag
3196 * Issue a soft reset to the core, and await the core finishing it.
3198 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3206 /* Kill any ep0 requests as controller will be reinitialized */
3207 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3210 if (dwc2_core_reset(hsotg, true))
3214 * we must now enable ep0 ready for host detection and then
3215 * set configuration.
3218 /* keep other bits untouched (so e.g. forced modes are not lost) */
3219 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3220 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3221 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3223 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3224 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3225 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3226 /* FS/LS Dedicated Transceiver Interface */
3227 usbcfg |= GUSBCFG_PHYSEL;
3229 /* set the PLL on, remove the HNP/SRP and set the PHY */
3230 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3231 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3232 (val << GUSBCFG_USBTRDTIM_SHIFT);
3234 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3236 dwc2_hsotg_init_fifo(hsotg);
3239 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3241 dcfg |= DCFG_EPMISCNT(1);
3243 switch (hsotg->params.speed) {
3244 case DWC2_SPEED_PARAM_LOW:
3245 dcfg |= DCFG_DEVSPD_LS;
3247 case DWC2_SPEED_PARAM_FULL:
3248 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3249 dcfg |= DCFG_DEVSPD_FS48;
3251 dcfg |= DCFG_DEVSPD_FS;
3254 dcfg |= DCFG_DEVSPD_HS;
3257 if (hsotg->params.ipg_isoc_en)
3258 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3260 dwc2_writel(dcfg, hsotg->regs + DCFG);
3262 /* Clear any pending OTG interrupts */
3263 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3265 /* Clear any pending interrupts */
3266 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3267 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3268 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3269 GINTSTS_USBRST | GINTSTS_RESETDET |
3270 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3271 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3272 GINTSTS_LPMTRANRCVD;
3274 if (!using_desc_dma(hsotg))
3275 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3277 if (!hsotg->params.external_id_pin_ctl)
3278 intmsk |= GINTSTS_CONIDSTSCHNG;
3280 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3282 if (using_dma(hsotg)) {
3283 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3284 hsotg->params.ahbcfg,
3285 hsotg->regs + GAHBCFG);
3287 /* Set DDMA mode support in the core if needed */
3288 if (using_desc_dma(hsotg))
3289 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3292 dwc2_writel(((hsotg->dedicated_fifos) ?
3293 (GAHBCFG_NP_TXF_EMP_LVL |
3294 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3295 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3299 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3300 * when we have no data to transfer. Otherwise we get being flooded by
3304 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3305 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3306 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3307 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3308 hsotg->regs + DIEPMSK);
3311 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3312 * DMA mode we may need this and StsPhseRcvd.
3314 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3315 DOEPMSK_STSPHSERCVDMSK) : 0) |
3316 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3318 hsotg->regs + DOEPMSK);
3320 /* Enable BNA interrupt for DDMA */
3321 if (using_desc_dma(hsotg)) {
3322 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3323 dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK);
3326 dwc2_writel(0, hsotg->regs + DAINTMSK);
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3329 dwc2_readl(hsotg->regs + DIEPCTL0),
3330 dwc2_readl(hsotg->regs + DOEPCTL0));
3332 /* enable in and out endpoint interrupts */
3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3336 * Enable the RXFIFO when in slave mode, as this is how we collect
3337 * the data. In DMA mode, we get events from the FIFO but also
3338 * things we cannot process, so do not use it.
3340 if (!using_dma(hsotg))
3341 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3343 /* Enable interrupts for EP0 in and out */
3344 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3347 if (!is_usb_reset) {
3348 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3349 udelay(10); /* see openiboot */
3350 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3357 * writing to the EPCTL register..
3360 /* set to read 1 8byte packet */
3361 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3362 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3364 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3365 DXEPCTL_CNAK | DXEPCTL_EPENA |
3367 hsotg->regs + DOEPCTL0);
3369 /* enable, but don't activate EP0in */
3370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3371 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3373 /* clear global NAKs */
3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3376 val |= DCTL_SFTDISCON;
3377 dwc2_set_bit(hsotg->regs + DCTL, val);
3379 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg);
3382 /* must be at-least 3ms to allow bus to see disconnect */
3385 hsotg->lx_state = DWC2_L0;
3387 dwc2_hsotg_enqueue_setup(hsotg);
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg->regs + DIEPCTL0),
3391 dwc2_readl(hsotg->regs + DOEPCTL0));
3394 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3396 /* set the soft-disconnect bit */
3397 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3400 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3402 /* remove the soft-disconnect and let's go */
3403 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
3407 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3408 * @hsotg: The device state:
3410 * This interrupt indicates one of the following conditions occurred while
3411 * transmitting an ISOC transaction.
3412 * - Corrupted IN Token for ISOC EP.
3413 * - Packet not complete in FIFO.
3415 * The following actions will be taken:
3416 * - Determine the EP
3417 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3419 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3421 struct dwc2_hsotg_ep *hs_ep;
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3428 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3430 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx];
3432 /* Proceed only unmasked ISOC EPs */
3433 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3436 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3437 if ((epctrl & DXEPCTL_EPENA) &&
3438 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3445 /* Clear interrupt */
3446 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3450 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3451 * @hsotg: The device state:
3453 * This interrupt indicates one of the following conditions occurred while
3454 * transmitting an ISOC transaction.
3455 * - Corrupted OUT Token for ISOC EP.
3456 * - Packet not complete in FIFO.
3458 * The following actions will be taken:
3459 * - Determine the EP
3460 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3462 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3468 struct dwc2_hsotg_ep *hs_ep;
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3473 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT;
3476 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3477 hs_ep = hsotg->eps_out[idx];
3478 /* Proceed only unmasked ISOC EPs */
3479 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3482 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3483 if ((epctrl & DXEPCTL_EPENA) &&
3484 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3490 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3492 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3498 /* Clear interrupt */
3499 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3503 * dwc2_hsotg_irq - handle device interrupt
3504 * @irq: The IRQ number triggered
3505 * @pw: The pw value when registered the handler.
3507 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3509 struct dwc2_hsotg *hsotg = pw;
3510 int retry_count = 8;
3514 if (!dwc2_is_device_mode(hsotg))
3517 spin_lock(&hsotg->lock);
3519 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3520 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3527 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3530 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3532 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) {
3534 dwc2_exit_partial_power_down(hsotg, true);
3535 hsotg->lx_state = DWC2_L0;
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3540 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3541 u32 connected = hsotg->connected;
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg->regs + GNPTXSTS));
3547 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3549 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg);
3552 /* Reset device address to zero */
3553 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK);
3555 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true);
3559 if (gintsts & GINTSTS_ENUMDONE) {
3560 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3562 dwc2_hsotg_irq_enumdone(hsotg);
3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3566 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3568 u32 daint_out, daint_in;
3572 daint_out = daint >> DAINT_OUTEP_SHIFT;
3573 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3575 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3577 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3578 ep++, daint_out >>= 1) {
3580 dwc2_hsotg_epint(hsotg, ep, 0);
3583 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3584 ep++, daint_in >>= 1) {
3586 dwc2_hsotg_epint(hsotg, ep, 1);
3590 /* check both FIFOs */
3592 if (gintsts & GINTSTS_NPTXFEMP) {
3593 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3596 * Disable the interrupt to stop it happening again
3597 * unless one of these endpoint routines decides that
3598 * it needs re-enabling
3601 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3602 dwc2_hsotg_irq_fifoempty(hsotg, false);
3605 if (gintsts & GINTSTS_PTXFEMP) {
3606 dev_dbg(hsotg->dev, "PTxFEmp\n");
3608 /* See note in GINTSTS_NPTxFEmp */
3610 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3611 dwc2_hsotg_irq_fifoempty(hsotg, true);
3614 if (gintsts & GINTSTS_RXFLVL) {
3616 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3617 * we need to retry dwc2_hsotg_handle_rx if this is still
3621 dwc2_hsotg_handle_rx(hsotg);
3624 if (gintsts & GINTSTS_ERLYSUSP) {
3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3626 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3630 * these next two seem to crop-up occasionally causing the core
3631 * to shutdown the USB transfer, so try clearing them and logging
3635 if (gintsts & GINTSTS_GOUTNAKEFF) {
3640 struct dwc2_hsotg_ep *hs_ep;
3642 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT;
3644 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3651 hs_ep = hsotg->eps_out[idx];
3652 /* Proceed only unmasked ISOC EPs */
3653 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3656 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3658 if (epctrl & DXEPCTL_EPENA) {
3659 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3665 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3668 if (gintsts & GINTSTS_GINNAKEFF) {
3669 dev_info(hsotg->dev, "GINNakEff triggered\n");
3671 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3673 dwc2_hsotg_dump(hsotg);
3676 if (gintsts & GINTSTS_INCOMPL_SOIN)
3677 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3679 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3680 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3683 * if we've had fifo events, we should try and go around the
3684 * loop again to see if there's any point in returning yet.
3687 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3690 spin_unlock(&hsotg->lock);
3695 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3696 struct dwc2_hsotg_ep *hs_ep)
3701 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3702 DOEPCTL(hs_ep->index);
3703 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3704 DOEPINT(hs_ep->index);
3706 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3709 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3711 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100))
3715 dev_warn(hsotg->dev,
3716 "%s: timeout DIEPINT.NAKEFF\n",
3719 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3720 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100))
3723 dev_warn(hsotg->dev,
3724 "%s: timeout GINTSTS.GINNAKEFF\n",
3728 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3729 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3731 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3733 GINTSTS_GOUTNAKEFF, 100))
3734 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3739 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3741 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3743 dev_warn(hsotg->dev,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3746 /* Clear EPDISBLD interrupt */
3747 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3749 if (hs_ep->dir_in) {
3750 unsigned short fifo_index;
3752 if (hsotg->dedicated_fifos || hs_ep->periodic)
3753 fifo_index = hs_ep->fifo_index;
3758 dwc2_flush_tx_fifo(hsotg, fifo_index);
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3762 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3765 /* Remove global NAKs */
3766 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3771 * dwc2_hsotg_ep_enable - enable the given endpoint
3772 * @ep: The USB endpint to configure
3773 * @desc: The USB endpoint descriptor to configure with.
3775 * This is called from the USB gadget code's usb_ep_enable().
3777 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3778 const struct usb_endpoint_descriptor *desc)
3780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3781 struct dwc2_hsotg *hsotg = hs_ep->parent;
3782 unsigned long flags;
3783 unsigned int index = hs_ep->index;
3789 unsigned int dir_in;
3790 unsigned int i, val, size;
3792 unsigned char ep_type;
3795 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3796 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3797 desc->wMaxPacketSize, desc->bInterval);
3799 /* not to be called for EP0 */
3801 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3805 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3806 if (dir_in != hs_ep->dir_in) {
3807 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3811 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
3812 mps = usb_endpoint_maxp(desc);
3813 mc = usb_endpoint_maxp_mult(desc);
3815 /* ISOC IN in DDMA supported bInterval up to 10 */
3816 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3817 dir_in && desc->bInterval > 10) {
3819 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
3823 /* High bandwidth ISOC OUT in DDMA not supported */
3824 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
3825 !dir_in && mc > 1) {
3827 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
3831 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3833 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3834 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3836 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3837 __func__, epctrl, epctrl_reg);
3839 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3840 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3841 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3842 MAX_DMA_DESC_NUM_GENERIC *
3843 sizeof(struct dwc2_dma_desc),
3844 &hs_ep->desc_list_dma, GFP_ATOMIC);
3845 if (!hs_ep->desc_list) {
3851 spin_lock_irqsave(&hsotg->lock, flags);
3853 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3854 epctrl |= DXEPCTL_MPS(mps);
3857 * mark the endpoint as active, otherwise the core may ignore
3858 * transactions entirely for this endpoint
3860 epctrl |= DXEPCTL_USBACTEP;
3862 /* update the endpoint state */
3863 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3865 /* default, set to non-periodic */
3866 hs_ep->isochronous = 0;
3867 hs_ep->periodic = 0;
3869 hs_ep->interval = desc->bInterval;
3872 case USB_ENDPOINT_XFER_ISOC:
3873 epctrl |= DXEPCTL_EPTYPE_ISO;
3874 epctrl |= DXEPCTL_SETEVENFR;
3875 hs_ep->isochronous = 1;
3876 hs_ep->interval = 1 << (desc->bInterval - 1);
3877 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3878 hs_ep->next_desc = 0;
3879 hs_ep->compl_desc = 0;
3881 hs_ep->periodic = 1;
3882 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3883 mask |= DIEPMSK_NAKMSK;
3884 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3886 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3887 mask |= DOEPMSK_OUTTKNEPDISMSK;
3888 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3892 case USB_ENDPOINT_XFER_BULK:
3893 epctrl |= DXEPCTL_EPTYPE_BULK;
3896 case USB_ENDPOINT_XFER_INT:
3898 hs_ep->periodic = 1;
3900 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3901 hs_ep->interval = 1 << (desc->bInterval - 1);
3903 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3906 case USB_ENDPOINT_XFER_CONTROL:
3907 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3912 * if the hardware has dedicated fifos, we must give each IN EP
3913 * a unique tx-fifo even if it is non-periodic.
3915 if (dir_in && hsotg->dedicated_fifos) {
3917 u32 fifo_size = UINT_MAX;
3919 size = hs_ep->ep.maxpacket * hs_ep->mc;
3920 for (i = 1; i < hsotg->num_of_eps; ++i) {
3921 if (hsotg->fifo_map & (1 << i))
3923 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3924 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3927 /* Search for smallest acceptable fifo */
3928 if (val < fifo_size) {
3935 "%s: No suitable fifo found\n", __func__);
3939 hsotg->fifo_map |= 1 << fifo_index;
3940 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3941 hs_ep->fifo_index = fifo_index;
3942 hs_ep->fifo_size = fifo_size;
3945 /* for non control endpoints, set PID to D0 */
3946 if (index && !hs_ep->isochronous)
3947 epctrl |= DXEPCTL_SETD0PID;
3949 /* WA for Full speed ISOC IN in DDMA mode.
3950 * By Clear NAK status of EP, core will send ZLP
3951 * to IN token and assert NAK interrupt relying
3952 * on TxFIFO status only
3955 if (hsotg->gadget.speed == USB_SPEED_FULL &&
3956 hs_ep->isochronous && dir_in) {
3957 /* The WA applies only to core versions from 2.72a
3958 * to 4.00a (including both). Also for FS_IOT_1.00a
3961 u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
3963 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
3964 gsnpsid <= DWC2_CORE_REV_4_00a) ||
3965 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
3966 gsnpsid == DWC2_HS_IOT_REV_1_00a)
3967 epctrl |= DXEPCTL_CNAK;
3970 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3973 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3974 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3975 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
3977 /* enable the endpoint interrupt */
3978 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
3981 spin_unlock_irqrestore(&hsotg->lock, flags);
3984 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
3985 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
3986 sizeof(struct dwc2_dma_desc),
3987 hs_ep->desc_list, hs_ep->desc_list_dma);
3988 hs_ep->desc_list = NULL;
3995 * dwc2_hsotg_ep_disable - disable given endpoint
3996 * @ep: The endpoint to disable.
3998 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4000 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4001 struct dwc2_hsotg *hsotg = hs_ep->parent;
4002 int dir_in = hs_ep->dir_in;
4003 int index = hs_ep->index;
4004 unsigned long flags;
4008 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4010 if (ep == &hsotg->eps_out[0]->ep) {
4011 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4015 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4016 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4020 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4022 spin_lock_irqsave(&hsotg->lock, flags);
4024 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
4026 if (ctrl & DXEPCTL_EPENA)
4027 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4029 ctrl &= ~DXEPCTL_EPENA;
4030 ctrl &= ~DXEPCTL_USBACTEP;
4031 ctrl |= DXEPCTL_SNAK;
4033 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4034 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
4036 /* disable endpoint interrupts */
4037 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4039 /* terminate all requests with shutdown */
4040 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4042 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4043 hs_ep->fifo_index = 0;
4044 hs_ep->fifo_size = 0;
4046 spin_unlock_irqrestore(&hsotg->lock, flags);
4051 * on_list - check request is on the given endpoint
4052 * @ep: The endpoint to check.
4053 * @test: The request to test if it is on the endpoint.
4055 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4057 struct dwc2_hsotg_req *req, *treq;
4059 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4068 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4069 * @ep: The endpoint to dequeue.
4070 * @req: The request to be removed from a queue.
4072 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4074 struct dwc2_hsotg_req *hs_req = our_req(req);
4075 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4076 struct dwc2_hsotg *hs = hs_ep->parent;
4077 unsigned long flags;
4079 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4081 spin_lock_irqsave(&hs->lock, flags);
4083 if (!on_list(hs_ep, hs_req)) {
4084 spin_unlock_irqrestore(&hs->lock, flags);
4088 /* Dequeue already started request */
4089 if (req == &hs_ep->req->req)
4090 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4092 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4093 spin_unlock_irqrestore(&hs->lock, flags);
4099 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4100 * @ep: The endpoint to set halt.
4101 * @value: Set or unset the halt.
4102 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4103 * the endpoint is busy processing requests.
4105 * We need to stall the endpoint immediately if request comes from set_feature
4106 * protocol command handler.
4108 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4110 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4111 struct dwc2_hsotg *hs = hs_ep->parent;
4112 int index = hs_ep->index;
4117 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4121 dwc2_hsotg_stall_ep0(hs);
4124 "%s: can't clear halt on ep0\n", __func__);
4128 if (hs_ep->isochronous) {
4129 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4133 if (!now && value && !list_empty(&hs_ep->queue)) {
4134 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4139 if (hs_ep->dir_in) {
4140 epreg = DIEPCTL(index);
4141 epctl = dwc2_readl(hs->regs + epreg);
4144 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4145 if (epctl & DXEPCTL_EPENA)
4146 epctl |= DXEPCTL_EPDIS;
4148 epctl &= ~DXEPCTL_STALL;
4149 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4150 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4151 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4152 epctl |= DXEPCTL_SETD0PID;
4154 dwc2_writel(epctl, hs->regs + epreg);
4156 epreg = DOEPCTL(index);
4157 epctl = dwc2_readl(hs->regs + epreg);
4160 epctl |= DXEPCTL_STALL;
4162 epctl &= ~DXEPCTL_STALL;
4163 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4164 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4165 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4166 epctl |= DXEPCTL_SETD0PID;
4168 dwc2_writel(epctl, hs->regs + epreg);
4171 hs_ep->halted = value;
4177 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4178 * @ep: The endpoint to set halt.
4179 * @value: Set or unset the halt.
4181 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4183 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4184 struct dwc2_hsotg *hs = hs_ep->parent;
4185 unsigned long flags = 0;
4188 spin_lock_irqsave(&hs->lock, flags);
4189 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4190 spin_unlock_irqrestore(&hs->lock, flags);
4195 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4196 .enable = dwc2_hsotg_ep_enable,
4197 .disable = dwc2_hsotg_ep_disable,
4198 .alloc_request = dwc2_hsotg_ep_alloc_request,
4199 .free_request = dwc2_hsotg_ep_free_request,
4200 .queue = dwc2_hsotg_ep_queue_lock,
4201 .dequeue = dwc2_hsotg_ep_dequeue,
4202 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4203 /* note, don't believe we have any call for the fifo routines */
4207 * dwc2_hsotg_init - initialize the usb core
4208 * @hsotg: The driver state
4210 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4214 /* unmask subset of endpoint interrupts */
4216 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4217 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4218 hsotg->regs + DIEPMSK);
4220 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4221 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4222 hsotg->regs + DOEPMSK);
4224 dwc2_writel(0, hsotg->regs + DAINTMSK);
4226 /* Be in disconnected state until gadget is registered */
4227 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
4231 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4232 dwc2_readl(hsotg->regs + GRXFSIZ),
4233 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4235 dwc2_hsotg_init_fifo(hsotg);
4237 /* keep other bits untouched (so e.g. forced modes are not lost) */
4238 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4239 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4240 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4242 /* set the PLL on, remove the HNP/SRP and set the PHY */
4243 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4244 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4245 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4246 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4248 if (using_dma(hsotg))
4249 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4253 * dwc2_hsotg_udc_start - prepare the udc for work
4254 * @gadget: The usb gadget state
4255 * @driver: The usb gadget driver
4257 * Perform initialization to prepare udc device and driver
4260 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4261 struct usb_gadget_driver *driver)
4263 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4264 unsigned long flags;
4268 pr_err("%s: called with no device\n", __func__);
4273 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4277 if (driver->max_speed < USB_SPEED_FULL)
4278 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4280 if (!driver->setup) {
4281 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4285 WARN_ON(hsotg->driver);
4287 driver->driver.bus = NULL;
4288 hsotg->driver = driver;
4289 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4290 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4292 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4293 ret = dwc2_lowlevel_hw_enable(hsotg);
4298 if (!IS_ERR_OR_NULL(hsotg->uphy))
4299 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4301 spin_lock_irqsave(&hsotg->lock, flags);
4302 if (dwc2_hw_is_device(hsotg)) {
4303 dwc2_hsotg_init(hsotg);
4304 dwc2_hsotg_core_init_disconnected(hsotg, false);
4308 spin_unlock_irqrestore(&hsotg->lock, flags);
4310 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4315 hsotg->driver = NULL;
4320 * dwc2_hsotg_udc_stop - stop the udc
4321 * @gadget: The usb gadget state
4323 * Stop udc hw block and stay tunned for future transmissions
4325 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4327 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4328 unsigned long flags = 0;
4334 /* all endpoints should be shutdown */
4335 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4336 if (hsotg->eps_in[ep])
4337 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4338 if (hsotg->eps_out[ep])
4339 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4342 spin_lock_irqsave(&hsotg->lock, flags);
4344 hsotg->driver = NULL;
4345 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4348 spin_unlock_irqrestore(&hsotg->lock, flags);
4350 if (!IS_ERR_OR_NULL(hsotg->uphy))
4351 otg_set_peripheral(hsotg->uphy->otg, NULL);
4353 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4354 dwc2_lowlevel_hw_disable(hsotg);
4360 * dwc2_hsotg_gadget_getframe - read the frame number
4361 * @gadget: The usb gadget state
4363 * Read the {micro} frame number
4365 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4367 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4371 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4372 * @gadget: The usb gadget state
4373 * @is_on: Current state of the USB PHY
4375 * Connect/Disconnect the USB PHY pullup
4377 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4379 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4380 unsigned long flags = 0;
4382 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4385 /* Don't modify pullup state while in host mode */
4386 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4387 hsotg->enabled = is_on;
4391 spin_lock_irqsave(&hsotg->lock, flags);
4394 dwc2_hsotg_core_init_disconnected(hsotg, false);
4395 /* Enable ACG feature in device mode,if supported */
4396 dwc2_enable_acg(hsotg);
4397 dwc2_hsotg_core_connect(hsotg);
4399 dwc2_hsotg_core_disconnect(hsotg);
4400 dwc2_hsotg_disconnect(hsotg);
4404 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4405 spin_unlock_irqrestore(&hsotg->lock, flags);
4410 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4412 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4413 unsigned long flags;
4415 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4416 spin_lock_irqsave(&hsotg->lock, flags);
4419 * If controller is hibernated, it must exit from power_down
4420 * before being initialized / de-initialized
4422 if (hsotg->lx_state == DWC2_L2)
4423 dwc2_exit_partial_power_down(hsotg, false);
4426 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4428 dwc2_hsotg_core_init_disconnected(hsotg, false);
4429 if (hsotg->enabled) {
4430 /* Enable ACG feature in device mode,if supported */
4431 dwc2_enable_acg(hsotg);
4432 dwc2_hsotg_core_connect(hsotg);
4435 dwc2_hsotg_core_disconnect(hsotg);
4436 dwc2_hsotg_disconnect(hsotg);
4439 spin_unlock_irqrestore(&hsotg->lock, flags);
4444 * dwc2_hsotg_vbus_draw - report bMaxPower field
4445 * @gadget: The usb gadget state
4446 * @mA: Amount of current
4448 * Report how much power the device may consume to the phy.
4450 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4452 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4454 if (IS_ERR_OR_NULL(hsotg->uphy))
4456 return usb_phy_set_power(hsotg->uphy, mA);
4459 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4460 .get_frame = dwc2_hsotg_gadget_getframe,
4461 .udc_start = dwc2_hsotg_udc_start,
4462 .udc_stop = dwc2_hsotg_udc_stop,
4463 .pullup = dwc2_hsotg_pullup,
4464 .vbus_session = dwc2_hsotg_vbus_session,
4465 .vbus_draw = dwc2_hsotg_vbus_draw,
4469 * dwc2_hsotg_initep - initialise a single endpoint
4470 * @hsotg: The device state.
4471 * @hs_ep: The endpoint to be initialised.
4472 * @epnum: The endpoint number
4473 * @dir_in: True if direction is in.
4475 * Initialise the given endpoint (as part of the probe and device state
4476 * creation) to give to the gadget driver. Setup the endpoint name, any
4477 * direction information and other state that may be required.
4479 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4480 struct dwc2_hsotg_ep *hs_ep,
4493 hs_ep->dir_in = dir_in;
4494 hs_ep->index = epnum;
4496 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4498 INIT_LIST_HEAD(&hs_ep->queue);
4499 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4501 /* add to the list of endpoints known by the gadget driver */
4503 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4505 hs_ep->parent = hsotg;
4506 hs_ep->ep.name = hs_ep->name;
4508 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4509 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4511 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4512 epnum ? 1024 : EP0_MPS_LIMIT);
4513 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4516 hs_ep->ep.caps.type_control = true;
4518 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4519 hs_ep->ep.caps.type_iso = true;
4520 hs_ep->ep.caps.type_bulk = true;
4522 hs_ep->ep.caps.type_int = true;
4526 hs_ep->ep.caps.dir_in = true;
4528 hs_ep->ep.caps.dir_out = true;
4531 * if we're using dma, we need to set the next-endpoint pointer
4532 * to be something valid.
4535 if (using_dma(hsotg)) {
4536 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4539 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4541 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4546 * dwc2_hsotg_hw_cfg - read HW configuration registers
4547 * @hsotg: Programming view of the DWC_otg controller
4549 * Read the USB core HW configuration registers
4551 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4557 /* check hardware configuration */
4559 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4562 hsotg->num_of_eps++;
4564 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4565 sizeof(struct dwc2_hsotg_ep),
4567 if (!hsotg->eps_in[0])
4569 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4570 hsotg->eps_out[0] = hsotg->eps_in[0];
4572 cfg = hsotg->hw_params.dev_ep_dirs;
4573 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4575 /* Direction in or both */
4576 if (!(ep_type & 2)) {
4577 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4578 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4579 if (!hsotg->eps_in[i])
4582 /* Direction out or both */
4583 if (!(ep_type & 1)) {
4584 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4585 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4586 if (!hsotg->eps_out[i])
4591 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4592 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4594 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4596 hsotg->dedicated_fifos ? "dedicated" : "shared",
4602 * dwc2_hsotg_dump - dump state of the udc
4603 * @hsotg: Programming view of the DWC_otg controller
4606 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4609 struct device *dev = hsotg->dev;
4610 void __iomem *regs = hsotg->regs;
4614 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4615 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4616 dwc2_readl(regs + DIEPMSK));
4618 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4619 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4621 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4622 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4624 /* show periodic fifo settings */
4626 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4627 val = dwc2_readl(regs + DPTXFSIZN(idx));
4628 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4629 val >> FIFOSIZE_DEPTH_SHIFT,
4630 val & FIFOSIZE_STARTADDR_MASK);
4633 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4635 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4636 dwc2_readl(regs + DIEPCTL(idx)),
4637 dwc2_readl(regs + DIEPTSIZ(idx)),
4638 dwc2_readl(regs + DIEPDMA(idx)));
4640 val = dwc2_readl(regs + DOEPCTL(idx));
4642 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4643 idx, dwc2_readl(regs + DOEPCTL(idx)),
4644 dwc2_readl(regs + DOEPTSIZ(idx)),
4645 dwc2_readl(regs + DOEPDMA(idx)));
4648 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4649 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4654 * dwc2_gadget_init - init function for gadget
4655 * @hsotg: Programming view of the DWC_otg controller
4658 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4660 struct device *dev = hsotg->dev;
4664 /* Dump fifo information */
4665 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4666 hsotg->params.g_np_tx_fifo_size);
4667 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4669 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4670 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4671 hsotg->gadget.name = dev_name(dev);
4672 hsotg->remote_wakeup_allowed = 0;
4674 if (hsotg->params.lpm)
4675 hsotg->gadget.lpm_capable = true;
4677 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4678 hsotg->gadget.is_otg = 1;
4679 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4680 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4682 ret = dwc2_hsotg_hw_cfg(hsotg);
4684 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4688 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4689 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4690 if (!hsotg->ctrl_buff)
4693 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4694 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4695 if (!hsotg->ep0_buff)
4698 if (using_desc_dma(hsotg)) {
4699 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4704 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4705 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4707 dev_err(dev, "cannot claim IRQ for gadget\n");
4711 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4713 if (hsotg->num_of_eps == 0) {
4714 dev_err(dev, "wrong number of EPs (zero)\n");
4718 /* setup endpoint information */
4720 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4721 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4723 /* allocate EP0 request */
4725 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4727 if (!hsotg->ctrl_req) {
4728 dev_err(dev, "failed to allocate ctrl req\n");
4732 /* initialise the endpoints now the core has been initialised */
4733 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4734 if (hsotg->eps_in[epnum])
4735 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4737 if (hsotg->eps_out[epnum])
4738 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4742 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
4744 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep,
4748 dwc2_hsotg_dump(hsotg);
4754 * dwc2_hsotg_remove - remove function for hsotg driver
4755 * @hsotg: Programming view of the DWC_otg controller
4758 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4760 usb_del_gadget_udc(&hsotg->gadget);
4761 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4766 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4768 unsigned long flags;
4770 if (hsotg->lx_state != DWC2_L0)
4773 if (hsotg->driver) {
4776 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4777 hsotg->driver->driver.name);
4779 spin_lock_irqsave(&hsotg->lock, flags);
4781 dwc2_hsotg_core_disconnect(hsotg);
4782 dwc2_hsotg_disconnect(hsotg);
4783 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4784 spin_unlock_irqrestore(&hsotg->lock, flags);
4786 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4787 if (hsotg->eps_in[ep])
4788 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4789 if (hsotg->eps_out[ep])
4790 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4797 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4799 unsigned long flags;
4801 if (hsotg->lx_state == DWC2_L2)
4804 if (hsotg->driver) {
4805 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4806 hsotg->driver->driver.name);
4808 spin_lock_irqsave(&hsotg->lock, flags);
4809 dwc2_hsotg_core_init_disconnected(hsotg, false);
4810 if (hsotg->enabled) {
4811 /* Enable ACG feature in device mode,if supported */
4812 dwc2_enable_acg(hsotg);
4813 dwc2_hsotg_core_connect(hsotg);
4815 spin_unlock_irqrestore(&hsotg->lock, flags);
4822 * dwc2_backup_device_registers() - Backup controller device registers.
4823 * When suspending usb bus, registers needs to be backuped
4824 * if controller power is disabled once suspended.
4826 * @hsotg: Programming view of the DWC_otg controller
4828 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4830 struct dwc2_dregs_backup *dr;
4833 dev_dbg(hsotg->dev, "%s\n", __func__);
4835 /* Backup dev regs */
4836 dr = &hsotg->dr_backup;
4838 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4839 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4840 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4841 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4842 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4844 for (i = 0; i < hsotg->num_of_eps; i++) {
4846 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4848 /* Ensure DATA PID is correctly configured */
4849 if (dr->diepctl[i] & DXEPCTL_DPID)
4850 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4852 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4854 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4855 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4857 /* Backup OUT EPs */
4858 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4860 /* Ensure DATA PID is correctly configured */
4861 if (dr->doepctl[i] & DXEPCTL_DPID)
4862 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4864 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4866 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4867 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4868 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
4875 * dwc2_restore_device_registers() - Restore controller device registers.
4876 * When resuming usb bus, device registers needs to be restored
4877 * if controller power were disabled.
4879 * @hsotg: Programming view of the DWC_otg controller
4880 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
4882 * Return: 0 if successful, negative error code otherwise
4884 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
4886 struct dwc2_dregs_backup *dr;
4889 dev_dbg(hsotg->dev, "%s\n", __func__);
4891 /* Restore dev regs */
4892 dr = &hsotg->dr_backup;
4894 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4901 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4903 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4904 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4905 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4907 for (i = 0; i < hsotg->num_of_eps; i++) {
4908 /* Restore IN EPs */
4909 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4910 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4911 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4912 /** WA for enabled EPx's IN in DDMA mode. On entering to
4913 * hibernation wrong value read and saved from DIEPDMAx,
4914 * as result BNA interrupt asserted on hibernation exit
4915 * by restoring from saved area.
4917 if (hsotg->params.g_dma_desc &&
4918 (dr->diepctl[i] & DXEPCTL_EPENA))
4919 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
4920 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
4921 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4922 /* Restore OUT EPs */
4923 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4924 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4925 * hibernation wrong value read and saved from DOEPDMAx,
4926 * as result BNA interrupt asserted on hibernation exit
4927 * by restoring from saved area.
4929 if (hsotg->params.g_dma_desc &&
4930 (dr->doepctl[i] & DXEPCTL_EPENA))
4931 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
4932 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4933 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4940 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
4942 * @hsotg: Programming view of DWC_otg controller
4945 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4949 if (!hsotg->params.lpm)
4952 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
4953 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
4954 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4955 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4956 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4957 dwc2_writel(val, hsotg->regs + GLPMCFG);
4958 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs
4963 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
4965 * @hsotg: Programming view of the DWC_otg controller
4967 * Return non-zero if failed to enter to hibernation.
4969 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4974 /* Change to L2(suspend) state */
4975 hsotg->lx_state = DWC2_L2;
4976 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
4977 ret = dwc2_backup_global_registers(hsotg);
4979 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
4983 ret = dwc2_backup_device_registers(hsotg);
4985 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
4990 gpwrdn = GPWRDN_PWRDNRSTN;
4991 gpwrdn |= GPWRDN_PMUACTV;
4992 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4995 /* Set flag to indicate that we are in hibernation */
4996 hsotg->hibernated = 1;
4998 /* Enable interrupts from wake up logic */
4999 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5000 gpwrdn |= GPWRDN_PMUINTSEL;
5001 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5004 /* Unmask device mode interrupts in GPWRDN */
5005 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5006 gpwrdn |= GPWRDN_RST_DET_MSK;
5007 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5008 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5009 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5012 /* Enable Power Down Clamp */
5013 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5014 gpwrdn |= GPWRDN_PWRDNCLMP;
5015 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5018 /* Switch off VDD */
5019 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5020 gpwrdn |= GPWRDN_PWRDNSWTCH;
5021 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5024 /* Save gpwrdn register for further usage if stschng interrupt */
5025 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5026 dev_dbg(hsotg->dev, "Hibernation completed\n");
5032 * dwc2_gadget_exit_hibernation()
5033 * This function is for exiting from Device mode hibernation by host initiated
5034 * resume/reset and device initiated remote-wakeup.
5036 * @hsotg: Programming view of the DWC_otg controller
5037 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5038 * @reset: indicates whether resume is initiated by Reset.
5040 * Return non-zero if failed to exit from hibernation.
5042 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5043 int rem_wakeup, int reset)
5049 struct dwc2_gregs_backup *gr;
5050 struct dwc2_dregs_backup *dr;
5052 gr = &hsotg->gr_backup;
5053 dr = &hsotg->dr_backup;
5055 if (!hsotg->hibernated) {
5056 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5060 "%s: called with rem_wakeup = %d reset = %d\n",
5061 __func__, rem_wakeup, reset);
5063 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5066 /* Clear all pending interupts */
5067 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5070 /* De-assert Restore */
5071 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5072 gpwrdn &= ~GPWRDN_RESTORE;
5073 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5077 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5078 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5079 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5082 /* Restore GUSBCFG, DCFG and DCTL */
5083 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5084 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
5085 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
5087 /* De-assert Wakeup Logic */
5088 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5089 gpwrdn &= ~GPWRDN_PMUACTV;
5090 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5094 /* Start Remote Wakeup Signaling */
5095 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL);
5098 /* Set Device programming done bit */
5099 dctl = dwc2_readl(hsotg->regs + DCTL);
5100 dctl |= DCTL_PWRONPRGDONE;
5101 dwc2_writel(dctl, hsotg->regs + DCTL);
5103 /* Wait for interrupts which must be cleared */
5105 /* Clear all pending interupts */
5106 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5108 /* Restore global registers */
5109 ret = dwc2_restore_global_registers(hsotg);
5111 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5116 /* Restore device registers */
5117 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5119 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5126 dctl = dwc2_readl(hsotg->regs + DCTL);
5127 dctl &= ~DCTL_RMTWKUPSIG;
5128 dwc2_writel(dctl, hsotg->regs + DCTL);
5131 hsotg->hibernated = 0;
5132 hsotg->lx_state = DWC2_L0;
5133 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");