2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/of_platform.h>
31 #include <linux/phy/phy.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
40 /* conversion functions */
41 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
43 return container_of(req, struct s3c_hsotg_req, req);
46 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
48 return container_of(ep, struct s3c_hsotg_ep, ep);
51 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
53 return container_of(gadget, struct s3c_hsotg, gadget);
56 static inline void __orr32(void __iomem *ptr, u32 val)
58 writel(readl(ptr) | val, ptr);
61 static inline void __bic32(void __iomem *ptr, u32 val)
63 writel(readl(ptr) & ~val, ptr);
66 /* forward decleration of functions */
67 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
70 * using_dma - return the DMA status of the driver.
71 * @hsotg: The driver state.
73 * Return true if we're using DMA.
75 * Currently, we have the DMA support code worked into everywhere
76 * that needs it, but the AMBA DMA implementation in the hardware can
77 * only DMA from 32bit aligned addresses. This means that gadgets such
78 * as the CDC Ethernet cannot work as they often pass packets which are
81 * Unfortunately the choice to use DMA or not is global to the controller
82 * and seems to be only settable when the controller is being put through
83 * a core reset. This means we either need to fix the gadgets to take
84 * account of DMA alignment, or add bounce buffers (yuerk).
86 * Until this issue is sorted out, we always return 'false'.
88 static inline bool using_dma(struct s3c_hsotg *hsotg)
90 return false; /* support is not complete */
94 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
95 * @hsotg: The device state
96 * @ints: A bitmask of the interrupts to enable
98 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
100 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
103 new_gsintmsk = gsintmsk | ints;
105 if (new_gsintmsk != gsintmsk) {
106 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
107 writel(new_gsintmsk, hsotg->regs + GINTMSK);
112 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
113 * @hsotg: The device state
114 * @ints: A bitmask of the interrupts to enable
116 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
118 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
121 new_gsintmsk = gsintmsk & ~ints;
123 if (new_gsintmsk != gsintmsk)
124 writel(new_gsintmsk, hsotg->regs + GINTMSK);
128 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
129 * @hsotg: The device state
130 * @ep: The endpoint index
131 * @dir_in: True if direction is in.
132 * @en: The enable value, true to enable
134 * Set or clear the mask for an individual endpoint's interrupt
137 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
138 unsigned int ep, unsigned int dir_in,
148 local_irq_save(flags);
149 daint = readl(hsotg->regs + DAINTMSK);
154 writel(daint, hsotg->regs + DAINTMSK);
155 local_irq_restore(flags);
159 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
160 * @hsotg: The device instance.
162 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
170 /* set FIFO sizes to 2048/1024 */
172 writel(2048, hsotg->regs + GRXFSIZ);
173 writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
174 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
177 * arange all the rest of the TX FIFOs, as some versions of this
178 * block have overlapping default addresses. This also ensures
179 * that if the settings have been changed, then they are set to
183 /* start at the end of the GNPTXFSIZ, rounded up */
188 * currently we allocate TX FIFOs for all possible endpoints,
189 * and assume that they are all the same size.
192 for (ep = 1; ep <= 15; ep++) {
194 val |= size << FIFOSIZE_DEPTH_SHIFT;
197 writel(val, hsotg->regs + DPTXFSIZN(ep));
201 * according to p428 of the design guide, we need to ensure that
202 * all fifos are flushed before continuing
205 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
206 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
208 /* wait until the fifos are both flushed */
211 val = readl(hsotg->regs + GRSTCTL);
213 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
216 if (--timeout == 0) {
218 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
225 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
229 * @ep: USB endpoint to allocate request for.
230 * @flags: Allocation flags
232 * Allocate a new USB request structure appropriate for the specified endpoint
234 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
237 struct s3c_hsotg_req *req;
239 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
243 INIT_LIST_HEAD(&req->queue);
249 * is_ep_periodic - return true if the endpoint is in periodic mode.
250 * @hs_ep: The endpoint to query.
252 * Returns true if the endpoint is in periodic mode, meaning it is being
253 * used for an Interrupt or ISO transfer.
255 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
257 return hs_ep->periodic;
261 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
262 * @hsotg: The device state.
263 * @hs_ep: The endpoint for the request
264 * @hs_req: The request being processed.
266 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
267 * of a request to ensure the buffer is ready for access by the caller.
269 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
270 struct s3c_hsotg_ep *hs_ep,
271 struct s3c_hsotg_req *hs_req)
273 struct usb_request *req = &hs_req->req;
275 /* ignore this if we're not moving any data */
276 if (hs_req->req.length == 0)
279 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
283 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
284 * @hsotg: The controller state.
285 * @hs_ep: The endpoint we're going to write for.
286 * @hs_req: The request to write data for.
288 * This is called when the TxFIFO has some space in it to hold a new
289 * transmission and we have something to give it. The actual setup of
290 * the data size is done elsewhere, so all we have to do is to actually
293 * The return value is zero if there is more space (or nothing was done)
294 * otherwise -ENOSPC is returned if the FIFO space was used up.
296 * This routine is only needed for PIO
298 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
299 struct s3c_hsotg_ep *hs_ep,
300 struct s3c_hsotg_req *hs_req)
302 bool periodic = is_ep_periodic(hs_ep);
303 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
304 int buf_pos = hs_req->req.actual;
305 int to_write = hs_ep->size_loaded;
311 to_write -= (buf_pos - hs_ep->last_load);
313 /* if there's nothing to write, get out early */
317 if (periodic && !hsotg->dedicated_fifos) {
318 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
323 * work out how much data was loaded so we can calculate
324 * how much data is left in the fifo.
327 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
330 * if shared fifo, we cannot write anything until the
331 * previous data has been completely sent.
333 if (hs_ep->fifo_load != 0) {
334 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
338 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
340 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
342 /* how much of the data has moved */
343 size_done = hs_ep->size_loaded - size_left;
345 /* how much data is left in the fifo */
346 can_write = hs_ep->fifo_load - size_done;
347 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
348 __func__, can_write);
350 can_write = hs_ep->fifo_size - can_write;
351 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
352 __func__, can_write);
354 if (can_write <= 0) {
355 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
358 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
359 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
364 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
366 "%s: no queue slots available (0x%08x)\n",
369 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
373 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
374 can_write *= 4; /* fifo size is in 32bit quantities. */
377 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
379 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
380 __func__, gnptxsts, can_write, to_write, max_transfer);
383 * limit to 512 bytes of data, it seems at least on the non-periodic
384 * FIFO, requests of >512 cause the endpoint to get stuck with a
385 * fragment of the end of the transfer in it.
387 if (can_write > 512 && !periodic)
391 * limit the write to one max-packet size worth of data, but allow
392 * the transfer to return that it did not run out of fifo space
395 if (to_write > max_transfer) {
396 to_write = max_transfer;
398 /* it's needed only when we do not use dedicated fifos */
399 if (!hsotg->dedicated_fifos)
400 s3c_hsotg_en_gsint(hsotg,
401 periodic ? GINTSTS_PTXFEMP :
405 /* see if we can write data */
407 if (to_write > can_write) {
408 to_write = can_write;
409 pkt_round = to_write % max_transfer;
412 * Round the write down to an
413 * exact number of packets.
415 * Note, we do not currently check to see if we can ever
416 * write a full packet or not to the FIFO.
420 to_write -= pkt_round;
423 * enable correct FIFO interrupt to alert us when there
427 /* it's needed only when we do not use dedicated fifos */
428 if (!hsotg->dedicated_fifos)
429 s3c_hsotg_en_gsint(hsotg,
430 periodic ? GINTSTS_PTXFEMP :
434 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
435 to_write, hs_req->req.length, can_write, buf_pos);
440 hs_req->req.actual = buf_pos + to_write;
441 hs_ep->total_data += to_write;
444 hs_ep->fifo_load += to_write;
446 to_write = DIV_ROUND_UP(to_write, 4);
447 data = hs_req->req.buf + buf_pos;
449 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
451 return (to_write >= can_write) ? -ENOSPC : 0;
455 * get_ep_limit - get the maximum data legnth for this endpoint
456 * @hs_ep: The endpoint
458 * Return the maximum data that can be queued in one go on a given endpoint
459 * so that transfers that are too long can be split.
461 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
463 int index = hs_ep->index;
468 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
469 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
473 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
478 /* we made the constant loading easier above by using +1 */
483 * constrain by packet count if maxpkts*pktsize is greater
484 * than the length register size.
487 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
488 maxsize = maxpkt * hs_ep->ep.maxpacket;
494 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
495 * @hsotg: The controller state.
496 * @hs_ep: The endpoint to process a request for
497 * @hs_req: The request to start.
498 * @continuing: True if we are doing more for the current request.
500 * Start the given request running by setting the endpoint registers
501 * appropriately, and writing any data to the FIFOs.
503 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
504 struct s3c_hsotg_ep *hs_ep,
505 struct s3c_hsotg_req *hs_req,
508 struct usb_request *ureq = &hs_req->req;
509 int index = hs_ep->index;
510 int dir_in = hs_ep->dir_in;
520 if (hs_ep->req && !continuing) {
521 dev_err(hsotg->dev, "%s: active request\n", __func__);
524 } else if (hs_ep->req != hs_req && continuing) {
526 "%s: continue different req\n", __func__);
532 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
533 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
535 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
536 __func__, readl(hsotg->regs + epctrl_reg), index,
537 hs_ep->dir_in ? "in" : "out");
539 /* If endpoint is stalled, we will restart request later */
540 ctrl = readl(hsotg->regs + epctrl_reg);
542 if (ctrl & DXEPCTL_STALL) {
543 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
547 length = ureq->length - ureq->actual;
548 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
549 ureq->length, ureq->actual);
552 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
553 ureq->buf, length, &ureq->dma,
554 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
556 maxreq = get_ep_limit(hs_ep);
557 if (length > maxreq) {
558 int round = maxreq % hs_ep->ep.maxpacket;
560 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
561 __func__, length, maxreq, round);
563 /* round down to multiple of packets */
571 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
573 packets = 1; /* send one packet if length is zero. */
575 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
576 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
580 if (dir_in && index != 0)
581 if (hs_ep->isochronous)
582 epsize = DXEPTSIZ_MC(packets);
584 epsize = DXEPTSIZ_MC(1);
588 if (index != 0 && ureq->zero) {
590 * test for the packets being exactly right for the
594 if (length == (packets * hs_ep->ep.maxpacket))
598 epsize |= DXEPTSIZ_PKTCNT(packets);
599 epsize |= DXEPTSIZ_XFERSIZE(length);
601 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
602 __func__, packets, length, ureq->length, epsize, epsize_reg);
604 /* store the request as the current one we're doing */
607 /* write size / packets */
608 writel(epsize, hsotg->regs + epsize_reg);
610 if (using_dma(hsotg) && !continuing) {
611 unsigned int dma_reg;
614 * write DMA address to control register, buffer already
615 * synced by s3c_hsotg_ep_queue().
618 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
619 writel(ureq->dma, hsotg->regs + dma_reg);
621 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
622 __func__, &ureq->dma, dma_reg);
625 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
626 ctrl |= DXEPCTL_USBACTEP;
628 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
630 /* For Setup request do not clear NAK */
631 if (hsotg->setup && index == 0)
634 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
637 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
638 writel(ctrl, hsotg->regs + epctrl_reg);
641 * set these, it seems that DMA support increments past the end
642 * of the packet buffer so we need to calculate the length from
645 hs_ep->size_loaded = length;
646 hs_ep->last_load = ureq->actual;
648 if (dir_in && !using_dma(hsotg)) {
649 /* set these anyway, we may need them for non-periodic in */
650 hs_ep->fifo_load = 0;
652 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
656 * clear the INTknTXFEmpMsk when we start request, more as a aide
657 * to debugging to see what is going on.
660 writel(DIEPMSK_INTKNTXFEMPMSK,
661 hsotg->regs + DIEPINT(index));
664 * Note, trying to clear the NAK here causes problems with transmit
665 * on the S3C6400 ending up with the TXFIFO becoming full.
668 /* check ep is enabled */
669 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
671 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
672 index, readl(hsotg->regs + epctrl_reg));
674 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
675 __func__, readl(hsotg->regs + epctrl_reg));
677 /* enable ep interrupts */
678 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
682 * s3c_hsotg_map_dma - map the DMA memory being used for the request
683 * @hsotg: The device state.
684 * @hs_ep: The endpoint the request is on.
685 * @req: The request being processed.
687 * We've been asked to queue a request, so ensure that the memory buffer
688 * is correctly setup for DMA. If we've been passed an extant DMA address
689 * then ensure the buffer has been synced to memory. If our buffer has no
690 * DMA memory, then we map the memory and mark our request to allow us to
691 * cleanup on completion.
693 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
694 struct s3c_hsotg_ep *hs_ep,
695 struct usb_request *req)
697 struct s3c_hsotg_req *hs_req = our_req(req);
700 /* if the length is zero, ignore the DMA data */
701 if (hs_req->req.length == 0)
704 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
711 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
712 __func__, req->buf, req->length);
717 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
720 struct s3c_hsotg_req *hs_req = our_req(req);
721 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
722 struct s3c_hsotg *hs = hs_ep->parent;
725 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
726 ep->name, req, req->length, req->buf, req->no_interrupt,
727 req->zero, req->short_not_ok);
729 /* initialise status of the request */
730 INIT_LIST_HEAD(&hs_req->queue);
732 req->status = -EINPROGRESS;
734 /* if we're using DMA, sync the buffers as necessary */
736 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
741 first = list_empty(&hs_ep->queue);
742 list_add_tail(&hs_req->queue, &hs_ep->queue);
745 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
750 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
753 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
754 struct s3c_hsotg *hs = hs_ep->parent;
755 unsigned long flags = 0;
758 spin_lock_irqsave(&hs->lock, flags);
759 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
760 spin_unlock_irqrestore(&hs->lock, flags);
765 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
766 struct usb_request *req)
768 struct s3c_hsotg_req *hs_req = our_req(req);
774 * s3c_hsotg_complete_oursetup - setup completion callback
775 * @ep: The endpoint the request was on.
776 * @req: The request completed.
778 * Called on completion of any requests the driver itself
779 * submitted that need cleaning up.
781 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
782 struct usb_request *req)
784 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
785 struct s3c_hsotg *hsotg = hs_ep->parent;
787 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
789 s3c_hsotg_ep_free_request(ep, req);
793 * ep_from_windex - convert control wIndex value to endpoint
794 * @hsotg: The driver state.
795 * @windex: The control request wIndex field (in host order).
797 * Convert the given wIndex into a pointer to an driver endpoint
798 * structure, or return NULL if it is not a valid endpoint.
800 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
803 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
804 int dir = (windex & USB_DIR_IN) ? 1 : 0;
805 int idx = windex & 0x7F;
810 if (idx > hsotg->num_of_eps)
813 if (idx && ep->dir_in != dir)
820 * s3c_hsotg_send_reply - send reply to control request
821 * @hsotg: The device state
823 * @buff: Buffer for request
824 * @length: Length of reply.
826 * Create a request and queue it on the given endpoint. This is useful as
827 * an internal method of sending replies to certain control requests, etc.
829 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
830 struct s3c_hsotg_ep *ep,
834 struct usb_request *req;
837 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
839 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
840 hsotg->ep0_reply = req;
842 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
846 req->buf = hsotg->ep0_buff;
847 req->length = length;
848 req->zero = 1; /* always do zero-length final transfer */
849 req->complete = s3c_hsotg_complete_oursetup;
852 memcpy(req->buf, buff, length);
856 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
858 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
866 * s3c_hsotg_process_req_status - process request GET_STATUS
867 * @hsotg: The device state
868 * @ctrl: USB control request
870 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
871 struct usb_ctrlrequest *ctrl)
873 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
874 struct s3c_hsotg_ep *ep;
878 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
881 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
885 switch (ctrl->bRequestType & USB_RECIP_MASK) {
886 case USB_RECIP_DEVICE:
887 reply = cpu_to_le16(0); /* bit 0 => self powered,
888 * bit 1 => remote wakeup */
891 case USB_RECIP_INTERFACE:
892 /* currently, the data result should be zero */
893 reply = cpu_to_le16(0);
896 case USB_RECIP_ENDPOINT:
897 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
901 reply = cpu_to_le16(ep->halted ? 1 : 0);
908 if (le16_to_cpu(ctrl->wLength) != 2)
911 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
913 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
920 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
923 * get_ep_head - return the first request on the endpoint
924 * @hs_ep: The controller endpoint to get
926 * Get the first request on the endpoint.
928 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
930 if (list_empty(&hs_ep->queue))
933 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
937 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
938 * @hsotg: The device state
939 * @ctrl: USB control request
941 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
942 struct usb_ctrlrequest *ctrl)
944 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
945 struct s3c_hsotg_req *hs_req;
947 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
948 struct s3c_hsotg_ep *ep;
952 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
953 __func__, set ? "SET" : "CLEAR");
955 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
956 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
958 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
959 __func__, le16_to_cpu(ctrl->wIndex));
963 switch (le16_to_cpu(ctrl->wValue)) {
964 case USB_ENDPOINT_HALT:
967 s3c_hsotg_ep_sethalt(&ep->ep, set);
969 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
972 "%s: failed to send reply\n", __func__);
977 * we have to complete all requests for ep if it was
978 * halted, and the halt was cleared by CLEAR_FEATURE
981 if (!set && halted) {
983 * If we have request in progress,
989 list_del_init(&hs_req->queue);
990 hs_req->req.complete(&ep->ep,
994 /* If we have pending request, then start it */
995 restart = !list_empty(&ep->queue);
997 hs_req = get_ep_head(ep);
998 s3c_hsotg_start_req(hsotg, ep,
1009 return -ENOENT; /* currently only deal with endpoint */
1014 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1015 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg);
1018 * s3c_hsotg_stall_ep0 - stall ep0
1019 * @hsotg: The device state
1021 * Set stall for ep0 as response for setup request.
1023 static void s3c_hsotg_stall_ep0(struct s3c_hsotg *hsotg)
1025 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1029 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1030 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1033 * DxEPCTL_Stall will be cleared by EP once it has
1034 * taken effect, so no need to clear later.
1037 ctrl = readl(hsotg->regs + reg);
1038 ctrl |= DXEPCTL_STALL;
1039 ctrl |= DXEPCTL_CNAK;
1040 writel(ctrl, hsotg->regs + reg);
1043 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1044 ctrl, reg, readl(hsotg->regs + reg));
1047 * complete won't be called, so we enqueue
1048 * setup request here
1050 s3c_hsotg_enqueue_setup(hsotg);
1054 * s3c_hsotg_process_control - process a control request
1055 * @hsotg: The device state
1056 * @ctrl: The control request received
1058 * The controller has received the SETUP phase of a control request, and
1059 * needs to work out what to do next (and whether to pass it on to the
1062 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1063 struct usb_ctrlrequest *ctrl)
1065 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1071 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1072 ctrl->bRequest, ctrl->bRequestType,
1073 ctrl->wValue, ctrl->wLength);
1076 * record the direction of the request, for later use when enquing
1080 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1081 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1084 * if we've no data with this request, then the last part of the
1085 * transaction is going to implicitly be IN.
1087 if (ctrl->wLength == 0)
1090 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1091 switch (ctrl->bRequest) {
1092 case USB_REQ_SET_ADDRESS:
1093 s3c_hsotg_disconnect(hsotg);
1094 dcfg = readl(hsotg->regs + DCFG);
1095 dcfg &= ~DCFG_DEVADDR_MASK;
1096 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1097 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1098 writel(dcfg, hsotg->regs + DCFG);
1100 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1102 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1105 case USB_REQ_GET_STATUS:
1106 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1109 case USB_REQ_CLEAR_FEATURE:
1110 case USB_REQ_SET_FEATURE:
1111 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1116 /* as a fallback, try delivering it to the driver to deal with */
1118 if (ret == 0 && hsotg->driver) {
1119 spin_unlock(&hsotg->lock);
1120 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1121 spin_lock(&hsotg->lock);
1123 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1127 * the request is either unhandlable, or is not formatted correctly
1128 * so respond with a STALL for the status stage to indicate failure.
1132 s3c_hsotg_stall_ep0(hsotg);
1136 * s3c_hsotg_complete_setup - completion of a setup transfer
1137 * @ep: The endpoint the request was on.
1138 * @req: The request completed.
1140 * Called on completion of any requests the driver itself submitted for
1143 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1144 struct usb_request *req)
1146 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1147 struct s3c_hsotg *hsotg = hs_ep->parent;
1149 if (req->status < 0) {
1150 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1154 spin_lock(&hsotg->lock);
1155 if (req->actual == 0)
1156 s3c_hsotg_enqueue_setup(hsotg);
1158 s3c_hsotg_process_control(hsotg, req->buf);
1159 spin_unlock(&hsotg->lock);
1163 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1164 * @hsotg: The device state.
1166 * Enqueue a request on EP0 if necessary to received any SETUP packets
1167 * received from the host.
1169 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1171 struct usb_request *req = hsotg->ctrl_req;
1172 struct s3c_hsotg_req *hs_req = our_req(req);
1175 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1179 req->buf = hsotg->ctrl_buff;
1180 req->complete = s3c_hsotg_complete_setup;
1182 if (!list_empty(&hs_req->queue)) {
1183 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1187 hsotg->eps[0].dir_in = 0;
1189 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1191 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1193 * Don't think there's much we can do other than watch the
1200 * s3c_hsotg_complete_request - complete a request given to us
1201 * @hsotg: The device state.
1202 * @hs_ep: The endpoint the request was on.
1203 * @hs_req: The request to complete.
1204 * @result: The result code (0 => Ok, otherwise errno)
1206 * The given request has finished, so call the necessary completion
1207 * if it has one and then look to see if we can start a new request
1210 * Note, expects the ep to already be locked as appropriate.
1212 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1213 struct s3c_hsotg_ep *hs_ep,
1214 struct s3c_hsotg_req *hs_req,
1220 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1224 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1225 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1228 * only replace the status if we've not already set an error
1229 * from a previous transaction
1232 if (hs_req->req.status == -EINPROGRESS)
1233 hs_req->req.status = result;
1236 list_del_init(&hs_req->queue);
1238 if (using_dma(hsotg))
1239 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1242 * call the complete request with the locks off, just in case the
1243 * request tries to queue more work for this endpoint.
1246 if (hs_req->req.complete) {
1247 spin_unlock(&hsotg->lock);
1248 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1249 spin_lock(&hsotg->lock);
1253 * Look to see if there is anything else to do. Note, the completion
1254 * of the previous request may have caused a new request to be started
1255 * so be careful when doing this.
1258 if (!hs_ep->req && result >= 0) {
1259 restart = !list_empty(&hs_ep->queue);
1261 hs_req = get_ep_head(hs_ep);
1262 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1268 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1269 * @hsotg: The device state.
1270 * @ep_idx: The endpoint index for the data
1271 * @size: The size of data in the fifo, in bytes
1273 * The FIFO status shows there is data to read from the FIFO for a given
1274 * endpoint, so sort out whether we need to read the data into a request
1275 * that has been made for that endpoint.
1277 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1279 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1280 struct s3c_hsotg_req *hs_req = hs_ep->req;
1281 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1288 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1291 dev_warn(hsotg->dev,
1292 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1293 __func__, size, ep_idx, epctl);
1295 /* dump the data from the FIFO, we've nothing we can do */
1296 for (ptr = 0; ptr < size; ptr += 4)
1303 read_ptr = hs_req->req.actual;
1304 max_req = hs_req->req.length - read_ptr;
1306 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1307 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1309 if (to_read > max_req) {
1311 * more data appeared than we where willing
1312 * to deal with in this request.
1315 /* currently we don't deal this */
1319 hs_ep->total_data += to_read;
1320 hs_req->req.actual += to_read;
1321 to_read = DIV_ROUND_UP(to_read, 4);
1324 * note, we might over-write the buffer end by 3 bytes depending on
1325 * alignment of the data.
1327 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1331 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1332 * @hsotg: The device instance
1333 * @req: The request currently on this endpoint
1335 * Generate a zero-length IN packet request for terminating a SETUP
1338 * Note, since we don't write any data to the TxFIFO, then it is
1339 * currently believed that we do not need to wait for any space in
1342 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1343 struct s3c_hsotg_req *req)
1348 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1352 if (req->req.length == 0) {
1353 hsotg->eps[0].sent_zlp = 1;
1354 s3c_hsotg_enqueue_setup(hsotg);
1358 hsotg->eps[0].dir_in = 1;
1359 hsotg->eps[0].sent_zlp = 1;
1361 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1363 /* issue a zero-sized packet to terminate this */
1364 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1365 DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
1367 ctrl = readl(hsotg->regs + DIEPCTL0);
1368 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1369 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1370 ctrl |= DXEPCTL_USBACTEP;
1371 writel(ctrl, hsotg->regs + DIEPCTL0);
1375 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1376 * @hsotg: The device instance
1377 * @epnum: The endpoint received from
1378 * @was_setup: Set if processing a SetupDone event.
1380 * The RXFIFO has delivered an OutDone event, which means that the data
1381 * transfer for an OUT endpoint has been completed, either by a short
1382 * packet or by the finish of a transfer.
1384 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1385 int epnum, bool was_setup)
1387 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1388 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1389 struct s3c_hsotg_req *hs_req = hs_ep->req;
1390 struct usb_request *req = &hs_req->req;
1391 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1395 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1399 if (using_dma(hsotg)) {
1403 * Calculate the size of the transfer by checking how much
1404 * is left in the endpoint size register and then working it
1405 * out from the amount we loaded for the transfer.
1407 * We need to do this as DMA pointers are always 32bit aligned
1408 * so may overshoot/undershoot the transfer.
1411 size_done = hs_ep->size_loaded - size_left;
1412 size_done += hs_ep->last_load;
1414 req->actual = size_done;
1417 /* if there is more request to do, schedule new transfer */
1418 if (req->actual < req->length && size_left == 0) {
1419 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1421 } else if (epnum == 0) {
1423 * After was_setup = 1 =>
1424 * set CNAK for non Setup requests
1426 hsotg->setup = was_setup ? 0 : 1;
1429 if (req->actual < req->length && req->short_not_ok) {
1430 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1431 __func__, req->actual, req->length);
1434 * todo - what should we return here? there's no one else
1435 * even bothering to check the status.
1441 * Condition req->complete != s3c_hsotg_complete_setup says:
1442 * send ZLP when we have an asynchronous request from gadget
1444 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1445 s3c_hsotg_send_zlp(hsotg, hs_req);
1448 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1452 * s3c_hsotg_read_frameno - read current frame number
1453 * @hsotg: The device instance
1455 * Return the current frame number
1457 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1461 dsts = readl(hsotg->regs + DSTS);
1462 dsts &= DSTS_SOFFN_MASK;
1463 dsts >>= DSTS_SOFFN_SHIFT;
1469 * s3c_hsotg_handle_rx - RX FIFO has data
1470 * @hsotg: The device instance
1472 * The IRQ handler has detected that the RX FIFO has some data in it
1473 * that requires processing, so find out what is in there and do the
1476 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1477 * chunks, so if you have x packets received on an endpoint you'll get x
1478 * FIFO events delivered, each with a packet's worth of data in it.
1480 * When using DMA, we should not be processing events from the RXFIFO
1481 * as the actual data should be sent to the memory directly and we turn
1482 * on the completion interrupts to get notifications of transfer completion.
1484 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1486 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1487 u32 epnum, status, size;
1489 WARN_ON(using_dma(hsotg));
1491 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1492 status = grxstsr & GRXSTS_PKTSTS_MASK;
1494 size = grxstsr & GRXSTS_BYTECNT_MASK;
1495 size >>= GRXSTS_BYTECNT_SHIFT;
1498 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1499 __func__, grxstsr, size, epnum);
1501 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1502 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1503 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1506 case GRXSTS_PKTSTS_OUTDONE:
1507 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1508 s3c_hsotg_read_frameno(hsotg));
1510 if (!using_dma(hsotg))
1511 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1514 case GRXSTS_PKTSTS_SETUPDONE:
1516 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1517 s3c_hsotg_read_frameno(hsotg),
1518 readl(hsotg->regs + DOEPCTL(0)));
1520 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1523 case GRXSTS_PKTSTS_OUTRX:
1524 s3c_hsotg_rx_data(hsotg, epnum, size);
1527 case GRXSTS_PKTSTS_SETUPRX:
1529 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1530 s3c_hsotg_read_frameno(hsotg),
1531 readl(hsotg->regs + DOEPCTL(0)));
1533 s3c_hsotg_rx_data(hsotg, epnum, size);
1537 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1540 s3c_hsotg_dump(hsotg);
1546 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1547 * @mps: The maximum packet size in bytes.
1549 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1553 return D0EPCTL_MPS_64;
1555 return D0EPCTL_MPS_32;
1557 return D0EPCTL_MPS_16;
1559 return D0EPCTL_MPS_8;
1562 /* bad max packet size, warn and return invalid result */
1568 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1569 * @hsotg: The driver state.
1570 * @ep: The index number of the endpoint
1571 * @mps: The maximum packet size in bytes
1573 * Configure the maximum packet size for the given endpoint, updating
1574 * the hardware control registers to reflect this.
1576 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1577 unsigned int ep, unsigned int mps)
1579 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1580 void __iomem *regs = hsotg->regs;
1586 /* EP0 is a special case */
1587 mpsval = s3c_hsotg_ep0_mps(mps);
1590 hs_ep->ep.maxpacket = mps;
1593 mpsval = mps & DXEPCTL_MPS_MASK;
1596 mcval = ((mps >> 11) & 0x3) + 1;
1600 hs_ep->ep.maxpacket = mpsval;
1604 * update both the in and out endpoint controldir_ registers, even
1605 * if one of the directions may not be in use.
1608 reg = readl(regs + DIEPCTL(ep));
1609 reg &= ~DXEPCTL_MPS_MASK;
1611 writel(reg, regs + DIEPCTL(ep));
1614 reg = readl(regs + DOEPCTL(ep));
1615 reg &= ~DXEPCTL_MPS_MASK;
1617 writel(reg, regs + DOEPCTL(ep));
1623 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1627 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1628 * @hsotg: The driver state
1629 * @idx: The index for the endpoint (0..15)
1631 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1636 writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1637 hsotg->regs + GRSTCTL);
1639 /* wait until the fifo is flushed */
1643 val = readl(hsotg->regs + GRSTCTL);
1645 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1648 if (--timeout == 0) {
1650 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1660 * s3c_hsotg_trytx - check to see if anything needs transmitting
1661 * @hsotg: The driver state
1662 * @hs_ep: The driver endpoint to check.
1664 * Check to see if there is a request that has data to send, and if so
1665 * make an attempt to write data into the FIFO.
1667 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1668 struct s3c_hsotg_ep *hs_ep)
1670 struct s3c_hsotg_req *hs_req = hs_ep->req;
1672 if (!hs_ep->dir_in || !hs_req) {
1674 * if request is not enqueued, we disable interrupts
1675 * for endpoints, excepting ep0
1677 if (hs_ep->index != 0)
1678 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1683 if (hs_req->req.actual < hs_req->req.length) {
1684 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1686 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1693 * s3c_hsotg_complete_in - complete IN transfer
1694 * @hsotg: The device state.
1695 * @hs_ep: The endpoint that has just completed.
1697 * An IN transfer has been completed, update the transfer's state and then
1698 * call the relevant completion routines.
1700 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1701 struct s3c_hsotg_ep *hs_ep)
1703 struct s3c_hsotg_req *hs_req = hs_ep->req;
1704 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1705 int size_left, size_done;
1708 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1712 /* Finish ZLP handling for IN EP0 transactions */
1713 if (hsotg->eps[0].sent_zlp) {
1714 dev_dbg(hsotg->dev, "zlp packet received\n");
1715 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1720 * Calculate the size of the transfer by checking how much is left
1721 * in the endpoint size register and then working it out from
1722 * the amount we loaded for the transfer.
1724 * We do this even for DMA, as the transfer may have incremented
1725 * past the end of the buffer (DMA transfers are always 32bit
1729 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1731 size_done = hs_ep->size_loaded - size_left;
1732 size_done += hs_ep->last_load;
1734 if (hs_req->req.actual != size_done)
1735 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1736 __func__, hs_req->req.actual, size_done);
1738 hs_req->req.actual = size_done;
1739 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1740 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1743 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1744 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1745 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1746 * inform the host that no more data is available.
1747 * The state of req.zero member is checked to be sure that the value to
1748 * send is smaller than wValue expected from host.
1749 * Check req.length to NOT send another ZLP when the current one is
1750 * under completion (the one for which this completion has been called).
1752 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1753 hs_req->req.length == hs_req->req.actual &&
1754 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1756 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1757 s3c_hsotg_send_zlp(hsotg, hs_req);
1762 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1763 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1764 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1766 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1770 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1771 * @hsotg: The driver state
1772 * @idx: The index for the endpoint (0..15)
1773 * @dir_in: Set if this is an IN endpoint
1775 * Process and clear any interrupt pending for an individual endpoint
1777 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1780 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1781 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1782 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1783 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1787 ints = readl(hsotg->regs + epint_reg);
1788 ctrl = readl(hsotg->regs + epctl_reg);
1790 /* Clear endpoint interrupts */
1791 writel(ints, hsotg->regs + epint_reg);
1793 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1794 __func__, idx, dir_in ? "in" : "out", ints);
1796 if (ints & DXEPINT_XFERCOMPL) {
1797 if (hs_ep->isochronous && hs_ep->interval == 1) {
1798 if (ctrl & DXEPCTL_EOFRNUM)
1799 ctrl |= DXEPCTL_SETEVENFR;
1801 ctrl |= DXEPCTL_SETODDFR;
1802 writel(ctrl, hsotg->regs + epctl_reg);
1806 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1807 __func__, readl(hsotg->regs + epctl_reg),
1808 readl(hsotg->regs + epsiz_reg));
1811 * we get OutDone from the FIFO, so we only need to look
1812 * at completing IN requests here
1815 s3c_hsotg_complete_in(hsotg, hs_ep);
1817 if (idx == 0 && !hs_ep->req)
1818 s3c_hsotg_enqueue_setup(hsotg);
1819 } else if (using_dma(hsotg)) {
1821 * We're using DMA, we need to fire an OutDone here
1822 * as we ignore the RXFIFO.
1825 s3c_hsotg_handle_outdone(hsotg, idx, false);
1829 if (ints & DXEPINT_EPDISBLD) {
1830 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1833 int epctl = readl(hsotg->regs + epctl_reg);
1835 s3c_hsotg_txfifo_flush(hsotg, idx);
1837 if ((epctl & DXEPCTL_STALL) &&
1838 (epctl & DXEPCTL_EPTYPE_BULK)) {
1839 int dctl = readl(hsotg->regs + DCTL);
1841 dctl |= DCTL_CGNPINNAK;
1842 writel(dctl, hsotg->regs + DCTL);
1847 if (ints & DXEPINT_AHBERR)
1848 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1850 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
1851 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1853 if (using_dma(hsotg) && idx == 0) {
1855 * this is the notification we've received a
1856 * setup packet. In non-DMA mode we'd get this
1857 * from the RXFIFO, instead we need to process
1864 s3c_hsotg_handle_outdone(hsotg, 0, true);
1868 if (ints & DXEPINT_BACK2BACKSETUP)
1869 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1871 if (dir_in && !hs_ep->isochronous) {
1872 /* not sure if this is important, but we'll clear it anyway */
1873 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
1874 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1878 /* this probably means something bad is happening */
1879 if (ints & DIEPMSK_INTKNEPMISMSK) {
1880 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1884 /* FIFO has space or is empty (see GAHBCFG) */
1885 if (hsotg->dedicated_fifos &&
1886 ints & DIEPMSK_TXFIFOEMPTY) {
1887 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1889 if (!using_dma(hsotg))
1890 s3c_hsotg_trytx(hsotg, hs_ep);
1896 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1897 * @hsotg: The device state.
1899 * Handle updating the device settings after the enumeration phase has
1902 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1904 u32 dsts = readl(hsotg->regs + DSTS);
1905 int ep0_mps = 0, ep_mps = 8;
1908 * This should signal the finish of the enumeration phase
1909 * of the USB handshaking, so we should now know what rate
1913 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1916 * note, since we're limited by the size of transfer on EP0, and
1917 * it seems IN transfers must be a even number of packets we do
1918 * not advertise a 64byte MPS on EP0.
1921 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1922 switch (dsts & DSTS_ENUMSPD_MASK) {
1923 case DSTS_ENUMSPD_FS:
1924 case DSTS_ENUMSPD_FS48:
1925 hsotg->gadget.speed = USB_SPEED_FULL;
1926 ep0_mps = EP0_MPS_LIMIT;
1930 case DSTS_ENUMSPD_HS:
1931 hsotg->gadget.speed = USB_SPEED_HIGH;
1932 ep0_mps = EP0_MPS_LIMIT;
1936 case DSTS_ENUMSPD_LS:
1937 hsotg->gadget.speed = USB_SPEED_LOW;
1939 * note, we don't actually support LS in this driver at the
1940 * moment, and the documentation seems to imply that it isn't
1941 * supported by the PHYs on some of the devices.
1945 dev_info(hsotg->dev, "new device is %s\n",
1946 usb_speed_string(hsotg->gadget.speed));
1949 * we should now know the maximum packet size for an
1950 * endpoint, so set the endpoints to a default value.
1955 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1956 for (i = 1; i < hsotg->num_of_eps; i++)
1957 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1960 /* ensure after enumeration our EP0 is active */
1962 s3c_hsotg_enqueue_setup(hsotg);
1964 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1965 readl(hsotg->regs + DIEPCTL0),
1966 readl(hsotg->regs + DOEPCTL0));
1970 * kill_all_requests - remove all requests from the endpoint's queue
1971 * @hsotg: The device state.
1972 * @ep: The endpoint the requests may be on.
1973 * @result: The result code to use.
1974 * @force: Force removal of any current requests
1976 * Go through the requests on the given endpoint and mark them
1977 * completed with the given result code.
1979 static void kill_all_requests(struct s3c_hsotg *hsotg,
1980 struct s3c_hsotg_ep *ep,
1981 int result, bool force)
1983 struct s3c_hsotg_req *req, *treq;
1985 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1987 * currently, we can't do much about an already
1988 * running request on an in endpoint
1991 if (ep->req == req && ep->dir_in && !force)
1994 s3c_hsotg_complete_request(hsotg, ep, req,
1997 if (hsotg->dedicated_fifos)
1998 if ((readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4 < 3072)
1999 s3c_hsotg_txfifo_flush(hsotg, ep->index);
2003 * s3c_hsotg_disconnect - disconnect service
2004 * @hsotg: The device state.
2006 * The device has been disconnected. Remove all current
2007 * transactions and signal the gadget driver that this
2010 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2014 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2015 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2017 call_gadget(hsotg, disconnect);
2021 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2022 * @hsotg: The device state:
2023 * @periodic: True if this is a periodic FIFO interrupt
2025 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2027 struct s3c_hsotg_ep *ep;
2030 /* look through for any more data to transmit */
2032 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2033 ep = &hsotg->eps[epno];
2038 if ((periodic && !ep->periodic) ||
2039 (!periodic && ep->periodic))
2042 ret = s3c_hsotg_trytx(hsotg, ep);
2048 /* IRQ flags which will trigger a retry around the IRQ loop */
2049 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2054 * s3c_hsotg_corereset - issue softreset to the core
2055 * @hsotg: The device state
2057 * Issue a soft reset to the core, and await the core finishing it.
2059 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2064 dev_dbg(hsotg->dev, "resetting core\n");
2066 /* issue soft reset */
2067 writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
2071 grstctl = readl(hsotg->regs + GRSTCTL);
2072 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
2074 if (grstctl & GRSTCTL_CSFTRST) {
2075 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2082 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2084 if (timeout-- < 0) {
2085 dev_info(hsotg->dev,
2086 "%s: reset failed, GRSTCTL=%08x\n",
2091 if (!(grstctl & GRSTCTL_AHBIDLE))
2094 break; /* reset done */
2097 dev_dbg(hsotg->dev, "reset successful\n");
2102 * s3c_hsotg_core_init - issue softreset to the core
2103 * @hsotg: The device state
2105 * Issue a soft reset to the core, and await the core finishing it.
2107 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2109 s3c_hsotg_corereset(hsotg);
2112 * we must now enable ep0 ready for host detection and then
2113 * set configuration.
2116 /* set the PLL on, remove the HNP/SRP and set the PHY */
2117 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2118 (0x5 << 10), hsotg->regs + GUSBCFG);
2120 s3c_hsotg_init_fifo(hsotg);
2122 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2124 writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2126 /* Clear any pending OTG interrupts */
2127 writel(0xffffffff, hsotg->regs + GOTGINT);
2129 /* Clear any pending interrupts */
2130 writel(0xffffffff, hsotg->regs + GINTSTS);
2132 writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2133 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2134 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2135 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2136 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2137 hsotg->regs + GINTMSK);
2139 if (using_dma(hsotg))
2140 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2141 GAHBCFG_HBSTLEN_INCR4,
2142 hsotg->regs + GAHBCFG);
2144 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2145 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2146 GAHBCFG_GLBL_INTR_EN,
2147 hsotg->regs + GAHBCFG);
2150 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2151 * when we have no data to transfer. Otherwise we get being flooded by
2155 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
2156 DIEPMSK_INTKNTXFEMPMSK : 0) |
2157 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2158 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2159 DIEPMSK_INTKNEPMISMSK,
2160 hsotg->regs + DIEPMSK);
2163 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2164 * DMA mode we may need this.
2166 writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2167 DIEPMSK_TIMEOUTMSK) : 0) |
2168 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2170 hsotg->regs + DOEPMSK);
2172 writel(0, hsotg->regs + DAINTMSK);
2174 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2175 readl(hsotg->regs + DIEPCTL0),
2176 readl(hsotg->regs + DOEPCTL0));
2178 /* enable in and out endpoint interrupts */
2179 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2182 * Enable the RXFIFO when in slave mode, as this is how we collect
2183 * the data. In DMA mode, we get events from the FIFO but also
2184 * things we cannot process, so do not use it.
2186 if (!using_dma(hsotg))
2187 s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2189 /* Enable interrupts for EP0 in and out */
2190 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2191 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2193 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2194 udelay(10); /* see openiboot */
2195 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2197 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2200 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2201 * writing to the EPCTL register..
2204 /* set to read 1 8byte packet */
2205 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2206 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2208 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2209 DXEPCTL_CNAK | DXEPCTL_EPENA |
2211 hsotg->regs + DOEPCTL0);
2213 /* enable, but don't activate EP0in */
2214 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2215 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2217 s3c_hsotg_enqueue_setup(hsotg);
2219 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2220 readl(hsotg->regs + DIEPCTL0),
2221 readl(hsotg->regs + DOEPCTL0));
2223 /* clear global NAKs */
2224 writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
2225 hsotg->regs + DCTL);
2227 /* must be at-least 3ms to allow bus to see disconnect */
2230 /* remove the soft-disconnect and let's go */
2231 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2235 * s3c_hsotg_irq - handle device interrupt
2236 * @irq: The IRQ number triggered
2237 * @pw: The pw value when registered the handler.
2239 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2241 struct s3c_hsotg *hsotg = pw;
2242 int retry_count = 8;
2246 spin_lock(&hsotg->lock);
2248 gintsts = readl(hsotg->regs + GINTSTS);
2249 gintmsk = readl(hsotg->regs + GINTMSK);
2251 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2252 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2256 if (gintsts & GINTSTS_OTGINT) {
2257 u32 otgint = readl(hsotg->regs + GOTGINT);
2259 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2261 writel(otgint, hsotg->regs + GOTGINT);
2264 if (gintsts & GINTSTS_SESSREQINT) {
2265 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2266 writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
2269 if (gintsts & GINTSTS_ENUMDONE) {
2270 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2272 s3c_hsotg_irq_enumdone(hsotg);
2275 if (gintsts & GINTSTS_CONIDSTSCHNG) {
2276 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2277 readl(hsotg->regs + DSTS),
2278 readl(hsotg->regs + GOTGCTL));
2280 writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
2283 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2284 u32 daint = readl(hsotg->regs + DAINT);
2285 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2286 u32 daint_out, daint_in;
2290 daint_out = daint >> DAINT_OUTEP_SHIFT;
2291 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2293 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2295 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2297 s3c_hsotg_epint(hsotg, ep, 0);
2300 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2302 s3c_hsotg_epint(hsotg, ep, 1);
2306 if (gintsts & GINTSTS_USBRST) {
2308 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2310 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2311 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2312 readl(hsotg->regs + GNPTXSTS));
2314 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2316 if (usb_status & GOTGCTL_BSESVLD) {
2317 if (time_after(jiffies, hsotg->last_rst +
2318 msecs_to_jiffies(200))) {
2320 kill_all_requests(hsotg, &hsotg->eps[0],
2323 s3c_hsotg_core_init(hsotg);
2324 hsotg->last_rst = jiffies;
2329 /* check both FIFOs */
2331 if (gintsts & GINTSTS_NPTXFEMP) {
2332 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2335 * Disable the interrupt to stop it happening again
2336 * unless one of these endpoint routines decides that
2337 * it needs re-enabling
2340 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2341 s3c_hsotg_irq_fifoempty(hsotg, false);
2344 if (gintsts & GINTSTS_PTXFEMP) {
2345 dev_dbg(hsotg->dev, "PTxFEmp\n");
2347 /* See note in GINTSTS_NPTxFEmp */
2349 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2350 s3c_hsotg_irq_fifoempty(hsotg, true);
2353 if (gintsts & GINTSTS_RXFLVL) {
2355 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2356 * we need to retry s3c_hsotg_handle_rx if this is still
2360 s3c_hsotg_handle_rx(hsotg);
2363 if (gintsts & GINTSTS_MODEMIS) {
2364 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2365 writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
2368 if (gintsts & GINTSTS_USBSUSP) {
2369 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2370 writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
2372 call_gadget(hsotg, suspend);
2375 if (gintsts & GINTSTS_WKUPINT) {
2376 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2377 writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
2379 call_gadget(hsotg, resume);
2382 if (gintsts & GINTSTS_ERLYSUSP) {
2383 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2384 writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2388 * these next two seem to crop-up occasionally causing the core
2389 * to shutdown the USB transfer, so try clearing them and logging
2393 if (gintsts & GINTSTS_GOUTNAKEFF) {
2394 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2396 writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
2398 s3c_hsotg_dump(hsotg);
2401 if (gintsts & GINTSTS_GINNAKEFF) {
2402 dev_info(hsotg->dev, "GINNakEff triggered\n");
2404 writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2406 s3c_hsotg_dump(hsotg);
2410 * if we've had fifo events, we should try and go around the
2411 * loop again to see if there's any point in returning yet.
2414 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2417 spin_unlock(&hsotg->lock);
2423 * s3c_hsotg_ep_enable - enable the given endpoint
2424 * @ep: The USB endpint to configure
2425 * @desc: The USB endpoint descriptor to configure with.
2427 * This is called from the USB gadget code's usb_ep_enable().
2429 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2430 const struct usb_endpoint_descriptor *desc)
2432 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2433 struct s3c_hsotg *hsotg = hs_ep->parent;
2434 unsigned long flags;
2435 int index = hs_ep->index;
2443 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2444 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2445 desc->wMaxPacketSize, desc->bInterval);
2447 /* not to be called for EP0 */
2448 WARN_ON(index == 0);
2450 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2451 if (dir_in != hs_ep->dir_in) {
2452 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2456 mps = usb_endpoint_maxp(desc);
2458 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2460 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2461 epctrl = readl(hsotg->regs + epctrl_reg);
2463 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2464 __func__, epctrl, epctrl_reg);
2466 spin_lock_irqsave(&hsotg->lock, flags);
2468 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2469 epctrl |= DXEPCTL_MPS(mps);
2472 * mark the endpoint as active, otherwise the core may ignore
2473 * transactions entirely for this endpoint
2475 epctrl |= DXEPCTL_USBACTEP;
2478 * set the NAK status on the endpoint, otherwise we might try and
2479 * do something with data that we've yet got a request to process
2480 * since the RXFIFO will take data for an endpoint even if the
2481 * size register hasn't been set.
2484 epctrl |= DXEPCTL_SNAK;
2486 /* update the endpoint state */
2487 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2489 /* default, set to non-periodic */
2490 hs_ep->isochronous = 0;
2491 hs_ep->periodic = 0;
2493 hs_ep->interval = desc->bInterval;
2495 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2496 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2498 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2499 case USB_ENDPOINT_XFER_ISOC:
2500 epctrl |= DXEPCTL_EPTYPE_ISO;
2501 epctrl |= DXEPCTL_SETEVENFR;
2502 hs_ep->isochronous = 1;
2504 hs_ep->periodic = 1;
2507 case USB_ENDPOINT_XFER_BULK:
2508 epctrl |= DXEPCTL_EPTYPE_BULK;
2511 case USB_ENDPOINT_XFER_INT:
2514 * Allocate our TxFNum by simply using the index
2515 * of the endpoint for the moment. We could do
2516 * something better if the host indicates how
2517 * many FIFOs we are expecting to use.
2520 hs_ep->periodic = 1;
2521 epctrl |= DXEPCTL_TXFNUM(index);
2524 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2527 case USB_ENDPOINT_XFER_CONTROL:
2528 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2533 * if the hardware has dedicated fifos, we must give each IN EP
2534 * a unique tx-fifo even if it is non-periodic.
2536 if (dir_in && hsotg->dedicated_fifos)
2537 epctrl |= DXEPCTL_TXFNUM(index);
2539 /* for non control endpoints, set PID to D0 */
2541 epctrl |= DXEPCTL_SETD0PID;
2543 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2546 writel(epctrl, hsotg->regs + epctrl_reg);
2547 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2548 __func__, readl(hsotg->regs + epctrl_reg));
2550 /* enable the endpoint interrupt */
2551 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2553 spin_unlock_irqrestore(&hsotg->lock, flags);
2558 * s3c_hsotg_ep_disable - disable given endpoint
2559 * @ep: The endpoint to disable.
2561 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2563 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2564 struct s3c_hsotg *hsotg = hs_ep->parent;
2565 int dir_in = hs_ep->dir_in;
2566 int index = hs_ep->index;
2567 unsigned long flags;
2571 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2573 if (ep == &hsotg->eps[0].ep) {
2574 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2578 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2580 spin_lock_irqsave(&hsotg->lock, flags);
2581 /* terminate all requests with shutdown */
2582 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2585 ctrl = readl(hsotg->regs + epctrl_reg);
2586 ctrl &= ~DXEPCTL_EPENA;
2587 ctrl &= ~DXEPCTL_USBACTEP;
2588 ctrl |= DXEPCTL_SNAK;
2590 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2591 writel(ctrl, hsotg->regs + epctrl_reg);
2593 /* disable endpoint interrupts */
2594 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2596 spin_unlock_irqrestore(&hsotg->lock, flags);
2601 * on_list - check request is on the given endpoint
2602 * @ep: The endpoint to check.
2603 * @test: The request to test if it is on the endpoint.
2605 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2607 struct s3c_hsotg_req *req, *treq;
2609 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2618 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2619 * @ep: The endpoint to dequeue.
2620 * @req: The request to be removed from a queue.
2622 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2624 struct s3c_hsotg_req *hs_req = our_req(req);
2625 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2626 struct s3c_hsotg *hs = hs_ep->parent;
2627 unsigned long flags;
2629 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2631 spin_lock_irqsave(&hs->lock, flags);
2633 if (!on_list(hs_ep, hs_req)) {
2634 spin_unlock_irqrestore(&hs->lock, flags);
2638 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2639 spin_unlock_irqrestore(&hs->lock, flags);
2645 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2646 * @ep: The endpoint to set halt.
2647 * @value: Set or unset the halt.
2649 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2651 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2652 struct s3c_hsotg *hs = hs_ep->parent;
2653 int index = hs_ep->index;
2658 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2662 s3c_hsotg_stall_ep0(hs);
2665 "%s: can't clear halt on ep0\n", __func__);
2669 /* write both IN and OUT control registers */
2671 epreg = DIEPCTL(index);
2672 epctl = readl(hs->regs + epreg);
2675 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2676 if (epctl & DXEPCTL_EPENA)
2677 epctl |= DXEPCTL_EPDIS;
2679 epctl &= ~DXEPCTL_STALL;
2680 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2681 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2682 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2683 epctl |= DXEPCTL_SETD0PID;
2686 writel(epctl, hs->regs + epreg);
2688 epreg = DOEPCTL(index);
2689 epctl = readl(hs->regs + epreg);
2692 epctl |= DXEPCTL_STALL;
2694 epctl &= ~DXEPCTL_STALL;
2695 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2696 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2697 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2698 epctl |= DXEPCTL_SETD0PID;
2701 writel(epctl, hs->regs + epreg);
2703 hs_ep->halted = value;
2709 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2710 * @ep: The endpoint to set halt.
2711 * @value: Set or unset the halt.
2713 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2715 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2716 struct s3c_hsotg *hs = hs_ep->parent;
2717 unsigned long flags = 0;
2720 spin_lock_irqsave(&hs->lock, flags);
2721 ret = s3c_hsotg_ep_sethalt(ep, value);
2722 spin_unlock_irqrestore(&hs->lock, flags);
2727 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2728 .enable = s3c_hsotg_ep_enable,
2729 .disable = s3c_hsotg_ep_disable,
2730 .alloc_request = s3c_hsotg_ep_alloc_request,
2731 .free_request = s3c_hsotg_ep_free_request,
2732 .queue = s3c_hsotg_ep_queue_lock,
2733 .dequeue = s3c_hsotg_ep_dequeue,
2734 .set_halt = s3c_hsotg_ep_sethalt_lock,
2735 /* note, don't believe we have any call for the fifo routines */
2739 * s3c_hsotg_phy_enable - enable platform phy dev
2740 * @hsotg: The driver state
2742 * A wrapper for platform code responsible for controlling
2743 * low-level USB code
2745 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2747 struct platform_device *pdev = to_platform_device(hsotg->dev);
2749 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2752 usb_phy_init(hsotg->uphy);
2753 else if (hsotg->plat && hsotg->plat->phy_init)
2754 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2756 phy_init(hsotg->phy);
2757 phy_power_on(hsotg->phy);
2762 * s3c_hsotg_phy_disable - disable platform phy dev
2763 * @hsotg: The driver state
2765 * A wrapper for platform code responsible for controlling
2766 * low-level USB code
2768 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2770 struct platform_device *pdev = to_platform_device(hsotg->dev);
2773 usb_phy_shutdown(hsotg->uphy);
2774 else if (hsotg->plat && hsotg->plat->phy_exit)
2775 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2777 phy_power_off(hsotg->phy);
2778 phy_exit(hsotg->phy);
2783 * s3c_hsotg_init - initalize the usb core
2784 * @hsotg: The driver state
2786 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2788 /* unmask subset of endpoint interrupts */
2790 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2791 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2792 hsotg->regs + DIEPMSK);
2794 writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2795 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2796 hsotg->regs + DOEPMSK);
2798 writel(0, hsotg->regs + DAINTMSK);
2800 /* Be in disconnected state until gadget is registered */
2801 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2804 /* post global nak until we're ready */
2805 writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2806 hsotg->regs + DCTL);
2811 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2812 readl(hsotg->regs + GRXFSIZ),
2813 readl(hsotg->regs + GNPTXFSIZ));
2815 s3c_hsotg_init_fifo(hsotg);
2817 /* set the PLL on, remove the HNP/SRP and set the PHY */
2818 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2819 hsotg->regs + GUSBCFG);
2821 writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
2822 hsotg->regs + GAHBCFG);
2826 * s3c_hsotg_udc_start - prepare the udc for work
2827 * @gadget: The usb gadget state
2828 * @driver: The usb gadget driver
2830 * Perform initialization to prepare udc device and driver
2833 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2834 struct usb_gadget_driver *driver)
2836 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2840 pr_err("%s: called with no device\n", __func__);
2845 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2849 if (driver->max_speed < USB_SPEED_FULL)
2850 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2852 if (!driver->setup) {
2853 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2857 WARN_ON(hsotg->driver);
2859 driver->driver.bus = NULL;
2860 hsotg->driver = driver;
2861 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
2862 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2864 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2867 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2871 hsotg->last_rst = jiffies;
2872 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2876 hsotg->driver = NULL;
2881 * s3c_hsotg_udc_stop - stop the udc
2882 * @gadget: The usb gadget state
2883 * @driver: The usb gadget driver
2885 * Stop udc hw block and stay tunned for future transmissions
2887 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
2888 struct usb_gadget_driver *driver)
2890 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2891 unsigned long flags = 0;
2897 /* all endpoints should be shutdown */
2898 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2899 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2901 spin_lock_irqsave(&hsotg->lock, flags);
2904 hsotg->driver = NULL;
2906 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2908 spin_unlock_irqrestore(&hsotg->lock, flags);
2910 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2916 * s3c_hsotg_gadget_getframe - read the frame number
2917 * @gadget: The usb gadget state
2919 * Read the {micro} frame number
2921 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2923 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2927 * s3c_hsotg_pullup - connect/disconnect the USB PHY
2928 * @gadget: The usb gadget state
2929 * @is_on: Current state of the USB PHY
2931 * Connect/Disconnect the USB PHY pullup
2933 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
2935 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2936 unsigned long flags = 0;
2938 dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on);
2940 spin_lock_irqsave(&hsotg->lock, flags);
2942 s3c_hsotg_phy_enable(hsotg);
2943 s3c_hsotg_core_init(hsotg);
2945 s3c_hsotg_phy_disable(hsotg);
2948 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2949 spin_unlock_irqrestore(&hsotg->lock, flags);
2954 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2955 .get_frame = s3c_hsotg_gadget_getframe,
2956 .udc_start = s3c_hsotg_udc_start,
2957 .udc_stop = s3c_hsotg_udc_stop,
2958 .pullup = s3c_hsotg_pullup,
2962 * s3c_hsotg_initep - initialise a single endpoint
2963 * @hsotg: The device state.
2964 * @hs_ep: The endpoint to be initialised.
2965 * @epnum: The endpoint number
2967 * Initialise the given endpoint (as part of the probe and device state
2968 * creation) to give to the gadget driver. Setup the endpoint name, any
2969 * direction information and other state that may be required.
2971 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2972 struct s3c_hsotg_ep *hs_ep,
2980 else if ((epnum % 2) == 0) {
2987 hs_ep->index = epnum;
2989 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2991 INIT_LIST_HEAD(&hs_ep->queue);
2992 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2994 /* add to the list of endpoints known by the gadget driver */
2996 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2998 hs_ep->parent = hsotg;
2999 hs_ep->ep.name = hs_ep->name;
3000 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3001 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3004 * Read the FIFO size for the Periodic TX FIFO, even if we're
3005 * an OUT endpoint, we may as well do this if in future the
3006 * code is changed to make each endpoint's direction changeable.
3009 ptxfifo = readl(hsotg->regs + DPTXFSIZN(epnum));
3010 hs_ep->fifo_size = FIFOSIZE_DEPTH_GET(ptxfifo) * 4;
3013 * if we're using dma, we need to set the next-endpoint pointer
3014 * to be something valid.
3017 if (using_dma(hsotg)) {
3018 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3019 writel(next, hsotg->regs + DIEPCTL(epnum));
3020 writel(next, hsotg->regs + DOEPCTL(epnum));
3025 * s3c_hsotg_hw_cfg - read HW configuration registers
3026 * @param: The device state
3028 * Read the USB core HW configuration registers
3030 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3033 /* check hardware configuration */
3035 cfg2 = readl(hsotg->regs + 0x48);
3036 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3038 dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
3040 cfg4 = readl(hsotg->regs + 0x50);
3041 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3043 dev_info(hsotg->dev, "%s fifos\n",
3044 hsotg->dedicated_fifos ? "dedicated" : "shared");
3048 * s3c_hsotg_dump - dump state of the udc
3049 * @param: The device state
3051 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3054 struct device *dev = hsotg->dev;
3055 void __iomem *regs = hsotg->regs;
3059 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3060 readl(regs + DCFG), readl(regs + DCTL),
3061 readl(regs + DIEPMSK));
3063 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3064 readl(regs + GAHBCFG), readl(regs + 0x44));
3066 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3067 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3069 /* show periodic fifo settings */
3071 for (idx = 1; idx <= 15; idx++) {
3072 val = readl(regs + DPTXFSIZN(idx));
3073 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3074 val >> FIFOSIZE_DEPTH_SHIFT,
3075 val & FIFOSIZE_STARTADDR_MASK);
3078 for (idx = 0; idx < 15; idx++) {
3080 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3081 readl(regs + DIEPCTL(idx)),
3082 readl(regs + DIEPTSIZ(idx)),
3083 readl(regs + DIEPDMA(idx)));
3085 val = readl(regs + DOEPCTL(idx));
3087 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3088 idx, readl(regs + DOEPCTL(idx)),
3089 readl(regs + DOEPTSIZ(idx)),
3090 readl(regs + DOEPDMA(idx)));
3094 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3095 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3100 * state_show - debugfs: show overall driver and device state.
3101 * @seq: The seq file to write to.
3102 * @v: Unused parameter.
3104 * This debugfs entry shows the overall state of the hardware and
3105 * some general information about each of the endpoints available
3108 static int state_show(struct seq_file *seq, void *v)
3110 struct s3c_hsotg *hsotg = seq->private;
3111 void __iomem *regs = hsotg->regs;
3114 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3117 readl(regs + DSTS));
3119 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3120 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3122 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3123 readl(regs + GINTMSK),
3124 readl(regs + GINTSTS));
3126 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3127 readl(regs + DAINTMSK),
3128 readl(regs + DAINT));
3130 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3131 readl(regs + GNPTXSTS),
3132 readl(regs + GRXSTSR));
3134 seq_puts(seq, "\nEndpoint status:\n");
3136 for (idx = 0; idx < 15; idx++) {
3139 in = readl(regs + DIEPCTL(idx));
3140 out = readl(regs + DOEPCTL(idx));
3142 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3145 in = readl(regs + DIEPTSIZ(idx));
3146 out = readl(regs + DOEPTSIZ(idx));
3148 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3151 seq_puts(seq, "\n");
3157 static int state_open(struct inode *inode, struct file *file)
3159 return single_open(file, state_show, inode->i_private);
3162 static const struct file_operations state_fops = {
3163 .owner = THIS_MODULE,
3166 .llseek = seq_lseek,
3167 .release = single_release,
3171 * fifo_show - debugfs: show the fifo information
3172 * @seq: The seq_file to write data to.
3173 * @v: Unused parameter.
3175 * Show the FIFO information for the overall fifo and all the
3176 * periodic transmission FIFOs.
3178 static int fifo_show(struct seq_file *seq, void *v)
3180 struct s3c_hsotg *hsotg = seq->private;
3181 void __iomem *regs = hsotg->regs;
3185 seq_puts(seq, "Non-periodic FIFOs:\n");
3186 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3188 val = readl(regs + GNPTXFSIZ);
3189 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3190 val >> FIFOSIZE_DEPTH_SHIFT,
3191 val & FIFOSIZE_DEPTH_MASK);
3193 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3195 for (idx = 1; idx <= 15; idx++) {
3196 val = readl(regs + DPTXFSIZN(idx));
3198 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3199 val >> FIFOSIZE_DEPTH_SHIFT,
3200 val & FIFOSIZE_STARTADDR_MASK);
3206 static int fifo_open(struct inode *inode, struct file *file)
3208 return single_open(file, fifo_show, inode->i_private);
3211 static const struct file_operations fifo_fops = {
3212 .owner = THIS_MODULE,
3215 .llseek = seq_lseek,
3216 .release = single_release,
3220 static const char *decode_direction(int is_in)
3222 return is_in ? "in" : "out";
3226 * ep_show - debugfs: show the state of an endpoint.
3227 * @seq: The seq_file to write data to.
3228 * @v: Unused parameter.
3230 * This debugfs entry shows the state of the given endpoint (one is
3231 * registered for each available).
3233 static int ep_show(struct seq_file *seq, void *v)
3235 struct s3c_hsotg_ep *ep = seq->private;
3236 struct s3c_hsotg *hsotg = ep->parent;
3237 struct s3c_hsotg_req *req;
3238 void __iomem *regs = hsotg->regs;
3239 int index = ep->index;
3240 int show_limit = 15;
3241 unsigned long flags;
3243 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3244 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3246 /* first show the register state */
3248 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3249 readl(regs + DIEPCTL(index)),
3250 readl(regs + DOEPCTL(index)));
3252 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3253 readl(regs + DIEPDMA(index)),
3254 readl(regs + DOEPDMA(index)));
3256 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3257 readl(regs + DIEPINT(index)),
3258 readl(regs + DOEPINT(index)));
3260 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3261 readl(regs + DIEPTSIZ(index)),
3262 readl(regs + DOEPTSIZ(index)));
3264 seq_puts(seq, "\n");
3265 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3266 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3268 seq_printf(seq, "request list (%p,%p):\n",
3269 ep->queue.next, ep->queue.prev);
3271 spin_lock_irqsave(&hsotg->lock, flags);
3273 list_for_each_entry(req, &ep->queue, queue) {
3274 if (--show_limit < 0) {
3275 seq_puts(seq, "not showing more requests...\n");
3279 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3280 req == ep->req ? '*' : ' ',
3281 req, req->req.length, req->req.buf);
3282 seq_printf(seq, "%d done, res %d\n",
3283 req->req.actual, req->req.status);
3286 spin_unlock_irqrestore(&hsotg->lock, flags);
3291 static int ep_open(struct inode *inode, struct file *file)
3293 return single_open(file, ep_show, inode->i_private);
3296 static const struct file_operations ep_fops = {
3297 .owner = THIS_MODULE,
3300 .llseek = seq_lseek,
3301 .release = single_release,
3305 * s3c_hsotg_create_debug - create debugfs directory and files
3306 * @hsotg: The driver state
3308 * Create the debugfs files to allow the user to get information
3309 * about the state of the system. The directory name is created
3310 * with the same name as the device itself, in case we end up
3311 * with multiple blocks in future systems.
3313 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3315 struct dentry *root;
3318 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3319 hsotg->debug_root = root;
3321 dev_err(hsotg->dev, "cannot create debug root\n");
3325 /* create general state file */
3327 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3328 hsotg, &state_fops);
3330 if (IS_ERR(hsotg->debug_file))
3331 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3333 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3336 if (IS_ERR(hsotg->debug_fifo))
3337 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3339 /* create one file for each endpoint */
3341 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3342 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3344 ep->debugfs = debugfs_create_file(ep->name, 0444,
3345 root, ep, &ep_fops);
3347 if (IS_ERR(ep->debugfs))
3348 dev_err(hsotg->dev, "failed to create %s debug file\n",
3354 * s3c_hsotg_delete_debug - cleanup debugfs entries
3355 * @hsotg: The driver state
3357 * Cleanup (remove) the debugfs files for use on module exit.
3359 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3363 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3364 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3365 debugfs_remove(ep->debugfs);
3368 debugfs_remove(hsotg->debug_file);
3369 debugfs_remove(hsotg->debug_fifo);
3370 debugfs_remove(hsotg->debug_root);
3374 * s3c_hsotg_probe - probe function for hsotg driver
3375 * @pdev: The platform information for the driver
3378 static int s3c_hsotg_probe(struct platform_device *pdev)
3380 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3382 struct usb_phy *uphy;
3383 struct device *dev = &pdev->dev;
3384 struct s3c_hsotg_ep *eps;
3385 struct s3c_hsotg *hsotg;
3386 struct resource *res;
3391 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3396 * Attempt to find a generic PHY, then look for an old style
3397 * USB PHY, finally fall back to pdata
3399 phy = devm_phy_get(&pdev->dev, "usb2-phy");
3401 uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3403 /* Fallback for pdata */
3404 plat = dev_get_platdata(&pdev->dev);
3407 "no platform data or transceiver defined\n");
3408 return -EPROBE_DEFER;
3418 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3419 if (IS_ERR(hsotg->clk)) {
3420 dev_err(dev, "cannot get otg clock\n");
3421 return PTR_ERR(hsotg->clk);
3424 platform_set_drvdata(pdev, hsotg);
3426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3428 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3429 if (IS_ERR(hsotg->regs)) {
3430 ret = PTR_ERR(hsotg->regs);
3434 ret = platform_get_irq(pdev, 0);
3436 dev_err(dev, "cannot find IRQ\n");
3440 spin_lock_init(&hsotg->lock);
3444 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3446 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3447 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3448 hsotg->gadget.name = dev_name(dev);
3450 /* reset the system */
3452 clk_prepare_enable(hsotg->clk);
3456 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3457 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3459 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3462 dev_err(dev, "failed to request supplies: %d\n", ret);
3466 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3470 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3474 /* Set default UTMI width */
3475 hsotg->phyif = GUSBCFG_PHYIF16;
3478 * If using the generic PHY framework, check if the PHY bus
3479 * width is 8-bit and set the phyif appropriately.
3481 if (hsotg->phy && (phy_get_bus_width(phy) == 8))
3482 hsotg->phyif = GUSBCFG_PHYIF8;
3484 /* usb phy enable */
3485 s3c_hsotg_phy_enable(hsotg);
3487 s3c_hsotg_corereset(hsotg);
3488 s3c_hsotg_init(hsotg);
3489 s3c_hsotg_hw_cfg(hsotg);
3491 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3492 dev_name(dev), hsotg);
3494 s3c_hsotg_phy_disable(hsotg);
3495 clk_disable_unprepare(hsotg->clk);
3496 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3498 dev_err(dev, "cannot claim IRQ\n");
3502 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3504 if (hsotg->num_of_eps == 0) {
3505 dev_err(dev, "wrong number of EPs (zero)\n");
3510 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3519 /* setup endpoint information */
3521 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3522 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3524 /* allocate EP0 request */
3526 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3528 if (!hsotg->ctrl_req) {
3529 dev_err(dev, "failed to allocate ctrl req\n");
3534 /* initialise the endpoints now the core has been initialised */
3535 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3536 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3538 /* disable power and clock */
3540 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3543 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3547 s3c_hsotg_phy_disable(hsotg);
3549 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3553 s3c_hsotg_create_debug(hsotg);
3555 s3c_hsotg_dump(hsotg);
3562 s3c_hsotg_phy_disable(hsotg);
3564 clk_disable_unprepare(hsotg->clk);
3570 * s3c_hsotg_remove - remove function for hsotg driver
3571 * @pdev: The platform information for the driver
3573 static int s3c_hsotg_remove(struct platform_device *pdev)
3575 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3577 usb_del_gadget_udc(&hsotg->gadget);
3579 s3c_hsotg_delete_debug(hsotg);
3581 if (hsotg->driver) {
3582 /* should have been done already by driver model core */
3583 usb_gadget_unregister_driver(hsotg->driver);
3586 clk_disable_unprepare(hsotg->clk);
3591 static int s3c_hsotg_suspend(struct platform_device *pdev, pm_message_t state)
3593 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3594 unsigned long flags;
3598 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3599 hsotg->driver->driver.name);
3601 spin_lock_irqsave(&hsotg->lock, flags);
3602 s3c_hsotg_disconnect(hsotg);
3603 s3c_hsotg_phy_disable(hsotg);
3604 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3605 spin_unlock_irqrestore(&hsotg->lock, flags);
3607 if (hsotg->driver) {
3609 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3610 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3612 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3619 static int s3c_hsotg_resume(struct platform_device *pdev)
3621 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3622 unsigned long flags;
3625 if (hsotg->driver) {
3626 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3627 hsotg->driver->driver.name);
3628 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3632 spin_lock_irqsave(&hsotg->lock, flags);
3633 hsotg->last_rst = jiffies;
3634 s3c_hsotg_phy_enable(hsotg);
3635 s3c_hsotg_core_init(hsotg);
3636 spin_unlock_irqrestore(&hsotg->lock, flags);
3642 static const struct of_device_id s3c_hsotg_of_ids[] = {
3643 { .compatible = "samsung,s3c6400-hsotg", },
3644 { .compatible = "snps,dwc2", },
3647 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3650 static struct platform_driver s3c_hsotg_driver = {
3652 .name = "s3c-hsotg",
3653 .owner = THIS_MODULE,
3654 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3656 .probe = s3c_hsotg_probe,
3657 .remove = s3c_hsotg_remove,
3658 .suspend = s3c_hsotg_suspend,
3659 .resume = s3c_hsotg_resume,
3662 module_platform_driver(s3c_hsotg_driver);
3664 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3665 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3666 MODULE_LICENSE("GPL");
3667 MODULE_ALIAS("platform:s3c-hsotg");