drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         defined(CONFIG_DEBUG_LL) &&             \
  57         !defined(MODULE)
  58
  59 extern void printascii(const char *);
  60
  61 __printf(1, 2)
  62 static void dbg(const char *fmt, ...)
  63 {
  64         va_list va;
  65         char buff[256];
  66
  67         va_start(va, fmt);
  68         vscnprintf(buff, sizeof(buff), fmt, va);
  69         va_end(va);
  70
  71         printascii(buff);
  72 }
  73
  74 #else
  75 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  76 #endif
  77
  78 /* UART name and device definitions */
  79
  80 #define S3C24XX_SERIAL_NAME     "ttySAC"
  81 #define S3C24XX_SERIAL_MAJOR    204
  82 #define S3C24XX_SERIAL_MINOR    64
  83
  84 #define S3C24XX_TX_PIO                  1
  85 #define S3C24XX_TX_DMA                  2
  86 #define S3C24XX_RX_PIO                  1
  87 #define S3C24XX_RX_DMA                  2
  88 /* macros to change one thing to another */
  89
  90 #define tx_enabled(port) ((port)->unused[0])
  91 #define rx_enabled(port) ((port)->unused[1])
  92
  93 /* flag to ignore all characters coming in */
  94 #define RXSTAT_DUMMY_READ (0x10000000)
  95
  96 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  97 {
  98         return container_of(port, struct s3c24xx_uart_port, port);
  99 }
 100
 101 /* translate a port to the device name */
 102
 103 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 104 {
 105         return to_platform_device(port->dev)->name;
 106 }
 107
 108 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 109 {
 110         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 111 }
 112
 113 /*
 114  * s3c64xx and later SoC's include the interrupt mask and status registers in
 115  * the controller itself, unlike the s3c24xx SoC's which have these registers
 116  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 117  */
 118 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 119 {
 120         return to_ourport(port)->info->type == PORT_S3C6400;
 121 }
 122
 123 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 124 {
 125         unsigned long flags;
 126         unsigned int ucon, ufcon;
 127         int count = 10000;
 128
 129         spin_lock_irqsave(&port->lock, flags);
 130
 131         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 132                 udelay(100);
 133
 134         ufcon = rd_regl(port, S3C2410_UFCON);
 135         ufcon |= S3C2410_UFCON_RESETRX;
 136         wr_regl(port, S3C2410_UFCON, ufcon);
 137
 138         ucon = rd_regl(port, S3C2410_UCON);
 139         ucon |= S3C2410_UCON_RXIRQMODE;
 140         wr_regl(port, S3C2410_UCON, ucon);
 141
 142         rx_enabled(port) = 1;
 143         spin_unlock_irqrestore(&port->lock, flags);
 144 }
 145
 146 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 147 {
 148         unsigned long flags;
 149         unsigned int ucon;
 150
 151         spin_lock_irqsave(&port->lock, flags);
 152
 153         ucon = rd_regl(port, S3C2410_UCON);
 154         ucon &= ~S3C2410_UCON_RXIRQMODE;
 155         wr_regl(port, S3C2410_UCON, ucon);
 156
 157         rx_enabled(port) = 0;
 158         spin_unlock_irqrestore(&port->lock, flags);
 159 }
 160
 161 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 162 {
 163         struct s3c24xx_uart_port *ourport = to_ourport(port);
 164         struct s3c24xx_uart_dma *dma = ourport->dma;
 165         struct circ_buf *xmit = &port->state->xmit;
 166         struct dma_tx_state state;
 167         int count;
 168
 169         if (!tx_enabled(port))
 170                 return;
 171
 172         if (s3c24xx_serial_has_interrupt_mask(port))
 173                 __set_bit(S3C64XX_UINTM_TXD,
 174                         portaddrl(port, S3C64XX_UINTM));
 175         else
 176                 disable_irq_nosync(ourport->tx_irq);
 177
 178         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 179                 dmaengine_pause(dma->tx_chan);
 180                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 181                 dmaengine_terminate_all(dma->tx_chan);
 182                 dma_sync_single_for_cpu(ourport->port.dev,
 183                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 184                 async_tx_ack(dma->tx_desc);
 185                 count = dma->tx_bytes_requested - state.residue;
 186                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 187                 port->icount.tx += count;
 188         }
 189
 190         tx_enabled(port) = 0;
 191         ourport->tx_in_progress = 0;
 192
 193         if (port->flags & UPF_CONS_FLOW)
 194                 s3c24xx_serial_rx_enable(port);
 195
 196         ourport->tx_mode = 0;
 197 }
 198
 199 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 200
 201 static void s3c24xx_serial_tx_dma_complete(void *args)
 202 {
 203         struct s3c24xx_uart_port *ourport = args;
 204         struct uart_port *port = &ourport->port;
 205         struct circ_buf *xmit = &port->state->xmit;
 206         struct s3c24xx_uart_dma *dma = ourport->dma;
 207         struct dma_tx_state state;
 208         unsigned long flags;
 209         int count;
 210
 211
 212         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 213         count = dma->tx_bytes_requested - state.residue;
 214         async_tx_ack(dma->tx_desc);
 215
 216         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 217                                 dma->tx_size, DMA_TO_DEVICE);
 218
 219         spin_lock_irqsave(&port->lock, flags);
 220
 221         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 222         port->icount.tx += count;
 223         ourport->tx_in_progress = 0;
 224
 225         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 226                 uart_write_wakeup(port);
 227
 228         s3c24xx_serial_start_next_tx(ourport);
 229         spin_unlock_irqrestore(&port->lock, flags);
 230 }
 231
 232 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 233 {
 234         struct uart_port *port = &ourport->port;
 235         u32 ucon;
 236
 237         /* Mask Tx interrupt */
 238         if (s3c24xx_serial_has_interrupt_mask(port))
 239                 __set_bit(S3C64XX_UINTM_TXD,
 240                           portaddrl(port, S3C64XX_UINTM));
 241         else
 242                 disable_irq_nosync(ourport->tx_irq);
 243
 244         /* Enable tx dma mode */
 245         ucon = rd_regl(port, S3C2410_UCON);
 246         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 247         ucon |= (dma_get_cache_alignment() >= 16) ?
 248                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 249         ucon |= S3C64XX_UCON_TXMODE_DMA;
 250         wr_regl(port,  S3C2410_UCON, ucon);
 251
 252         ourport->tx_mode = S3C24XX_TX_DMA;
 253 }
 254
 255 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 256 {
 257         struct uart_port *port = &ourport->port;
 258         u32 ucon, ufcon;
 259
 260         /* Set ufcon txtrig */
 261         ourport->tx_in_progress = S3C24XX_TX_PIO;
 262         ufcon = rd_regl(port, S3C2410_UFCON);
 263         wr_regl(port,  S3C2410_UFCON, ufcon);
 264
 265         /* Enable tx pio mode */
 266         ucon = rd_regl(port, S3C2410_UCON);
 267         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 268         ucon |= S3C64XX_UCON_TXMODE_CPU;
 269         wr_regl(port,  S3C2410_UCON, ucon);
 270
 271         /* Unmask Tx interrupt */
 272         if (s3c24xx_serial_has_interrupt_mask(port))
 273                 __clear_bit(S3C64XX_UINTM_TXD,
 274                             portaddrl(port, S3C64XX_UINTM));
 275         else
 276                 enable_irq(ourport->tx_irq);
 277
 278         ourport->tx_mode = S3C24XX_TX_PIO;
 279 }
 280
 281 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 282 {
 283         if (ourport->tx_mode != S3C24XX_TX_PIO)
 284                 enable_tx_pio(ourport);
 285 }
 286
 287 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 288                                       unsigned int count)
 289 {
 290         struct uart_port *port = &ourport->port;
 291         struct circ_buf *xmit = &port->state->xmit;
 292         struct s3c24xx_uart_dma *dma = ourport->dma;
 293
 294
 295         if (ourport->tx_mode != S3C24XX_TX_DMA)
 296                 enable_tx_dma(ourport);
 297
 298         while (xmit->tail & (dma_get_cache_alignment() - 1)) {
 299                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 300                         return 0;
 301                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 302                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 303                 port->icount.tx++;
 304                 count--;
 305         }
 306
 307         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 308         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 309
 310         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 311                                 dma->tx_size, DMA_TO_DEVICE);
 312
 313         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 314                                 dma->tx_transfer_addr, dma->tx_size,
 315                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 316         if (!dma->tx_desc) {
 317                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 318                 return -EIO;
 319         }
 320
 321         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 322         dma->tx_desc->callback_param = ourport;
 323         dma->tx_bytes_requested = dma->tx_size;
 324
 325         ourport->tx_in_progress = S3C24XX_TX_DMA;
 326         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 327         dma_async_issue_pending(dma->tx_chan);
 328         return 0;
 329 }
 330
 331 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 332 {
 333         struct uart_port *port = &ourport->port;
 334         struct circ_buf *xmit = &port->state->xmit;
 335         unsigned long count;
 336
 337         /* Get data size up to the end of buffer */
 338         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 339
 340         if (!count) {
 341                 s3c24xx_serial_stop_tx(port);
 342                 return;
 343         }
 344
 345         if (!ourport->dma || !ourport->dma->tx_chan || count < port->fifosize)
 346                 s3c24xx_serial_start_tx_pio(ourport);
 347         else
 348                 s3c24xx_serial_start_tx_dma(ourport, count);
 349 }
 350
 351 void s3c24xx_serial_start_tx(struct uart_port *port)
 352 {
 353         struct s3c24xx_uart_port *ourport = to_ourport(port);
 354         struct circ_buf *xmit = &port->state->xmit;
 355
 356         if (!tx_enabled(port)) {
 357                 if (port->flags & UPF_CONS_FLOW)
 358                         s3c24xx_serial_rx_disable(port);
 359
 360                 tx_enabled(port) = 1;
 361                 if (!ourport->dma || !ourport->dma->tx_chan)
 362                         s3c24xx_serial_start_tx_pio(ourport);
 363         }
 364
 365         if (ourport->dma && ourport->dma->tx_chan) {
 366                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 367                         s3c24xx_serial_start_next_tx(ourport);
 368         }
 369 }
 370
 371 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 372                 struct tty_port *tty, int count)
 373 {
 374         struct s3c24xx_uart_dma *dma = ourport->dma;
 375         int copied;
 376
 377         if (!count)
 378                 return;
 379
 380         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 381                                 dma->rx_size, DMA_FROM_DEVICE);
 382
 383         ourport->port.icount.rx += count;
 384         if (!tty) {
 385                 dev_err(ourport->port.dev, "No tty port\n");
 386                 return;
 387         }
 388         copied = tty_insert_flip_string(tty,
 389                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 390         if (copied != count) {
 391                 WARN_ON(1);
 392                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 393         }
 394 }
 395
 396 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 397                                      unsigned long ufstat);
 398
 399 static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 400 {
 401         struct uart_port *port = &ourport->port;
 402         struct tty_port *tty = &port->state->port;
 403         unsigned int ch, ufstat;
 404         unsigned int count;
 405
 406         ufstat = rd_regl(port, S3C2410_UFSTAT);
 407         count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 408
 409         if (!count)
 410                 return;
 411
 412         while (count-- > 0) {
 413                 ch = rd_regb(port, S3C2410_URXH);
 414
 415                 ourport->port.icount.rx++;
 416                 tty_insert_flip_char(tty, ch, TTY_NORMAL);
 417         }
 418
 419         tty_flip_buffer_push(tty);
 420 }
 421
 422 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 423 {
 424         struct s3c24xx_uart_port *ourport = to_ourport(port);
 425         struct s3c24xx_uart_dma *dma = ourport->dma;
 426         struct tty_port *t = &port->state->port;
 427         struct dma_tx_state state;
 428         enum dma_status dma_status;
 429         unsigned int received;
 430
 431         if (rx_enabled(port)) {
 432                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 433                 if (s3c24xx_serial_has_interrupt_mask(port))
 434                         __set_bit(S3C64XX_UINTM_RXD,
 435                                 portaddrl(port, S3C64XX_UINTM));
 436                 else
 437                         disable_irq_nosync(ourport->rx_irq);
 438                 rx_enabled(port) = 0;
 439         }
 440         if (dma && dma->rx_chan) {
 441                 dmaengine_pause(dma->tx_chan);
 442                 dma_status = dmaengine_tx_status(dma->rx_chan,
 443                                 dma->rx_cookie, &state);
 444                 if (dma_status == DMA_IN_PROGRESS ||
 445                         dma_status == DMA_PAUSED) {
 446                         received = dma->rx_bytes_requested - state.residue;
 447                         dmaengine_terminate_all(dma->rx_chan);
 448                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 449                 }
 450         }
 451 }
 452
 453 static inline struct s3c24xx_uart_info
 454         *s3c24xx_port_to_info(struct uart_port *port)
 455 {
 456         return to_ourport(port)->info;
 457 }
 458
 459 static inline struct s3c2410_uartcfg
 460         *s3c24xx_port_to_cfg(struct uart_port *port)
 461 {
 462         struct s3c24xx_uart_port *ourport;
 463
 464         if (port->dev == NULL)
 465                 return NULL;
 466
 467         ourport = container_of(port, struct s3c24xx_uart_port, port);
 468         return ourport->cfg;
 469 }
 470
 471 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 472                                      unsigned long ufstat)
 473 {
 474         struct s3c24xx_uart_info *info = ourport->info;
 475
 476         if (ufstat & info->rx_fifofull)
 477                 return ourport->port.fifosize;
 478
 479         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 480 }
 481
 482 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 483 static void s3c24xx_serial_rx_dma_complete(void *args)
 484 {
 485         struct s3c24xx_uart_port *ourport = args;
 486         struct uart_port *port = &ourport->port;
 487
 488         struct s3c24xx_uart_dma *dma = ourport->dma;
 489         struct tty_port *t = &port->state->port;
 490         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 491
 492         struct dma_tx_state state;
 493         unsigned long flags;
 494         int received;
 495
 496         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 497         received  = dma->rx_bytes_requested - state.residue;
 498         async_tx_ack(dma->rx_desc);
 499
 500         spin_lock_irqsave(&port->lock, flags);
 501
 502         if (received)
 503                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 504
 505         if (tty) {
 506                 tty_flip_buffer_push(t);
 507                 tty_kref_put(tty);
 508         }
 509
 510         s3c64xx_start_rx_dma(ourport);
 511
 512         spin_unlock_irqrestore(&port->lock, flags);
 513 }
 514
 515 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 516 {
 517         struct s3c24xx_uart_dma *dma = ourport->dma;
 518
 519         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 520                                 dma->rx_size, DMA_FROM_DEVICE);
 521
 522         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 523                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 524                                 DMA_PREP_INTERRUPT);
 525         if (!dma->rx_desc) {
 526                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 527                 return;
 528         }
 529
 530         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 531         dma->rx_desc->callback_param = ourport;
 532         dma->rx_bytes_requested = dma->rx_size;
 533
 534         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 535         dma_async_issue_pending(dma->rx_chan);
 536 }
 537
 538 /* ? - where has parity gone?? */
 539 #define S3C2410_UERSTAT_PARITY (0x1000)
 540
 541 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 542 {
 543         struct uart_port *port = &ourport->port;
 544         unsigned int ucon;
 545
 546         /* set Rx mode to DMA mode */
 547         ucon = rd_regl(port, S3C2410_UCON);
 548         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 549                         S3C64XX_UCON_TIMEOUT_MASK |
 550                         S3C64XX_UCON_EMPTYINT_EN |
 551                         S3C64XX_UCON_DMASUS_EN |
 552                         S3C64XX_UCON_TIMEOUT_EN |
 553                         S3C64XX_UCON_RXMODE_MASK);
 554         ucon |= S3C64XX_UCON_RXBURST_16 |
 555                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 556                         S3C64XX_UCON_EMPTYINT_EN |
 557                         S3C64XX_UCON_TIMEOUT_EN |
 558                         S3C64XX_UCON_RXMODE_DMA;
 559         wr_regl(port, S3C2410_UCON, ucon);
 560
 561         ourport->rx_mode = S3C24XX_RX_DMA;
 562 }
 563
 564 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 565 {
 566         struct uart_port *port = &ourport->port;
 567         unsigned int ucon;
 568
 569         /* set Rx mode to DMA mode */
 570         ucon = rd_regl(port, S3C2410_UCON);
 571         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 572                         S3C64XX_UCON_EMPTYINT_EN |
 573                         S3C64XX_UCON_DMASUS_EN |
 574                         S3C64XX_UCON_TIMEOUT_EN |
 575                         S3C64XX_UCON_RXMODE_MASK);
 576         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 577                         S3C64XX_UCON_TIMEOUT_EN |
 578                         S3C64XX_UCON_RXMODE_CPU;
 579         wr_regl(port, S3C2410_UCON, ucon);
 580
 581         ourport->rx_mode = S3C24XX_RX_PIO;
 582 }
 583
 584 static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
 585 {
 586         unsigned int utrstat, ufstat, received;
 587         struct s3c24xx_uart_port *ourport = dev_id;
 588         struct uart_port *port = &ourport->port;
 589         struct s3c24xx_uart_dma *dma = ourport->dma;
 590         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 591         struct tty_port *t = &port->state->port;
 592         unsigned long flags;
 593         struct dma_tx_state state;
 594
 595         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 596         ufstat = rd_regl(port, S3C2410_UFSTAT);
 597
 598         spin_lock_irqsave(&port->lock, flags);
 599
 600         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 601                 s3c64xx_start_rx_dma(ourport);
 602                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 603                         enable_rx_dma(ourport);
 604                 goto finish;
 605         }
 606
 607         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 608                 dmaengine_pause(dma->rx_chan);
 609                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 610                 dmaengine_terminate_all(dma->rx_chan);
 611                 received = dma->rx_bytes_requested - state.residue;
 612                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 613
 614                 enable_rx_pio(ourport);
 615         }
 616
 617         uart_rx_drain_fifo(ourport);
 618
 619         if (tty) {
 620                 tty_flip_buffer_push(t);
 621                 tty_kref_put(tty);
 622         }
 623
 624         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 625
 626 finish:
 627         spin_unlock_irqrestore(&port->lock, flags);
 628
 629         return IRQ_HANDLED;
 630 }
 631
 632 static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
 633 {
 634         struct s3c24xx_uart_port *ourport = dev_id;
 635         struct uart_port *port = &ourport->port;
 636         unsigned int ufcon, ch, flag, ufstat, uerstat;
 637         unsigned long flags;
 638         int max_count = port->fifosize;
 639
 640         spin_lock_irqsave(&port->lock, flags);
 641
 642         while (max_count-- > 0) {
 643                 ufcon = rd_regl(port, S3C2410_UFCON);
 644                 ufstat = rd_regl(port, S3C2410_UFSTAT);
 645
 646                 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
 647                         break;
 648
 649                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 650                 ch = rd_regb(port, S3C2410_URXH);
 651
 652                 if (port->flags & UPF_CONS_FLOW) {
 653                         int txe = s3c24xx_serial_txempty_nofifo(port);
 654
 655                         if (rx_enabled(port)) {
 656                                 if (!txe) {
 657                                         rx_enabled(port) = 0;
 658                                         continue;
 659                                 }
 660                         } else {
 661                                 if (txe) {
 662                                         ufcon |= S3C2410_UFCON_RESETRX;
 663                                         wr_regl(port, S3C2410_UFCON, ufcon);
 664                                         rx_enabled(port) = 1;
 665                                         spin_unlock_irqrestore(&port->lock,
 666                                                         flags);
 667                                         goto out;
 668                                 }
 669                                 continue;
 670                         }
 671                 }
 672
 673                 /* insert the character into the buffer */
 674
 675                 flag = TTY_NORMAL;
 676                 port->icount.rx++;
 677
 678                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 679                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 680                             ch, uerstat);
 681
 682                         /* check for break */
 683                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 684                                 dbg("break!\n");
 685                                 port->icount.brk++;
 686                                 if (uart_handle_break(port))
 687                                         goto ignore_char;
 688                         }
 689
 690                         if (uerstat & S3C2410_UERSTAT_FRAME)
 691                                 port->icount.frame++;
 692                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 693                                 port->icount.overrun++;
 694
 695                         uerstat &= port->read_status_mask;
 696
 697                         if (uerstat & S3C2410_UERSTAT_BREAK)
 698                                 flag = TTY_BREAK;
 699                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 700                                 flag = TTY_PARITY;
 701                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 702                                             S3C2410_UERSTAT_OVERRUN))
 703                                 flag = TTY_FRAME;
 704                 }
 705
 706                 if (uart_handle_sysrq_char(port, ch))
 707                         goto ignore_char;
 708
 709                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 710                                  ch, flag);
 711
 712 ignore_char:
 713                 continue;
 714         }
 715
 716         spin_unlock_irqrestore(&port->lock, flags);
 717         tty_flip_buffer_push(&port->state->port);
 718
 719 out:
 720         return IRQ_HANDLED;
 721 }
 722
 723
 724 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 725 {
 726         struct s3c24xx_uart_port *ourport = dev_id;
 727
 728         if (ourport->dma && ourport->dma->rx_chan)
 729                 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
 730         return s3c24xx_serial_rx_chars_pio(irq, dev_id);
 731 }
 732
 733 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 734 {
 735         struct s3c24xx_uart_port *ourport = id;
 736         struct uart_port *port = &ourport->port;
 737         struct circ_buf *xmit = &port->state->xmit;
 738         unsigned long flags;
 739         int count;
 740
 741         spin_lock_irqsave(&port->lock, flags);
 742
 743         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 744
 745         if (ourport->dma && ourport->dma->tx_chan && count >= port->fifosize) {
 746                 s3c24xx_serial_start_tx_dma(ourport, count);
 747                 goto out;
 748         }
 749
 750         if (port->x_char) {
 751                 wr_regb(port, S3C2410_UTXH, port->x_char);
 752                 port->icount.tx++;
 753                 port->x_char = 0;
 754                 goto out;
 755         }
 756
 757         /* if there isn't anything more to transmit, or the uart is now
 758          * stopped, disable the uart and exit
 759         */
 760
 761         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 762                 s3c24xx_serial_stop_tx(port);
 763                 goto out;
 764         }
 765
 766         /* try and drain the buffer... */
 767
 768         count = port->fifosize;
 769         while (!uart_circ_empty(xmit) && count-- > 0) {
 770                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 771                         break;
 772
 773                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 774                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 775                 port->icount.tx++;
 776         }
 777
 778         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 779                 spin_unlock(&port->lock);
 780                 uart_write_wakeup(port);
 781                 spin_lock(&port->lock);
 782         }
 783
 784         if (uart_circ_empty(xmit))
 785                 s3c24xx_serial_stop_tx(port);
 786
 787 out:
 788         spin_unlock_irqrestore(&port->lock, flags);
 789         return IRQ_HANDLED;
 790 }
 791
 792 /* interrupt handler for s3c64xx and later SoC's.*/
 793 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 794 {
 795         struct s3c24xx_uart_port *ourport = id;
 796         struct uart_port *port = &ourport->port;
 797         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 798         irqreturn_t ret = IRQ_HANDLED;
 799
 800         if (pend & S3C64XX_UINTM_RXD_MSK) {
 801                 ret = s3c24xx_serial_rx_chars(irq, id);
 802                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 803         }
 804         if (pend & S3C64XX_UINTM_TXD_MSK) {
 805                 ret = s3c24xx_serial_tx_chars(irq, id);
 806                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 807         }
 808         return ret;
 809 }
 810
 811 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 812 {
 813         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 814         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 815         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 816
 817         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 818                 if ((ufstat & info->tx_fifomask) != 0 ||
 819                     (ufstat & info->tx_fifofull))
 820                         return 0;
 821
 822                 return 1;
 823         }
 824
 825         return s3c24xx_serial_txempty_nofifo(port);
 826 }
 827
 828 /* no modem control lines */
 829 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 830 {
 831         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 832
 833         if (umstat & S3C2410_UMSTAT_CTS)
 834                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 835         else
 836                 return TIOCM_CAR | TIOCM_DSR;
 837 }
 838
 839 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 840 {
 841         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 842
 843         if (mctrl & TIOCM_RTS)
 844                 umcon |= S3C2410_UMCOM_RTS_LOW;
 845         else
 846                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 847
 848         wr_regl(port, S3C2410_UMCON, umcon);
 849 }
 850
 851 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 852 {
 853         unsigned long flags;
 854         unsigned int ucon;
 855
 856         spin_lock_irqsave(&port->lock, flags);
 857
 858         ucon = rd_regl(port, S3C2410_UCON);
 859
 860         if (break_state)
 861                 ucon |= S3C2410_UCON_SBREAK;
 862         else
 863                 ucon &= ~S3C2410_UCON_SBREAK;
 864
 865         wr_regl(port, S3C2410_UCON, ucon);
 866
 867         spin_unlock_irqrestore(&port->lock, flags);
 868 }
 869
 870 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 871 {
 872         struct s3c24xx_uart_dma *dma = p->dma;
 873         dma_cap_mask_t mask;
 874         unsigned long flags;
 875
 876         /* Default slave configuration parameters */
 877         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 878         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 879         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 880         dma->rx_conf.src_maxburst       = 16;
 881
 882         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 883         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 884         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 885         if (dma_get_cache_alignment() >= 16)
 886                 dma->tx_conf.dst_maxburst = 16;
 887         else
 888                 dma->tx_conf.dst_maxburst = 1;
 889
 890         dma_cap_zero(mask);
 891         dma_cap_set(DMA_SLAVE, mask);
 892
 893         dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 894                                         dma->rx_param, p->port.dev, "rx");
 895         if (!dma->rx_chan)
 896                 return -ENODEV;
 897
 898         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 899
 900         dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 901                                         dma->tx_param, p->port.dev, "tx");
 902         if (!dma->tx_chan) {
 903                 dma_release_channel(dma->rx_chan);
 904                 return -ENODEV;
 905         }
 906
 907         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 908
 909         /* RX buffer */
 910         dma->rx_size = PAGE_SIZE;
 911
 912         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 913
 914         if (!dma->rx_buf) {
 915                 dma_release_channel(dma->rx_chan);
 916                 dma_release_channel(dma->tx_chan);
 917                 return -ENOMEM;
 918         }
 919
 920         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
 921                                 dma->rx_size, DMA_FROM_DEVICE);
 922
 923         spin_lock_irqsave(&p->port.lock, flags);
 924
 925         /* TX buffer */
 926         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
 927                                 p->port.state->xmit.buf,
 928                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 929
 930         spin_unlock_irqrestore(&p->port.lock, flags);
 931
 932         return 0;
 933 }
 934
 935 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 936 {
 937         struct s3c24xx_uart_dma *dma = p->dma;
 938
 939         if (dma->rx_chan) {
 940                 dmaengine_terminate_all(dma->rx_chan);
 941                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
 942                                 dma->rx_size, DMA_FROM_DEVICE);
 943                 kfree(dma->rx_buf);
 944                 dma_release_channel(dma->rx_chan);
 945                 dma->rx_chan = NULL;
 946         }
 947
 948         if (dma->tx_chan) {
 949                 dmaengine_terminate_all(dma->tx_chan);
 950                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
 951                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 952                 dma_release_channel(dma->tx_chan);
 953                 dma->tx_chan = NULL;
 954         }
 955 }
 956
 957 static void s3c24xx_serial_shutdown(struct uart_port *port)
 958 {
 959         struct s3c24xx_uart_port *ourport = to_ourport(port);
 960
 961         if (ourport->tx_claimed) {
 962                 if (!s3c24xx_serial_has_interrupt_mask(port))
 963                         free_irq(ourport->tx_irq, ourport);
 964                 tx_enabled(port) = 0;
 965                 ourport->tx_claimed = 0;
 966         }
 967
 968         if (ourport->rx_claimed) {
 969                 if (!s3c24xx_serial_has_interrupt_mask(port))
 970                         free_irq(ourport->rx_irq, ourport);
 971                 ourport->rx_claimed = 0;
 972                 rx_enabled(port) = 0;
 973         }
 974
 975         /* Clear pending interrupts and mask all interrupts */
 976         if (s3c24xx_serial_has_interrupt_mask(port)) {
 977                 free_irq(port->irq, ourport);
 978
 979                 wr_regl(port, S3C64XX_UINTP, 0xf);
 980                 wr_regl(port, S3C64XX_UINTM, 0xf);
 981         }
 982
 983         if (ourport->dma)
 984                 s3c24xx_serial_release_dma(ourport);
 985
 986         ourport->tx_in_progress = 0;
 987 }
 988
 989 static int s3c24xx_serial_startup(struct uart_port *port)
 990 {
 991         struct s3c24xx_uart_port *ourport = to_ourport(port);
 992         int ret;
 993
 994         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 995             port, (unsigned long long)port->mapbase, port->membase);
 996
 997         rx_enabled(port) = 1;
 998
 999         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1000                           s3c24xx_serial_portname(port), ourport);
1001
1002         if (ret != 0) {
1003                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1004                 return ret;
1005         }
1006
1007         ourport->rx_claimed = 1;
1008
1009         dbg("requesting tx irq...\n");
1010
1011         tx_enabled(port) = 1;
1012
1013         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1014                           s3c24xx_serial_portname(port), ourport);
1015
1016         if (ret) {
1017                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1018                 goto err;
1019         }
1020
1021         ourport->tx_claimed = 1;
1022
1023         dbg("s3c24xx_serial_startup ok\n");
1024
1025         /* the port reset code should have done the correct
1026          * register setup for the port controls */
1027
1028         return ret;
1029
1030 err:
1031         s3c24xx_serial_shutdown(port);
1032         return ret;
1033 }
1034
1035 static int s3c64xx_serial_startup(struct uart_port *port)
1036 {
1037         struct s3c24xx_uart_port *ourport = to_ourport(port);
1038         unsigned long flags;
1039         unsigned int ufcon;
1040         int ret;
1041
1042         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1043             port, (unsigned long long)port->mapbase, port->membase);
1044
1045         wr_regl(port, S3C64XX_UINTM, 0xf);
1046         if (ourport->dma) {
1047                 ret = s3c24xx_serial_request_dma(ourport);
1048                 if (ret < 0) {
1049                         dev_warn(port->dev, "DMA request failed\n");
1050                         return ret;
1051                 }
1052         }
1053
1054         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1055                           s3c24xx_serial_portname(port), ourport);
1056         if (ret) {
1057                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1058                 return ret;
1059         }
1060
1061         /* For compatibility with s3c24xx Soc's */
1062         rx_enabled(port) = 1;
1063         ourport->rx_claimed = 1;
1064         tx_enabled(port) = 0;
1065         ourport->tx_claimed = 1;
1066
1067         spin_lock_irqsave(&port->lock, flags);
1068
1069         ufcon = rd_regl(port, S3C2410_UFCON);
1070         ufcon |= S3C2410_UFCON_RESETRX | S3C2410_UFCON_RESETTX |
1071                         S5PV210_UFCON_RXTRIG8;
1072         wr_regl(port, S3C2410_UFCON, ufcon);
1073
1074         enable_rx_pio(ourport);
1075
1076         spin_unlock_irqrestore(&port->lock, flags);
1077
1078         /* Enable Rx Interrupt */
1079         __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
1080
1081         dbg("s3c64xx_serial_startup ok\n");
1082         return ret;
1083 }
1084
1085 /* power power management control */
1086
1087 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1088                               unsigned int old)
1089 {
1090         struct s3c24xx_uart_port *ourport = to_ourport(port);
1091         int timeout = 10000;
1092
1093         ourport->pm_level = level;
1094
1095         switch (level) {
1096         case 3:
1097                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1098                         udelay(100);
1099
1100                 if (!IS_ERR(ourport->baudclk))
1101                         clk_disable_unprepare(ourport->baudclk);
1102
1103                 clk_disable_unprepare(ourport->clk);
1104                 break;
1105
1106         case 0:
1107                 clk_prepare_enable(ourport->clk);
1108
1109                 if (!IS_ERR(ourport->baudclk))
1110                         clk_prepare_enable(ourport->baudclk);
1111
1112                 break;
1113         default:
1114                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1115         }
1116 }
1117
1118 /* baud rate calculation
1119  *
1120  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1121  * of different sources, including the peripheral clock ("pclk") and an
1122  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1123  * with a programmable extra divisor.
1124  *
1125  * The following code goes through the clock sources, and calculates the
1126  * baud clocks (and the resultant actual baud rates) and then tries to
1127  * pick the closest one and select that.
1128  *
1129 */
1130
1131 #define MAX_CLK_NAME_LENGTH 15
1132
1133 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1134 {
1135         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1136         unsigned int ucon;
1137
1138         if (info->num_clks == 1)
1139                 return 0;
1140
1141         ucon = rd_regl(port, S3C2410_UCON);
1142         ucon &= info->clksel_mask;
1143         return ucon >> info->clksel_shift;
1144 }
1145
1146 static void s3c24xx_serial_setsource(struct uart_port *port,
1147                         unsigned int clk_sel)
1148 {
1149         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1150         unsigned int ucon;
1151
1152         if (info->num_clks == 1)
1153                 return;
1154
1155         ucon = rd_regl(port, S3C2410_UCON);
1156         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1157                 return;
1158
1159         ucon &= ~info->clksel_mask;
1160         ucon |= clk_sel << info->clksel_shift;
1161         wr_regl(port, S3C2410_UCON, ucon);
1162 }
1163
1164 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1165                         unsigned int req_baud, struct clk **best_clk,
1166                         unsigned int *clk_num)
1167 {
1168         struct s3c24xx_uart_info *info = ourport->info;
1169         struct clk *clk;
1170         unsigned long rate;
1171         unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1172         char clkname[MAX_CLK_NAME_LENGTH];
1173         int calc_deviation, deviation = (1 << 30) - 1;
1174
1175         clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1176                         ourport->info->def_clk_sel;
1177         for (cnt = 0; cnt < info->num_clks; cnt++) {
1178                 if (!(clk_sel & (1 << cnt)))
1179                         continue;
1180
1181                 sprintf(clkname, "clk_uart_baud%d", cnt);
1182                 clk = clk_get(ourport->port.dev, clkname);
1183                 if (IS_ERR(clk))
1184                         continue;
1185
1186                 rate = clk_get_rate(clk);
1187                 if (!rate)
1188                         continue;
1189
1190                 if (ourport->info->has_divslot) {
1191                         unsigned long div = rate / req_baud;
1192
1193                         /* The UDIVSLOT register on the newer UARTs allows us to
1194                          * get a divisor adjustment of 1/16th on the baud clock.
1195                          *
1196                          * We don't keep the UDIVSLOT value (the 16ths we
1197                          * calculated by not multiplying the baud by 16) as it
1198                          * is easy enough to recalculate.
1199                          */
1200
1201                         quot = div / 16;
1202                         baud = rate / div;
1203                 } else {
1204                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1205                         baud = rate / (quot * 16);
1206                 }
1207                 quot--;
1208
1209                 calc_deviation = req_baud - baud;
1210                 if (calc_deviation < 0)
1211                         calc_deviation = -calc_deviation;
1212
1213                 if (calc_deviation < deviation) {
1214                         *best_clk = clk;
1215                         best_quot = quot;
1216                         *clk_num = cnt;
1217                         deviation = calc_deviation;
1218                 }
1219         }
1220
1221         return best_quot;
1222 }
1223
1224 /* udivslot_table[]
1225  *
1226  * This table takes the fractional value of the baud divisor and gives
1227  * the recommended setting for the UDIVSLOT register.
1228  */
1229 static u16 udivslot_table[16] = {
1230         [0] = 0x0000,
1231         [1] = 0x0080,
1232         [2] = 0x0808,
1233         [3] = 0x0888,
1234         [4] = 0x2222,
1235         [5] = 0x4924,
1236         [6] = 0x4A52,
1237         [7] = 0x54AA,
1238         [8] = 0x5555,
1239         [9] = 0xD555,
1240         [10] = 0xD5D5,
1241         [11] = 0xDDD5,
1242         [12] = 0xDDDD,
1243         [13] = 0xDFDD,
1244         [14] = 0xDFDF,
1245         [15] = 0xFFDF,
1246 };
1247
1248 static void s3c24xx_serial_set_termios(struct uart_port *port,
1249                                        struct ktermios *termios,
1250                                        struct ktermios *old)
1251 {
1252         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1253         struct s3c24xx_uart_port *ourport = to_ourport(port);
1254         struct clk *clk = ERR_PTR(-EINVAL);
1255         unsigned long flags;
1256         unsigned int baud, quot, clk_sel = 0;
1257         unsigned int ulcon;
1258         unsigned int umcon;
1259         unsigned int udivslot = 0;
1260
1261         /*
1262          * We don't support modem control lines.
1263          */
1264         termios->c_cflag &= ~(HUPCL | CMSPAR);
1265         termios->c_cflag |= CLOCAL;
1266
1267         /*
1268          * Ask the core to calculate the divisor for us.
1269          */
1270
1271         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1272         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1273         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1274                 quot = port->custom_divisor;
1275         if (IS_ERR(clk))
1276                 return;
1277
1278         /* check to see if we need  to change clock source */
1279
1280         if (ourport->baudclk != clk) {
1281                 s3c24xx_serial_setsource(port, clk_sel);
1282
1283                 if (!IS_ERR(ourport->baudclk)) {
1284                         clk_disable_unprepare(ourport->baudclk);
1285                         ourport->baudclk = ERR_PTR(-EINVAL);
1286                 }
1287
1288                 clk_prepare_enable(clk);
1289
1290                 ourport->baudclk = clk;
1291                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1292         }
1293
1294         if (ourport->info->has_divslot) {
1295                 unsigned int div = ourport->baudclk_rate / baud;
1296
1297                 if (cfg->has_fracval) {
1298                         udivslot = (div & 15);
1299                         dbg("fracval = %04x\n", udivslot);
1300                 } else {
1301                         udivslot = udivslot_table[div & 15];
1302                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1303                 }
1304         }
1305
1306         switch (termios->c_cflag & CSIZE) {
1307         case CS5:
1308                 dbg("config: 5bits/char\n");
1309                 ulcon = S3C2410_LCON_CS5;
1310                 break;
1311         case CS6:
1312                 dbg("config: 6bits/char\n");
1313                 ulcon = S3C2410_LCON_CS6;
1314                 break;
1315         case CS7:
1316                 dbg("config: 7bits/char\n");
1317                 ulcon = S3C2410_LCON_CS7;
1318                 break;
1319         case CS8:
1320         default:
1321                 dbg("config: 8bits/char\n");
1322                 ulcon = S3C2410_LCON_CS8;
1323                 break;
1324         }
1325
1326         /* preserve original lcon IR settings */
1327         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1328
1329         if (termios->c_cflag & CSTOPB)
1330                 ulcon |= S3C2410_LCON_STOPB;
1331
1332         if (termios->c_cflag & PARENB) {
1333                 if (termios->c_cflag & PARODD)
1334                         ulcon |= S3C2410_LCON_PODD;
1335                 else
1336                         ulcon |= S3C2410_LCON_PEVEN;
1337         } else {
1338                 ulcon |= S3C2410_LCON_PNONE;
1339         }
1340
1341         spin_lock_irqsave(&port->lock, flags);
1342
1343         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1344             ulcon, quot, udivslot);
1345
1346         wr_regl(port, S3C2410_ULCON, ulcon);
1347         wr_regl(port, S3C2410_UBRDIV, quot);
1348
1349         umcon = rd_regl(port, S3C2410_UMCON);
1350         if (termios->c_cflag & CRTSCTS) {
1351                 umcon |= S3C2410_UMCOM_AFC;
1352                 /* Disable RTS when RX FIFO contains 63 bytes */
1353                 umcon &= ~S3C2412_UMCON_AFC_8;
1354         } else {
1355                 umcon &= ~S3C2410_UMCOM_AFC;
1356         }
1357         wr_regl(port, S3C2410_UMCON, umcon);
1358
1359         if (ourport->info->has_divslot)
1360                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1361
1362         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1363             rd_regl(port, S3C2410_ULCON),
1364             rd_regl(port, S3C2410_UCON),
1365             rd_regl(port, S3C2410_UFCON));
1366
1367         /*
1368          * Update the per-port timeout.
1369          */
1370         uart_update_timeout(port, termios->c_cflag, baud);
1371
1372         /*
1373          * Which character status flags are we interested in?
1374          */
1375         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1376         if (termios->c_iflag & INPCK)
1377                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1378                         S3C2410_UERSTAT_PARITY;
1379         /*
1380          * Which character status flags should we ignore?
1381          */
1382         port->ignore_status_mask = 0;
1383         if (termios->c_iflag & IGNPAR)
1384                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1385         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1386                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1387
1388         /*
1389          * Ignore all characters if CREAD is not set.
1390          */
1391         if ((termios->c_cflag & CREAD) == 0)
1392                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1393
1394         spin_unlock_irqrestore(&port->lock, flags);
1395 }
1396
1397 static const char *s3c24xx_serial_type(struct uart_port *port)
1398 {
1399         switch (port->type) {
1400         case PORT_S3C2410:
1401                 return "S3C2410";
1402         case PORT_S3C2440:
1403                 return "S3C2440";
1404         case PORT_S3C2412:
1405                 return "S3C2412";
1406         case PORT_S3C6400:
1407                 return "S3C6400/10";
1408         default:
1409                 return NULL;
1410         }
1411 }
1412
1413 #define MAP_SIZE (0x100)
1414
1415 static void s3c24xx_serial_release_port(struct uart_port *port)
1416 {
1417         release_mem_region(port->mapbase, MAP_SIZE);
1418 }
1419
1420 static int s3c24xx_serial_request_port(struct uart_port *port)
1421 {
1422         const char *name = s3c24xx_serial_portname(port);
1423         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1424 }
1425
1426 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1427 {
1428         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1429
1430         if (flags & UART_CONFIG_TYPE &&
1431             s3c24xx_serial_request_port(port) == 0)
1432                 port->type = info->type;
1433 }
1434
1435 /*
1436  * verify the new serial_struct (for TIOCSSERIAL).
1437  */
1438 static int
1439 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1440 {
1441         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1442
1443         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1444                 return -EINVAL;
1445
1446         return 0;
1447 }
1448
1449
1450 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1451
1452 static struct console s3c24xx_serial_console;
1453
1454 static int __init s3c24xx_serial_console_init(void)
1455 {
1456         register_console(&s3c24xx_serial_console);
1457         return 0;
1458 }
1459 console_initcall(s3c24xx_serial_console_init);
1460
1461 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1462 #else
1463 #define S3C24XX_SERIAL_CONSOLE NULL
1464 #endif
1465
1466 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1467 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1468 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1469                          unsigned char c);
1470 #endif
1471
1472 static struct uart_ops s3c24xx_serial_ops = {
1473         .pm             = s3c24xx_serial_pm,
1474         .tx_empty       = s3c24xx_serial_tx_empty,
1475         .get_mctrl      = s3c24xx_serial_get_mctrl,
1476         .set_mctrl      = s3c24xx_serial_set_mctrl,
1477         .stop_tx        = s3c24xx_serial_stop_tx,
1478         .start_tx       = s3c24xx_serial_start_tx,
1479         .stop_rx        = s3c24xx_serial_stop_rx,
1480         .break_ctl      = s3c24xx_serial_break_ctl,
1481         .startup        = s3c24xx_serial_startup,
1482         .shutdown       = s3c24xx_serial_shutdown,
1483         .set_termios    = s3c24xx_serial_set_termios,
1484         .type           = s3c24xx_serial_type,
1485         .release_port   = s3c24xx_serial_release_port,
1486         .request_port   = s3c24xx_serial_request_port,
1487         .config_port    = s3c24xx_serial_config_port,
1488         .verify_port    = s3c24xx_serial_verify_port,
1489 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1490         .poll_get_char = s3c24xx_serial_get_poll_char,
1491         .poll_put_char = s3c24xx_serial_put_poll_char,
1492 #endif
1493 };
1494
1495 static struct uart_driver s3c24xx_uart_drv = {
1496         .owner          = THIS_MODULE,
1497         .driver_name    = "s3c2410_serial",
1498         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1499         .cons           = S3C24XX_SERIAL_CONSOLE,
1500         .dev_name       = S3C24XX_SERIAL_NAME,
1501         .major          = S3C24XX_SERIAL_MAJOR,
1502         .minor          = S3C24XX_SERIAL_MINOR,
1503 };
1504
1505 #define __PORT_LOCK_UNLOCKED(i) \
1506         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1507 static struct s3c24xx_uart_port
1508 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1509         [0] = {
1510                 .port = {
1511                         .lock           = __PORT_LOCK_UNLOCKED(0),
1512                         .iotype         = UPIO_MEM,
1513                         .uartclk        = 0,
1514                         .fifosize       = 16,
1515                         .ops            = &s3c24xx_serial_ops,
1516                         .flags          = UPF_BOOT_AUTOCONF,
1517                         .line           = 0,
1518                 }
1519         },
1520         [1] = {
1521                 .port = {
1522                         .lock           = __PORT_LOCK_UNLOCKED(1),
1523                         .iotype         = UPIO_MEM,
1524                         .uartclk        = 0,
1525                         .fifosize       = 16,
1526                         .ops            = &s3c24xx_serial_ops,
1527                         .flags          = UPF_BOOT_AUTOCONF,
1528                         .line           = 1,
1529                 }
1530         },
1531 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1532
1533         [2] = {
1534                 .port = {
1535                         .lock           = __PORT_LOCK_UNLOCKED(2),
1536                         .iotype         = UPIO_MEM,
1537                         .uartclk        = 0,
1538                         .fifosize       = 16,
1539                         .ops            = &s3c24xx_serial_ops,
1540                         .flags          = UPF_BOOT_AUTOCONF,
1541                         .line           = 2,
1542                 }
1543         },
1544 #endif
1545 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1546         [3] = {
1547                 .port = {
1548                         .lock           = __PORT_LOCK_UNLOCKED(3),
1549                         .iotype         = UPIO_MEM,
1550                         .uartclk        = 0,
1551                         .fifosize       = 16,
1552                         .ops            = &s3c24xx_serial_ops,
1553                         .flags          = UPF_BOOT_AUTOCONF,
1554                         .line           = 3,
1555                 }
1556         }
1557 #endif
1558 };
1559 #undef __PORT_LOCK_UNLOCKED
1560
1561 /* s3c24xx_serial_resetport
1562  *
1563  * reset the fifos and other the settings.
1564 */
1565
1566 static void s3c24xx_serial_resetport(struct uart_port *port,
1567                                    struct s3c2410_uartcfg *cfg)
1568 {
1569         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1570         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1571         unsigned int ucon_mask;
1572
1573         ucon_mask = info->clksel_mask;
1574         if (info->type == PORT_S3C2440)
1575                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1576
1577         ucon &= ucon_mask;
1578         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1579
1580         /* reset both fifos */
1581         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1582         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1583
1584         /* some delay is required after fifo reset */
1585         udelay(1);
1586 }
1587
1588
1589 #ifdef CONFIG_CPU_FREQ
1590
1591 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1592                                              unsigned long val, void *data)
1593 {
1594         struct s3c24xx_uart_port *port;
1595         struct uart_port *uport;
1596
1597         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1598         uport = &port->port;
1599
1600         /* check to see if port is enabled */
1601
1602         if (port->pm_level != 0)
1603                 return 0;
1604
1605         /* try and work out if the baudrate is changing, we can detect
1606          * a change in rate, but we do not have support for detecting
1607          * a disturbance in the clock-rate over the change.
1608          */
1609
1610         if (IS_ERR(port->baudclk))
1611                 goto exit;
1612
1613         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1614                 goto exit;
1615
1616         if (val == CPUFREQ_PRECHANGE) {
1617                 /* we should really shut the port down whilst the
1618                  * frequency change is in progress. */
1619
1620         } else if (val == CPUFREQ_POSTCHANGE) {
1621                 struct ktermios *termios;
1622                 struct tty_struct *tty;
1623
1624                 if (uport->state == NULL)
1625                         goto exit;
1626
1627                 tty = uport->state->port.tty;
1628
1629                 if (tty == NULL)
1630                         goto exit;
1631
1632                 termios = &tty->termios;
1633
1634                 if (termios == NULL) {
1635                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1636                         goto exit;
1637                 }
1638
1639                 s3c24xx_serial_set_termios(uport, termios, NULL);
1640         }
1641
1642 exit:
1643         return 0;
1644 }
1645
1646 static inline int
1647 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1648 {
1649         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1650
1651         return cpufreq_register_notifier(&port->freq_transition,
1652                                          CPUFREQ_TRANSITION_NOTIFIER);
1653 }
1654
1655 static inline void
1656 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1657 {
1658         cpufreq_unregister_notifier(&port->freq_transition,
1659                                     CPUFREQ_TRANSITION_NOTIFIER);
1660 }
1661
1662 #else
1663 static inline int
1664 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1665 {
1666         return 0;
1667 }
1668
1669 static inline void
1670 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1671 {
1672 }
1673 #endif
1674
1675 /* s3c24xx_serial_init_port
1676  *
1677  * initialise a single serial port from the platform device given
1678  */
1679
1680 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1681                                     struct platform_device *platdev)
1682 {
1683         struct uart_port *port = &ourport->port;
1684         struct s3c2410_uartcfg *cfg = ourport->cfg;
1685         struct resource *res;
1686         int ret;
1687
1688         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1689
1690         if (platdev == NULL)
1691                 return -ENODEV;
1692
1693         if (port->mapbase != 0)
1694                 return 0;
1695
1696         /* setup info for port */
1697         port->dev       = &platdev->dev;
1698
1699         /* Startup sequence is different for s3c64xx and higher SoC's */
1700         if (s3c24xx_serial_has_interrupt_mask(port))
1701                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1702
1703         port->uartclk = 1;
1704
1705         if (cfg->uart_flags & UPF_CONS_FLOW) {
1706                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1707                 port->flags |= UPF_CONS_FLOW;
1708         }
1709
1710         /* sort our the physical and virtual addresses for each UART */
1711
1712         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1713         if (res == NULL) {
1714                 dev_err(port->dev, "failed to find memory resource for uart\n");
1715                 return -EINVAL;
1716         }
1717
1718         dbg("resource %pR)\n", res);
1719
1720         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1721         if (!port->membase) {
1722                 dev_err(port->dev, "failed to remap controller address\n");
1723                 return -EBUSY;
1724         }
1725
1726         port->mapbase = res->start;
1727         ret = platform_get_irq(platdev, 0);
1728         if (ret < 0)
1729                 port->irq = 0;
1730         else {
1731                 port->irq = ret;
1732                 ourport->rx_irq = ret;
1733                 ourport->tx_irq = ret + 1;
1734         }
1735
1736         ret = platform_get_irq(platdev, 1);
1737         if (ret > 0)
1738                 ourport->tx_irq = ret;
1739         /*
1740          * DMA is currently supported only on DT platforms, if DMA properties
1741          * are specified.
1742          */
1743         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1744                                                      "dmas", NULL)) {
1745                 ourport->dma = devm_kzalloc(port->dev,
1746                                             sizeof(*ourport->dma),
1747                                             GFP_KERNEL);
1748                 if (!ourport->dma)
1749                         return -ENOMEM;
1750         }
1751
1752         ourport->clk    = clk_get(&platdev->dev, "uart");
1753         if (IS_ERR(ourport->clk)) {
1754                 pr_err("%s: Controller clock not found\n",
1755                                 dev_name(&platdev->dev));
1756                 return PTR_ERR(ourport->clk);
1757         }
1758
1759         ret = clk_prepare_enable(ourport->clk);
1760         if (ret) {
1761                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1762                 clk_put(ourport->clk);
1763                 return ret;
1764         }
1765
1766         /* Keep all interrupts masked and cleared */
1767         if (s3c24xx_serial_has_interrupt_mask(port)) {
1768                 wr_regl(port, S3C64XX_UINTM, 0xf);
1769                 wr_regl(port, S3C64XX_UINTP, 0xf);
1770                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1771         }
1772
1773         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1774             &port->mapbase, port->membase, port->irq,
1775             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1776
1777         /* reset the fifos (and setup the uart) */
1778         s3c24xx_serial_resetport(port, cfg);
1779         return 0;
1780 }
1781
1782 /* Device driver serial port probe */
1783
1784 static const struct of_device_id s3c24xx_uart_dt_match[];
1785 static int probe_index;
1786
1787 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1788                         struct platform_device *pdev)
1789 {
1790 #ifdef CONFIG_OF
1791         if (pdev->dev.of_node) {
1792                 const struct of_device_id *match;
1793                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1794                 return (struct s3c24xx_serial_drv_data *)match->data;
1795         }
1796 #endif
1797         return (struct s3c24xx_serial_drv_data *)
1798                         platform_get_device_id(pdev)->driver_data;
1799 }
1800
1801 static int s3c24xx_serial_probe(struct platform_device *pdev)
1802 {
1803         struct device_node *np = pdev->dev.of_node;
1804         struct s3c24xx_uart_port *ourport;
1805         int index = probe_index;
1806         int ret;
1807
1808         if (np) {
1809                 ret = of_alias_get_id(np, "serial");
1810                 if (ret >= 0)
1811                         index = ret;
1812         }
1813
1814         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1815
1816         ourport = &s3c24xx_serial_ports[index];
1817
1818         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1819         if (!ourport->drv_data) {
1820                 dev_err(&pdev->dev, "could not find driver data\n");
1821                 return -ENODEV;
1822         }
1823
1824         ourport->baudclk = ERR_PTR(-EINVAL);
1825         ourport->info = ourport->drv_data->info;
1826         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1827                         dev_get_platdata(&pdev->dev) :
1828                         ourport->drv_data->def_cfg;
1829
1830         if (np)
1831                 of_property_read_u32(np,
1832                         "samsung,uart-fifosize", &ourport->port.fifosize);
1833
1834         if (ourport->drv_data->fifosize[index])
1835                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1836         else if (ourport->info->fifosize)
1837                 ourport->port.fifosize = ourport->info->fifosize;
1838
1839         probe_index++;
1840
1841         dbg("%s: initialising port %p...\n", __func__, ourport);
1842
1843         ret = s3c24xx_serial_init_port(ourport, pdev);
1844         if (ret < 0)
1845                 return ret;
1846
1847         if (!s3c24xx_uart_drv.state) {
1848                 ret = uart_register_driver(&s3c24xx_uart_drv);
1849                 if (ret < 0) {
1850                         pr_err("Failed to register Samsung UART driver\n");
1851                         return ret;
1852                 }
1853         }
1854
1855         dbg("%s: adding port\n", __func__);
1856         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1857         platform_set_drvdata(pdev, &ourport->port);
1858
1859         /*
1860          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1861          * so that a potential re-enablement through the pm-callback overlaps
1862          * and keeps the clock enabled in this case.
1863          */
1864         clk_disable_unprepare(ourport->clk);
1865
1866         ret = s3c24xx_serial_cpufreq_register(ourport);
1867         if (ret < 0)
1868                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1869
1870         return 0;
1871 }
1872
1873 static int s3c24xx_serial_remove(struct platform_device *dev)
1874 {
1875         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1876
1877         if (port) {
1878                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1879                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1880         }
1881
1882         uart_unregister_driver(&s3c24xx_uart_drv);
1883
1884         return 0;
1885 }
1886
1887 /* UART power management code */
1888 #ifdef CONFIG_PM_SLEEP
1889 static int s3c24xx_serial_suspend(struct device *dev)
1890 {
1891         struct uart_port *port = s3c24xx_dev_to_port(dev);
1892
1893         if (port)
1894                 uart_suspend_port(&s3c24xx_uart_drv, port);
1895
1896         return 0;
1897 }
1898
1899 static int s3c24xx_serial_resume(struct device *dev)
1900 {
1901         struct uart_port *port = s3c24xx_dev_to_port(dev);
1902         struct s3c24xx_uart_port *ourport = to_ourport(port);
1903
1904         if (port) {
1905                 clk_prepare_enable(ourport->clk);
1906                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1907                 clk_disable_unprepare(ourport->clk);
1908
1909                 uart_resume_port(&s3c24xx_uart_drv, port);
1910         }
1911
1912         return 0;
1913 }
1914
1915 static int s3c24xx_serial_resume_noirq(struct device *dev)
1916 {
1917         struct uart_port *port = s3c24xx_dev_to_port(dev);
1918
1919         if (port) {
1920                 /* restore IRQ mask */
1921                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1922                         unsigned int uintm = 0xf;
1923                         if (tx_enabled(port))
1924                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1925                         if (rx_enabled(port))
1926                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1927                         wr_regl(port, S3C64XX_UINTM, uintm);
1928                 }
1929         }
1930
1931         return 0;
1932 }
1933
1934 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1935         .suspend = s3c24xx_serial_suspend,
1936         .resume = s3c24xx_serial_resume,
1937         .resume_noirq = s3c24xx_serial_resume_noirq,
1938 };
1939 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1940
1941 #else /* !CONFIG_PM_SLEEP */
1942
1943 #define SERIAL_SAMSUNG_PM_OPS   NULL
1944 #endif /* CONFIG_PM_SLEEP */
1945
1946 /* Console code */
1947
1948 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1949
1950 static struct uart_port *cons_uart;
1951
1952 static int
1953 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1954 {
1955         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1956         unsigned long ufstat, utrstat;
1957
1958         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1959                 /* fifo mode - check amount of data in fifo registers... */
1960
1961                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1962                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1963         }
1964
1965         /* in non-fifo mode, we go and use the tx buffer empty */
1966
1967         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1968         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1969 }
1970
1971 static bool
1972 s3c24xx_port_configured(unsigned int ucon)
1973 {
1974         /* consider the serial port configured if the tx/rx mode set */
1975         return (ucon & 0xf) != 0;
1976 }
1977
1978 #ifdef CONFIG_CONSOLE_POLL
1979 /*
1980  * Console polling routines for writing and reading from the uart while
1981  * in an interrupt or debug context.
1982  */
1983
1984 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1985 {
1986         struct s3c24xx_uart_port *ourport = to_ourport(port);
1987         unsigned int ufstat;
1988
1989         ufstat = rd_regl(port, S3C2410_UFSTAT);
1990         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1991                 return NO_POLL_CHAR;
1992
1993         return rd_regb(port, S3C2410_URXH);
1994 }
1995
1996 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1997                 unsigned char c)
1998 {
1999         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2000         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2001
2002         /* not possible to xmit on unconfigured port */
2003         if (!s3c24xx_port_configured(ucon))
2004                 return;
2005
2006         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2007                 cpu_relax();
2008         wr_regb(port, S3C2410_UTXH, c);
2009 }
2010
2011 #endif /* CONFIG_CONSOLE_POLL */
2012
2013 static void
2014 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2015 {
2016         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2017
2018         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2019                 cpu_relax();
2020         wr_regb(port, S3C2410_UTXH, ch);
2021 }
2022
2023 static void
2024 s3c24xx_serial_console_write(struct console *co, const char *s,
2025                              unsigned int count)
2026 {
2027         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2028
2029         /* not possible to xmit on unconfigured port */
2030         if (!s3c24xx_port_configured(ucon))
2031                 return;
2032
2033         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2034 }
2035
2036 static void __init
2037 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2038                            int *parity, int *bits)
2039 {
2040         struct clk *clk;
2041         unsigned int ulcon;
2042         unsigned int ucon;
2043         unsigned int ubrdiv;
2044         unsigned long rate;
2045         unsigned int clk_sel;
2046         char clk_name[MAX_CLK_NAME_LENGTH];
2047
2048         ulcon  = rd_regl(port, S3C2410_ULCON);
2049         ucon   = rd_regl(port, S3C2410_UCON);
2050         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2051
2052         dbg("s3c24xx_serial_get_options: port=%p\n"
2053             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2054             port, ulcon, ucon, ubrdiv);
2055
2056         if (s3c24xx_port_configured(ucon)) {
2057                 switch (ulcon & S3C2410_LCON_CSMASK) {
2058                 case S3C2410_LCON_CS5:
2059                         *bits = 5;
2060                         break;
2061                 case S3C2410_LCON_CS6:
2062                         *bits = 6;
2063                         break;
2064                 case S3C2410_LCON_CS7:
2065                         *bits = 7;
2066                         break;
2067                 case S3C2410_LCON_CS8:
2068                 default:
2069                         *bits = 8;
2070                         break;
2071                 }
2072
2073                 switch (ulcon & S3C2410_LCON_PMASK) {
2074                 case S3C2410_LCON_PEVEN:
2075                         *parity = 'e';
2076                         break;
2077
2078                 case S3C2410_LCON_PODD:
2079                         *parity = 'o';
2080                         break;
2081
2082                 case S3C2410_LCON_PNONE:
2083                 default:
2084                         *parity = 'n';
2085                 }
2086
2087                 /* now calculate the baud rate */
2088
2089                 clk_sel = s3c24xx_serial_getsource(port);
2090                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2091
2092                 clk = clk_get(port->dev, clk_name);
2093                 if (!IS_ERR(clk))
2094                         rate = clk_get_rate(clk);
2095                 else
2096                         rate = 1;
2097
2098                 *baud = rate / (16 * (ubrdiv + 1));
2099                 dbg("calculated baud %d\n", *baud);
2100         }
2101
2102 }
2103
2104 static int __init
2105 s3c24xx_serial_console_setup(struct console *co, char *options)
2106 {
2107         struct uart_port *port;
2108         int baud = 9600;
2109         int bits = 8;
2110         int parity = 'n';
2111         int flow = 'n';
2112
2113         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2114             co, co->index, options);
2115
2116         /* is this a valid port */
2117
2118         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2119                 co->index = 0;
2120
2121         port = &s3c24xx_serial_ports[co->index].port;
2122
2123         /* is the port configured? */
2124
2125         if (port->mapbase == 0x0)
2126                 return -ENODEV;
2127
2128         cons_uart = port;
2129
2130         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2131
2132         /*
2133          * Check whether an invalid uart number has been specified, and
2134          * if so, search for the first available port that does have
2135          * console support.
2136          */
2137         if (options)
2138                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2139         else
2140                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2141
2142         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2143
2144         return uart_set_options(port, co, baud, parity, bits, flow);
2145 }
2146
2147 static struct console s3c24xx_serial_console = {
2148         .name           = S3C24XX_SERIAL_NAME,
2149         .device         = uart_console_device,
2150         .flags          = CON_PRINTBUFFER,
2151         .index          = -1,
2152         .write          = s3c24xx_serial_console_write,
2153         .setup          = s3c24xx_serial_console_setup,
2154         .data           = &s3c24xx_uart_drv,
2155 };
2156 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2157
2158 #ifdef CONFIG_CPU_S3C2410
2159 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2160         .info = &(struct s3c24xx_uart_info) {
2161                 .name           = "Samsung S3C2410 UART",
2162                 .type           = PORT_S3C2410,
2163                 .fifosize       = 16,
2164                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2165                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2166                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2167                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2168                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2169                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2170                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2171                 .num_clks       = 2,
2172                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2173                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2174         },
2175         .def_cfg = &(struct s3c2410_uartcfg) {
2176                 .ucon           = S3C2410_UCON_DEFAULT,
2177                 .ufcon          = S3C2410_UFCON_DEFAULT,
2178         },
2179 };
2180 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2181 #else
2182 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2183 #endif
2184
2185 #ifdef CONFIG_CPU_S3C2412
2186 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2187         .info = &(struct s3c24xx_uart_info) {
2188                 .name           = "Samsung S3C2412 UART",
2189                 .type           = PORT_S3C2412,
2190                 .fifosize       = 64,
2191                 .has_divslot    = 1,
2192                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2193                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2194                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2195                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2196                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2197                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2198                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2199                 .num_clks       = 4,
2200                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2201                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2202         },
2203         .def_cfg = &(struct s3c2410_uartcfg) {
2204                 .ucon           = S3C2410_UCON_DEFAULT,
2205                 .ufcon          = S3C2410_UFCON_DEFAULT,
2206         },
2207 };
2208 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2209 #else
2210 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2211 #endif
2212
2213 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2214         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2215 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2216         .info = &(struct s3c24xx_uart_info) {
2217                 .name           = "Samsung S3C2440 UART",
2218                 .type           = PORT_S3C2440,
2219                 .fifosize       = 64,
2220                 .has_divslot    = 1,
2221                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2222                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2223                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2224                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2225                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2226                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2227                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2228                 .num_clks       = 4,
2229                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2230                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2231         },
2232         .def_cfg = &(struct s3c2410_uartcfg) {
2233                 .ucon           = S3C2410_UCON_DEFAULT,
2234                 .ufcon          = S3C2410_UFCON_DEFAULT,
2235         },
2236 };
2237 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2238 #else
2239 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2240 #endif
2241
2242 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2243 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2244         .info = &(struct s3c24xx_uart_info) {
2245                 .name           = "Samsung S3C6400 UART",
2246                 .type           = PORT_S3C6400,
2247                 .fifosize       = 64,
2248                 .has_divslot    = 1,
2249                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2250                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2251                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2252                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2253                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2254                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2255                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2256                 .num_clks       = 4,
2257                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2258                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2259         },
2260         .def_cfg = &(struct s3c2410_uartcfg) {
2261                 .ucon           = S3C2410_UCON_DEFAULT,
2262                 .ufcon          = S3C2410_UFCON_DEFAULT,
2263         },
2264 };
2265 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2266 #else
2267 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2268 #endif
2269
2270 #ifdef CONFIG_CPU_S5PV210
2271 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2272         .info = &(struct s3c24xx_uart_info) {
2273                 .name           = "Samsung S5PV210 UART",
2274                 .type           = PORT_S3C6400,
2275                 .has_divslot    = 1,
2276                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2277                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2278                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2279                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2280                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2281                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2282                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2283                 .num_clks       = 2,
2284                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2285                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2286         },
2287         .def_cfg = &(struct s3c2410_uartcfg) {
2288                 .ucon           = S5PV210_UCON_DEFAULT,
2289                 .ufcon          = S5PV210_UFCON_DEFAULT,
2290         },
2291         .fifosize = { 256, 64, 16, 16 },
2292 };
2293 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2294 #else
2295 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2296 #endif
2297
2298 #if defined(CONFIG_ARCH_EXYNOS)
2299 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2300         .info = &(struct s3c24xx_uart_info) {                   \
2301                 .name           = "Samsung Exynos UART",        \
2302                 .type           = PORT_S3C6400,                 \
2303                 .has_divslot    = 1,                            \
2304                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2305                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2306                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2307                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2308                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2309                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2310                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2311                 .num_clks       = 1,                            \
2312                 .clksel_mask    = 0,                            \
2313                 .clksel_shift   = 0,                            \
2314         },                                                      \
2315         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2316                 .ucon           = S5PV210_UCON_DEFAULT,         \
2317                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2318                 .has_fracval    = 1,                            \
2319         }                                                       \
2320
2321 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2322         EXYNOS_COMMON_SERIAL_DRV_DATA,
2323         .fifosize = { 256, 64, 16, 16 },
2324 };
2325
2326 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2327         EXYNOS_COMMON_SERIAL_DRV_DATA,
2328         .fifosize = { 64, 256, 16, 256 },
2329 };
2330
2331 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2332 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2333 #else
2334 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2335 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2336 #endif
2337
2338 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
2339         {
2340                 .name           = "s3c2410-uart",
2341                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2342         }, {
2343                 .name           = "s3c2412-uart",
2344                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2345         }, {
2346                 .name           = "s3c2440-uart",
2347                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2348         }, {
2349                 .name           = "s3c6400-uart",
2350                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2351         }, {
2352                 .name           = "s5pv210-uart",
2353                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2354         }, {
2355                 .name           = "exynos4210-uart",
2356                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2357         }, {
2358                 .name           = "exynos5433-uart",
2359                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2360         },
2361         { },
2362 };
2363 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2364
2365 #ifdef CONFIG_OF
2366 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2367         { .compatible = "samsung,s3c2410-uart",
2368                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2369         { .compatible = "samsung,s3c2412-uart",
2370                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2371         { .compatible = "samsung,s3c2440-uart",
2372                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2373         { .compatible = "samsung,s3c6400-uart",
2374                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2375         { .compatible = "samsung,s5pv210-uart",
2376                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2377         { .compatible = "samsung,exynos4210-uart",
2378                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2379         { .compatible = "samsung,exynos5433-uart",
2380                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2381         {},
2382 };
2383 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2384 #endif
2385
2386 static struct platform_driver samsung_serial_driver = {
2387         .probe          = s3c24xx_serial_probe,
2388         .remove         = s3c24xx_serial_remove,
2389         .id_table       = s3c24xx_serial_driver_ids,
2390         .driver         = {
2391                 .name   = "samsung-uart",
2392                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2393                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2394         },
2395 };
2396
2397 module_platform_driver(samsung_serial_driver);
2398
2399 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2400 /*
2401  * Early console.
2402  */
2403
2404 struct samsung_early_console_data {
2405         u32 txfull_mask;
2406 };
2407
2408 static void samsung_early_busyuart(struct uart_port *port)
2409 {
2410         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2411                 ;
2412 }
2413
2414 static void samsung_early_busyuart_fifo(struct uart_port *port)
2415 {
2416         struct samsung_early_console_data *data = port->private_data;
2417
2418         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2419                 ;
2420 }
2421
2422 static void samsung_early_putc(struct uart_port *port, int c)
2423 {
2424         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2425                 samsung_early_busyuart_fifo(port);
2426         else
2427                 samsung_early_busyuart(port);
2428
2429         writeb(c, port->membase + S3C2410_UTXH);
2430 }
2431
2432 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2433 {
2434         struct earlycon_device *dev = con->data;
2435
2436         uart_console_write(&dev->port, s, n, samsung_early_putc);
2437 }
2438
2439 static int __init samsung_early_console_setup(struct earlycon_device *device,
2440                                               const char *opt)
2441 {
2442         if (!device->port.membase)
2443                 return -ENODEV;
2444
2445         device->con->write = samsung_early_write;
2446         return 0;
2447 }
2448
2449 /* S3C2410 */
2450 static struct samsung_early_console_data s3c2410_early_console_data = {
2451         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2452 };
2453
2454 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2455                                               const char *opt)
2456 {
2457         device->port.private_data = &s3c2410_early_console_data;
2458         return samsung_early_console_setup(device, opt);
2459 }
2460 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2461                         s3c2410_early_console_setup);
2462 EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2463
2464 /* S3C2412, S3C2440, S3C64xx */
2465 static struct samsung_early_console_data s3c2440_early_console_data = {
2466         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2467 };
2468
2469 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2470                                               const char *opt)
2471 {
2472         device->port.private_data = &s3c2440_early_console_data;
2473         return samsung_early_console_setup(device, opt);
2474 }
2475 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2476                         s3c2440_early_console_setup);
2477 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2478                         s3c2440_early_console_setup);
2479 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2480                         s3c2440_early_console_setup);
2481 EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2482 EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2483 EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2484
2485 /* S5PV210, EXYNOS */
2486 static struct samsung_early_console_data s5pv210_early_console_data = {
2487         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2488 };
2489
2490 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2491                                               const char *opt)
2492 {
2493         device->port.private_data = &s5pv210_early_console_data;
2494         return samsung_early_console_setup(device, opt);
2495 }
2496 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2497                         s5pv210_early_console_setup);
2498 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2499                         s5pv210_early_console_setup);
2500 EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2501 EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2502 #endif
2503
2504 MODULE_ALIAS("platform:samsung-uart");
2505 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2506 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2507 MODULE_LICENSE("GPL v2");