drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   9 #define SUPPORT_SYSRQ
  10 #endif
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dmapool.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/slab.h>
  25 #include <linux/tty_flip.h>
  26
  27 /* All registers are 8-bit width */
  28 #define UARTBDH                 0x00
  29 #define UARTBDL                 0x01
  30 #define UARTCR1                 0x02
  31 #define UARTCR2                 0x03
  32 #define UARTSR1                 0x04
  33 #define UARTCR3                 0x06
  34 #define UARTDR                  0x07
  35 #define UARTCR4                 0x0a
  36 #define UARTCR5                 0x0b
  37 #define UARTMODEM               0x0d
  38 #define UARTPFIFO               0x10
  39 #define UARTCFIFO               0x11
  40 #define UARTSFIFO               0x12
  41 #define UARTTWFIFO              0x13
  42 #define UARTTCFIFO              0x14
  43 #define UARTRWFIFO              0x15
  44
  45 #define UARTBDH_LBKDIE          0x80
  46 #define UARTBDH_RXEDGIE         0x40
  47 #define UARTBDH_SBR_MASK        0x1f
  48
  49 #define UARTCR1_LOOPS           0x80
  50 #define UARTCR1_RSRC            0x20
  51 #define UARTCR1_M               0x10
  52 #define UARTCR1_WAKE            0x08
  53 #define UARTCR1_ILT             0x04
  54 #define UARTCR1_PE              0x02
  55 #define UARTCR1_PT              0x01
  56
  57 #define UARTCR2_TIE             0x80
  58 #define UARTCR2_TCIE            0x40
  59 #define UARTCR2_RIE             0x20
  60 #define UARTCR2_ILIE            0x10
  61 #define UARTCR2_TE              0x08
  62 #define UARTCR2_RE              0x04
  63 #define UARTCR2_RWU             0x02
  64 #define UARTCR2_SBK             0x01
  65
  66 #define UARTSR1_TDRE            0x80
  67 #define UARTSR1_TC              0x40
  68 #define UARTSR1_RDRF            0x20
  69 #define UARTSR1_IDLE            0x10
  70 #define UARTSR1_OR              0x08
  71 #define UARTSR1_NF              0x04
  72 #define UARTSR1_FE              0x02
  73 #define UARTSR1_PE              0x01
  74
  75 #define UARTCR3_R8              0x80
  76 #define UARTCR3_T8              0x40
  77 #define UARTCR3_TXDIR           0x20
  78 #define UARTCR3_TXINV           0x10
  79 #define UARTCR3_ORIE            0x08
  80 #define UARTCR3_NEIE            0x04
  81 #define UARTCR3_FEIE            0x02
  82 #define UARTCR3_PEIE            0x01
  83
  84 #define UARTCR4_MAEN1           0x80
  85 #define UARTCR4_MAEN2           0x40
  86 #define UARTCR4_M10             0x20
  87 #define UARTCR4_BRFA_MASK       0x1f
  88 #define UARTCR4_BRFA_OFF        0
  89
  90 #define UARTCR5_TDMAS           0x80
  91 #define UARTCR5_RDMAS           0x20
  92
  93 #define UARTMODEM_RXRTSE        0x08
  94 #define UARTMODEM_TXRTSPOL      0x04
  95 #define UARTMODEM_TXRTSE        0x02
  96 #define UARTMODEM_TXCTSE        0x01
  97
  98 #define UARTPFIFO_TXFE          0x80
  99 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 100 #define UARTPFIFO_TXSIZE_OFF    4
 101 #define UARTPFIFO_RXFE          0x08
 102 #define UARTPFIFO_RXSIZE_OFF    0
 103
 104 #define UARTCFIFO_TXFLUSH       0x80
 105 #define UARTCFIFO_RXFLUSH       0x40
 106 #define UARTCFIFO_RXOFE         0x04
 107 #define UARTCFIFO_TXOFE         0x02
 108 #define UARTCFIFO_RXUFE         0x01
 109
 110 #define UARTSFIFO_TXEMPT        0x80
 111 #define UARTSFIFO_RXEMPT        0x40
 112 #define UARTSFIFO_RXOF          0x04
 113 #define UARTSFIFO_TXOF          0x02
 114 #define UARTSFIFO_RXUF          0x01
 115
 116 /* 32-bit register definition */
 117 #define UARTBAUD                0x00
 118 #define UARTSTAT                0x04
 119 #define UARTCTRL                0x08
 120 #define UARTDATA                0x0C
 121 #define UARTMATCH               0x10
 122 #define UARTMODIR               0x14
 123 #define UARTFIFO                0x18
 124 #define UARTWATER               0x1c
 125
 126 #define UARTBAUD_MAEN1          0x80000000
 127 #define UARTBAUD_MAEN2          0x40000000
 128 #define UARTBAUD_M10            0x20000000
 129 #define UARTBAUD_TDMAE          0x00800000
 130 #define UARTBAUD_RDMAE          0x00200000
 131 #define UARTBAUD_MATCFG         0x00400000
 132 #define UARTBAUD_BOTHEDGE       0x00020000
 133 #define UARTBAUD_RESYNCDIS      0x00010000
 134 #define UARTBAUD_LBKDIE         0x00008000
 135 #define UARTBAUD_RXEDGIE        0x00004000
 136 #define UARTBAUD_SBNS           0x00002000
 137 #define UARTBAUD_SBR            0x00000000
 138 #define UARTBAUD_SBR_MASK       0x1fff
 139 #define UARTBAUD_OSR_MASK       0x1f
 140 #define UARTBAUD_OSR_SHIFT      24
 141
 142 #define UARTSTAT_LBKDIF         0x80000000
 143 #define UARTSTAT_RXEDGIF        0x40000000
 144 #define UARTSTAT_MSBF           0x20000000
 145 #define UARTSTAT_RXINV          0x10000000
 146 #define UARTSTAT_RWUID          0x08000000
 147 #define UARTSTAT_BRK13          0x04000000
 148 #define UARTSTAT_LBKDE          0x02000000
 149 #define UARTSTAT_RAF            0x01000000
 150 #define UARTSTAT_TDRE           0x00800000
 151 #define UARTSTAT_TC             0x00400000
 152 #define UARTSTAT_RDRF           0x00200000
 153 #define UARTSTAT_IDLE           0x00100000
 154 #define UARTSTAT_OR             0x00080000
 155 #define UARTSTAT_NF             0x00040000
 156 #define UARTSTAT_FE             0x00020000
 157 #define UARTSTAT_PE             0x00010000
 158 #define UARTSTAT_MA1F           0x00008000
 159 #define UARTSTAT_M21F           0x00004000
 160
 161 #define UARTCTRL_R8T9           0x80000000
 162 #define UARTCTRL_R9T8           0x40000000
 163 #define UARTCTRL_TXDIR          0x20000000
 164 #define UARTCTRL_TXINV          0x10000000
 165 #define UARTCTRL_ORIE           0x08000000
 166 #define UARTCTRL_NEIE           0x04000000
 167 #define UARTCTRL_FEIE           0x02000000
 168 #define UARTCTRL_PEIE           0x01000000
 169 #define UARTCTRL_TIE            0x00800000
 170 #define UARTCTRL_TCIE           0x00400000
 171 #define UARTCTRL_RIE            0x00200000
 172 #define UARTCTRL_ILIE           0x00100000
 173 #define UARTCTRL_TE             0x00080000
 174 #define UARTCTRL_RE             0x00040000
 175 #define UARTCTRL_RWU            0x00020000
 176 #define UARTCTRL_SBK            0x00010000
 177 #define UARTCTRL_MA1IE          0x00008000
 178 #define UARTCTRL_MA2IE          0x00004000
 179 #define UARTCTRL_IDLECFG        0x00000100
 180 #define UARTCTRL_LOOPS          0x00000080
 181 #define UARTCTRL_DOZEEN         0x00000040
 182 #define UARTCTRL_RSRC           0x00000020
 183 #define UARTCTRL_M              0x00000010
 184 #define UARTCTRL_WAKE           0x00000008
 185 #define UARTCTRL_ILT            0x00000004
 186 #define UARTCTRL_PE             0x00000002
 187 #define UARTCTRL_PT             0x00000001
 188
 189 #define UARTDATA_NOISY          0x00008000
 190 #define UARTDATA_PARITYE        0x00004000
 191 #define UARTDATA_FRETSC         0x00002000
 192 #define UARTDATA_RXEMPT         0x00001000
 193 #define UARTDATA_IDLINE         0x00000800
 194 #define UARTDATA_MASK           0x3ff
 195
 196 #define UARTMODIR_IREN          0x00020000
 197 #define UARTMODIR_TXCTSSRC      0x00000020
 198 #define UARTMODIR_TXCTSC        0x00000010
 199 #define UARTMODIR_RXRTSE        0x00000008
 200 #define UARTMODIR_TXRTSPOL      0x00000004
 201 #define UARTMODIR_TXRTSE        0x00000002
 202 #define UARTMODIR_TXCTSE        0x00000001
 203
 204 #define UARTFIFO_TXEMPT         0x00800000
 205 #define UARTFIFO_RXEMPT         0x00400000
 206 #define UARTFIFO_TXOF           0x00020000
 207 #define UARTFIFO_RXUF           0x00010000
 208 #define UARTFIFO_TXFLUSH        0x00008000
 209 #define UARTFIFO_RXFLUSH        0x00004000
 210 #define UARTFIFO_TXOFE          0x00000200
 211 #define UARTFIFO_RXUFE          0x00000100
 212 #define UARTFIFO_TXFE           0x00000080
 213 #define UARTFIFO_FIFOSIZE_MASK  0x7
 214 #define UARTFIFO_TXSIZE_OFF     4
 215 #define UARTFIFO_RXFE           0x00000008
 216 #define UARTFIFO_RXSIZE_OFF     0
 217
 218 #define UARTWATER_COUNT_MASK    0xff
 219 #define UARTWATER_TXCNT_OFF     8
 220 #define UARTWATER_RXCNT_OFF     24
 221 #define UARTWATER_WATER_MASK    0xff
 222 #define UARTWATER_TXWATER_OFF   0
 223 #define UARTWATER_RXWATER_OFF   16
 224
 225 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 226 #define DMA_RX_TIMEOUT          (10)
 227
 228 #define DRIVER_NAME     "fsl-lpuart"
 229 #define DEV_NAME        "ttyLP"
 230 #define UART_NR         6
 231
 232 /* IMX lpuart has four extra unused regs located at the beginning */
 233 #define IMX_REG_OFF     0x10
 234
 235 static DEFINE_IDA(fsl_lpuart_ida);
 236
 237 struct lpuart_port {
 238         struct uart_port        port;
 239         struct clk              *clk;
 240         unsigned int            txfifo_size;
 241         unsigned int            rxfifo_size;
 242
 243         bool                    lpuart_dma_tx_use;
 244         bool                    lpuart_dma_rx_use;
 245         struct dma_chan         *dma_tx_chan;
 246         struct dma_chan         *dma_rx_chan;
 247         struct dma_async_tx_descriptor  *dma_tx_desc;
 248         struct dma_async_tx_descriptor  *dma_rx_desc;
 249         dma_cookie_t            dma_tx_cookie;
 250         dma_cookie_t            dma_rx_cookie;
 251         unsigned int            dma_tx_bytes;
 252         unsigned int            dma_rx_bytes;
 253         bool                    dma_tx_in_progress;
 254         unsigned int            dma_rx_timeout;
 255         struct timer_list       lpuart_timer;
 256         struct scatterlist      rx_sgl, tx_sgl[2];
 257         struct circ_buf         rx_ring;
 258         int                     rx_dma_rng_buf_len;
 259         unsigned int            dma_tx_nents;
 260         wait_queue_head_t       dma_wait;
 261 };
 262
 263 struct lpuart_soc_data {
 264         char    iotype;
 265         u8      reg_off;
 266 };
 267
 268 static const struct lpuart_soc_data vf_data = {
 269         .iotype = UPIO_MEM,
 270 };
 271
 272 static const struct lpuart_soc_data ls_data = {
 273         .iotype = UPIO_MEM32BE,
 274 };
 275
 276 static struct lpuart_soc_data imx_data = {
 277         .iotype = UPIO_MEM32,
 278         .reg_off = IMX_REG_OFF,
 279 };
 280
 281 static const struct of_device_id lpuart_dt_ids[] = {
 282         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 283         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls_data, },
 284         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx_data, },
 285         { /* sentinel */ }
 286 };
 287 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 288
 289 /* Forward declare this for the dma callbacks*/
 290 static void lpuart_dma_tx_complete(void *arg);
 291
 292 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 293 {
 294         switch (port->iotype) {
 295         case UPIO_MEM32:
 296                 return readl(port->membase + off);
 297         case UPIO_MEM32BE:
 298                 return ioread32be(port->membase + off);
 299         default:
 300                 return 0;
 301         }
 302 }
 303
 304 static inline void lpuart32_write(struct uart_port *port, u32 val,
 305                                   u32 off)
 306 {
 307         switch (port->iotype) {
 308         case UPIO_MEM32:
 309                 writel(val, port->membase + off);
 310                 break;
 311         case UPIO_MEM32BE:
 312                 iowrite32be(val, port->membase + off);
 313                 break;
 314         }
 315 }
 316
 317 static void lpuart_stop_tx(struct uart_port *port)
 318 {
 319         unsigned char temp;
 320
 321         temp = readb(port->membase + UARTCR2);
 322         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 323         writeb(temp, port->membase + UARTCR2);
 324 }
 325
 326 static void lpuart32_stop_tx(struct uart_port *port)
 327 {
 328         unsigned long temp;
 329
 330         temp = lpuart32_read(port, UARTCTRL);
 331         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 332         lpuart32_write(port, temp, UARTCTRL);
 333 }
 334
 335 static void lpuart_stop_rx(struct uart_port *port)
 336 {
 337         unsigned char temp;
 338
 339         temp = readb(port->membase + UARTCR2);
 340         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 341 }
 342
 343 static void lpuart32_stop_rx(struct uart_port *port)
 344 {
 345         unsigned long temp;
 346
 347         temp = lpuart32_read(port, UARTCTRL);
 348         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 349 }
 350
 351 static void lpuart_dma_tx(struct lpuart_port *sport)
 352 {
 353         struct circ_buf *xmit = &sport->port.state->xmit;
 354         struct scatterlist *sgl = sport->tx_sgl;
 355         struct device *dev = sport->port.dev;
 356         int ret;
 357
 358         if (sport->dma_tx_in_progress)
 359                 return;
 360
 361         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 362
 363         if (xmit->tail < xmit->head || xmit->head == 0) {
 364                 sport->dma_tx_nents = 1;
 365                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 366         } else {
 367                 sport->dma_tx_nents = 2;
 368                 sg_init_table(sgl, 2);
 369                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 370                                 UART_XMIT_SIZE - xmit->tail);
 371                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 372         }
 373
 374         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 375         if (!ret) {
 376                 dev_err(dev, "DMA mapping error for TX.\n");
 377                 return;
 378         }
 379
 380         sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
 381                                         sport->dma_tx_nents,
 382                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 383         if (!sport->dma_tx_desc) {
 384                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 385                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 386                 return;
 387         }
 388
 389         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 390         sport->dma_tx_desc->callback_param = sport;
 391         sport->dma_tx_in_progress = true;
 392         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 393         dma_async_issue_pending(sport->dma_tx_chan);
 394 }
 395
 396 static void lpuart_dma_tx_complete(void *arg)
 397 {
 398         struct lpuart_port *sport = arg;
 399         struct scatterlist *sgl = &sport->tx_sgl[0];
 400         struct circ_buf *xmit = &sport->port.state->xmit;
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&sport->port.lock, flags);
 404
 405         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 406
 407         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 408
 409         sport->port.icount.tx += sport->dma_tx_bytes;
 410         sport->dma_tx_in_progress = false;
 411         spin_unlock_irqrestore(&sport->port.lock, flags);
 412
 413         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 414                 uart_write_wakeup(&sport->port);
 415
 416         if (waitqueue_active(&sport->dma_wait)) {
 417                 wake_up(&sport->dma_wait);
 418                 return;
 419         }
 420
 421         spin_lock_irqsave(&sport->port.lock, flags);
 422
 423         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 424                 lpuart_dma_tx(sport);
 425
 426         spin_unlock_irqrestore(&sport->port.lock, flags);
 427 }
 428
 429 static int lpuart_dma_tx_request(struct uart_port *port)
 430 {
 431         struct lpuart_port *sport = container_of(port,
 432                                         struct lpuart_port, port);
 433         struct dma_slave_config dma_tx_sconfig = {};
 434         int ret;
 435
 436         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 437         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 438         dma_tx_sconfig.dst_maxburst = 1;
 439         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 440         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 441
 442         if (ret) {
 443                 dev_err(sport->port.dev,
 444                                 "DMA slave config failed, err = %d\n", ret);
 445                 return ret;
 446         }
 447
 448         return 0;
 449 }
 450
 451 static void lpuart_flush_buffer(struct uart_port *port)
 452 {
 453         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 454
 455         if (sport->lpuart_dma_tx_use) {
 456                 if (sport->dma_tx_in_progress) {
 457                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
 458                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 459                         sport->dma_tx_in_progress = false;
 460                 }
 461                 dmaengine_terminate_all(sport->dma_tx_chan);
 462         }
 463 }
 464
 465 #if defined(CONFIG_CONSOLE_POLL)
 466
 467 static int lpuart_poll_init(struct uart_port *port)
 468 {
 469         struct lpuart_port *sport = container_of(port,
 470                                         struct lpuart_port, port);
 471         unsigned long flags;
 472         unsigned char temp;
 473
 474         sport->port.fifosize = 0;
 475
 476         spin_lock_irqsave(&sport->port.lock, flags);
 477         /* Disable Rx & Tx */
 478         writeb(0, sport->port.membase + UARTCR2);
 479
 480         temp = readb(sport->port.membase + UARTPFIFO);
 481         /* Enable Rx and Tx FIFO */
 482         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 483                         sport->port.membase + UARTPFIFO);
 484
 485         /* flush Tx and Rx FIFO */
 486         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 487                         sport->port.membase + UARTCFIFO);
 488
 489         /* explicitly clear RDRF */
 490         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 491                 readb(sport->port.membase + UARTDR);
 492                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 493         }
 494
 495         writeb(0, sport->port.membase + UARTTWFIFO);
 496         writeb(1, sport->port.membase + UARTRWFIFO);
 497
 498         /* Enable Rx and Tx */
 499         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 500         spin_unlock_irqrestore(&sport->port.lock, flags);
 501
 502         return 0;
 503 }
 504
 505 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 506 {
 507         /* drain */
 508         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
 509                 barrier();
 510
 511         writeb(c, port->membase + UARTDR);
 512 }
 513
 514 static int lpuart_poll_get_char(struct uart_port *port)
 515 {
 516         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 517                 return NO_POLL_CHAR;
 518
 519         return readb(port->membase + UARTDR);
 520 }
 521
 522 static int lpuart32_poll_init(struct uart_port *port)
 523 {
 524         unsigned long flags;
 525         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 526         u32 temp;
 527
 528         sport->port.fifosize = 0;
 529
 530         spin_lock_irqsave(&sport->port.lock, flags);
 531
 532         /* Disable Rx & Tx */
 533         writel(0, sport->port.membase + UARTCTRL);
 534
 535         temp = readl(sport->port.membase + UARTFIFO);
 536
 537         /* Enable Rx and Tx FIFO */
 538         writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE,
 539                    sport->port.membase + UARTFIFO);
 540
 541         /* flush Tx and Rx FIFO */
 542         writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH,
 543                         sport->port.membase + UARTFIFO);
 544
 545         /* explicitly clear RDRF */
 546         if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) {
 547                 readl(sport->port.membase + UARTDATA);
 548                 writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO);
 549         }
 550
 551         /* Enable Rx and Tx */
 552         writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL);
 553         spin_unlock_irqrestore(&sport->port.lock, flags);
 554
 555         return 0;
 556 }
 557
 558 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 559 {
 560         while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE))
 561                 barrier();
 562
 563         writel(c, port->membase + UARTDATA);
 564 }
 565
 566 static int lpuart32_poll_get_char(struct uart_port *port)
 567 {
 568         if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF))
 569                 return NO_POLL_CHAR;
 570
 571         return readl(port->membase + UARTDATA);
 572 }
 573 #endif
 574
 575 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 576 {
 577         struct circ_buf *xmit = &sport->port.state->xmit;
 578
 579         while (!uart_circ_empty(xmit) &&
 580                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 581                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 582                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 583                 sport->port.icount.tx++;
 584         }
 585
 586         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 587                 uart_write_wakeup(&sport->port);
 588
 589         if (uart_circ_empty(xmit))
 590                 lpuart_stop_tx(&sport->port);
 591 }
 592
 593 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 594 {
 595         struct circ_buf *xmit = &sport->port.state->xmit;
 596         unsigned long txcnt;
 597
 598         txcnt = lpuart32_read(&sport->port, UARTWATER);
 599         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 600         txcnt &= UARTWATER_COUNT_MASK;
 601         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 602                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 603                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 604                 sport->port.icount.tx++;
 605                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 606                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 607                 txcnt &= UARTWATER_COUNT_MASK;
 608         }
 609
 610         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 611                 uart_write_wakeup(&sport->port);
 612
 613         if (uart_circ_empty(xmit))
 614                 lpuart32_stop_tx(&sport->port);
 615 }
 616
 617 static void lpuart_start_tx(struct uart_port *port)
 618 {
 619         struct lpuart_port *sport = container_of(port,
 620                         struct lpuart_port, port);
 621         struct circ_buf *xmit = &sport->port.state->xmit;
 622         unsigned char temp;
 623
 624         temp = readb(port->membase + UARTCR2);
 625         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 626
 627         if (sport->lpuart_dma_tx_use) {
 628                 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
 629                         lpuart_dma_tx(sport);
 630         } else {
 631                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 632                         lpuart_transmit_buffer(sport);
 633         }
 634 }
 635
 636 static void lpuart32_start_tx(struct uart_port *port)
 637 {
 638         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 639         unsigned long temp;
 640
 641         temp = lpuart32_read(port, UARTCTRL);
 642         lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 643
 644         if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 645                 lpuart32_transmit_buffer(sport);
 646 }
 647
 648 /* return TIOCSER_TEMT when transmitter is not busy */
 649 static unsigned int lpuart_tx_empty(struct uart_port *port)
 650 {
 651         struct lpuart_port *sport = container_of(port,
 652                         struct lpuart_port, port);
 653         unsigned char sr1 = readb(port->membase + UARTSR1);
 654         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 655
 656         if (sport->dma_tx_in_progress)
 657                 return 0;
 658
 659         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 660                 return TIOCSER_TEMT;
 661
 662         return 0;
 663 }
 664
 665 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 666 {
 667         return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
 668                 TIOCSER_TEMT : 0;
 669 }
 670
 671 static bool lpuart_is_32(struct lpuart_port *sport)
 672 {
 673         return sport->port.iotype == UPIO_MEM32 ||
 674                sport->port.iotype ==  UPIO_MEM32BE;
 675 }
 676
 677 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 678 {
 679         struct lpuart_port *sport = dev_id;
 680         struct circ_buf *xmit = &sport->port.state->xmit;
 681         unsigned long flags;
 682
 683         spin_lock_irqsave(&sport->port.lock, flags);
 684         if (sport->port.x_char) {
 685                 if (lpuart_is_32(sport))
 686                         lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 687                 else
 688                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 689                 goto out;
 690         }
 691
 692         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 693                 if (lpuart_is_32(sport))
 694                         lpuart32_stop_tx(&sport->port);
 695                 else
 696                         lpuart_stop_tx(&sport->port);
 697                 goto out;
 698         }
 699
 700         if (lpuart_is_32(sport))
 701                 lpuart32_transmit_buffer(sport);
 702         else
 703                 lpuart_transmit_buffer(sport);
 704
 705         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 706                 uart_write_wakeup(&sport->port);
 707
 708 out:
 709         spin_unlock_irqrestore(&sport->port.lock, flags);
 710         return IRQ_HANDLED;
 711 }
 712
 713 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 714 {
 715         struct lpuart_port *sport = dev_id;
 716         unsigned int flg, ignored = 0;
 717         struct tty_port *port = &sport->port.state->port;
 718         unsigned long flags;
 719         unsigned char rx, sr;
 720
 721         spin_lock_irqsave(&sport->port.lock, flags);
 722
 723         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 724                 flg = TTY_NORMAL;
 725                 sport->port.icount.rx++;
 726                 /*
 727                  * to clear the FE, OR, NF, FE, PE flags,
 728                  * read SR1 then read DR
 729                  */
 730                 sr = readb(sport->port.membase + UARTSR1);
 731                 rx = readb(sport->port.membase + UARTDR);
 732
 733                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 734                         continue;
 735
 736                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 737                         if (sr & UARTSR1_PE)
 738                                 sport->port.icount.parity++;
 739                         else if (sr & UARTSR1_FE)
 740                                 sport->port.icount.frame++;
 741
 742                         if (sr & UARTSR1_OR)
 743                                 sport->port.icount.overrun++;
 744
 745                         if (sr & sport->port.ignore_status_mask) {
 746                                 if (++ignored > 100)
 747                                         goto out;
 748                                 continue;
 749                         }
 750
 751                         sr &= sport->port.read_status_mask;
 752
 753                         if (sr & UARTSR1_PE)
 754                                 flg = TTY_PARITY;
 755                         else if (sr & UARTSR1_FE)
 756                                 flg = TTY_FRAME;
 757
 758                         if (sr & UARTSR1_OR)
 759                                 flg = TTY_OVERRUN;
 760
 761 #ifdef SUPPORT_SYSRQ
 762                         sport->port.sysrq = 0;
 763 #endif
 764                 }
 765
 766                 tty_insert_flip_char(port, rx, flg);
 767         }
 768
 769 out:
 770         spin_unlock_irqrestore(&sport->port.lock, flags);
 771
 772         tty_flip_buffer_push(port);
 773         return IRQ_HANDLED;
 774 }
 775
 776 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 777 {
 778         struct lpuart_port *sport = dev_id;
 779         unsigned int flg, ignored = 0;
 780         struct tty_port *port = &sport->port.state->port;
 781         unsigned long flags;
 782         unsigned long rx, sr;
 783
 784         spin_lock_irqsave(&sport->port.lock, flags);
 785
 786         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 787                 flg = TTY_NORMAL;
 788                 sport->port.icount.rx++;
 789                 /*
 790                  * to clear the FE, OR, NF, FE, PE flags,
 791                  * read STAT then read DATA reg
 792                  */
 793                 sr = lpuart32_read(&sport->port, UARTSTAT);
 794                 rx = lpuart32_read(&sport->port, UARTDATA);
 795                 rx &= 0x3ff;
 796
 797                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 798                         continue;
 799
 800                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 801                         if (sr & UARTSTAT_PE)
 802                                 sport->port.icount.parity++;
 803                         else if (sr & UARTSTAT_FE)
 804                                 sport->port.icount.frame++;
 805
 806                         if (sr & UARTSTAT_OR)
 807                                 sport->port.icount.overrun++;
 808
 809                         if (sr & sport->port.ignore_status_mask) {
 810                                 if (++ignored > 100)
 811                                         goto out;
 812                                 continue;
 813                         }
 814
 815                         sr &= sport->port.read_status_mask;
 816
 817                         if (sr & UARTSTAT_PE)
 818                                 flg = TTY_PARITY;
 819                         else if (sr & UARTSTAT_FE)
 820                                 flg = TTY_FRAME;
 821
 822                         if (sr & UARTSTAT_OR)
 823                                 flg = TTY_OVERRUN;
 824
 825 #ifdef SUPPORT_SYSRQ
 826                         sport->port.sysrq = 0;
 827 #endif
 828                 }
 829
 830                 tty_insert_flip_char(port, rx, flg);
 831         }
 832
 833 out:
 834         spin_unlock_irqrestore(&sport->port.lock, flags);
 835
 836         tty_flip_buffer_push(port);
 837         return IRQ_HANDLED;
 838 }
 839
 840 static irqreturn_t lpuart_int(int irq, void *dev_id)
 841 {
 842         struct lpuart_port *sport = dev_id;
 843         unsigned char sts;
 844
 845         sts = readb(sport->port.membase + UARTSR1);
 846
 847         if (sts & UARTSR1_RDRF)
 848                 lpuart_rxint(irq, dev_id);
 849
 850         if (sts & UARTSR1_TDRE)
 851                 lpuart_txint(irq, dev_id);
 852
 853         return IRQ_HANDLED;
 854 }
 855
 856 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 857 {
 858         struct lpuart_port *sport = dev_id;
 859         unsigned long sts, rxcount;
 860
 861         sts = lpuart32_read(&sport->port, UARTSTAT);
 862         rxcount = lpuart32_read(&sport->port, UARTWATER);
 863         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 864
 865         if (sts & UARTSTAT_RDRF || rxcount > 0)
 866                 lpuart32_rxint(irq, dev_id);
 867
 868         if ((sts & UARTSTAT_TDRE) &&
 869                 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
 870                 lpuart_txint(irq, dev_id);
 871
 872         lpuart32_write(&sport->port, sts, UARTSTAT);
 873         return IRQ_HANDLED;
 874 }
 875
 876 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 877 {
 878         struct tty_port *port = &sport->port.state->port;
 879         struct dma_tx_state state;
 880         enum dma_status dmastat;
 881         struct circ_buf *ring = &sport->rx_ring;
 882         unsigned long flags;
 883         int count = 0;
 884         unsigned char sr;
 885
 886         sr = readb(sport->port.membase + UARTSR1);
 887
 888         if (sr & (UARTSR1_PE | UARTSR1_FE)) {
 889                 /* Read DR to clear the error flags */
 890                 readb(sport->port.membase + UARTDR);
 891
 892                 if (sr & UARTSR1_PE)
 893                     sport->port.icount.parity++;
 894                 else if (sr & UARTSR1_FE)
 895                     sport->port.icount.frame++;
 896         }
 897
 898         async_tx_ack(sport->dma_rx_desc);
 899
 900         spin_lock_irqsave(&sport->port.lock, flags);
 901
 902         dmastat = dmaengine_tx_status(sport->dma_rx_chan,
 903                                 sport->dma_rx_cookie,
 904                                 &state);
 905
 906         if (dmastat == DMA_ERROR) {
 907                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
 908                 spin_unlock_irqrestore(&sport->port.lock, flags);
 909                 return;
 910         }
 911
 912         /* CPU claims ownership of RX DMA buffer */
 913         dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
 914
 915         /*
 916          * ring->head points to the end of data already written by the DMA.
 917          * ring->tail points to the beginning of data to be read by the
 918          * framework.
 919          * The current transfer size should not be larger than the dma buffer
 920          * length.
 921          */
 922         ring->head = sport->rx_sgl.length - state.residue;
 923         BUG_ON(ring->head > sport->rx_sgl.length);
 924         /*
 925          * At this point ring->head may point to the first byte right after the
 926          * last byte of the dma buffer:
 927          * 0 <= ring->head <= sport->rx_sgl.length
 928          *
 929          * However ring->tail must always points inside the dma buffer:
 930          * 0 <= ring->tail <= sport->rx_sgl.length - 1
 931          *
 932          * Since we use a ring buffer, we have to handle the case
 933          * where head is lower than tail. In such a case, we first read from
 934          * tail to the end of the buffer then reset tail.
 935          */
 936         if (ring->head < ring->tail) {
 937                 count = sport->rx_sgl.length - ring->tail;
 938
 939                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 940                 ring->tail = 0;
 941                 sport->port.icount.rx += count;
 942         }
 943
 944         /* Finally we read data from tail to head */
 945         if (ring->tail < ring->head) {
 946                 count = ring->head - ring->tail;
 947                 tty_insert_flip_string(port, ring->buf + ring->tail, count);
 948                 /* Wrap ring->head if needed */
 949                 if (ring->head >= sport->rx_sgl.length)
 950                         ring->head = 0;
 951                 ring->tail = ring->head;
 952                 sport->port.icount.rx += count;
 953         }
 954
 955         dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
 956                                DMA_FROM_DEVICE);
 957
 958         spin_unlock_irqrestore(&sport->port.lock, flags);
 959
 960         tty_flip_buffer_push(port);
 961         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
 962 }
 963
 964 static void lpuart_dma_rx_complete(void *arg)
 965 {
 966         struct lpuart_port *sport = arg;
 967
 968         lpuart_copy_rx_to_tty(sport);
 969 }
 970
 971 static void lpuart_timer_func(struct timer_list *t)
 972 {
 973         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
 974
 975         lpuart_copy_rx_to_tty(sport);
 976 }
 977
 978 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
 979 {
 980         struct dma_slave_config dma_rx_sconfig = {};
 981         struct circ_buf *ring = &sport->rx_ring;
 982         int ret, nent;
 983         int bits, baud;
 984         struct tty_port *port = &sport->port.state->port;
 985         struct tty_struct *tty = port->tty;
 986         struct ktermios *termios = &tty->termios;
 987
 988         baud = tty_get_baud_rate(tty);
 989
 990         bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
 991         if (termios->c_cflag & PARENB)
 992                 bits++;
 993
 994         /*
 995          * Calculate length of one DMA buffer size to keep latency below
 996          * 10ms at any baud rate.
 997          */
 998         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
 999         sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1000         if (sport->rx_dma_rng_buf_len < 16)
1001                 sport->rx_dma_rng_buf_len = 16;
1002
1003         ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1004         if (!ring->buf) {
1005                 dev_err(sport->port.dev, "Ring buf alloc failed\n");
1006                 return -ENOMEM;
1007         }
1008
1009         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1010         sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1011         nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1012
1013         if (!nent) {
1014                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1015                 return -EINVAL;
1016         }
1017
1018         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1019         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1020         dma_rx_sconfig.src_maxburst = 1;
1021         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1022         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1023
1024         if (ret < 0) {
1025                 dev_err(sport->port.dev,
1026                                 "DMA Rx slave config failed, err = %d\n", ret);
1027                 return ret;
1028         }
1029
1030         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1031                                  sg_dma_address(&sport->rx_sgl),
1032                                  sport->rx_sgl.length,
1033                                  sport->rx_sgl.length / 2,
1034                                  DMA_DEV_TO_MEM,
1035                                  DMA_PREP_INTERRUPT);
1036         if (!sport->dma_rx_desc) {
1037                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1038                 return -EFAULT;
1039         }
1040
1041         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1042         sport->dma_rx_desc->callback_param = sport;
1043         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1044         dma_async_issue_pending(sport->dma_rx_chan);
1045
1046         writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1047                                 sport->port.membase + UARTCR5);
1048
1049         return 0;
1050 }
1051
1052 static void lpuart_dma_rx_free(struct uart_port *port)
1053 {
1054         struct lpuart_port *sport = container_of(port,
1055                                         struct lpuart_port, port);
1056
1057         if (sport->dma_rx_chan)
1058                 dmaengine_terminate_all(sport->dma_rx_chan);
1059
1060         dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1061         kfree(sport->rx_ring.buf);
1062         sport->rx_ring.tail = 0;
1063         sport->rx_ring.head = 0;
1064         sport->dma_rx_desc = NULL;
1065         sport->dma_rx_cookie = -EINVAL;
1066 }
1067
1068 static int lpuart_config_rs485(struct uart_port *port,
1069                         struct serial_rs485 *rs485)
1070 {
1071         struct lpuart_port *sport = container_of(port,
1072                         struct lpuart_port, port);
1073
1074         u8 modem = readb(sport->port.membase + UARTMODEM) &
1075                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1076         writeb(modem, sport->port.membase + UARTMODEM);
1077
1078         /* clear unsupported configurations */
1079         rs485->delay_rts_before_send = 0;
1080         rs485->delay_rts_after_send = 0;
1081         rs485->flags &= ~SER_RS485_RX_DURING_TX;
1082
1083         if (rs485->flags & SER_RS485_ENABLED) {
1084                 /* Enable auto RS-485 RTS mode */
1085                 modem |= UARTMODEM_TXRTSE;
1086
1087                 /*
1088                  * RTS needs to be logic HIGH either during transer _or_ after
1089                  * transfer, other variants are not supported by the hardware.
1090                  */
1091
1092                 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1093                                 SER_RS485_RTS_AFTER_SEND)))
1094                         rs485->flags |= SER_RS485_RTS_ON_SEND;
1095
1096                 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1097                                 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1098                         rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1099
1100                 /*
1101                  * The hardware defaults to RTS logic HIGH while transfer.
1102                  * Switch polarity in case RTS shall be logic HIGH
1103                  * after transfer.
1104                  * Note: UART is assumed to be active high.
1105                  */
1106                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1107                         modem &= ~UARTMODEM_TXRTSPOL;
1108                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1109                         modem |= UARTMODEM_TXRTSPOL;
1110         }
1111
1112         /* Store the new configuration */
1113         sport->port.rs485 = *rs485;
1114
1115         writeb(modem, sport->port.membase + UARTMODEM);
1116         return 0;
1117 }
1118
1119 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1120 {
1121         unsigned int temp = 0;
1122         unsigned char reg;
1123
1124         reg = readb(port->membase + UARTMODEM);
1125         if (reg & UARTMODEM_TXCTSE)
1126                 temp |= TIOCM_CTS;
1127
1128         if (reg & UARTMODEM_RXRTSE)
1129                 temp |= TIOCM_RTS;
1130
1131         return temp;
1132 }
1133
1134 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1135 {
1136         unsigned int temp = 0;
1137         unsigned long reg;
1138
1139         reg = lpuart32_read(port, UARTMODIR);
1140         if (reg & UARTMODIR_TXCTSE)
1141                 temp |= TIOCM_CTS;
1142
1143         if (reg & UARTMODIR_RXRTSE)
1144                 temp |= TIOCM_RTS;
1145
1146         return temp;
1147 }
1148
1149 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1150 {
1151         unsigned char temp;
1152         struct lpuart_port *sport = container_of(port,
1153                                 struct lpuart_port, port);
1154
1155         /* Make sure RXRTSE bit is not set when RS485 is enabled */
1156         if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1157                 temp = readb(sport->port.membase + UARTMODEM) &
1158                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1159
1160                 if (mctrl & TIOCM_RTS)
1161                         temp |= UARTMODEM_RXRTSE;
1162
1163                 if (mctrl & TIOCM_CTS)
1164                         temp |= UARTMODEM_TXCTSE;
1165
1166                 writeb(temp, port->membase + UARTMODEM);
1167         }
1168 }
1169
1170 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1171 {
1172         unsigned long temp;
1173
1174         temp = lpuart32_read(port, UARTMODIR) &
1175                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1176
1177         if (mctrl & TIOCM_RTS)
1178                 temp |= UARTMODIR_RXRTSE;
1179
1180         if (mctrl & TIOCM_CTS)
1181                 temp |= UARTMODIR_TXCTSE;
1182
1183         lpuart32_write(port, temp, UARTMODIR);
1184 }
1185
1186 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1187 {
1188         unsigned char temp;
1189
1190         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1191
1192         if (break_state != 0)
1193                 temp |= UARTCR2_SBK;
1194
1195         writeb(temp, port->membase + UARTCR2);
1196 }
1197
1198 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1199 {
1200         unsigned long temp;
1201
1202         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1203
1204         if (break_state != 0)
1205                 temp |= UARTCTRL_SBK;
1206
1207         lpuart32_write(port, temp, UARTCTRL);
1208 }
1209
1210 static void lpuart_setup_watermark(struct lpuart_port *sport)
1211 {
1212         unsigned char val, cr2;
1213         unsigned char cr2_saved;
1214
1215         cr2 = readb(sport->port.membase + UARTCR2);
1216         cr2_saved = cr2;
1217         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1218                         UARTCR2_RIE | UARTCR2_RE);
1219         writeb(cr2, sport->port.membase + UARTCR2);
1220
1221         val = readb(sport->port.membase + UARTPFIFO);
1222         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1223                         sport->port.membase + UARTPFIFO);
1224
1225         /* flush Tx and Rx FIFO */
1226         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1227                         sport->port.membase + UARTCFIFO);
1228
1229         /* explicitly clear RDRF */
1230         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1231                 readb(sport->port.membase + UARTDR);
1232                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1233         }
1234
1235         writeb(0, sport->port.membase + UARTTWFIFO);
1236         writeb(1, sport->port.membase + UARTRWFIFO);
1237
1238         /* Restore cr2 */
1239         writeb(cr2_saved, sport->port.membase + UARTCR2);
1240 }
1241
1242 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1243 {
1244         unsigned long val, ctrl;
1245         unsigned long ctrl_saved;
1246
1247         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1248         ctrl_saved = ctrl;
1249         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1250                         UARTCTRL_RIE | UARTCTRL_RE);
1251         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1252
1253         /* enable FIFO mode */
1254         val = lpuart32_read(&sport->port, UARTFIFO);
1255         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1256         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1257         lpuart32_write(&sport->port, val, UARTFIFO);
1258
1259         /* set the watermark */
1260         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1261         lpuart32_write(&sport->port, val, UARTWATER);
1262
1263         /* Restore cr2 */
1264         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1265 }
1266
1267 static void rx_dma_timer_init(struct lpuart_port *sport)
1268 {
1269                 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1270                 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1271                 add_timer(&sport->lpuart_timer);
1272 }
1273
1274 static int lpuart_startup(struct uart_port *port)
1275 {
1276         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1277         unsigned long flags;
1278         unsigned char temp;
1279
1280         /* determine FIFO size and enable FIFO mode */
1281         temp = readb(sport->port.membase + UARTPFIFO);
1282
1283         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1284                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1285
1286         sport->port.fifosize = sport->txfifo_size;
1287
1288         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1289                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1290
1291         spin_lock_irqsave(&sport->port.lock, flags);
1292
1293         lpuart_setup_watermark(sport);
1294
1295         temp = readb(sport->port.membase + UARTCR2);
1296         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1297         writeb(temp, sport->port.membase + UARTCR2);
1298
1299         if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1300                 /* set Rx DMA timeout */
1301                 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1302                 if (!sport->dma_rx_timeout)
1303                      sport->dma_rx_timeout = 1;
1304
1305                 sport->lpuart_dma_rx_use = true;
1306                 rx_dma_timer_init(sport);
1307         } else {
1308                 sport->lpuart_dma_rx_use = false;
1309         }
1310
1311         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1312                 init_waitqueue_head(&sport->dma_wait);
1313                 sport->lpuart_dma_tx_use = true;
1314                 temp = readb(port->membase + UARTCR5);
1315                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1316         } else {
1317                 sport->lpuart_dma_tx_use = false;
1318         }
1319
1320         spin_unlock_irqrestore(&sport->port.lock, flags);
1321
1322         return 0;
1323 }
1324
1325 static int lpuart32_startup(struct uart_port *port)
1326 {
1327         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1328         unsigned long flags;
1329         unsigned long temp;
1330
1331         /* determine FIFO size */
1332         temp = lpuart32_read(&sport->port, UARTFIFO);
1333
1334         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1335                 UARTFIFO_FIFOSIZE_MASK) - 1);
1336
1337         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1338                 UARTFIFO_FIFOSIZE_MASK) - 1);
1339
1340         spin_lock_irqsave(&sport->port.lock, flags);
1341
1342         lpuart32_setup_watermark(sport);
1343
1344         temp = lpuart32_read(&sport->port, UARTCTRL);
1345         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1346         temp |= UARTCTRL_ILIE;
1347         lpuart32_write(&sport->port, temp, UARTCTRL);
1348
1349         spin_unlock_irqrestore(&sport->port.lock, flags);
1350         return 0;
1351 }
1352
1353 static void lpuart_shutdown(struct uart_port *port)
1354 {
1355         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1356         unsigned char temp;
1357         unsigned long flags;
1358
1359         spin_lock_irqsave(&port->lock, flags);
1360
1361         /* disable Rx/Tx and interrupts */
1362         temp = readb(port->membase + UARTCR2);
1363         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1364                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1365         writeb(temp, port->membase + UARTCR2);
1366
1367         spin_unlock_irqrestore(&port->lock, flags);
1368
1369         if (sport->lpuart_dma_rx_use) {
1370                 del_timer_sync(&sport->lpuart_timer);
1371                 lpuart_dma_rx_free(&sport->port);
1372         }
1373
1374         if (sport->lpuart_dma_tx_use) {
1375                 if (wait_event_interruptible(sport->dma_wait,
1376                         !sport->dma_tx_in_progress) != false) {
1377                         sport->dma_tx_in_progress = false;
1378                         dmaengine_terminate_all(sport->dma_tx_chan);
1379                 }
1380
1381                 lpuart_stop_tx(port);
1382         }
1383 }
1384
1385 static void lpuart32_shutdown(struct uart_port *port)
1386 {
1387         unsigned long temp;
1388         unsigned long flags;
1389
1390         spin_lock_irqsave(&port->lock, flags);
1391
1392         /* disable Rx/Tx and interrupts */
1393         temp = lpuart32_read(port, UARTCTRL);
1394         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1395                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1396         lpuart32_write(port, temp, UARTCTRL);
1397
1398         spin_unlock_irqrestore(&port->lock, flags);
1399 }
1400
1401 static void
1402 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1403                    struct ktermios *old)
1404 {
1405         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1406         unsigned long flags;
1407         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1408         unsigned int  baud;
1409         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1410         unsigned int sbr, brfa;
1411
1412         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1413         old_cr2 = readb(sport->port.membase + UARTCR2);
1414         cr3 = readb(sport->port.membase + UARTCR3);
1415         cr4 = readb(sport->port.membase + UARTCR4);
1416         bdh = readb(sport->port.membase + UARTBDH);
1417         modem = readb(sport->port.membase + UARTMODEM);
1418         /*
1419          * only support CS8 and CS7, and for CS7 must enable PE.
1420          * supported mode:
1421          *  - (7,e/o,1)
1422          *  - (8,n,1)
1423          *  - (8,m/s,1)
1424          *  - (8,e/o,1)
1425          */
1426         while ((termios->c_cflag & CSIZE) != CS8 &&
1427                 (termios->c_cflag & CSIZE) != CS7) {
1428                 termios->c_cflag &= ~CSIZE;
1429                 termios->c_cflag |= old_csize;
1430                 old_csize = CS8;
1431         }
1432
1433         if ((termios->c_cflag & CSIZE) == CS8 ||
1434                 (termios->c_cflag & CSIZE) == CS7)
1435                 cr1 = old_cr1 & ~UARTCR1_M;
1436
1437         if (termios->c_cflag & CMSPAR) {
1438                 if ((termios->c_cflag & CSIZE) != CS8) {
1439                         termios->c_cflag &= ~CSIZE;
1440                         termios->c_cflag |= CS8;
1441                 }
1442                 cr1 |= UARTCR1_M;
1443         }
1444
1445         /*
1446          * When auto RS-485 RTS mode is enabled,
1447          * hardware flow control need to be disabled.
1448          */
1449         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1450                 termios->c_cflag &= ~CRTSCTS;
1451
1452         if (termios->c_cflag & CRTSCTS) {
1453                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1454         } else {
1455                 termios->c_cflag &= ~CRTSCTS;
1456                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1457         }
1458
1459         if (termios->c_cflag & CSTOPB)
1460                 termios->c_cflag &= ~CSTOPB;
1461
1462         /* parity must be enabled when CS7 to match 8-bits format */
1463         if ((termios->c_cflag & CSIZE) == CS7)
1464                 termios->c_cflag |= PARENB;
1465
1466         if ((termios->c_cflag & PARENB)) {
1467                 if (termios->c_cflag & CMSPAR) {
1468                         cr1 &= ~UARTCR1_PE;
1469                         if (termios->c_cflag & PARODD)
1470                                 cr3 |= UARTCR3_T8;
1471                         else
1472                                 cr3 &= ~UARTCR3_T8;
1473                 } else {
1474                         cr1 |= UARTCR1_PE;
1475                         if ((termios->c_cflag & CSIZE) == CS8)
1476                                 cr1 |= UARTCR1_M;
1477                         if (termios->c_cflag & PARODD)
1478                                 cr1 |= UARTCR1_PT;
1479                         else
1480                                 cr1 &= ~UARTCR1_PT;
1481                 }
1482         }
1483
1484         /* ask the core to calculate the divisor */
1485         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1486
1487         /*
1488          * Need to update the Ring buffer length according to the selected
1489          * baud rate and restart Rx DMA path.
1490          *
1491          * Since timer function acqures sport->port.lock, need to stop before
1492          * acquring same lock because otherwise del_timer_sync() can deadlock.
1493          */
1494         if (old && sport->lpuart_dma_rx_use) {
1495                 del_timer_sync(&sport->lpuart_timer);
1496                 lpuart_dma_rx_free(&sport->port);
1497         }
1498
1499         spin_lock_irqsave(&sport->port.lock, flags);
1500
1501         sport->port.read_status_mask = 0;
1502         if (termios->c_iflag & INPCK)
1503                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1504         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1505                 sport->port.read_status_mask |= UARTSR1_FE;
1506
1507         /* characters to ignore */
1508         sport->port.ignore_status_mask = 0;
1509         if (termios->c_iflag & IGNPAR)
1510                 sport->port.ignore_status_mask |= UARTSR1_PE;
1511         if (termios->c_iflag & IGNBRK) {
1512                 sport->port.ignore_status_mask |= UARTSR1_FE;
1513                 /*
1514                  * if we're ignoring parity and break indicators,
1515                  * ignore overruns too (for real raw support).
1516                  */
1517                 if (termios->c_iflag & IGNPAR)
1518                         sport->port.ignore_status_mask |= UARTSR1_OR;
1519         }
1520
1521         /* update the per-port timeout */
1522         uart_update_timeout(port, termios->c_cflag, baud);
1523
1524         /* wait transmit engin complete */
1525         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1526                 barrier();
1527
1528         /* disable transmit and receive */
1529         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1530                         sport->port.membase + UARTCR2);
1531
1532         sbr = sport->port.uartclk / (16 * baud);
1533         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1534         bdh &= ~UARTBDH_SBR_MASK;
1535         bdh |= (sbr >> 8) & 0x1F;
1536         cr4 &= ~UARTCR4_BRFA_MASK;
1537         brfa &= UARTCR4_BRFA_MASK;
1538         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1539         writeb(bdh, sport->port.membase + UARTBDH);
1540         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1541         writeb(cr3, sport->port.membase + UARTCR3);
1542         writeb(cr1, sport->port.membase + UARTCR1);
1543         writeb(modem, sport->port.membase + UARTMODEM);
1544
1545         /* restore control register */
1546         writeb(old_cr2, sport->port.membase + UARTCR2);
1547
1548         if (old && sport->lpuart_dma_rx_use) {
1549                 if (!lpuart_start_rx_dma(sport))
1550                         rx_dma_timer_init(sport);
1551                 else
1552                         sport->lpuart_dma_rx_use = false;
1553         }
1554
1555         spin_unlock_irqrestore(&sport->port.lock, flags);
1556 }
1557
1558 static void
1559 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1560 {
1561         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1562         u32 clk = sport->port.uartclk;
1563
1564         /*
1565          * The idea is to use the best OSR (over-sampling rate) possible.
1566          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1567          * Loop to find the best OSR value possible, one that generates minimum
1568          * baud_diff iterate through the rest of the supported values of OSR.
1569          *
1570          * Calculation Formula:
1571          *  Baud Rate = baud clock / ((OSR+1) × SBR)
1572          */
1573         baud_diff = baudrate;
1574         osr = 0;
1575         sbr = 0;
1576
1577         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1578                 /* calculate the temporary sbr value  */
1579                 tmp_sbr = (clk / (baudrate * tmp_osr));
1580                 if (tmp_sbr == 0)
1581                         tmp_sbr = 1;
1582
1583                 /*
1584                  * calculate the baud rate difference based on the temporary
1585                  * osr and sbr values
1586                  */
1587                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1588
1589                 /* select best values between sbr and sbr+1 */
1590                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1591                 if (tmp_diff > (baudrate - tmp)) {
1592                         tmp_diff = baudrate - tmp;
1593                         tmp_sbr++;
1594                 }
1595
1596                 if (tmp_diff <= baud_diff) {
1597                         baud_diff = tmp_diff;
1598                         osr = tmp_osr;
1599                         sbr = tmp_sbr;
1600
1601                         if (!baud_diff)
1602                                 break;
1603                 }
1604         }
1605
1606         /* handle buadrate outside acceptable rate */
1607         if (baud_diff > ((baudrate / 100) * 3))
1608                 dev_warn(sport->port.dev,
1609                          "unacceptable baud rate difference of more than 3%%\n");
1610
1611         tmp = lpuart32_read(&sport->port, UARTBAUD);
1612
1613         if ((osr > 3) && (osr < 8))
1614                 tmp |= UARTBAUD_BOTHEDGE;
1615
1616         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1617         tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
1618
1619         tmp &= ~UARTBAUD_SBR_MASK;
1620         tmp |= sbr & UARTBAUD_SBR_MASK;
1621
1622         tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1623
1624         lpuart32_write(&sport->port, tmp, UARTBAUD);
1625 }
1626
1627 static void
1628 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1629                    struct ktermios *old)
1630 {
1631         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1632         unsigned long flags;
1633         unsigned long ctrl, old_ctrl, modem;
1634         unsigned int  baud;
1635         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1636
1637         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1638         modem = lpuart32_read(&sport->port, UARTMODIR);
1639         /*
1640          * only support CS8 and CS7, and for CS7 must enable PE.
1641          * supported mode:
1642          *  - (7,e/o,1)
1643          *  - (8,n,1)
1644          *  - (8,m/s,1)
1645          *  - (8,e/o,1)
1646          */
1647         while ((termios->c_cflag & CSIZE) != CS8 &&
1648                 (termios->c_cflag & CSIZE) != CS7) {
1649                 termios->c_cflag &= ~CSIZE;
1650                 termios->c_cflag |= old_csize;
1651                 old_csize = CS8;
1652         }
1653
1654         if ((termios->c_cflag & CSIZE) == CS8 ||
1655                 (termios->c_cflag & CSIZE) == CS7)
1656                 ctrl = old_ctrl & ~UARTCTRL_M;
1657
1658         if (termios->c_cflag & CMSPAR) {
1659                 if ((termios->c_cflag & CSIZE) != CS8) {
1660                         termios->c_cflag &= ~CSIZE;
1661                         termios->c_cflag |= CS8;
1662                 }
1663                 ctrl |= UARTCTRL_M;
1664         }
1665
1666         if (termios->c_cflag & CRTSCTS) {
1667                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1668         } else {
1669                 termios->c_cflag &= ~CRTSCTS;
1670                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1671         }
1672
1673         if (termios->c_cflag & CSTOPB)
1674                 termios->c_cflag &= ~CSTOPB;
1675
1676         /* parity must be enabled when CS7 to match 8-bits format */
1677         if ((termios->c_cflag & CSIZE) == CS7)
1678                 termios->c_cflag |= PARENB;
1679
1680         if ((termios->c_cflag & PARENB)) {
1681                 if (termios->c_cflag & CMSPAR) {
1682                         ctrl &= ~UARTCTRL_PE;
1683                         ctrl |= UARTCTRL_M;
1684                 } else {
1685                         ctrl |= UARTCR1_PE;
1686                         if ((termios->c_cflag & CSIZE) == CS8)
1687                                 ctrl |= UARTCTRL_M;
1688                         if (termios->c_cflag & PARODD)
1689                                 ctrl |= UARTCTRL_PT;
1690                         else
1691                                 ctrl &= ~UARTCTRL_PT;
1692                 }
1693         }
1694
1695         /* ask the core to calculate the divisor */
1696         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1697
1698         spin_lock_irqsave(&sport->port.lock, flags);
1699
1700         sport->port.read_status_mask = 0;
1701         if (termios->c_iflag & INPCK)
1702                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1703         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1704                 sport->port.read_status_mask |= UARTSTAT_FE;
1705
1706         /* characters to ignore */
1707         sport->port.ignore_status_mask = 0;
1708         if (termios->c_iflag & IGNPAR)
1709                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1710         if (termios->c_iflag & IGNBRK) {
1711                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1712                 /*
1713                  * if we're ignoring parity and break indicators,
1714                  * ignore overruns too (for real raw support).
1715                  */
1716                 if (termios->c_iflag & IGNPAR)
1717                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1718         }
1719
1720         /* update the per-port timeout */
1721         uart_update_timeout(port, termios->c_cflag, baud);
1722
1723         /* wait transmit engin complete */
1724         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1725                 barrier();
1726
1727         /* disable transmit and receive */
1728         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1729                        UARTCTRL);
1730
1731         lpuart32_serial_setbrg(sport, baud);
1732         lpuart32_write(&sport->port, modem, UARTMODIR);
1733         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1734         /* restore control register */
1735
1736         spin_unlock_irqrestore(&sport->port.lock, flags);
1737 }
1738
1739 static const char *lpuart_type(struct uart_port *port)
1740 {
1741         return "FSL_LPUART";
1742 }
1743
1744 static void lpuart_release_port(struct uart_port *port)
1745 {
1746         /* nothing to do */
1747 }
1748
1749 static int lpuart_request_port(struct uart_port *port)
1750 {
1751         return  0;
1752 }
1753
1754 /* configure/autoconfigure the port */
1755 static void lpuart_config_port(struct uart_port *port, int flags)
1756 {
1757         if (flags & UART_CONFIG_TYPE)
1758                 port->type = PORT_LPUART;
1759 }
1760
1761 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1762 {
1763         int ret = 0;
1764
1765         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1766                 ret = -EINVAL;
1767         if (port->irq != ser->irq)
1768                 ret = -EINVAL;
1769         if (ser->io_type != UPIO_MEM)
1770                 ret = -EINVAL;
1771         if (port->uartclk / 16 != ser->baud_base)
1772                 ret = -EINVAL;
1773         if (port->iobase != ser->port)
1774                 ret = -EINVAL;
1775         if (ser->hub6 != 0)
1776                 ret = -EINVAL;
1777         return ret;
1778 }
1779
1780 static const struct uart_ops lpuart_pops = {
1781         .tx_empty       = lpuart_tx_empty,
1782         .set_mctrl      = lpuart_set_mctrl,
1783         .get_mctrl      = lpuart_get_mctrl,
1784         .stop_tx        = lpuart_stop_tx,
1785         .start_tx       = lpuart_start_tx,
1786         .stop_rx        = lpuart_stop_rx,
1787         .break_ctl      = lpuart_break_ctl,
1788         .startup        = lpuart_startup,
1789         .shutdown       = lpuart_shutdown,
1790         .set_termios    = lpuart_set_termios,
1791         .type           = lpuart_type,
1792         .request_port   = lpuart_request_port,
1793         .release_port   = lpuart_release_port,
1794         .config_port    = lpuart_config_port,
1795         .verify_port    = lpuart_verify_port,
1796         .flush_buffer   = lpuart_flush_buffer,
1797 #if defined(CONFIG_CONSOLE_POLL)
1798         .poll_init      = lpuart_poll_init,
1799         .poll_get_char  = lpuart_poll_get_char,
1800         .poll_put_char  = lpuart_poll_put_char,
1801 #endif
1802 };
1803
1804 static const struct uart_ops lpuart32_pops = {
1805         .tx_empty       = lpuart32_tx_empty,
1806         .set_mctrl      = lpuart32_set_mctrl,
1807         .get_mctrl      = lpuart32_get_mctrl,
1808         .stop_tx        = lpuart32_stop_tx,
1809         .start_tx       = lpuart32_start_tx,
1810         .stop_rx        = lpuart32_stop_rx,
1811         .break_ctl      = lpuart32_break_ctl,
1812         .startup        = lpuart32_startup,
1813         .shutdown       = lpuart32_shutdown,
1814         .set_termios    = lpuart32_set_termios,
1815         .type           = lpuart_type,
1816         .request_port   = lpuart_request_port,
1817         .release_port   = lpuart_release_port,
1818         .config_port    = lpuart_config_port,
1819         .verify_port    = lpuart_verify_port,
1820         .flush_buffer   = lpuart_flush_buffer,
1821 #if defined(CONFIG_CONSOLE_POLL)
1822         .poll_init      = lpuart32_poll_init,
1823         .poll_get_char  = lpuart32_poll_get_char,
1824         .poll_put_char  = lpuart32_poll_put_char,
1825 #endif
1826 };
1827
1828 static struct lpuart_port *lpuart_ports[UART_NR];
1829
1830 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1831 static void lpuart_console_putchar(struct uart_port *port, int ch)
1832 {
1833         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1834                 barrier();
1835
1836         writeb(ch, port->membase + UARTDR);
1837 }
1838
1839 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1840 {
1841         while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
1842                 barrier();
1843
1844         lpuart32_write(port, ch, UARTDATA);
1845 }
1846
1847 static void
1848 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1849 {
1850         struct lpuart_port *sport = lpuart_ports[co->index];
1851         unsigned char  old_cr2, cr2;
1852         unsigned long flags;
1853         int locked = 1;
1854
1855         if (sport->port.sysrq || oops_in_progress)
1856                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1857         else
1858                 spin_lock_irqsave(&sport->port.lock, flags);
1859
1860         /* first save CR2 and then disable interrupts */
1861         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1862         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1863         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1864         writeb(cr2, sport->port.membase + UARTCR2);
1865
1866         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1867
1868         /* wait for transmitter finish complete and restore CR2 */
1869         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1870                 barrier();
1871
1872         writeb(old_cr2, sport->port.membase + UARTCR2);
1873
1874         if (locked)
1875                 spin_unlock_irqrestore(&sport->port.lock, flags);
1876 }
1877
1878 static void
1879 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1880 {
1881         struct lpuart_port *sport = lpuart_ports[co->index];
1882         unsigned long  old_cr, cr;
1883         unsigned long flags;
1884         int locked = 1;
1885
1886         if (sport->port.sysrq || oops_in_progress)
1887                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1888         else
1889                 spin_lock_irqsave(&sport->port.lock, flags);
1890
1891         /* first save CR2 and then disable interrupts */
1892         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
1893         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1894         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1895         lpuart32_write(&sport->port, cr, UARTCTRL);
1896
1897         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1898
1899         /* wait for transmitter finish complete and restore CR2 */
1900         while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
1901                 barrier();
1902
1903         lpuart32_write(&sport->port, old_cr, UARTCTRL);
1904
1905         if (locked)
1906                 spin_unlock_irqrestore(&sport->port.lock, flags);
1907 }
1908
1909 /*
1910  * if the port was already initialised (eg, by a boot loader),
1911  * try to determine the current setup.
1912  */
1913 static void __init
1914 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1915                            int *parity, int *bits)
1916 {
1917         unsigned char cr, bdh, bdl, brfa;
1918         unsigned int sbr, uartclk, baud_raw;
1919
1920         cr = readb(sport->port.membase + UARTCR2);
1921         cr &= UARTCR2_TE | UARTCR2_RE;
1922         if (!cr)
1923                 return;
1924
1925         /* ok, the port was enabled */
1926
1927         cr = readb(sport->port.membase + UARTCR1);
1928
1929         *parity = 'n';
1930         if (cr & UARTCR1_PE) {
1931                 if (cr & UARTCR1_PT)
1932                         *parity = 'o';
1933                 else
1934                         *parity = 'e';
1935         }
1936
1937         if (cr & UARTCR1_M)
1938                 *bits = 9;
1939         else
1940                 *bits = 8;
1941
1942         bdh = readb(sport->port.membase + UARTBDH);
1943         bdh &= UARTBDH_SBR_MASK;
1944         bdl = readb(sport->port.membase + UARTBDL);
1945         sbr = bdh;
1946         sbr <<= 8;
1947         sbr |= bdl;
1948         brfa = readb(sport->port.membase + UARTCR4);
1949         brfa &= UARTCR4_BRFA_MASK;
1950
1951         uartclk = clk_get_rate(sport->clk);
1952         /*
1953          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1954          */
1955         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1956
1957         if (*baud != baud_raw)
1958                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1959                                 "from %d to %d\n", baud_raw, *baud);
1960 }
1961
1962 static void __init
1963 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1964                            int *parity, int *bits)
1965 {
1966         unsigned long cr, bd;
1967         unsigned int sbr, uartclk, baud_raw;
1968
1969         cr = lpuart32_read(&sport->port, UARTCTRL);
1970         cr &= UARTCTRL_TE | UARTCTRL_RE;
1971         if (!cr)
1972                 return;
1973
1974         /* ok, the port was enabled */
1975
1976         cr = lpuart32_read(&sport->port, UARTCTRL);
1977
1978         *parity = 'n';
1979         if (cr & UARTCTRL_PE) {
1980                 if (cr & UARTCTRL_PT)
1981                         *parity = 'o';
1982                 else
1983                         *parity = 'e';
1984         }
1985
1986         if (cr & UARTCTRL_M)
1987                 *bits = 9;
1988         else
1989                 *bits = 8;
1990
1991         bd = lpuart32_read(&sport->port, UARTBAUD);
1992         bd &= UARTBAUD_SBR_MASK;
1993         sbr = bd;
1994         uartclk = clk_get_rate(sport->clk);
1995         /*
1996          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1997          */
1998         baud_raw = uartclk / (16 * sbr);
1999
2000         if (*baud != baud_raw)
2001                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
2002                                 "from %d to %d\n", baud_raw, *baud);
2003 }
2004
2005 static int __init lpuart_console_setup(struct console *co, char *options)
2006 {
2007         struct lpuart_port *sport;
2008         int baud = 115200;
2009         int bits = 8;
2010         int parity = 'n';
2011         int flow = 'n';
2012
2013         /*
2014          * check whether an invalid uart number has been specified, and
2015          * if so, search for the first available port that does have
2016          * console support.
2017          */
2018         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2019                 co->index = 0;
2020
2021         sport = lpuart_ports[co->index];
2022         if (sport == NULL)
2023                 return -ENODEV;
2024
2025         if (options)
2026                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2027         else
2028                 if (lpuart_is_32(sport))
2029                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2030                 else
2031                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2032
2033         if (lpuart_is_32(sport))
2034                 lpuart32_setup_watermark(sport);
2035         else
2036                 lpuart_setup_watermark(sport);
2037
2038         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2039 }
2040
2041 static struct uart_driver lpuart_reg;
2042 static struct console lpuart_console = {
2043         .name           = DEV_NAME,
2044         .write          = lpuart_console_write,
2045         .device         = uart_console_device,
2046         .setup          = lpuart_console_setup,
2047         .flags          = CON_PRINTBUFFER,
2048         .index          = -1,
2049         .data           = &lpuart_reg,
2050 };
2051
2052 static struct console lpuart32_console = {
2053         .name           = DEV_NAME,
2054         .write          = lpuart32_console_write,
2055         .device         = uart_console_device,
2056         .setup          = lpuart_console_setup,
2057         .flags          = CON_PRINTBUFFER,
2058         .index          = -1,
2059         .data           = &lpuart_reg,
2060 };
2061
2062 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2063 {
2064         struct earlycon_device *dev = con->data;
2065
2066         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2067 }
2068
2069 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2070 {
2071         struct earlycon_device *dev = con->data;
2072
2073         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2074 }
2075
2076 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2077                                           const char *opt)
2078 {
2079         if (!device->port.membase)
2080                 return -ENODEV;
2081
2082         device->con->write = lpuart_early_write;
2083         return 0;
2084 }
2085
2086 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2087                                           const char *opt)
2088 {
2089         if (!device->port.membase)
2090                 return -ENODEV;
2091
2092         device->port.iotype = UPIO_MEM32BE;
2093         device->con->write = lpuart32_early_write;
2094         return 0;
2095 }
2096
2097 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2098                                                    const char *opt)
2099 {
2100         if (!device->port.membase)
2101                 return -ENODEV;
2102
2103         device->port.iotype = UPIO_MEM32;
2104         device->port.membase += IMX_REG_OFF;
2105         device->con->write = lpuart32_early_write;
2106
2107         return 0;
2108 }
2109 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2110 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2111 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2112 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2113 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2114
2115 #define LPUART_CONSOLE  (&lpuart_console)
2116 #define LPUART32_CONSOLE        (&lpuart32_console)
2117 #else
2118 #define LPUART_CONSOLE  NULL
2119 #define LPUART32_CONSOLE        NULL
2120 #endif
2121
2122 static struct uart_driver lpuart_reg = {
2123         .owner          = THIS_MODULE,
2124         .driver_name    = DRIVER_NAME,
2125         .dev_name       = DEV_NAME,
2126         .nr             = ARRAY_SIZE(lpuart_ports),
2127         .cons           = LPUART_CONSOLE,
2128 };
2129
2130 static int lpuart_probe(struct platform_device *pdev)
2131 {
2132         const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2133                                                            &pdev->dev);
2134         const struct lpuart_soc_data *sdata = of_id->data;
2135         struct device_node *np = pdev->dev.of_node;
2136         struct lpuart_port *sport;
2137         struct resource *res;
2138         int ret;
2139
2140         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2141         if (!sport)
2142                 return -ENOMEM;
2143
2144         pdev->dev.coherent_dma_mask = 0;
2145
2146         ret = of_alias_get_id(np, "serial");
2147         if (ret < 0) {
2148                 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2149                 if (ret < 0) {
2150                         dev_err(&pdev->dev, "port line is full, add device failed\n");
2151                         return ret;
2152                 }
2153         }
2154         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2155                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2156                 return -EINVAL;
2157         }
2158         sport->port.line = ret;
2159         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2160         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2161         if (IS_ERR(sport->port.membase))
2162                 return PTR_ERR(sport->port.membase);
2163
2164         sport->port.membase += sdata->reg_off;
2165         sport->port.mapbase = res->start;
2166         sport->port.dev = &pdev->dev;
2167         sport->port.type = PORT_LPUART;
2168         ret = platform_get_irq(pdev, 0);
2169         if (ret < 0) {
2170                 dev_err(&pdev->dev, "cannot obtain irq\n");
2171                 return ret;
2172         }
2173         sport->port.irq = ret;
2174         sport->port.iotype = sdata->iotype;
2175         if (lpuart_is_32(sport))
2176                 sport->port.ops = &lpuart32_pops;
2177         else
2178                 sport->port.ops = &lpuart_pops;
2179         sport->port.flags = UPF_BOOT_AUTOCONF;
2180
2181         sport->port.rs485_config = lpuart_config_rs485;
2182
2183         sport->clk = devm_clk_get(&pdev->dev, "ipg");
2184         if (IS_ERR(sport->clk)) {
2185                 ret = PTR_ERR(sport->clk);
2186                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2187                 return ret;
2188         }
2189
2190         ret = clk_prepare_enable(sport->clk);
2191         if (ret) {
2192                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2193                 return ret;
2194         }
2195
2196         sport->port.uartclk = clk_get_rate(sport->clk);
2197
2198         lpuart_ports[sport->port.line] = sport;
2199
2200         platform_set_drvdata(pdev, &sport->port);
2201
2202         if (lpuart_is_32(sport)) {
2203                 lpuart_reg.cons = LPUART32_CONSOLE;
2204                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2205                                         DRIVER_NAME, sport);
2206         } else {
2207                 lpuart_reg.cons = LPUART_CONSOLE;
2208                 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2209                                         DRIVER_NAME, sport);
2210         }
2211
2212         if (ret)
2213                 goto failed_irq_request;
2214
2215         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2216         if (ret)
2217                 goto failed_attach_port;
2218
2219         uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2220
2221         if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2222                 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2223
2224         if (sport->port.rs485.delay_rts_before_send ||
2225             sport->port.rs485.delay_rts_after_send)
2226                 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2227
2228         lpuart_config_rs485(&sport->port, &sport->port.rs485);
2229
2230         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2231         if (!sport->dma_tx_chan)
2232                 dev_info(sport->port.dev, "DMA tx channel request failed, "
2233                                 "operating without tx DMA\n");
2234
2235         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2236         if (!sport->dma_rx_chan)
2237                 dev_info(sport->port.dev, "DMA rx channel request failed, "
2238                                 "operating without rx DMA\n");
2239
2240         return 0;
2241
2242 failed_attach_port:
2243 failed_irq_request:
2244         clk_disable_unprepare(sport->clk);
2245         return ret;
2246 }
2247
2248 static int lpuart_remove(struct platform_device *pdev)
2249 {
2250         struct lpuart_port *sport = platform_get_drvdata(pdev);
2251
2252         uart_remove_one_port(&lpuart_reg, &sport->port);
2253
2254         ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2255
2256         clk_disable_unprepare(sport->clk);
2257
2258         if (sport->dma_tx_chan)
2259                 dma_release_channel(sport->dma_tx_chan);
2260
2261         if (sport->dma_rx_chan)
2262                 dma_release_channel(sport->dma_rx_chan);
2263
2264         return 0;
2265 }
2266
2267 #ifdef CONFIG_PM_SLEEP
2268 static int lpuart_suspend(struct device *dev)
2269 {
2270         struct lpuart_port *sport = dev_get_drvdata(dev);
2271         unsigned long temp;
2272         bool irq_wake;
2273
2274         if (lpuart_is_32(sport)) {
2275                 /* disable Rx/Tx and interrupts */
2276                 temp = lpuart32_read(&sport->port, UARTCTRL);
2277                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2278                 lpuart32_write(&sport->port, temp, UARTCTRL);
2279         } else {
2280                 /* disable Rx/Tx and interrupts */
2281                 temp = readb(sport->port.membase + UARTCR2);
2282                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2283                 writeb(temp, sport->port.membase + UARTCR2);
2284         }
2285
2286         uart_suspend_port(&lpuart_reg, &sport->port);
2287
2288         /* uart_suspend_port() might set wakeup flag */
2289         irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2290
2291         if (sport->lpuart_dma_rx_use) {
2292                 /*
2293                  * EDMA driver during suspend will forcefully release any
2294                  * non-idle DMA channels. If port wakeup is enabled or if port
2295                  * is console port or 'no_console_suspend' is set the Rx DMA
2296                  * cannot resume as as expected, hence gracefully release the
2297                  * Rx DMA path before suspend and start Rx DMA path on resume.
2298                  */
2299                 if (irq_wake) {
2300                         del_timer_sync(&sport->lpuart_timer);
2301                         lpuart_dma_rx_free(&sport->port);
2302                 }
2303
2304                 /* Disable Rx DMA to use UART port as wakeup source */
2305                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2306                                         sport->port.membase + UARTCR5);
2307         }
2308
2309         if (sport->lpuart_dma_tx_use) {
2310                 sport->dma_tx_in_progress = false;
2311                 dmaengine_terminate_all(sport->dma_tx_chan);
2312         }
2313
2314         if (sport->port.suspended && !irq_wake)
2315                 clk_disable_unprepare(sport->clk);
2316
2317         return 0;
2318 }
2319
2320 static int lpuart_resume(struct device *dev)
2321 {
2322         struct lpuart_port *sport = dev_get_drvdata(dev);
2323         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2324         unsigned long temp;
2325
2326         if (sport->port.suspended && !irq_wake)
2327                 clk_prepare_enable(sport->clk);
2328
2329         if (lpuart_is_32(sport)) {
2330                 lpuart32_setup_watermark(sport);
2331                 temp = lpuart32_read(&sport->port, UARTCTRL);
2332                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2333                          UARTCTRL_TE | UARTCTRL_ILIE);
2334                 lpuart32_write(&sport->port, temp, UARTCTRL);
2335         } else {
2336                 lpuart_setup_watermark(sport);
2337                 temp = readb(sport->port.membase + UARTCR2);
2338                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2339                 writeb(temp, sport->port.membase + UARTCR2);
2340         }
2341
2342         if (sport->lpuart_dma_rx_use) {
2343                 if (irq_wake) {
2344                         if (!lpuart_start_rx_dma(sport))
2345                                 rx_dma_timer_init(sport);
2346                         else
2347                                 sport->lpuart_dma_rx_use = false;
2348                 }
2349         }
2350
2351         if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2352                         init_waitqueue_head(&sport->dma_wait);
2353                         sport->lpuart_dma_tx_use = true;
2354                         writeb(readb(sport->port.membase + UARTCR5) |
2355                                 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2356         } else {
2357                 sport->lpuart_dma_tx_use = false;
2358         }
2359
2360         uart_resume_port(&lpuart_reg, &sport->port);
2361
2362         return 0;
2363 }
2364 #endif
2365
2366 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2367
2368 static struct platform_driver lpuart_driver = {
2369         .probe          = lpuart_probe,
2370         .remove         = lpuart_remove,
2371         .driver         = {
2372                 .name   = "fsl-lpuart",
2373                 .of_match_table = lpuart_dt_ids,
2374                 .pm     = &lpuart_pm_ops,
2375         },
2376 };
2377
2378 static int __init lpuart_serial_init(void)
2379 {
2380         int ret = uart_register_driver(&lpuart_reg);
2381
2382         if (ret)
2383                 return ret;
2384
2385         ret = platform_driver_register(&lpuart_driver);
2386         if (ret)
2387                 uart_unregister_driver(&lpuart_reg);
2388
2389         return ret;
2390 }
2391
2392 static void __exit lpuart_serial_exit(void)
2393 {
2394         ida_destroy(&fsl_lpuart_ida);
2395         platform_driver_unregister(&lpuart_driver);
2396         uart_unregister_driver(&lpuart_reg);
2397 }
2398
2399 module_init(lpuart_serial_init);
2400 module_exit(lpuart_serial_exit);
2401
2402 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2403 MODULE_LICENSE("GPL v2");