2 * Driver for Atmel AT91 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/tty.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/serial.h>
30 #include <linux/clk.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/tty_flip.h>
34 #include <linux/platform_device.h>
36 #include <linux/of_device.h>
37 #include <linux/of_gpio.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/atmel_pdc.h>
41 #include <linux/uaccess.h>
42 #include <linux/platform_data/atmel.h>
43 #include <linux/timer.h>
44 #include <linux/gpio.h>
45 #include <linux/gpio/consumer.h>
46 #include <linux/err.h>
47 #include <linux/irq.h>
48 #include <linux/suspend.h>
52 #include <asm/ioctls.h>
54 #define PDC_BUFFER_SIZE 512
55 /* Revisit: We should calculate this based on the actual port settings */
56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
58 /* The minium number of data FIFOs should be able to contain */
59 #define ATMEL_MIN_FIFO_SIZE 8
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
64 #define ATMEL_RTS_HIGH_OFFSET 16
65 #define ATMEL_RTS_LOW_OFFSET 20
67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
71 #include <linux/serial_core.h>
73 #include "serial_mctrl_gpio.h"
74 #include "atmel_serial.h"
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
98 #define ATMEL_ISR_PASS_LIMIT 256
100 struct atmel_dma_buffer {
103 unsigned int dma_size;
107 struct atmel_uart_char {
113 * Be careful, the real size of the ring buffer is
114 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
115 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
118 #define ATMEL_SERIAL_RINGSIZE 1024
121 * at91: 6 USARTs and one DBGU port (SAM9260)
122 * samx7: 3 USARTs and 5 UARTs
124 #define ATMEL_MAX_UART 8
127 * We wrap our port structure around the generic uart_port.
129 struct atmel_uart_port {
130 struct uart_port uart; /* uart */
131 struct clk *clk; /* uart clock */
132 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
133 u32 backup_imr; /* IMR saved during suspend */
134 int break_active; /* break being received */
136 bool use_dma_rx; /* enable DMA receiver */
137 bool use_pdc_rx; /* enable PDC receiver */
138 short pdc_rx_idx; /* current PDC RX buffer */
139 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
141 bool use_dma_tx; /* enable DMA transmitter */
142 bool use_pdc_tx; /* enable PDC transmitter */
143 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
145 spinlock_t lock_tx; /* port lock */
146 spinlock_t lock_rx; /* port lock */
147 struct dma_chan *chan_tx;
148 struct dma_chan *chan_rx;
149 struct dma_async_tx_descriptor *desc_tx;
150 struct dma_async_tx_descriptor *desc_rx;
151 dma_cookie_t cookie_tx;
152 dma_cookie_t cookie_rx;
153 struct scatterlist sg_tx;
154 struct scatterlist sg_rx;
155 struct tasklet_struct tasklet_rx;
156 struct tasklet_struct tasklet_tx;
157 atomic_t tasklet_shutdown;
158 unsigned int irq_status_prev;
161 struct circ_buf rx_ring;
163 struct mctrl_gpios *gpios;
164 unsigned int tx_done_mask;
169 u32 rtor; /* address of receiver timeout register if it exists */
170 bool has_frac_baudrate;
172 struct timer_list uart_timer;
175 unsigned int pending;
176 unsigned int pending_status;
177 spinlock_t lock_suspended;
192 int (*prepare_rx)(struct uart_port *port);
193 int (*prepare_tx)(struct uart_port *port);
194 void (*schedule_rx)(struct uart_port *port);
195 void (*schedule_tx)(struct uart_port *port);
196 void (*release_rx)(struct uart_port *port);
197 void (*release_tx)(struct uart_port *port);
200 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
201 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
204 static struct console atmel_console;
207 #if defined(CONFIG_OF)
208 static const struct of_device_id atmel_serial_dt_ids[] = {
209 { .compatible = "atmel,at91rm9200-usart" },
210 { .compatible = "atmel,at91sam9260-usart" },
215 static inline struct atmel_uart_port *
216 to_atmel_uart_port(struct uart_port *uart)
218 return container_of(uart, struct atmel_uart_port, uart);
221 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
223 return __raw_readl(port->membase + reg);
226 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
228 __raw_writel(value, port->membase + reg);
231 static inline u8 atmel_uart_read_char(struct uart_port *port)
233 return __raw_readb(port->membase + ATMEL_US_RHR);
236 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
238 __raw_writeb(value, port->membase + ATMEL_US_THR);
241 #ifdef CONFIG_SERIAL_ATMEL_PDC
242 static bool atmel_use_pdc_rx(struct uart_port *port)
244 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
246 return atmel_port->use_pdc_rx;
249 static bool atmel_use_pdc_tx(struct uart_port *port)
251 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
253 return atmel_port->use_pdc_tx;
256 static bool atmel_use_pdc_rx(struct uart_port *port)
261 static bool atmel_use_pdc_tx(struct uart_port *port)
267 static bool atmel_use_dma_tx(struct uart_port *port)
269 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
271 return atmel_port->use_dma_tx;
274 static bool atmel_use_dma_rx(struct uart_port *port)
276 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
278 return atmel_port->use_dma_rx;
281 static bool atmel_use_fifo(struct uart_port *port)
283 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
285 return atmel_port->fifo_size;
288 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
289 struct tasklet_struct *t)
291 if (!atomic_read(&atmel_port->tasklet_shutdown))
295 static unsigned int atmel_get_lines_status(struct uart_port *port)
297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
298 unsigned int status, ret = 0;
300 status = atmel_uart_readl(port, ATMEL_US_CSR);
302 mctrl_gpio_get(atmel_port->gpios, &ret);
304 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 status &= ~ATMEL_US_CTS;
309 status |= ATMEL_US_CTS;
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 status &= ~ATMEL_US_DSR;
317 status |= ATMEL_US_DSR;
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 status &= ~ATMEL_US_RI;
325 status |= ATMEL_US_RI;
328 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
331 status &= ~ATMEL_US_DCD;
333 status |= ATMEL_US_DCD;
339 /* Enable or disable the rs485 support */
340 static int atmel_config_rs485(struct uart_port *port,
341 struct serial_rs485 *rs485conf)
343 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
346 /* Disable interrupts */
347 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
349 mode = atmel_uart_readl(port, ATMEL_US_MR);
351 /* Resetting serial mode to RS232 (0x0) */
352 mode &= ~ATMEL_US_USMODE;
354 port->rs485 = *rs485conf;
356 if (rs485conf->flags & SER_RS485_ENABLED) {
357 dev_dbg(port->dev, "Setting UART to RS485\n");
358 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
359 atmel_uart_writel(port, ATMEL_US_TTGR,
360 rs485conf->delay_rts_after_send);
361 mode |= ATMEL_US_USMODE_RS485;
363 dev_dbg(port->dev, "Setting UART to RS232\n");
364 if (atmel_use_pdc_tx(port))
365 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
368 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
370 atmel_uart_writel(port, ATMEL_US_MR, mode);
372 /* Enable interrupts */
373 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
379 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
381 static u_int atmel_tx_empty(struct uart_port *port)
383 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
389 * Set state of the modem control output lines
391 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
393 unsigned int control = 0;
394 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
395 unsigned int rts_paused, rts_ready;
396 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
398 /* override mode to RS485 if needed, otherwise keep the current mode */
399 if (port->rs485.flags & SER_RS485_ENABLED) {
400 atmel_uart_writel(port, ATMEL_US_TTGR,
401 port->rs485.delay_rts_after_send);
402 mode &= ~ATMEL_US_USMODE;
403 mode |= ATMEL_US_USMODE_RS485;
406 /* set the RTS line state according to the mode */
407 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
408 /* force RTS line to high level */
409 rts_paused = ATMEL_US_RTSEN;
411 /* give the control of the RTS line back to the hardware */
412 rts_ready = ATMEL_US_RTSDIS;
414 /* force RTS line to high level */
415 rts_paused = ATMEL_US_RTSDIS;
417 /* force RTS line to low level */
418 rts_ready = ATMEL_US_RTSEN;
421 if (mctrl & TIOCM_RTS)
422 control |= rts_ready;
424 control |= rts_paused;
426 if (mctrl & TIOCM_DTR)
427 control |= ATMEL_US_DTREN;
429 control |= ATMEL_US_DTRDIS;
431 atmel_uart_writel(port, ATMEL_US_CR, control);
433 mctrl_gpio_set(atmel_port->gpios, mctrl);
435 /* Local loopback mode? */
436 mode &= ~ATMEL_US_CHMODE;
437 if (mctrl & TIOCM_LOOP)
438 mode |= ATMEL_US_CHMODE_LOC_LOOP;
440 mode |= ATMEL_US_CHMODE_NORMAL;
442 atmel_uart_writel(port, ATMEL_US_MR, mode);
446 * Get state of the modem control input lines
448 static u_int atmel_get_mctrl(struct uart_port *port)
450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
451 unsigned int ret = 0, status;
453 status = atmel_uart_readl(port, ATMEL_US_CSR);
456 * The control signals are active low.
458 if (!(status & ATMEL_US_DCD))
460 if (!(status & ATMEL_US_CTS))
462 if (!(status & ATMEL_US_DSR))
464 if (!(status & ATMEL_US_RI))
467 return mctrl_gpio_get(atmel_port->gpios, &ret);
473 static void atmel_stop_tx(struct uart_port *port)
475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
477 if (atmel_use_pdc_tx(port)) {
478 /* disable PDC transmit */
479 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
483 * Disable the transmitter.
484 * This is mandatory when DMA is used, otherwise the DMA buffer
485 * is fully transmitted.
487 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
489 /* Disable interrupts */
490 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
492 if ((port->rs485.flags & SER_RS485_ENABLED) &&
493 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
494 atmel_start_rx(port);
498 * Start transmitting.
500 static void atmel_start_tx(struct uart_port *port)
502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
504 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
506 /* The transmitter is already running. Yes, we
510 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
511 if ((port->rs485.flags & SER_RS485_ENABLED) &&
512 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
515 if (atmel_use_pdc_tx(port))
516 /* re-enable PDC transmit */
517 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
519 /* Enable interrupts */
520 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
522 /* re-enable the transmitter */
523 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
527 * start receiving - port is in process of being opened.
529 static void atmel_start_rx(struct uart_port *port)
531 /* reset status and receiver */
532 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
534 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
536 if (atmel_use_pdc_rx(port)) {
537 /* enable PDC controller */
538 atmel_uart_writel(port, ATMEL_US_IER,
539 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
540 port->read_status_mask);
541 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
543 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
548 * Stop receiving - port is in process of being closed.
550 static void atmel_stop_rx(struct uart_port *port)
552 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
554 if (atmel_use_pdc_rx(port)) {
555 /* disable PDC receive */
556 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
557 atmel_uart_writel(port, ATMEL_US_IDR,
558 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
559 port->read_status_mask);
561 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
566 * Enable modem status interrupts
568 static void atmel_enable_ms(struct uart_port *port)
570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
574 * Interrupt should not be enabled twice
576 if (atmel_port->ms_irq_enabled)
579 atmel_port->ms_irq_enabled = true;
581 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
582 ier |= ATMEL_US_CTSIC;
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
585 ier |= ATMEL_US_DSRIC;
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
588 ier |= ATMEL_US_RIIC;
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
591 ier |= ATMEL_US_DCDIC;
593 atmel_uart_writel(port, ATMEL_US_IER, ier);
595 mctrl_gpio_enable_ms(atmel_port->gpios);
599 * Disable modem status interrupts
601 static void atmel_disable_ms(struct uart_port *port)
603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
607 * Interrupt should not be disabled twice
609 if (!atmel_port->ms_irq_enabled)
612 atmel_port->ms_irq_enabled = false;
614 mctrl_gpio_disable_ms(atmel_port->gpios);
616 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
617 idr |= ATMEL_US_CTSIC;
619 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
620 idr |= ATMEL_US_DSRIC;
622 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
623 idr |= ATMEL_US_RIIC;
625 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
626 idr |= ATMEL_US_DCDIC;
628 atmel_uart_writel(port, ATMEL_US_IDR, idr);
632 * Control the transmission of a break signal
634 static void atmel_break_ctl(struct uart_port *port, int break_state)
636 if (break_state != 0)
638 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
641 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
645 * Stores the incoming character in the ring buffer
648 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
652 struct circ_buf *ring = &atmel_port->rx_ring;
653 struct atmel_uart_char *c;
655 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
656 /* Buffer overflow, ignore char */
659 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
663 /* Make sure the character is stored before we update head. */
666 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
670 * Deal with parity, framing and overrun errors.
672 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
675 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
677 if (status & ATMEL_US_RXBRK) {
678 /* ignore side-effect */
679 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
682 if (status & ATMEL_US_PARE)
683 port->icount.parity++;
684 if (status & ATMEL_US_FRAME)
685 port->icount.frame++;
686 if (status & ATMEL_US_OVRE)
687 port->icount.overrun++;
691 * Characters received (called from interrupt handler)
693 static void atmel_rx_chars(struct uart_port *port)
695 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
696 unsigned int status, ch;
698 status = atmel_uart_readl(port, ATMEL_US_CSR);
699 while (status & ATMEL_US_RXRDY) {
700 ch = atmel_uart_read_char(port);
703 * note that the error handling code is
704 * out of the main execution path
706 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
707 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
708 || atmel_port->break_active)) {
711 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
713 if (status & ATMEL_US_RXBRK
714 && !atmel_port->break_active) {
715 atmel_port->break_active = 1;
716 atmel_uart_writel(port, ATMEL_US_IER,
720 * This is either the end-of-break
721 * condition or we've received at
722 * least one character without RXBRK
723 * being set. In both cases, the next
724 * RXBRK will indicate start-of-break.
726 atmel_uart_writel(port, ATMEL_US_IDR,
728 status &= ~ATMEL_US_RXBRK;
729 atmel_port->break_active = 0;
733 atmel_buffer_rx_char(port, status, ch);
734 status = atmel_uart_readl(port, ATMEL_US_CSR);
737 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
741 * Transmit characters (called from tasklet with TXRDY interrupt
744 static void atmel_tx_chars(struct uart_port *port)
746 struct circ_buf *xmit = &port->state->xmit;
747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
750 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
751 atmel_uart_write_char(port, port->x_char);
755 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
758 while (atmel_uart_readl(port, ATMEL_US_CSR) &
759 atmel_port->tx_done_mask) {
760 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
761 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
763 if (uart_circ_empty(xmit))
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
768 uart_write_wakeup(port);
770 if (!uart_circ_empty(xmit))
771 /* Enable interrupts */
772 atmel_uart_writel(port, ATMEL_US_IER,
773 atmel_port->tx_done_mask);
776 static void atmel_complete_tx_dma(void *arg)
778 struct atmel_uart_port *atmel_port = arg;
779 struct uart_port *port = &atmel_port->uart;
780 struct circ_buf *xmit = &port->state->xmit;
781 struct dma_chan *chan = atmel_port->chan_tx;
784 spin_lock_irqsave(&port->lock, flags);
787 dmaengine_terminate_all(chan);
788 xmit->tail += atmel_port->tx_len;
789 xmit->tail &= UART_XMIT_SIZE - 1;
791 port->icount.tx += atmel_port->tx_len;
793 spin_lock_irq(&atmel_port->lock_tx);
794 async_tx_ack(atmel_port->desc_tx);
795 atmel_port->cookie_tx = -EINVAL;
796 atmel_port->desc_tx = NULL;
797 spin_unlock_irq(&atmel_port->lock_tx);
799 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
800 uart_write_wakeup(port);
803 * xmit is a circular buffer so, if we have just send data from
804 * xmit->tail to the end of xmit->buf, now we have to transmit the
805 * remaining data from the beginning of xmit->buf to xmit->head.
807 if (!uart_circ_empty(xmit))
808 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
809 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
810 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
811 /* DMA done, stop TX, start RX for RS485 */
812 atmel_start_rx(port);
815 spin_unlock_irqrestore(&port->lock, flags);
818 static void atmel_release_tx_dma(struct uart_port *port)
820 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
821 struct dma_chan *chan = atmel_port->chan_tx;
824 dmaengine_terminate_all(chan);
825 dma_release_channel(chan);
826 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
830 atmel_port->desc_tx = NULL;
831 atmel_port->chan_tx = NULL;
832 atmel_port->cookie_tx = -EINVAL;
836 * Called from tasklet with TXRDY interrupt is disabled.
838 static void atmel_tx_dma(struct uart_port *port)
840 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
841 struct circ_buf *xmit = &port->state->xmit;
842 struct dma_chan *chan = atmel_port->chan_tx;
843 struct dma_async_tx_descriptor *desc;
844 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
845 unsigned int tx_len, part1_len, part2_len, sg_len;
846 dma_addr_t phys_addr;
848 /* Make sure we have an idle channel */
849 if (atmel_port->desc_tx != NULL)
852 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
855 * Port xmit buffer is already mapped,
856 * and it is one page... Just adjust
857 * offsets and lengths. Since it is a circular buffer,
858 * we have to transmit till the end, and then the rest.
859 * Take the port lock to get a
860 * consistent xmit buffer state.
862 tx_len = CIRC_CNT_TO_END(xmit->head,
866 if (atmel_port->fifo_size) {
867 /* multi data mode */
868 part1_len = (tx_len & ~0x3); /* DWORD access */
869 part2_len = (tx_len & 0x3); /* BYTE access */
871 /* single data (legacy) mode */
873 part2_len = tx_len; /* BYTE access only */
876 sg_init_table(sgl, 2);
878 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
881 sg_dma_address(sg) = phys_addr;
882 sg_dma_len(sg) = part1_len;
884 phys_addr += part1_len;
889 sg_dma_address(sg) = phys_addr;
890 sg_dma_len(sg) = part2_len;
894 * save tx_len so atmel_complete_tx_dma() will increase
895 * xmit->tail correctly
897 atmel_port->tx_len = tx_len;
899 desc = dmaengine_prep_slave_sg(chan,
906 dev_err(port->dev, "Failed to send via dma!\n");
910 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
912 atmel_port->desc_tx = desc;
913 desc->callback = atmel_complete_tx_dma;
914 desc->callback_param = atmel_port;
915 atmel_port->cookie_tx = dmaengine_submit(desc);
918 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
919 uart_write_wakeup(port);
922 static int atmel_prepare_tx_dma(struct uart_port *port)
924 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
926 struct dma_slave_config config;
930 dma_cap_set(DMA_SLAVE, mask);
932 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
933 if (atmel_port->chan_tx == NULL)
935 dev_info(port->dev, "using %s for tx DMA transfers\n",
936 dma_chan_name(atmel_port->chan_tx));
938 spin_lock_init(&atmel_port->lock_tx);
939 sg_init_table(&atmel_port->sg_tx, 1);
940 /* UART circular tx buffer is an aligned page. */
941 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
942 sg_set_page(&atmel_port->sg_tx,
943 virt_to_page(port->state->xmit.buf),
945 offset_in_page(port->state->xmit.buf));
946 nent = dma_map_sg(port->dev,
952 dev_dbg(port->dev, "need to release resource of dma\n");
955 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
956 sg_dma_len(&atmel_port->sg_tx),
957 port->state->xmit.buf,
958 &sg_dma_address(&atmel_port->sg_tx));
961 /* Configure the slave DMA */
962 memset(&config, 0, sizeof(config));
963 config.direction = DMA_MEM_TO_DEV;
964 config.dst_addr_width = (atmel_port->fifo_size) ?
965 DMA_SLAVE_BUSWIDTH_4_BYTES :
966 DMA_SLAVE_BUSWIDTH_1_BYTE;
967 config.dst_addr = port->mapbase + ATMEL_US_THR;
968 config.dst_maxburst = 1;
970 ret = dmaengine_slave_config(atmel_port->chan_tx,
973 dev_err(port->dev, "DMA tx slave configuration failed\n");
980 dev_err(port->dev, "TX channel not available, switch to pio\n");
981 atmel_port->use_dma_tx = 0;
982 if (atmel_port->chan_tx)
983 atmel_release_tx_dma(port);
987 static void atmel_complete_rx_dma(void *arg)
989 struct uart_port *port = arg;
990 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
992 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
995 static void atmel_release_rx_dma(struct uart_port *port)
997 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
998 struct dma_chan *chan = atmel_port->chan_rx;
1001 dmaengine_terminate_all(chan);
1002 dma_release_channel(chan);
1003 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1007 atmel_port->desc_rx = NULL;
1008 atmel_port->chan_rx = NULL;
1009 atmel_port->cookie_rx = -EINVAL;
1012 static void atmel_rx_from_dma(struct uart_port *port)
1014 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1015 struct tty_port *tport = &port->state->port;
1016 struct circ_buf *ring = &atmel_port->rx_ring;
1017 struct dma_chan *chan = atmel_port->chan_rx;
1018 struct dma_tx_state state;
1019 enum dma_status dmastat;
1023 /* Reset the UART timeout early so that we don't miss one */
1024 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1025 dmastat = dmaengine_tx_status(chan,
1026 atmel_port->cookie_rx,
1028 /* Restart a new tasklet if DMA status is error */
1029 if (dmastat == DMA_ERROR) {
1030 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1031 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1032 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1036 /* CPU claims ownership of RX DMA buffer */
1037 dma_sync_sg_for_cpu(port->dev,
1043 * ring->head points to the end of data already written by the DMA.
1044 * ring->tail points to the beginning of data to be read by the
1046 * The current transfer size should not be larger than the dma buffer
1049 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1050 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1052 * At this point ring->head may point to the first byte right after the
1053 * last byte of the dma buffer:
1054 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1056 * However ring->tail must always points inside the dma buffer:
1057 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1059 * Since we use a ring buffer, we have to handle the case
1060 * where head is lower than tail. In such a case, we first read from
1061 * tail to the end of the buffer then reset tail.
1063 if (ring->head < ring->tail) {
1064 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1066 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1068 port->icount.rx += count;
1071 /* Finally we read data from tail to head */
1072 if (ring->tail < ring->head) {
1073 count = ring->head - ring->tail;
1075 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1076 /* Wrap ring->head if needed */
1077 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1079 ring->tail = ring->head;
1080 port->icount.rx += count;
1083 /* USART retreives ownership of RX DMA buffer */
1084 dma_sync_sg_for_device(port->dev,
1090 * Drop the lock here since it might end up calling
1091 * uart_start(), which takes the lock.
1093 spin_unlock(&port->lock);
1094 tty_flip_buffer_push(tport);
1095 spin_lock(&port->lock);
1097 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1100 static int atmel_prepare_rx_dma(struct uart_port *port)
1102 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1103 struct dma_async_tx_descriptor *desc;
1104 dma_cap_mask_t mask;
1105 struct dma_slave_config config;
1106 struct circ_buf *ring;
1109 ring = &atmel_port->rx_ring;
1112 dma_cap_set(DMA_CYCLIC, mask);
1114 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1115 if (atmel_port->chan_rx == NULL)
1117 dev_info(port->dev, "using %s for rx DMA transfers\n",
1118 dma_chan_name(atmel_port->chan_rx));
1120 spin_lock_init(&atmel_port->lock_rx);
1121 sg_init_table(&atmel_port->sg_rx, 1);
1122 /* UART circular rx buffer is an aligned page. */
1123 BUG_ON(!PAGE_ALIGNED(ring->buf));
1124 sg_set_page(&atmel_port->sg_rx,
1125 virt_to_page(ring->buf),
1126 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1127 offset_in_page(ring->buf));
1128 nent = dma_map_sg(port->dev,
1134 dev_dbg(port->dev, "need to release resource of dma\n");
1137 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1138 sg_dma_len(&atmel_port->sg_rx),
1140 &sg_dma_address(&atmel_port->sg_rx));
1143 /* Configure the slave DMA */
1144 memset(&config, 0, sizeof(config));
1145 config.direction = DMA_DEV_TO_MEM;
1146 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1147 config.src_addr = port->mapbase + ATMEL_US_RHR;
1148 config.src_maxburst = 1;
1150 ret = dmaengine_slave_config(atmel_port->chan_rx,
1153 dev_err(port->dev, "DMA rx slave configuration failed\n");
1157 * Prepare a cyclic dma transfer, assign 2 descriptors,
1158 * each one is half ring buffer size
1160 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1161 sg_dma_address(&atmel_port->sg_rx),
1162 sg_dma_len(&atmel_port->sg_rx),
1163 sg_dma_len(&atmel_port->sg_rx)/2,
1165 DMA_PREP_INTERRUPT);
1166 desc->callback = atmel_complete_rx_dma;
1167 desc->callback_param = port;
1168 atmel_port->desc_rx = desc;
1169 atmel_port->cookie_rx = dmaengine_submit(desc);
1174 dev_err(port->dev, "RX channel not available, switch to pio\n");
1175 atmel_port->use_dma_rx = 0;
1176 if (atmel_port->chan_rx)
1177 atmel_release_rx_dma(port);
1181 static void atmel_uart_timer_callback(unsigned long data)
1183 struct uart_port *port = (void *)data;
1184 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1186 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1187 tasklet_schedule(&atmel_port->tasklet_rx);
1188 mod_timer(&atmel_port->uart_timer,
1189 jiffies + uart_poll_timeout(port));
1194 * receive interrupt handler.
1197 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1199 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1201 if (atmel_use_pdc_rx(port)) {
1203 * PDC receive. Just schedule the tasklet and let it
1204 * figure out the details.
1206 * TODO: We're not handling error flags correctly at
1209 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1210 atmel_uart_writel(port, ATMEL_US_IDR,
1211 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1212 atmel_tasklet_schedule(atmel_port,
1213 &atmel_port->tasklet_rx);
1216 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1217 ATMEL_US_FRAME | ATMEL_US_PARE))
1218 atmel_pdc_rxerr(port, pending);
1221 if (atmel_use_dma_rx(port)) {
1222 if (pending & ATMEL_US_TIMEOUT) {
1223 atmel_uart_writel(port, ATMEL_US_IDR,
1225 atmel_tasklet_schedule(atmel_port,
1226 &atmel_port->tasklet_rx);
1230 /* Interrupt receive */
1231 if (pending & ATMEL_US_RXRDY)
1232 atmel_rx_chars(port);
1233 else if (pending & ATMEL_US_RXBRK) {
1235 * End of break detected. If it came along with a
1236 * character, atmel_rx_chars will handle it.
1238 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1239 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1240 atmel_port->break_active = 0;
1245 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1248 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1252 if (pending & atmel_port->tx_done_mask) {
1253 /* Either PDC or interrupt transmission */
1254 atmel_uart_writel(port, ATMEL_US_IDR,
1255 atmel_port->tx_done_mask);
1256 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1261 * status flags interrupt handler.
1264 atmel_handle_status(struct uart_port *port, unsigned int pending,
1265 unsigned int status)
1267 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1268 unsigned int status_change;
1270 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1271 | ATMEL_US_CTSIC)) {
1272 status_change = status ^ atmel_port->irq_status_prev;
1273 atmel_port->irq_status_prev = status;
1275 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1276 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1277 /* TODO: All reads to CSR will clear these interrupts! */
1278 if (status_change & ATMEL_US_RI)
1280 if (status_change & ATMEL_US_DSR)
1282 if (status_change & ATMEL_US_DCD)
1283 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1284 if (status_change & ATMEL_US_CTS)
1285 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1287 wake_up_interruptible(&port->state->port.delta_msr_wait);
1295 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1297 struct uart_port *port = dev_id;
1298 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1299 unsigned int status, pending, mask, pass_counter = 0;
1301 spin_lock(&atmel_port->lock_suspended);
1304 status = atmel_get_lines_status(port);
1305 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1306 pending = status & mask;
1310 if (atmel_port->suspended) {
1311 atmel_port->pending |= pending;
1312 atmel_port->pending_status = status;
1313 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1318 atmel_handle_receive(port, pending);
1319 atmel_handle_status(port, pending, status);
1320 atmel_handle_transmit(port, pending);
1321 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1323 spin_unlock(&atmel_port->lock_suspended);
1325 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1328 static void atmel_release_tx_pdc(struct uart_port *port)
1330 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1331 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1333 dma_unmap_single(port->dev,
1340 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1342 static void atmel_tx_pdc(struct uart_port *port)
1344 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1345 struct circ_buf *xmit = &port->state->xmit;
1346 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1349 /* nothing left to transmit? */
1350 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1353 xmit->tail += pdc->ofs;
1354 xmit->tail &= UART_XMIT_SIZE - 1;
1356 port->icount.tx += pdc->ofs;
1359 /* more to transmit - setup next transfer */
1361 /* disable PDC transmit */
1362 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1364 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1365 dma_sync_single_for_device(port->dev,
1370 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1373 atmel_uart_writel(port, ATMEL_PDC_TPR,
1374 pdc->dma_addr + xmit->tail);
1375 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1376 /* re-enable PDC transmit */
1377 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1378 /* Enable interrupts */
1379 atmel_uart_writel(port, ATMEL_US_IER,
1380 atmel_port->tx_done_mask);
1382 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1383 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1384 /* DMA done, stop TX, start RX for RS485 */
1385 atmel_start_rx(port);
1389 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1390 uart_write_wakeup(port);
1393 static int atmel_prepare_tx_pdc(struct uart_port *port)
1395 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1396 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1397 struct circ_buf *xmit = &port->state->xmit;
1399 pdc->buf = xmit->buf;
1400 pdc->dma_addr = dma_map_single(port->dev,
1404 pdc->dma_size = UART_XMIT_SIZE;
1410 static void atmel_rx_from_ring(struct uart_port *port)
1412 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1413 struct circ_buf *ring = &atmel_port->rx_ring;
1415 unsigned int status;
1417 while (ring->head != ring->tail) {
1418 struct atmel_uart_char c;
1420 /* Make sure c is loaded after head. */
1423 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1425 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1432 * note that the error handling code is
1433 * out of the main execution path
1435 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1436 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1437 if (status & ATMEL_US_RXBRK) {
1438 /* ignore side-effect */
1439 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1442 if (uart_handle_break(port))
1445 if (status & ATMEL_US_PARE)
1446 port->icount.parity++;
1447 if (status & ATMEL_US_FRAME)
1448 port->icount.frame++;
1449 if (status & ATMEL_US_OVRE)
1450 port->icount.overrun++;
1452 status &= port->read_status_mask;
1454 if (status & ATMEL_US_RXBRK)
1456 else if (status & ATMEL_US_PARE)
1458 else if (status & ATMEL_US_FRAME)
1463 if (uart_handle_sysrq_char(port, c.ch))
1466 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1470 * Drop the lock here since it might end up calling
1471 * uart_start(), which takes the lock.
1473 spin_unlock(&port->lock);
1474 tty_flip_buffer_push(&port->state->port);
1475 spin_lock(&port->lock);
1478 static void atmel_release_rx_pdc(struct uart_port *port)
1480 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1483 for (i = 0; i < 2; i++) {
1484 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1486 dma_unmap_single(port->dev,
1494 static void atmel_rx_from_pdc(struct uart_port *port)
1496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1497 struct tty_port *tport = &port->state->port;
1498 struct atmel_dma_buffer *pdc;
1499 int rx_idx = atmel_port->pdc_rx_idx;
1505 /* Reset the UART timeout early so that we don't miss one */
1506 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1508 pdc = &atmel_port->pdc_rx[rx_idx];
1509 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1512 /* If the PDC has switched buffers, RPR won't contain
1513 * any address within the current buffer. Since head
1514 * is unsigned, we just need a one-way comparison to
1517 * In this case, we just need to consume the entire
1518 * buffer and resubmit it for DMA. This will clear the
1519 * ENDRX bit as well, so that we can safely re-enable
1520 * all interrupts below.
1522 head = min(head, pdc->dma_size);
1524 if (likely(head != tail)) {
1525 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1526 pdc->dma_size, DMA_FROM_DEVICE);
1529 * head will only wrap around when we recycle
1530 * the DMA buffer, and when that happens, we
1531 * explicitly set tail to 0. So head will
1532 * always be greater than tail.
1534 count = head - tail;
1536 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1539 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1540 pdc->dma_size, DMA_FROM_DEVICE);
1542 port->icount.rx += count;
1547 * If the current buffer is full, we need to check if
1548 * the next one contains any additional data.
1550 if (head >= pdc->dma_size) {
1552 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1553 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1556 atmel_port->pdc_rx_idx = rx_idx;
1558 } while (head >= pdc->dma_size);
1561 * Drop the lock here since it might end up calling
1562 * uart_start(), which takes the lock.
1564 spin_unlock(&port->lock);
1565 tty_flip_buffer_push(tport);
1566 spin_lock(&port->lock);
1568 atmel_uart_writel(port, ATMEL_US_IER,
1569 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1572 static int atmel_prepare_rx_pdc(struct uart_port *port)
1574 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1577 for (i = 0; i < 2; i++) {
1578 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1580 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1581 if (pdc->buf == NULL) {
1583 dma_unmap_single(port->dev,
1584 atmel_port->pdc_rx[0].dma_addr,
1587 kfree(atmel_port->pdc_rx[0].buf);
1589 atmel_port->use_pdc_rx = 0;
1592 pdc->dma_addr = dma_map_single(port->dev,
1596 pdc->dma_size = PDC_BUFFER_SIZE;
1600 atmel_port->pdc_rx_idx = 0;
1602 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1603 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1605 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1606 atmel_port->pdc_rx[1].dma_addr);
1607 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1613 * tasklet handling tty stuff outside the interrupt handler.
1615 static void atmel_tasklet_rx_func(unsigned long data)
1617 struct uart_port *port = (struct uart_port *)data;
1618 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1620 /* The interrupt handler does not take the lock */
1621 spin_lock(&port->lock);
1622 atmel_port->schedule_rx(port);
1623 spin_unlock(&port->lock);
1626 static void atmel_tasklet_tx_func(unsigned long data)
1628 struct uart_port *port = (struct uart_port *)data;
1629 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1631 /* The interrupt handler does not take the lock */
1632 spin_lock(&port->lock);
1633 atmel_port->schedule_tx(port);
1634 spin_unlock(&port->lock);
1637 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1638 struct platform_device *pdev)
1640 struct device_node *np = pdev->dev.of_node;
1641 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1644 /* DMA/PDC usage specification */
1645 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1646 if (of_property_read_bool(np, "dmas")) {
1647 atmel_port->use_dma_rx = true;
1648 atmel_port->use_pdc_rx = false;
1650 atmel_port->use_dma_rx = false;
1651 atmel_port->use_pdc_rx = true;
1654 atmel_port->use_dma_rx = false;
1655 atmel_port->use_pdc_rx = false;
1658 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1659 if (of_property_read_bool(np, "dmas")) {
1660 atmel_port->use_dma_tx = true;
1661 atmel_port->use_pdc_tx = false;
1663 atmel_port->use_dma_tx = false;
1664 atmel_port->use_pdc_tx = true;
1667 atmel_port->use_dma_tx = false;
1668 atmel_port->use_pdc_tx = false;
1672 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1673 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1674 atmel_port->use_dma_rx = false;
1675 atmel_port->use_dma_tx = false;
1680 static void atmel_init_rs485(struct uart_port *port,
1681 struct platform_device *pdev)
1683 struct device_node *np = pdev->dev.of_node;
1684 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1687 struct serial_rs485 *rs485conf = &port->rs485;
1689 /* rs485 properties */
1690 if (of_property_read_u32_array(np, "rs485-rts-delay",
1691 rs485_delay, 2) == 0) {
1692 rs485conf->delay_rts_before_send = rs485_delay[0];
1693 rs485conf->delay_rts_after_send = rs485_delay[1];
1694 rs485conf->flags = 0;
1697 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1698 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1700 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1702 rs485conf->flags |= SER_RS485_ENABLED;
1704 port->rs485 = pdata->rs485;
1709 static void atmel_set_ops(struct uart_port *port)
1711 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1713 if (atmel_use_dma_rx(port)) {
1714 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1715 atmel_port->schedule_rx = &atmel_rx_from_dma;
1716 atmel_port->release_rx = &atmel_release_rx_dma;
1717 } else if (atmel_use_pdc_rx(port)) {
1718 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1719 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1720 atmel_port->release_rx = &atmel_release_rx_pdc;
1722 atmel_port->prepare_rx = NULL;
1723 atmel_port->schedule_rx = &atmel_rx_from_ring;
1724 atmel_port->release_rx = NULL;
1727 if (atmel_use_dma_tx(port)) {
1728 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1729 atmel_port->schedule_tx = &atmel_tx_dma;
1730 atmel_port->release_tx = &atmel_release_tx_dma;
1731 } else if (atmel_use_pdc_tx(port)) {
1732 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1733 atmel_port->schedule_tx = &atmel_tx_pdc;
1734 atmel_port->release_tx = &atmel_release_tx_pdc;
1736 atmel_port->prepare_tx = NULL;
1737 atmel_port->schedule_tx = &atmel_tx_chars;
1738 atmel_port->release_tx = NULL;
1743 * Get ip name usart or uart
1745 static void atmel_get_ip_name(struct uart_port *port)
1747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1748 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1750 u32 usart, dbgu_uart, new_uart;
1751 /* ASCII decoding for IP version */
1752 usart = 0x55534152; /* USAR(T) */
1753 dbgu_uart = 0x44424755; /* DBGU */
1754 new_uart = 0x55415254; /* UART */
1757 * Only USART devices from at91sam9260 SOC implement fractional
1758 * baudrate. It is available for all asynchronous modes, with the
1759 * following restriction: the sampling clock's duty cycle is not
1762 atmel_port->has_frac_baudrate = false;
1763 atmel_port->has_hw_timer = false;
1765 if (name == new_uart) {
1766 dev_dbg(port->dev, "Uart with hw timer");
1767 atmel_port->has_hw_timer = true;
1768 atmel_port->rtor = ATMEL_UA_RTOR;
1769 } else if (name == usart) {
1770 dev_dbg(port->dev, "Usart\n");
1771 atmel_port->has_frac_baudrate = true;
1772 atmel_port->has_hw_timer = true;
1773 atmel_port->rtor = ATMEL_US_RTOR;
1774 } else if (name == dbgu_uart) {
1775 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1777 /* fallback for older SoCs: use version field */
1778 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1782 dev_dbg(port->dev, "This version is usart\n");
1783 atmel_port->has_frac_baudrate = true;
1784 atmel_port->has_hw_timer = true;
1785 atmel_port->rtor = ATMEL_US_RTOR;
1789 dev_dbg(port->dev, "This version is uart\n");
1792 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1798 * Perform initialization and enable port for reception
1800 static int atmel_startup(struct uart_port *port)
1802 struct platform_device *pdev = to_platform_device(port->dev);
1803 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1804 struct tty_struct *tty = port->state->port.tty;
1808 * Ensure that no interrupts are enabled otherwise when
1809 * request_irq() is called we could get stuck trying to
1810 * handle an unexpected interrupt
1812 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1813 atmel_port->ms_irq_enabled = false;
1818 retval = request_irq(port->irq, atmel_interrupt,
1819 IRQF_SHARED | IRQF_COND_SUSPEND,
1820 tty ? tty->name : "atmel_serial", port);
1822 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1826 atomic_set(&atmel_port->tasklet_shutdown, 0);
1827 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1828 (unsigned long)port);
1829 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1830 (unsigned long)port);
1833 * Initialize DMA (if necessary)
1835 atmel_init_property(atmel_port, pdev);
1836 atmel_set_ops(port);
1838 if (atmel_port->prepare_rx) {
1839 retval = atmel_port->prepare_rx(port);
1841 atmel_set_ops(port);
1844 if (atmel_port->prepare_tx) {
1845 retval = atmel_port->prepare_tx(port);
1847 atmel_set_ops(port);
1851 * Enable FIFO when available
1853 if (atmel_port->fifo_size) {
1854 unsigned int txrdym = ATMEL_US_ONE_DATA;
1855 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1858 atmel_uart_writel(port, ATMEL_US_CR,
1863 if (atmel_use_dma_tx(port))
1864 txrdym = ATMEL_US_FOUR_DATA;
1866 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1867 if (atmel_port->rts_high &&
1868 atmel_port->rts_low)
1869 fmr |= ATMEL_US_FRTSC |
1870 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1871 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1873 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1876 /* Save current CSR for comparison in atmel_tasklet_func() */
1877 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1880 * Finally, enable the serial port
1882 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1883 /* enable xmit & rcvr */
1884 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1886 setup_timer(&atmel_port->uart_timer,
1887 atmel_uart_timer_callback,
1888 (unsigned long)port);
1890 if (atmel_use_pdc_rx(port)) {
1891 /* set UART timeout */
1892 if (!atmel_port->has_hw_timer) {
1893 mod_timer(&atmel_port->uart_timer,
1894 jiffies + uart_poll_timeout(port));
1895 /* set USART timeout */
1897 atmel_uart_writel(port, atmel_port->rtor,
1899 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1901 atmel_uart_writel(port, ATMEL_US_IER,
1902 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1904 /* enable PDC controller */
1905 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1906 } else if (atmel_use_dma_rx(port)) {
1907 /* set UART timeout */
1908 if (!atmel_port->has_hw_timer) {
1909 mod_timer(&atmel_port->uart_timer,
1910 jiffies + uart_poll_timeout(port));
1911 /* set USART timeout */
1913 atmel_uart_writel(port, atmel_port->rtor,
1915 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1917 atmel_uart_writel(port, ATMEL_US_IER,
1921 /* enable receive only */
1922 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1929 * Flush any TX data submitted for DMA. Called when the TX circular
1932 static void atmel_flush_buffer(struct uart_port *port)
1934 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1936 if (atmel_use_pdc_tx(port)) {
1937 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1938 atmel_port->pdc_tx.ofs = 0;
1941 * in uart_flush_buffer(), the xmit circular buffer has just
1942 * been cleared, so we have to reset tx_len accordingly.
1944 atmel_port->tx_len = 0;
1950 static void atmel_shutdown(struct uart_port *port)
1952 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1954 /* Disable modem control lines interrupts */
1955 atmel_disable_ms(port);
1957 /* Disable interrupts at device level */
1958 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1960 /* Prevent spurious interrupts from scheduling the tasklet */
1961 atomic_inc(&atmel_port->tasklet_shutdown);
1964 * Prevent any tasklets being scheduled during
1967 del_timer_sync(&atmel_port->uart_timer);
1969 /* Make sure that no interrupt is on the fly */
1970 synchronize_irq(port->irq);
1973 * Clear out any scheduled tasklets before
1974 * we destroy the buffers
1976 tasklet_kill(&atmel_port->tasklet_rx);
1977 tasklet_kill(&atmel_port->tasklet_tx);
1980 * Ensure everything is stopped and
1981 * disable port and break condition.
1983 atmel_stop_rx(port);
1984 atmel_stop_tx(port);
1986 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1989 * Shut-down the DMA.
1991 if (atmel_port->release_rx)
1992 atmel_port->release_rx(port);
1993 if (atmel_port->release_tx)
1994 atmel_port->release_tx(port);
1997 * Reset ring buffer pointers
1999 atmel_port->rx_ring.head = 0;
2000 atmel_port->rx_ring.tail = 0;
2003 * Free the interrupts
2005 free_irq(port->irq, port);
2007 atmel_flush_buffer(port);
2011 * Power / Clock management.
2013 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2014 unsigned int oldstate)
2016 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2021 * Enable the peripheral clock for this serial port.
2022 * This is called on uart_open() or a resume event.
2024 clk_prepare_enable(atmel_port->clk);
2026 /* re-enable interrupts if we disabled some on suspend */
2027 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2030 /* Back up the interrupt mask and disable all interrupts */
2031 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2032 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2035 * Disable the peripheral clock for this serial port.
2036 * This is called on uart_close() or a suspend event.
2038 clk_disable_unprepare(atmel_port->clk);
2041 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2046 * Change the port parameters
2048 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2049 struct ktermios *old)
2051 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2052 unsigned long flags;
2053 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2055 /* save the current mode register */
2056 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2058 /* reset the mode, clock divisor, parity, stop bits and data size */
2059 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2060 ATMEL_US_PAR | ATMEL_US_USMODE);
2062 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2065 switch (termios->c_cflag & CSIZE) {
2067 mode |= ATMEL_US_CHRL_5;
2070 mode |= ATMEL_US_CHRL_6;
2073 mode |= ATMEL_US_CHRL_7;
2076 mode |= ATMEL_US_CHRL_8;
2081 if (termios->c_cflag & CSTOPB)
2082 mode |= ATMEL_US_NBSTOP_2;
2085 if (termios->c_cflag & PARENB) {
2086 /* Mark or Space parity */
2087 if (termios->c_cflag & CMSPAR) {
2088 if (termios->c_cflag & PARODD)
2089 mode |= ATMEL_US_PAR_MARK;
2091 mode |= ATMEL_US_PAR_SPACE;
2092 } else if (termios->c_cflag & PARODD)
2093 mode |= ATMEL_US_PAR_ODD;
2095 mode |= ATMEL_US_PAR_EVEN;
2097 mode |= ATMEL_US_PAR_NONE;
2099 spin_lock_irqsave(&port->lock, flags);
2101 port->read_status_mask = ATMEL_US_OVRE;
2102 if (termios->c_iflag & INPCK)
2103 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2104 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2105 port->read_status_mask |= ATMEL_US_RXBRK;
2107 if (atmel_use_pdc_rx(port))
2108 /* need to enable error interrupts */
2109 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2112 * Characters to ignore
2114 port->ignore_status_mask = 0;
2115 if (termios->c_iflag & IGNPAR)
2116 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2117 if (termios->c_iflag & IGNBRK) {
2118 port->ignore_status_mask |= ATMEL_US_RXBRK;
2120 * If we're ignoring parity and break indicators,
2121 * ignore overruns too (for real raw support).
2123 if (termios->c_iflag & IGNPAR)
2124 port->ignore_status_mask |= ATMEL_US_OVRE;
2126 /* TODO: Ignore all characters if CREAD is set.*/
2128 /* update the per-port timeout */
2129 uart_update_timeout(port, termios->c_cflag, baud);
2132 * save/disable interrupts. The tty layer will ensure that the
2133 * transmitter is empty if requested by the caller, so there's
2134 * no need to wait for it here.
2136 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2137 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2139 /* disable receiver and transmitter */
2140 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2143 if (port->rs485.flags & SER_RS485_ENABLED) {
2144 atmel_uart_writel(port, ATMEL_US_TTGR,
2145 port->rs485.delay_rts_after_send);
2146 mode |= ATMEL_US_USMODE_RS485;
2147 } else if (termios->c_cflag & CRTSCTS) {
2148 /* RS232 with hardware handshake (RTS/CTS) */
2149 if (atmel_use_fifo(port) &&
2150 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2152 * with ATMEL_US_USMODE_HWHS set, the controller will
2153 * be able to drive the RTS pin high/low when the RX
2154 * FIFO is above RXFTHRES/below RXFTHRES2.
2155 * It will also disable the transmitter when the CTS
2157 * This mode is not activated if CTS pin is a GPIO
2158 * because in this case, the transmitter is always
2159 * disabled (there must be an internal pull-up
2160 * responsible for this behaviour).
2161 * If the RTS pin is a GPIO, the controller won't be
2162 * able to drive it according to the FIFO thresholds,
2163 * but it will be handled by the driver.
2165 mode |= ATMEL_US_USMODE_HWHS;
2168 * For platforms without FIFO, the flow control is
2169 * handled by the driver.
2171 mode |= ATMEL_US_USMODE_NORMAL;
2174 /* RS232 without hadware handshake */
2175 mode |= ATMEL_US_USMODE_NORMAL;
2178 /* set the mode, clock divisor, parity, stop bits and data size */
2179 atmel_uart_writel(port, ATMEL_US_MR, mode);
2182 * when switching the mode, set the RTS line state according to the
2183 * new mode, otherwise keep the former state
2185 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2186 unsigned int rts_state;
2188 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2189 /* let the hardware control the RTS line */
2190 rts_state = ATMEL_US_RTSDIS;
2192 /* force RTS line to low level */
2193 rts_state = ATMEL_US_RTSEN;
2196 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2200 * Set the baud rate:
2201 * Fractional baudrate allows to setup output frequency more
2202 * accurately. This feature is enabled only when using normal mode.
2203 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2204 * Currently, OVER is always set to 0 so we get
2205 * baudrate = selected clock / (16 * (CD + FP / 8))
2207 * 8 CD + FP = selected clock / (2 * baudrate)
2209 if (atmel_port->has_frac_baudrate) {
2210 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2212 fp = div & ATMEL_US_FP_MASK;
2214 cd = uart_get_divisor(port, baud);
2217 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2219 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2221 quot = cd | fp << ATMEL_US_FP_OFFSET;
2223 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2224 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2225 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2227 /* restore interrupts */
2228 atmel_uart_writel(port, ATMEL_US_IER, imr);
2230 /* CTS flow-control and modem-status interrupts */
2231 if (UART_ENABLE_MS(port, termios->c_cflag))
2232 atmel_enable_ms(port);
2234 atmel_disable_ms(port);
2236 spin_unlock_irqrestore(&port->lock, flags);
2239 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2241 if (termios->c_line == N_PPS) {
2242 port->flags |= UPF_HARDPPS_CD;
2243 spin_lock_irq(&port->lock);
2244 atmel_enable_ms(port);
2245 spin_unlock_irq(&port->lock);
2247 port->flags &= ~UPF_HARDPPS_CD;
2248 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2249 spin_lock_irq(&port->lock);
2250 atmel_disable_ms(port);
2251 spin_unlock_irq(&port->lock);
2257 * Return string describing the specified port
2259 static const char *atmel_type(struct uart_port *port)
2261 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2265 * Release the memory region(s) being used by 'port'.
2267 static void atmel_release_port(struct uart_port *port)
2269 struct platform_device *pdev = to_platform_device(port->dev);
2270 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2272 release_mem_region(port->mapbase, size);
2274 if (port->flags & UPF_IOREMAP) {
2275 iounmap(port->membase);
2276 port->membase = NULL;
2281 * Request the memory region(s) being used by 'port'.
2283 static int atmel_request_port(struct uart_port *port)
2285 struct platform_device *pdev = to_platform_device(port->dev);
2286 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2288 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2291 if (port->flags & UPF_IOREMAP) {
2292 port->membase = ioremap(port->mapbase, size);
2293 if (port->membase == NULL) {
2294 release_mem_region(port->mapbase, size);
2303 * Configure/autoconfigure the port.
2305 static void atmel_config_port(struct uart_port *port, int flags)
2307 if (flags & UART_CONFIG_TYPE) {
2308 port->type = PORT_ATMEL;
2309 atmel_request_port(port);
2314 * Verify the new serial_struct (for TIOCSSERIAL).
2316 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2319 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2321 if (port->irq != ser->irq)
2323 if (ser->io_type != SERIAL_IO_MEM)
2325 if (port->uartclk / 16 != ser->baud_base)
2327 if (port->mapbase != (unsigned long)ser->iomem_base)
2329 if (port->iobase != ser->port)
2336 #ifdef CONFIG_CONSOLE_POLL
2337 static int atmel_poll_get_char(struct uart_port *port)
2339 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2342 return atmel_uart_read_char(port);
2345 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2347 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2350 atmel_uart_write_char(port, ch);
2354 static const struct uart_ops atmel_pops = {
2355 .tx_empty = atmel_tx_empty,
2356 .set_mctrl = atmel_set_mctrl,
2357 .get_mctrl = atmel_get_mctrl,
2358 .stop_tx = atmel_stop_tx,
2359 .start_tx = atmel_start_tx,
2360 .stop_rx = atmel_stop_rx,
2361 .enable_ms = atmel_enable_ms,
2362 .break_ctl = atmel_break_ctl,
2363 .startup = atmel_startup,
2364 .shutdown = atmel_shutdown,
2365 .flush_buffer = atmel_flush_buffer,
2366 .set_termios = atmel_set_termios,
2367 .set_ldisc = atmel_set_ldisc,
2369 .release_port = atmel_release_port,
2370 .request_port = atmel_request_port,
2371 .config_port = atmel_config_port,
2372 .verify_port = atmel_verify_port,
2373 .pm = atmel_serial_pm,
2374 #ifdef CONFIG_CONSOLE_POLL
2375 .poll_get_char = atmel_poll_get_char,
2376 .poll_put_char = atmel_poll_put_char,
2381 * Configure the port from the platform device resource info.
2383 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2384 struct platform_device *pdev)
2387 struct uart_port *port = &atmel_port->uart;
2388 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2390 atmel_init_property(atmel_port, pdev);
2391 atmel_set_ops(port);
2393 atmel_init_rs485(port, pdev);
2395 port->iotype = UPIO_MEM;
2396 port->flags = UPF_BOOT_AUTOCONF;
2397 port->ops = &atmel_pops;
2399 port->dev = &pdev->dev;
2400 port->mapbase = pdev->resource[0].start;
2401 port->irq = pdev->resource[1].start;
2402 port->rs485_config = atmel_config_rs485;
2404 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2406 if (pdata && pdata->regs) {
2407 /* Already mapped by setup code */
2408 port->membase = pdata->regs;
2410 port->flags |= UPF_IOREMAP;
2411 port->membase = NULL;
2414 /* for console, the clock could already be configured */
2415 if (!atmel_port->clk) {
2416 atmel_port->clk = clk_get(&pdev->dev, "usart");
2417 if (IS_ERR(atmel_port->clk)) {
2418 ret = PTR_ERR(atmel_port->clk);
2419 atmel_port->clk = NULL;
2422 ret = clk_prepare_enable(atmel_port->clk);
2424 clk_put(atmel_port->clk);
2425 atmel_port->clk = NULL;
2428 port->uartclk = clk_get_rate(atmel_port->clk);
2429 clk_disable_unprepare(atmel_port->clk);
2430 /* only enable clock when USART is in use */
2433 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2434 if (port->rs485.flags & SER_RS485_ENABLED)
2435 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2436 else if (atmel_use_pdc_tx(port)) {
2437 port->fifosize = PDC_BUFFER_SIZE;
2438 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2440 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2446 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2447 static void atmel_console_putchar(struct uart_port *port, int ch)
2449 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2451 atmel_uart_write_char(port, ch);
2455 * Interrupts are disabled on entering
2457 static void atmel_console_write(struct console *co, const char *s, u_int count)
2459 struct uart_port *port = &atmel_ports[co->index].uart;
2460 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2461 unsigned int status, imr;
2462 unsigned int pdc_tx;
2465 * First, save IMR and then disable interrupts
2467 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2468 atmel_uart_writel(port, ATMEL_US_IDR,
2469 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2471 /* Store PDC transmit status and disable it */
2472 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2473 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2475 /* Make sure that tx path is actually able to send characters */
2476 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2478 uart_console_write(port, s, count, atmel_console_putchar);
2481 * Finally, wait for transmitter to become empty
2485 status = atmel_uart_readl(port, ATMEL_US_CSR);
2486 } while (!(status & ATMEL_US_TXRDY));
2488 /* Restore PDC transmit status */
2490 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2492 /* set interrupts back the way they were */
2493 atmel_uart_writel(port, ATMEL_US_IER, imr);
2497 * If the port was already initialised (eg, by a boot loader),
2498 * try to determine the current setup.
2500 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2501 int *parity, int *bits)
2503 unsigned int mr, quot;
2506 * If the baud rate generator isn't running, the port wasn't
2507 * initialized by the boot loader.
2509 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2513 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2514 if (mr == ATMEL_US_CHRL_8)
2519 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2520 if (mr == ATMEL_US_PAR_EVEN)
2522 else if (mr == ATMEL_US_PAR_ODD)
2526 * The serial core only rounds down when matching this to a
2527 * supported baud rate. Make sure we don't end up slightly
2528 * lower than one of those, as it would make us fall through
2529 * to a much lower baud rate than we really want.
2531 *baud = port->uartclk / (16 * (quot - 1));
2534 static int __init atmel_console_setup(struct console *co, char *options)
2537 struct uart_port *port = &atmel_ports[co->index].uart;
2543 if (port->membase == NULL) {
2544 /* Port not initialized yet - delay setup */
2548 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2552 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2553 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2554 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2557 uart_parse_options(options, &baud, &parity, &bits, &flow);
2559 atmel_console_get_options(port, &baud, &parity, &bits);
2561 return uart_set_options(port, co, baud, parity, bits, flow);
2564 static struct uart_driver atmel_uart;
2566 static struct console atmel_console = {
2567 .name = ATMEL_DEVICENAME,
2568 .write = atmel_console_write,
2569 .device = uart_console_device,
2570 .setup = atmel_console_setup,
2571 .flags = CON_PRINTBUFFER,
2573 .data = &atmel_uart,
2576 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2578 static inline bool atmel_is_console_port(struct uart_port *port)
2580 return port->cons && port->cons->index == port->line;
2584 #define ATMEL_CONSOLE_DEVICE NULL
2586 static inline bool atmel_is_console_port(struct uart_port *port)
2592 static struct uart_driver atmel_uart = {
2593 .owner = THIS_MODULE,
2594 .driver_name = "atmel_serial",
2595 .dev_name = ATMEL_DEVICENAME,
2596 .major = SERIAL_ATMEL_MAJOR,
2597 .minor = MINOR_START,
2598 .nr = ATMEL_MAX_UART,
2599 .cons = ATMEL_CONSOLE_DEVICE,
2603 static bool atmel_serial_clk_will_stop(void)
2605 #ifdef CONFIG_ARCH_AT91
2606 return at91_suspend_entering_slow_clock();
2612 static int atmel_serial_suspend(struct platform_device *pdev,
2615 struct uart_port *port = platform_get_drvdata(pdev);
2616 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2618 if (atmel_is_console_port(port) && console_suspend_enabled) {
2619 /* Drain the TX shifter */
2620 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2625 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2626 /* Cache register values as we won't get a full shutdown/startup
2629 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2630 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2631 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2632 atmel_port->cache.rtor = atmel_uart_readl(port,
2634 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2635 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2636 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2639 /* we can not wake up if we're running on slow clock */
2640 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2641 if (atmel_serial_clk_will_stop()) {
2642 unsigned long flags;
2644 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2645 atmel_port->suspended = true;
2646 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2647 device_set_wakeup_enable(&pdev->dev, 0);
2650 uart_suspend_port(&atmel_uart, port);
2655 static int atmel_serial_resume(struct platform_device *pdev)
2657 struct uart_port *port = platform_get_drvdata(pdev);
2658 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2659 unsigned long flags;
2661 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2662 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2663 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2664 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2665 atmel_uart_writel(port, atmel_port->rtor,
2666 atmel_port->cache.rtor);
2667 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2669 if (atmel_port->fifo_size) {
2670 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2671 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2672 atmel_uart_writel(port, ATMEL_US_FMR,
2673 atmel_port->cache.fmr);
2674 atmel_uart_writel(port, ATMEL_US_FIER,
2675 atmel_port->cache.fimr);
2677 atmel_start_rx(port);
2680 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2681 if (atmel_port->pending) {
2682 atmel_handle_receive(port, atmel_port->pending);
2683 atmel_handle_status(port, atmel_port->pending,
2684 atmel_port->pending_status);
2685 atmel_handle_transmit(port, atmel_port->pending);
2686 atmel_port->pending = 0;
2688 atmel_port->suspended = false;
2689 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2691 uart_resume_port(&atmel_uart, port);
2692 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2697 #define atmel_serial_suspend NULL
2698 #define atmel_serial_resume NULL
2701 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2702 struct platform_device *pdev)
2704 atmel_port->fifo_size = 0;
2705 atmel_port->rts_low = 0;
2706 atmel_port->rts_high = 0;
2708 if (of_property_read_u32(pdev->dev.of_node,
2710 &atmel_port->fifo_size))
2713 if (!atmel_port->fifo_size)
2716 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2717 atmel_port->fifo_size = 0;
2718 dev_err(&pdev->dev, "Invalid FIFO size\n");
2723 * 0 <= rts_low <= rts_high <= fifo_size
2724 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2725 * to flush their internal TX FIFO, commonly up to 16 data, before
2726 * actually stopping to send new data. So we try to set the RTS High
2727 * Threshold to a reasonably high value respecting this 16 data
2728 * empirical rule when possible.
2730 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2731 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2732 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2733 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2735 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2736 atmel_port->fifo_size);
2737 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2738 atmel_port->rts_high);
2739 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2740 atmel_port->rts_low);
2743 static int atmel_serial_probe(struct platform_device *pdev)
2745 struct atmel_uart_port *atmel_port;
2746 struct device_node *np = pdev->dev.of_node;
2747 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2752 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2755 ret = of_alias_get_id(np, "serial");
2761 /* port id not found in platform data nor device-tree aliases:
2762 * auto-enumerate it */
2763 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2765 if (ret >= ATMEL_MAX_UART) {
2770 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2771 /* port already in use */
2776 atmel_port = &atmel_ports[ret];
2777 atmel_port->backup_imr = 0;
2778 atmel_port->uart.line = ret;
2779 atmel_serial_probe_fifos(atmel_port, pdev);
2781 atomic_set(&atmel_port->tasklet_shutdown, 0);
2782 spin_lock_init(&atmel_port->lock_suspended);
2784 ret = atmel_init_port(atmel_port, pdev);
2788 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2789 if (IS_ERR(atmel_port->gpios)) {
2790 ret = PTR_ERR(atmel_port->gpios);
2794 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2796 data = kmalloc(sizeof(struct atmel_uart_char)
2797 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2799 goto err_alloc_ring;
2800 atmel_port->rx_ring.buf = data;
2803 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2805 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2809 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2810 if (atmel_is_console_port(&atmel_port->uart)
2811 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2813 * The serial core enabled the clock for us, so undo
2814 * the clk_prepare_enable() in atmel_console_setup()
2816 clk_disable_unprepare(atmel_port->clk);
2820 device_init_wakeup(&pdev->dev, 1);
2821 platform_set_drvdata(pdev, atmel_port);
2824 * The peripheral clock has been disabled by atmel_init_port():
2825 * enable it before accessing I/O registers
2827 clk_prepare_enable(atmel_port->clk);
2829 if (rs485_enabled) {
2830 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2831 ATMEL_US_USMODE_NORMAL);
2832 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2837 * Get port name of usart or uart
2839 atmel_get_ip_name(&atmel_port->uart);
2842 * The peripheral clock can now safely be disabled till the port
2845 clk_disable_unprepare(atmel_port->clk);
2850 kfree(atmel_port->rx_ring.buf);
2851 atmel_port->rx_ring.buf = NULL;
2853 if (!atmel_is_console_port(&atmel_port->uart)) {
2854 clk_put(atmel_port->clk);
2855 atmel_port->clk = NULL;
2858 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2864 * Even if the driver is not modular, it makes sense to be able to
2865 * unbind a device: there can be many bound devices, and there are
2866 * situations where dynamic binding and unbinding can be useful.
2868 * For example, a connected device can require a specific firmware update
2869 * protocol that needs bitbanging on IO lines, but use the regular serial
2870 * port in the normal case.
2872 static int atmel_serial_remove(struct platform_device *pdev)
2874 struct uart_port *port = platform_get_drvdata(pdev);
2875 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2878 tasklet_kill(&atmel_port->tasklet_rx);
2879 tasklet_kill(&atmel_port->tasklet_tx);
2881 device_init_wakeup(&pdev->dev, 0);
2883 ret = uart_remove_one_port(&atmel_uart, port);
2885 kfree(atmel_port->rx_ring.buf);
2887 /* "port" is allocated statically, so we shouldn't free it */
2889 clear_bit(port->line, atmel_ports_in_use);
2891 clk_put(atmel_port->clk);
2892 atmel_port->clk = NULL;
2897 static struct platform_driver atmel_serial_driver = {
2898 .probe = atmel_serial_probe,
2899 .remove = atmel_serial_remove,
2900 .suspend = atmel_serial_suspend,
2901 .resume = atmel_serial_resume,
2903 .name = "atmel_usart",
2904 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2908 static int __init atmel_serial_init(void)
2912 ret = uart_register_driver(&atmel_uart);
2916 ret = platform_driver_register(&atmel_serial_driver);
2918 uart_unregister_driver(&atmel_uart);
2922 device_initcall(atmel_serial_init);