1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
8 #include <linux/spi/spi.h>
19 static const struct wilc_hif_func wilc_hif_spi;
21 /********************************************
25 ********************************************/
27 static const u8 crc7_syndrome_table[256] = {
28 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
29 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
30 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
31 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
32 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
33 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
34 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
35 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
36 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
37 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
38 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
39 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
40 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
41 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
42 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
43 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
44 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
45 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
46 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
47 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
48 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
49 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
50 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
51 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
52 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
53 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
54 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
55 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
56 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
57 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
58 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
59 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
62 static u8 crc7_byte(u8 crc, u8 data)
64 return crc7_syndrome_table[(crc << 1) ^ data];
67 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
70 crc = crc7_byte(crc, *buffer++);
74 /********************************************
76 * Spi protocol Function
78 ********************************************/
80 #define CMD_DMA_WRITE 0xc1
81 #define CMD_DMA_READ 0xc2
82 #define CMD_INTERNAL_WRITE 0xc3
83 #define CMD_INTERNAL_READ 0xc4
84 #define CMD_TERMINATE 0xc5
85 #define CMD_REPEAT 0xc6
86 #define CMD_DMA_EXT_WRITE 0xc7
87 #define CMD_DMA_EXT_READ 0xc8
88 #define CMD_SINGLE_WRITE 0xc9
89 #define CMD_SINGLE_READ 0xca
90 #define CMD_RESET 0xcf
97 #define DATA_PKT_SZ_256 256
98 #define DATA_PKT_SZ_512 512
99 #define DATA_PKT_SZ_1K 1024
100 #define DATA_PKT_SZ_4K (4 * 1024)
101 #define DATA_PKT_SZ_8K (8 * 1024)
102 #define DATA_PKT_SZ DATA_PKT_SZ_8K
104 #define USE_SPI_DMA 0
106 static int wilc_bus_probe(struct spi_device *spi)
110 struct gpio_desc *gpio;
111 struct wilc_spi *spi_priv;
113 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
117 gpio = gpiod_get(&spi->dev, "irq", GPIOD_IN);
119 /* get the GPIO descriptor from hardcode GPIO number */
120 gpio = gpio_to_desc(GPIO_NUM);
122 dev_err(&spi->dev, "failed to get the irq gpio\n");
125 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
131 spi_set_drvdata(spi, wilc);
132 wilc->dev = &spi->dev;
133 wilc->bus_data = spi_priv;
134 wilc->gpio_irq = gpio;
136 wilc->rtc_clk = devm_clk_get(&spi->dev, "rtc_clk");
137 if (PTR_ERR_OR_ZERO(wilc->rtc_clk) == -EPROBE_DEFER)
138 return -EPROBE_DEFER;
139 else if (!IS_ERR(wilc->rtc_clk))
140 clk_prepare_enable(wilc->rtc_clk);
145 static int wilc_bus_remove(struct spi_device *spi)
147 struct wilc *wilc = spi_get_drvdata(spi);
149 /* free the GPIO in module remove */
151 gpiod_put(wilc->gpio_irq);
153 if (!IS_ERR(wilc->rtc_clk))
154 clk_disable_unprepare(wilc->rtc_clk);
156 wilc_netdev_cleanup(wilc);
160 static const struct of_device_id wilc_of_match[] = {
161 { .compatible = "microchip,wilc1000-spi", },
164 MODULE_DEVICE_TABLE(of, wilc_of_match);
166 static struct spi_driver wilc_spi_driver = {
169 .of_match_table = wilc_of_match,
171 .probe = wilc_bus_probe,
172 .remove = wilc_bus_remove,
174 module_spi_driver(wilc_spi_driver);
175 MODULE_LICENSE("GPL");
177 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
179 struct spi_device *spi = to_spi_device(wilc->dev);
181 struct spi_message msg;
184 struct spi_transfer tr = {
189 char *r_buffer = kzalloc(len, GFP_KERNEL);
194 tr.rx_buf = r_buffer;
195 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
197 memset(&msg, 0, sizeof(msg));
198 spi_message_init(&msg);
200 msg.is_dma_mapped = USE_SPI_DMA;
201 spi_message_add_tail(&tr, &msg);
203 ret = spi_sync(spi, &msg);
205 dev_err(&spi->dev, "SPI transaction failed\n");
210 "can't write data with the following length: %d\n",
218 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
220 struct spi_device *spi = to_spi_device(wilc->dev);
224 struct spi_message msg;
225 struct spi_transfer tr = {
231 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
236 tr.tx_buf = t_buffer;
238 memset(&msg, 0, sizeof(msg));
239 spi_message_init(&msg);
241 msg.is_dma_mapped = USE_SPI_DMA;
242 spi_message_add_tail(&tr, &msg);
244 ret = spi_sync(spi, &msg);
246 dev_err(&spi->dev, "SPI transaction failed\n");
250 "can't read data with the following length: %u\n",
258 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
260 struct spi_device *spi = to_spi_device(wilc->dev);
264 struct spi_message msg;
265 struct spi_transfer tr = {
274 memset(&msg, 0, sizeof(msg));
275 spi_message_init(&msg);
277 msg.is_dma_mapped = USE_SPI_DMA;
279 spi_message_add_tail(&tr, &msg);
280 ret = spi_sync(spi, &msg);
282 dev_err(&spi->dev, "SPI transaction failed\n");
285 "can't read data with the following length: %u\n",
293 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
296 struct spi_device *spi = to_spi_device(wilc->dev);
297 struct wilc_spi *spi_priv = wilc->bus_data;
309 case CMD_SINGLE_READ: /* single word (4 bytes) read */
310 wb[1] = (u8)(adr >> 16);
311 wb[2] = (u8)(adr >> 8);
316 case CMD_INTERNAL_READ: /* internal register read */
317 wb[1] = (u8)(adr >> 8);
346 case CMD_DMA_WRITE: /* dma write */
347 case CMD_DMA_READ: /* dma read */
348 wb[1] = (u8)(adr >> 16);
349 wb[2] = (u8)(adr >> 8);
351 wb[4] = (u8)(sz >> 8);
356 case CMD_DMA_EXT_WRITE: /* dma extended write */
357 case CMD_DMA_EXT_READ: /* dma extended read */
358 wb[1] = (u8)(adr >> 16);
359 wb[2] = (u8)(adr >> 8);
361 wb[4] = (u8)(sz >> 16);
362 wb[5] = (u8)(sz >> 8);
367 case CMD_INTERNAL_WRITE: /* internal register write */
368 wb[1] = (u8)(adr >> 8);
379 case CMD_SINGLE_WRITE: /* single word write */
380 wb[1] = (u8)(adr >> 16);
381 wb[2] = (u8)(adr >> 8);
398 if (!spi_priv->crc_off)
399 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
403 #define NUM_SKIP_BYTES (1)
404 #define NUM_RSP_BYTES (2)
405 #define NUM_DATA_HDR_BYTES (1)
406 #define NUM_DATA_BYTES (4)
407 #define NUM_CRC_BYTES (2)
408 #define NUM_DUMMY_BYTES (3)
409 if (cmd == CMD_RESET ||
410 cmd == CMD_TERMINATE ||
412 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
413 } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
414 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
416 if (!spi_priv->crc_off)
417 len2 = len + tmp + NUM_CRC_BYTES;
421 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
423 #undef NUM_DUMMY_BYTES
425 if (len2 > ARRAY_SIZE(wb)) {
426 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
427 len2, ARRAY_SIZE(wb));
430 /* zero spi write buffers. */
431 for (wix = len; wix < len2; wix++)
435 if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
436 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
441 * Command/Control response
443 if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
444 rix++; /* skip 1 byte */
450 "Failed cmd response, cmd (%02x), resp (%02x)\n",
460 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
465 if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
466 cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
468 * Data Respnose header
473 * ensure there is room in buffer later
474 * to read data and crc
482 if (((rsp >> 4) & 0xf) == 0xf)
488 "Error, data read response (%02x)\n", rsp);
493 if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
497 if ((rix + 3) < len2) {
504 "buffer overrun when reading data.\n");
508 if (!spi_priv->crc_off) {
512 if ((rix + 1) < len2) {
517 "buffer overrun when reading crc.\n");
521 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
524 /* some data may be read in response to dummy bytes. */
525 for (ix = 0; (rix < len2) && (ix < sz); )
533 if (sz <= (DATA_PKT_SZ - ix))
536 nbytes = DATA_PKT_SZ - ix;
541 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
543 "Failed block read, bus err\n");
550 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
552 "Failed block crc read, bus err\n");
561 * if any data in left unread,
562 * then read the rest using normal DMA code.
567 if (sz <= DATA_PKT_SZ)
570 nbytes = DATA_PKT_SZ;
573 * read data response only on the next DMA cycles not
574 * the first DMA since data response header is already
575 * handled above for the first DMA.
578 * Data Respnose header
582 if (wilc_spi_rx(wilc, &rsp, 1)) {
584 "Failed resp read, bus err\n");
588 if (((rsp >> 4) & 0xf) == 0xf)
592 if (result == N_FAIL)
598 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
600 "Failed block read, bus err\n");
608 if (!spi_priv->crc_off && wilc_spi_rx(wilc, crc, 2)) {
610 "Failed block crc read, bus err\n");
622 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
624 struct spi_device *spi = to_spi_device(wilc->dev);
625 struct wilc_spi *spi_priv = wilc->bus_data;
628 u8 cmd, order, crc[2] = {0};
635 if (sz <= DATA_PKT_SZ) {
639 nbytes = DATA_PKT_SZ;
652 if (wilc_spi_tx(wilc, &cmd, 1)) {
654 "Failed data block cmd write, bus error...\n");
662 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
664 "Failed data block write, bus error...\n");
672 if (!spi_priv->crc_off) {
673 if (wilc_spi_tx(wilc, crc, 2)) {
674 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
681 * No need to wait for response
690 /********************************************
692 * Spi Internal Read/Write Function
694 ********************************************/
696 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
698 struct spi_device *spi = to_spi_device(wilc->dev);
702 result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
705 dev_err(&spi->dev, "Failed internal write cmd...\n");
710 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
712 struct spi_device *spi = to_spi_device(wilc->dev);
715 result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
717 if (result != N_OK) {
718 dev_err(&spi->dev, "Failed internal read cmd...\n");
727 /********************************************
731 ********************************************/
733 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
735 struct spi_device *spi = to_spi_device(wilc->dev);
737 u8 cmd = CMD_SINGLE_WRITE;
742 /* Clockless register */
743 cmd = CMD_INTERNAL_WRITE;
747 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
749 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
754 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
756 struct spi_device *spi = to_spi_device(wilc->dev);
760 * has to be greated than 4
765 result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
766 if (result != N_OK) {
768 "Failed cmd, write block (%08x)...\n", addr);
775 result = spi_data_write(wilc, buf, size);
777 dev_err(&spi->dev, "Failed block data write...\n");
782 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
784 struct spi_device *spi = to_spi_device(wilc->dev);
786 u8 cmd = CMD_SINGLE_READ;
790 /* Clockless register */
791 cmd = CMD_INTERNAL_READ;
795 result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
796 if (result != N_OK) {
797 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
806 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
808 struct spi_device *spi = to_spi_device(wilc->dev);
814 result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
815 if (result != N_OK) {
816 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
823 /********************************************
827 ********************************************/
829 static int wilc_spi_deinit(struct wilc *wilc)
837 static int wilc_spi_init(struct wilc *wilc, bool resume)
839 struct spi_device *spi = to_spi_device(wilc->dev);
840 struct wilc_spi *spi_priv = wilc->bus_data;
846 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
847 dev_err(&spi->dev, "Fail cmd read chip id...\n");
858 * TODO: We can remove the CRC trials if there is a definite
861 /* the SPI to it's initial value. */
862 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
864 * Read failed. Try with CRC off. This might happen when module
865 * is removed but chip isn't reset
867 spi_priv->crc_off = 1;
869 "Failed read with CRC on, retrying with CRC off\n");
870 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) {
872 * Read failed with both CRC on and off,
875 dev_err(&spi->dev, "Failed internal read protocol\n");
879 if (spi_priv->crc_off == 0) {
880 reg &= ~0xc; /* disable crc checking */
883 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
885 "[wilc spi %d]: Failed internal write reg\n",
889 spi_priv->crc_off = 1;
893 * make sure can read back chip id correctly
895 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
896 dev_err(&spi->dev, "Fail cmd read chip id...\n");
900 spi_priv->has_thrpt_enh = 1;
907 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
909 struct spi_device *spi = to_spi_device(wilc->dev);
910 struct wilc_spi *spi_priv = wilc->bus_data;
913 if (spi_priv->has_thrpt_enh) {
914 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
916 *size = *size & IRQ_DMA_WD_CNT_MASK;
921 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
925 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
928 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
935 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
937 struct spi_device *spi = to_spi_device(wilc->dev);
938 struct wilc_spi *spi_priv = wilc->bus_data;
946 int k = IRG_FLAGS_OFFSET + 5;
948 if (spi_priv->has_thrpt_enh)
949 return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
951 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
954 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
957 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
961 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
962 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
964 if (spi_priv->nint > 5) {
965 wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
966 tmp |= (((irq_flags >> 0) & 0x7) << k);
969 unknown_mask = ~((1ul << spi_priv->nint) - 1);
971 unexpected_irq = (tmp >> IRG_FLAGS_OFFSET) & unknown_mask;
972 if (unexpected_irq) {
974 "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
975 j, tmp, unknown_mask);
979 } while (unexpected_irq);
986 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
988 struct spi_device *spi = to_spi_device(wilc->dev);
989 struct wilc_spi *spi_priv = wilc->bus_data;
994 if (spi_priv->has_thrpt_enh) {
995 return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
999 flags = val & (BIT(MAX_NUM_INT) - 1);
1004 for (i = 0; i < spi_priv->nint; i++) {
1006 * No matter what you write 1 or 0,
1007 * it will clear interrupt.
1010 ret = wilc_spi_write_reg(wilc,
1018 "Failed wilc_spi_write_reg, set reg %x ...\n",
1022 for (i = spi_priv->nint; i < MAX_NUM_INT; i++) {
1025 "Unexpected interrupt cleared %d...\n",
1032 /* select VMM table 0 */
1033 if (val & SEL_VMM_TBL0)
1035 /* select VMM table 1 */
1036 if (val & SEL_VMM_TBL1)
1039 ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
1041 dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
1047 * enable vmm transfer.
1049 ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
1051 dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1059 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1061 struct spi_device *spi = to_spi_device(wilc->dev);
1062 struct wilc_spi *spi_priv = wilc->bus_data;
1066 if (nint > MAX_NUM_INT) {
1067 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1071 spi_priv->nint = nint;
1074 * interrupt pin mux select
1076 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1078 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1083 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1085 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1093 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1095 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1100 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1101 reg |= (BIT((27 + i)));
1103 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1105 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1110 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1112 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1117 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1120 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1122 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1131 /* Global spi HIF function table */
1132 static const struct wilc_hif_func wilc_hif_spi = {
1133 .hif_init = wilc_spi_init,
1134 .hif_deinit = wilc_spi_deinit,
1135 .hif_read_reg = wilc_spi_read_reg,
1136 .hif_write_reg = wilc_spi_write_reg,
1137 .hif_block_rx = wilc_spi_read,
1138 .hif_block_tx = wilc_spi_write,
1139 .hif_read_int = wilc_spi_read_int,
1140 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1141 .hif_read_size = wilc_spi_read_size,
1142 .hif_block_tx_ext = wilc_spi_write,
1143 .hif_block_rx_ext = wilc_spi_read,
1144 .hif_sync_ext = wilc_spi_sync_ext,