1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Implementation of host-to-chip MIBs of WFxxx Split Mac (WSM) API.
5 * Copyright (c) 2017-2019, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
7 * Copyright (C) 2010, ST-Ericsson SA
9 #ifndef WFX_HIF_TX_MIB_H
10 #define WFX_HIF_TX_MIB_H
12 #include <linux/etherdevice.h>
16 #include "hif_api_mib.h"
18 static inline int hif_set_output_power(struct wfx_vif *wvif, int power_level)
20 __le32 val = cpu_to_le32(power_level);
22 return hif_write_mib(wvif->wdev, wvif->id,
23 HIF_MIB_ID_CURRENT_TX_POWER_LEVEL,
27 static inline int hif_set_beacon_wakeup_period(struct wfx_vif *wvif,
28 unsigned int dtim_interval,
29 unsigned int listen_interval)
31 struct hif_mib_beacon_wake_up_period val = {
32 .wakeup_period_min = dtim_interval,
34 .wakeup_period_max = cpu_to_le16(listen_interval),
37 if (dtim_interval > 0xFF || listen_interval > 0xFFFF)
39 return hif_write_mib(wvif->wdev, wvif->id,
40 HIF_MIB_ID_BEACON_WAKEUP_PERIOD,
44 static inline int hif_set_rcpi_rssi_threshold(struct wfx_vif *wvif,
45 struct hif_mib_rcpi_rssi_threshold *arg)
47 return hif_write_mib(wvif->wdev, wvif->id,
48 HIF_MIB_ID_RCPI_RSSI_THRESHOLD, arg, sizeof(*arg));
51 static inline int hif_get_counters_table(struct wfx_dev *wdev,
52 struct hif_mib_extended_count_table *arg)
54 if (wfx_api_older_than(wdev, 1, 3)) {
55 // extended_count_table is wider than count_table
56 memset(arg, 0xFF, sizeof(*arg));
57 return hif_read_mib(wdev, 0, HIF_MIB_ID_COUNTERS_TABLE,
58 arg, sizeof(struct hif_mib_count_table));
60 return hif_read_mib(wdev, 0,
61 HIF_MIB_ID_EXTENDED_COUNTERS_TABLE, arg,
62 sizeof(struct hif_mib_extended_count_table));
66 static inline int hif_set_macaddr(struct wfx_vif *wvif, u8 *mac)
68 struct hif_mib_mac_address msg = { };
71 ether_addr_copy(msg.mac_addr, mac);
72 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_MAC_ADDRESS,
76 static inline int hif_set_rx_filter(struct wfx_vif *wvif, bool filter_bssid,
79 struct hif_mib_rx_filter val = { };
84 val.fwd_probe_req = 1;
85 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_RX_FILTER,
89 static inline int hif_set_beacon_filter_table(struct wfx_vif *wvif,
91 struct hif_ie_table_entry *tbl)
94 struct hif_mib_bcn_filter_table *val;
95 int buf_len = struct_size(val, ie_table, tbl_len);
97 val = kzalloc(buf_len, GFP_KERNEL);
100 val->num_of_info_elmts = cpu_to_le32(tbl_len);
101 memcpy(val->ie_table, tbl, tbl_len * sizeof(*tbl));
102 ret = hif_write_mib(wvif->wdev, wvif->id,
103 HIF_MIB_ID_BEACON_FILTER_TABLE, val, buf_len);
108 static inline int hif_beacon_filter_control(struct wfx_vif *wvif,
109 int enable, int beacon_count)
111 struct hif_mib_bcn_filter_enable arg = {
112 .enable = cpu_to_le32(enable),
113 .bcn_count = cpu_to_le32(beacon_count),
115 return hif_write_mib(wvif->wdev, wvif->id,
116 HIF_MIB_ID_BEACON_FILTER_ENABLE,
120 static inline int hif_set_operational_mode(struct wfx_dev *wdev,
121 enum hif_op_power_mode mode)
123 struct hif_mib_gl_operational_power_mode val = {
125 .wup_ind_activation = 1,
128 return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE,
132 static inline int hif_set_template_frame(struct wfx_vif *wvif,
133 struct hif_mib_template_frame *arg)
135 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_TEMPLATE_FRAME,
139 static inline int hif_set_mfp(struct wfx_vif *wvif, bool capable, bool required)
141 struct hif_mib_protected_mgmt_policy val = { };
143 WARN(required && !capable, "incoherent arguments");
146 val.host_enc_auth_frames = 1;
149 val.unpmf_allowed = 1;
150 cpu_to_le32s((u32 *) &val);
151 return hif_write_mib(wvif->wdev, wvif->id,
152 HIF_MIB_ID_PROTECTED_MGMT_POLICY,
156 static inline int hif_set_block_ack_policy(struct wfx_vif *wvif,
157 u8 tx_tid_policy, u8 rx_tid_policy)
159 struct hif_mib_block_ack_policy val = {
160 .block_ack_tx_tid_policy = tx_tid_policy,
161 .block_ack_rx_tid_policy = rx_tid_policy,
164 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BLOCK_ACK_POLICY,
168 static inline int hif_set_association_mode(struct wfx_vif *wvif,
169 struct hif_mib_set_association_mode *arg)
171 return hif_write_mib(wvif->wdev, wvif->id,
172 HIF_MIB_ID_SET_ASSOCIATION_MODE, arg, sizeof(*arg));
175 static inline int hif_set_tx_rate_retry_policy(struct wfx_vif *wvif,
176 struct hif_mib_set_tx_rate_retry_policy *arg)
178 size_t size = struct_size(arg, tx_rate_retry_policy,
179 arg->num_tx_rate_policies);
181 return hif_write_mib(wvif->wdev, wvif->id,
182 HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY, arg, size);
185 static inline int hif_set_mac_addr_condition(struct wfx_vif *wvif,
186 struct hif_mib_mac_addr_data_frame_condition *arg)
188 return hif_write_mib(wvif->wdev, wvif->id,
189 HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION,
193 static inline int hif_set_uc_mc_bc_condition(struct wfx_vif *wvif,
194 struct hif_mib_uc_mc_bc_data_frame_condition *arg)
196 return hif_write_mib(wvif->wdev, wvif->id,
197 HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION,
201 static inline int hif_set_config_data_filter(struct wfx_vif *wvif,
202 struct hif_mib_config_data_filter *arg)
204 return hif_write_mib(wvif->wdev, wvif->id,
205 HIF_MIB_ID_CONFIG_DATA_FILTER, arg, sizeof(*arg));
208 static inline int hif_set_data_filtering(struct wfx_vif *wvif,
209 struct hif_mib_set_data_filtering *arg)
211 return hif_write_mib(wvif->wdev, wvif->id,
212 HIF_MIB_ID_SET_DATA_FILTERING, arg, sizeof(*arg));
215 static inline int hif_keep_alive_period(struct wfx_vif *wvif, int period)
217 struct hif_mib_keep_alive_period arg = {
218 .keep_alive_period = cpu_to_le16(period),
221 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_KEEP_ALIVE_PERIOD,
225 static inline int hif_set_arp_ipv4_filter(struct wfx_vif *wvif,
226 struct hif_mib_arp_ip_addr_table *fp)
228 return hif_write_mib(wvif->wdev, wvif->id,
229 HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE,
233 static inline int hif_use_multi_tx_conf(struct wfx_dev *wdev,
236 __le32 arg = enabled ? cpu_to_le32(1) : 0;
238 return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_SET_MULTI_MSG,
242 static inline int hif_set_uapsd_info(struct wfx_vif *wvif,
243 struct hif_mib_set_uapsd_information *arg)
245 return hif_write_mib(wvif->wdev, wvif->id,
246 HIF_MIB_ID_SET_UAPSD_INFORMATION,
250 static inline int hif_erp_use_protection(struct wfx_vif *wvif, bool enable)
252 __le32 arg = enable ? cpu_to_le32(1) : 0;
254 return hif_write_mib(wvif->wdev, wvif->id,
255 HIF_MIB_ID_NON_ERP_PROTECTION, &arg, sizeof(arg));
258 static inline int hif_slot_time(struct wfx_vif *wvif, int val)
260 __le32 arg = cpu_to_le32(val);
262 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SLOT_TIME,
266 static inline int hif_dual_cts_protection(struct wfx_vif *wvif, bool val)
268 struct hif_mib_set_ht_protection arg = {
269 .dual_cts_prot = val,
272 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SET_HT_PROTECTION,
276 static inline int hif_wep_default_key_id(struct wfx_vif *wvif, int val)
278 __le32 arg = cpu_to_le32(val);
280 return hif_write_mib(wvif->wdev, wvif->id,
281 HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID,
285 static inline int hif_rts_threshold(struct wfx_vif *wvif, int val)
287 __le32 arg = cpu_to_le32(val > 0 ? val : 0xFFFF);
289 return hif_write_mib(wvif->wdev, wvif->id,
290 HIF_MIB_ID_DOT11_RTS_THRESHOLD, &arg, sizeof(arg));