drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  */
   7
   8 #include <asm/unaligned.h>
   9 #include <linux/bitfield.h>
  10 #include <media/v4l2-mem2mem.h>
  11 #include "hantro.h"
  12 #include "hantro_hw.h"
  13
  14 #define VDPU_SWREG(nr)                  ((nr) * 4)
  15
  16 #define VDPU_REG_DEC_OUT_BASE           VDPU_SWREG(63)
  17 #define VDPU_REG_RLC_VLC_BASE           VDPU_SWREG(64)
  18 #define VDPU_REG_QTABLE_BASE            VDPU_SWREG(61)
  19 #define VDPU_REG_REFER0_BASE            VDPU_SWREG(131)
  20 #define VDPU_REG_REFER2_BASE            VDPU_SWREG(134)
  21 #define VDPU_REG_REFER3_BASE            VDPU_SWREG(135)
  22 #define VDPU_REG_REFER1_BASE            VDPU_SWREG(148)
  23 #define VDPU_REG_DEC_E(v)               ((v) ? BIT(0) : 0)
  24
  25 #define VDPU_REG_DEC_ADV_PRE_DIS(v)     ((v) ? BIT(11) : 0)
  26 #define VDPU_REG_DEC_SCMD_DIS(v)        ((v) ? BIT(10) : 0)
  27 #define VDPU_REG_FILTERING_DIS(v)       ((v) ? BIT(8) : 0)
  28 #define VDPU_REG_DEC_LATENCY(v)         (((v) << 1) & GENMASK(6, 1))
  29
  30 #define VDPU_REG_INIT_QP(v)             (((v) << 25) & GENMASK(30, 25))
  31 #define VDPU_REG_STREAM_LEN(v)          (((v) << 0) & GENMASK(23, 0))
  32
  33 #define VDPU_REG_APF_THRESHOLD(v)       (((v) << 17) & GENMASK(30, 17))
  34 #define VDPU_REG_STARTMB_X(v)           (((v) << 8) & GENMASK(16, 8))
  35 #define VDPU_REG_STARTMB_Y(v)           (((v) << 0) & GENMASK(7, 0))
  36
  37 #define VDPU_REG_DEC_MODE(v)            (((v) << 0) & GENMASK(3, 0))
  38
  39 #define VDPU_REG_DEC_STRENDIAN_E(v)     ((v) ? BIT(5) : 0)
  40 #define VDPU_REG_DEC_STRSWAP32_E(v)     ((v) ? BIT(4) : 0)
  41 #define VDPU_REG_DEC_OUTSWAP32_E(v)     ((v) ? BIT(3) : 0)
  42 #define VDPU_REG_DEC_INSWAP32_E(v)      ((v) ? BIT(2) : 0)
  43 #define VDPU_REG_DEC_OUT_ENDIAN(v)      ((v) ? BIT(1) : 0)
  44 #define VDPU_REG_DEC_IN_ENDIAN(v)       ((v) ? BIT(0) : 0)
  45
  46 #define VDPU_REG_DEC_DATA_DISC_E(v)     ((v) ? BIT(22) : 0)
  47 #define VDPU_REG_DEC_MAX_BURST(v)       (((v) << 16) & GENMASK(20, 16))
  48 #define VDPU_REG_DEC_AXI_WR_ID(v)       (((v) << 8) & GENMASK(15, 8))
  49 #define VDPU_REG_DEC_AXI_RD_ID(v)       (((v) << 0) & GENMASK(7, 0))
  50
  51 #define VDPU_REG_RLC_MODE_E(v)          ((v) ? BIT(20) : 0)
  52 #define VDPU_REG_PIC_INTERLACE_E(v)     ((v) ? BIT(17) : 0)
  53 #define VDPU_REG_PIC_FIELDMODE_E(v)     ((v) ? BIT(16) : 0)
  54 #define VDPU_REG_PIC_B_E(v)             ((v) ? BIT(15) : 0)
  55 #define VDPU_REG_PIC_INTER_E(v)         ((v) ? BIT(14) : 0)
  56 #define VDPU_REG_PIC_TOPFIELD_E(v)      ((v) ? BIT(13) : 0)
  57 #define VDPU_REG_FWD_INTERLACE_E(v)     ((v) ? BIT(12) : 0)
  58 #define VDPU_REG_WRITE_MVS_E(v)         ((v) ? BIT(10) : 0)
  59 #define VDPU_REG_DEC_TIMEOUT_E(v)       ((v) ? BIT(5) : 0)
  60 #define VDPU_REG_DEC_CLK_GATE_E(v)      ((v) ? BIT(4) : 0)
  61
  62 #define VDPU_REG_PIC_MB_WIDTH(v)        (((v) << 23) & GENMASK(31, 23))
  63 #define VDPU_REG_PIC_MB_HEIGHT_P(v)     (((v) << 11) & GENMASK(18, 11))
  64 #define VDPU_REG_ALT_SCAN_E(v)          ((v) ? BIT(6) : 0)
  65 #define VDPU_REG_TOPFIELDFIRST_E(v)     ((v) ? BIT(5) : 0)
  66
  67 #define VDPU_REG_STRM_START_BIT(v)      (((v) << 26) & GENMASK(31, 26))
  68 #define VDPU_REG_QSCALE_TYPE(v)         ((v) ? BIT(24) : 0)
  69 #define VDPU_REG_CON_MV_E(v)            ((v) ? BIT(4) : 0)
  70 #define VDPU_REG_INTRA_DC_PREC(v)       (((v) << 2) & GENMASK(3, 2))
  71 #define VDPU_REG_INTRA_VLC_TAB(v)       ((v) ? BIT(1) : 0)
  72 #define VDPU_REG_FRAME_PRED_DCT(v)      ((v) ? BIT(0) : 0)
  73
  74 #define VDPU_REG_ALT_SCAN_FLAG_E(v)     ((v) ? BIT(19) : 0)
  75 #define VDPU_REG_FCODE_FWD_HOR(v)       (((v) << 15) & GENMASK(18, 15))
  76 #define VDPU_REG_FCODE_FWD_VER(v)       (((v) << 11) & GENMASK(14, 11))
  77 #define VDPU_REG_FCODE_BWD_HOR(v)       (((v) << 7) & GENMASK(10, 7))
  78 #define VDPU_REG_FCODE_BWD_VER(v)       (((v) << 3) & GENMASK(6, 3))
  79 #define VDPU_REG_MV_ACCURACY_FWD(v)     ((v) ? BIT(2) : 0)
  80 #define VDPU_REG_MV_ACCURACY_BWD(v)     ((v) ? BIT(1) : 0)
  81
  82 #define PICT_TOP_FIELD     1
  83 #define PICT_BOTTOM_FIELD  2
  84 #define PICT_FRAME         3
  85
  86 static void
  87 rk3399_vpu_mpeg2_dec_set_quantization(struct hantro_dev *vpu,
  88                                       struct hantro_ctx *ctx)
  89 {
  90         struct v4l2_ctrl_mpeg2_quantization *quantization;
  91
  92         quantization = hantro_get_ctrl(ctx,
  93                                        V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
  94         hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, quantization);
  95         vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma,
  96                            VDPU_REG_QTABLE_BASE);
  97 }
  98
  99 static void
 100 rk3399_vpu_mpeg2_dec_set_buffers(struct hantro_dev *vpu,
 101                                  struct hantro_ctx *ctx,
 102                                  struct vb2_buffer *src_buf,
 103                                  struct vb2_buffer *dst_buf,
 104                                  const struct v4l2_mpeg2_sequence *sequence,
 105                                  const struct v4l2_mpeg2_picture *picture,
 106                                  const struct v4l2_ctrl_mpeg2_slice_params *slice_params)
 107 {
 108         dma_addr_t forward_addr = 0, backward_addr = 0;
 109         dma_addr_t current_addr, addr;
 110         struct vb2_queue *vq;
 111
 112         vq = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
 113
 114         switch (picture->picture_coding_type) {
 115         case V4L2_MPEG2_PICTURE_CODING_TYPE_B:
 116                 backward_addr = hantro_get_ref(vq,
 117                                                slice_params->backward_ref_ts);
 118                 /* fall-through */
 119         case V4L2_MPEG2_PICTURE_CODING_TYPE_P:
 120                 forward_addr = hantro_get_ref(vq,
 121                                               slice_params->forward_ref_ts);
 122         }
 123
 124         /* Source bitstream buffer */
 125         addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
 126         vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);
 127
 128         /* Destination frame buffer */
 129         addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
 130         current_addr = addr;
 131
 132         if (picture->picture_structure == PICT_BOTTOM_FIELD)
 133                 addr += ALIGN(ctx->dst_fmt.width, 16);
 134         vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);
 135
 136         if (!forward_addr)
 137                 forward_addr = current_addr;
 138         if (!backward_addr)
 139                 backward_addr = current_addr;
 140
 141         /* Set forward ref frame (top/bottom field) */
 142         if (picture->picture_structure == PICT_FRAME ||
 143             picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B ||
 144             (picture->picture_structure == PICT_TOP_FIELD &&
 145              picture->top_field_first) ||
 146             (picture->picture_structure == PICT_BOTTOM_FIELD &&
 147              !picture->top_field_first)) {
 148                 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
 149                 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
 150         } else if (picture->picture_structure == PICT_TOP_FIELD) {
 151                 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
 152                 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE);
 153         } else if (picture->picture_structure == PICT_BOTTOM_FIELD) {
 154                 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE);
 155                 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
 156         }
 157
 158         /* Set backward ref frame (top/bottom field) */
 159         vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE);
 160         vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);
 161 }
 162
 163 void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx)
 164 {
 165         struct hantro_dev *vpu = ctx->dev;
 166         struct vb2_v4l2_buffer *src_buf, *dst_buf;
 167         const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
 168         const struct v4l2_mpeg2_sequence *sequence;
 169         const struct v4l2_mpeg2_picture *picture;
 170         u32 reg;
 171
 172         src_buf = hantro_get_src_buf(ctx);
 173         dst_buf = hantro_get_dst_buf(ctx);
 174
 175         hantro_prepare_run(ctx);
 176
 177         slice_params = hantro_get_ctrl(ctx,
 178                                        V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
 179         sequence = &slice_params->sequence;
 180         picture = &slice_params->picture;
 181
 182         reg = VDPU_REG_DEC_ADV_PRE_DIS(0) |
 183               VDPU_REG_DEC_SCMD_DIS(0) |
 184               VDPU_REG_FILTERING_DIS(1) |
 185               VDPU_REG_DEC_LATENCY(0);
 186         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
 187
 188         reg = VDPU_REG_INIT_QP(1) |
 189               VDPU_REG_STREAM_LEN(slice_params->bit_size >> 3);
 190         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
 191
 192         reg = VDPU_REG_APF_THRESHOLD(8) |
 193               VDPU_REG_STARTMB_X(0) |
 194               VDPU_REG_STARTMB_Y(0);
 195         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
 196
 197         reg = VDPU_REG_DEC_MODE(5);
 198         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
 199
 200         reg = VDPU_REG_DEC_STRENDIAN_E(1) |
 201               VDPU_REG_DEC_STRSWAP32_E(1) |
 202               VDPU_REG_DEC_OUTSWAP32_E(1) |
 203               VDPU_REG_DEC_INSWAP32_E(1) |
 204               VDPU_REG_DEC_OUT_ENDIAN(1) |
 205               VDPU_REG_DEC_IN_ENDIAN(1);
 206         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
 207
 208         reg = VDPU_REG_DEC_DATA_DISC_E(0) |
 209               VDPU_REG_DEC_MAX_BURST(16) |
 210               VDPU_REG_DEC_AXI_WR_ID(0) |
 211               VDPU_REG_DEC_AXI_RD_ID(0);
 212         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
 213
 214         reg = VDPU_REG_RLC_MODE_E(0) |
 215               VDPU_REG_PIC_INTERLACE_E(!sequence->progressive_sequence) |
 216               VDPU_REG_PIC_FIELDMODE_E(picture->picture_structure != PICT_FRAME) |
 217               VDPU_REG_PIC_B_E(picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B) |
 218               VDPU_REG_PIC_INTER_E(picture->picture_coding_type != V4L2_MPEG2_PICTURE_CODING_TYPE_I) |
 219               VDPU_REG_PIC_TOPFIELD_E(picture->picture_structure == PICT_TOP_FIELD) |
 220               VDPU_REG_FWD_INTERLACE_E(0) |
 221               VDPU_REG_WRITE_MVS_E(0) |
 222               VDPU_REG_DEC_TIMEOUT_E(1) |
 223               VDPU_REG_DEC_CLK_GATE_E(1);
 224         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
 225
 226         reg = VDPU_REG_PIC_MB_WIDTH(MPEG2_MB_WIDTH(ctx->dst_fmt.width)) |
 227               VDPU_REG_PIC_MB_HEIGHT_P(MPEG2_MB_HEIGHT(ctx->dst_fmt.height)) |
 228               VDPU_REG_ALT_SCAN_E(picture->alternate_scan) |
 229               VDPU_REG_TOPFIELDFIRST_E(picture->top_field_first);
 230         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));
 231
 232         reg = VDPU_REG_STRM_START_BIT(slice_params->data_bit_offset) |
 233               VDPU_REG_QSCALE_TYPE(picture->q_scale_type) |
 234               VDPU_REG_CON_MV_E(picture->concealment_motion_vectors) |
 235               VDPU_REG_INTRA_DC_PREC(picture->intra_dc_precision) |
 236               VDPU_REG_INTRA_VLC_TAB(picture->intra_vlc_format) |
 237               VDPU_REG_FRAME_PRED_DCT(picture->frame_pred_frame_dct);
 238         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));
 239
 240         reg = VDPU_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) |
 241               VDPU_REG_FCODE_FWD_HOR(picture->f_code[0][0]) |
 242               VDPU_REG_FCODE_FWD_VER(picture->f_code[0][1]) |
 243               VDPU_REG_FCODE_BWD_HOR(picture->f_code[1][0]) |
 244               VDPU_REG_FCODE_BWD_VER(picture->f_code[1][1]) |
 245               VDPU_REG_MV_ACCURACY_FWD(1) |
 246               VDPU_REG_MV_ACCURACY_BWD(1);
 247         vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));
 248
 249         rk3399_vpu_mpeg2_dec_set_quantization(vpu, ctx);
 250
 251         rk3399_vpu_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
 252                                          &dst_buf->vb2_buf,
 253                                          sequence, picture, slice_params);
 254
 255         /* Kick the watchdog and start decoding */
 256         hantro_finish_run(ctx);
 257
 258         reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
 259         vdpu_write(vpu, reg, VDPU_SWREG(57));
 260 }