4 * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
6 * I modified this file from the plx9060.h header for the
7 * wanXL device driver in the linux kernel,
8 * for the register offsets and bit definitions. Made minor modifications,
9 * added plx9080 registers and
10 * stripped out stuff that was specifically for the wanXL driver.
11 * Note: I've only made sure the definitions are correct as far
12 * as I make use of them. There are still various plx9060-isms
13 * left in this header file.
15 ********************************************************************
17 * Copyright (C) 1999 RG Studio s.c.
18 * Written by Krzysztof Halasa <khc@rgstudio.com.pl>
20 * Portions (C) SBE Inc., used by permission.
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
28 #ifndef __COMEDI_PLX9080_H
29 #define __COMEDI_PLX9080_H
31 /* descriptor block used for chained dma transfers */
33 __le32 pci_start_addr;
34 __le32 local_start_addr;
35 /* transfer_size is in bytes, only first 23 bits of register are used */
38 * address of next descriptor (quad word aligned), plus some
39 * additional bits (see PLX_REG_DMADPR)
44 /**********************************************************************
45 ** Register Offsets and Bit Definitions
47 ** Note: All offsets zero relative. IE. Some standard base address
48 ** must be added to the Register Number to properly access the register.
50 **********************************************************************/
52 /* Local Address Space 0 Range Register */
53 #define PLX_REG_LAS0RR 0x0000
54 /* Local Address Space 1 Range Register */
55 #define PLX_REG_LAS1RR 0x00f0
57 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
58 #define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */
59 #define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */
60 #define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */
61 #define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
62 #define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
63 /* bits that specify range for memory space decode bits */
64 #define PLX_LASRR_MEM_MASK GENMASK(31, 4)
65 /* bits that specify range for i/o space decode bits */
66 #define PLX_LASRR_IO_MASK GENMASK(31, 2)
68 /* Local Address Space 0 Local Base Address (Remap) Register */
69 #define PLX_REG_LAS0BA 0x0004
70 /* Local Address Space 1 Local Base Address (Remap) Register */
71 #define PLX_REG_LAS1BA 0x00f4
73 #define PLX_LASBA_EN BIT(0) /* Enable slave decode */
74 /* bits that specify local base address for memory space */
75 #define PLX_LASBA_MEM_MASK GENMASK(31, 4)
76 /* bits that specify local base address for i/o space */
77 #define PLX_LASBA_IO_MASK GENMASK(31, 2)
79 /* Mode/Arbitration Register */
80 #define PLX_REG_MARBR 0x0008
81 /* DMA Arbitration Register (alias of MARBR). */
82 #define PLX_REG_DMAARB 0x00ac
84 /* Local Bus Latency Timer */
85 #define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff))
86 #define PLX_MARBR_LT_MASK GENMASK(7, 0)
87 #define PLX_MARBR_LT_SHIFT 0
88 /* Local Bus Pause Timer */
89 #define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff))
90 #define PLX_MARBR_PT_MASK GENMASK(15, 8)
91 #define PLX_MARBR_PT_SHIFT 8
92 /* Local Bus Latency Timer Enable */
93 #define PLX_MARBR_LTEN BIT(16)
94 /* Local Bus Pause Timer Enable */
95 #define PLX_MARBR_PTEN BIT(17)
96 /* Local Bus BREQ Enable */
97 #define PLX_MARBR_BREQEN BIT(18)
98 /* DMA Channel Priority */
99 #define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */
100 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
101 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
102 #define PLX_MARBR_PRIO_MASK GENMASK(20, 19)
103 /* Local Bus Direct Slave Give Up Bus Mode */
104 #define PLX_MARBR_DSGUBM BIT(21)
105 /* Direct Slace LLOCKo# Enable */
106 #define PLX_MARBR_DSLLOCKOEN BIT(22)
107 /* PCI Request Mode */
108 #define PLX_MARBR_PCIREQM BIT(23)
109 /* PCI Specification v2.1 Mode */
110 #define PLX_MARBR_PCIV21M BIT(24)
111 /* PCI Read No Write Mode */
112 #define PLX_MARBR_PCIRNWM BIT(25)
113 /* PCI Read with Write Flush Mode */
114 #define PLX_MARBR_PCIRWFM BIT(26)
115 /* Gate Local Bus Latency Timer with BREQ */
116 #define PLX_MARBR_GLTBREQ BIT(27)
117 /* PCI Read No Flush Mode */
118 #define PLX_MARBR_PCIRNFM BIT(28)
120 * Make reads from PCI Configuration register 0 return Subsystem ID and
121 * Subsystem Vendor ID instead of Device ID and Vendor ID
123 #define PLX_MARBR_SUBSYSIDS BIT(29)
125 /* Big/Little Endian Descriptor Register */
126 #define PLX_REG_BIGEND 0x000c
128 /* Configuration Register Big Endian Mode */
129 #define PLX_BIGEND_CONFIG BIT(0)
130 /* Direct Master Big Endian Mode */
131 #define PLX_BIGEND_DM BIT(1)
132 /* Direct Slave Address Space 0 Big Endian Mode */
133 #define PLX_BIGEND_DSAS0 BIT(2)
134 /* Direct Slave Expansion ROM Big Endian Mode */
135 #define PLX_BIGEND_EROM BIT(3)
136 /* Big Endian Byte Lane Mode - use most significant byte lanes */
137 #define PLX_BIGEND_BEBLM BIT(4)
138 /* Direct Slave Address Space 1 Big Endian Mode */
139 #define PLX_BIGEND_DSAS1 BIT(5)
140 /* DMA Channel 1 Big Endian Mode */
141 #define PLX_BIGEND_DMA1 BIT(6)
142 /* DMA Channel 0 Big Endian Mode */
143 #define PLX_BIGEND_DMA0 BIT(7)
144 /* DMA Channel N Big Endian Mode (N <= 1) */
145 #define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
148 ** Note: The Expansion ROM stuff is only relevant to the PC environment.
149 ** This expansion ROM code is executed by the host CPU at boot time.
150 ** For this reason no bit definitions are provided here.
152 /* Expansion ROM Range Register */
153 #define PLX_REG_EROMRR 0x0010
154 /* Expansion ROM Local Base Address (Remap) Register */
155 #define PLX_REG_EROMBA 0x0014
157 /* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */
158 #define PLX_REG_LBRD0 0x0018
159 /* Local Address Space 1 Bus Region Descriptor Register */
160 #define PLX_REG_LBRD1 0x00f8
162 /* Memory Space Local Bus Width */
163 #define PLX_LBRD_MSWIDTH8 (BIT(0) * 0) /* 8 bits wide */
164 #define PLX_LBRD_MSWIDTH16 (BIT(0) * 1) /* 16 bits wide */
165 #define PLX_LBRD_MSWIDTH32 (BIT(0) * 2) /* 32 bits wide */
166 #define PLX_LBRD_MSWIDTH32A (BIT(0) * 3) /* 32 bits wide */
167 #define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0)
168 #define PLX_LBRD_MSWIDTH_SHIFT 0
169 /* Memory Space Internal Wait States */
170 #define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf))
171 #define PLX_LBRD_MSIWS_MASK GENMASK(5, 2)
172 #define PLX_LBRD_MSIWS_SHIFT 2
173 /* Memory Space Ready Input Enable */
174 #define PLX_LBRD_MSREADYIEN BIT(6)
175 /* Memory Space BTERM# Input Enable */
176 #define PLX_LBRD_MSBTERMIEN BIT(7)
177 /* Memory Space 0 Prefetch Disable (LBRD0 only) */
178 #define PLX_LBRD0_MSPREDIS BIT(8)
179 /* Memory Space 1 Burst Enable (LBRD1 only) */
180 #define PLX_LBRD1_MSBURSTEN BIT(8)
181 /* Expansion ROM Space Prefetch Disable (LBRD0 only) */
182 #define PLX_LBRD0_EROMPREDIS BIT(9)
183 /* Memory Space 1 Prefetch Disable (LBRD1 only) */
184 #define PLX_LBRD1_MSPREDIS BIT(9)
185 /* Read Prefetch Count Enable */
186 #define PLX_LBRD_RPFCOUNTEN BIT(10)
187 /* Prefetch Counter */
188 #define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf))
189 #define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11)
190 #define PLX_LBRD_PFCOUNT_SHIFT 11
191 /* Expansion ROM Space Local Bus Width (LBRD0 only) */
192 #define PLX_LBRD0_EROMWIDTH8 (BIT(16) * 0) /* 8 bits wide */
193 #define PLX_LBRD0_EROMWIDTH16 (BIT(16) * 1) /* 16 bits wide */
194 #define PLX_LBRD0_EROMWIDTH32 (BIT(16) * 2) /* 32 bits wide */
195 #define PLX_LBRD0_EROMWIDTH32A (BIT(16) * 3) /* 32 bits wide */
196 #define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16)
197 #define PLX_LBRD0_EROMWIDTH_SHIFT 16
198 /* Expansion ROM Space Internal Wait States (LBRD0 only) */
199 #define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf))
200 #define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18)
201 #define PLX_LBRD0_EROMIWS_SHIFT 18
202 /* Expansion ROM Space Ready Input Enable (LBDR0 only) */
203 #define PLX_LBRD0_EROMREADYIEN BIT(22)
204 /* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */
205 #define PLX_LBRD0_EROMBTERMIEN BIT(23)
206 /* Memory Space 0 Burst Enable (LBRD0 only) */
207 #define PLX_LBRD0_MSBURSTEN BIT(24)
208 /* Extra Long Load From Serial EEPROM (LBRD0 only) */
209 #define PLX_LBRD0_EELONGLOAD BIT(25)
210 /* Expansion ROM Space Burst Enable (LBRD0 only) */
211 #define PLX_LBRD0_EROMBURSTEN BIT(26)
212 /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
213 #define PLX_LBRD0_DSWMTRDY BIT(27)
214 /* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */
215 #define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF))
216 #define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28)
217 #define PLX_LBRD0_TRDELAY_SHIFT 28
219 /* Local Range Register for Direct Master to PCI */
220 #define PLX_REG_DMRR 0x001c
222 /* Local Bus Base Address Register for Direct Master to PCI Memory */
223 #define PLX_REG_DMLBAM 0x0020
225 /* Local Base Address Register for Direct Master to PCI IO/CFG */
226 #define PLX_REG_DMLBAI 0x0024
228 /* PCI Base Address (Remap) Register for Direct Master to PCI Memory */
229 #define PLX_REG_DMPBAM 0x0028
231 /* Direct Master Memory Access Enable */
232 #define PLX_DMPBAM_MEMACCEN BIT(0)
233 /* Direct Master I/O Access Enable */
234 #define PLX_DMPBAM_IOACCEN BIT(1)
235 /* LLOCK# Input Enable */
236 #define PLX_DMPBAM_LLOCKIEN BIT(2)
237 /* Direct Master Read Prefetch Size Control (bits 12, 3) */
238 #define PLX_DMPBAM_RPSIZECONT ((BIT(12) * 0) | (BIT(3) * 0))
239 #define PLX_DMPBAM_RPSIZE4 ((BIT(12) * 0) | (BIT(3) * 1))
240 #define PLX_DMPBAM_RPSIZE8 ((BIT(12) * 1) | (BIT(3) * 0))
241 #define PLX_DMPBAM_RPSIZE16 ((BIT(12) * 1) | (BIT(3) * 1))
242 #define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3))
243 /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
244 #define PLX_DMPBAM_RMIRDY BIT(4)
245 /* Programmable Almost Full Level (bits 10, 8:5) */
246 #define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \
247 (BIT(5) * ((x) & 0xf)))
248 #define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \
249 (GENMASK(8, 5) & (v))) >> 5)
250 #define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5))
251 /* Write And Invalidate Mode */
252 #define PLX_DMPBAM_WIM BIT(9)
253 /* Direct Master Prefetch Limit */
254 #define PLX_DBPBAM_PFLIMIT BIT(11)
255 /* I/O Remap Select */
256 #define PLX_DMPBAM_IOREMAPSEL BIT(13)
257 /* Direct Master Write Delay */
258 #define PLX_DMPBAM_WDELAYNONE (BIT(14) * 0)
259 #define PLX_DMPBAM_WDELAY4 (BIT(14) * 1)
260 #define PLX_DMPBAM_WDELAY8 (BIT(14) * 2)
261 #define PLX_DMPBAM_WDELAY16 (BIT(14) * 3)
262 #define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14)
263 /* Remap of Local-to-PCI Space Into PCI Address Space */
264 #define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16)
266 /* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
267 #define PLX_REG_DMCFGA 0x002c
269 /* Congiguration Type */
270 #define PLX_DMCFGA_TYPE0 (BIT(0) * 0)
271 #define PLX_DMCFGA_TYPE1 (BIT(0) * 1)
272 #define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0)
273 /* Register Number */
274 #define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f))
275 #define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2)
276 #define PLX_DMCFGA_REGNUM_SHIFT 2
277 /* Function Number */
278 #define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7))
279 #define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8)
280 #define PLX_DMCFGA_FUNCNUM_SHIFT 8
282 #define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f))
283 #define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11)
284 #define PLX_DMCFGA_DEVNUM_SHIFT 11
286 #define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff))
287 #define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16)
288 #define PLX_DMCFGA_BUSNUM_SHIFT 16
289 /* Configuration Enable */
290 #define PLX_DMCFGA_CONFIGEN BIT(31)
293 * Mailbox Register N (N <= 7)
295 * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0
296 * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced
297 * by the Outbound Queue Port. However, Mailbox Register 0 and 1 are always
298 * accessible at alternative offsets if the I2O feature is enabled.
300 #define PLX_REG_MBOX(n) (0x0040 + (n) * 4)
301 #define PLX_REG_MBOX0 PLX_REG_MBOX(0)
302 #define PLX_REG_MBOX1 PLX_REG_MBOX(1)
303 #define PLX_REG_MBOX2 PLX_REG_MBOX(2)
304 #define PLX_REG_MBOX3 PLX_REG_MBOX(3)
305 #define PLX_REG_MBOX4 PLX_REG_MBOX(4)
306 #define PLX_REG_MBOX5 PLX_REG_MBOX(5)
307 #define PLX_REG_MBOX6 PLX_REG_MBOX(6)
308 #define PLX_REG_MBOX7 PLX_REG_MBOX(7)
310 /* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */
311 #define PLX_REG_ALT_MBOX(n) ((n) < 2 ? 0x0078 + (n) * 4 : PLX_REG_MBOX(n))
312 #define PLX_REG_ALT_MBOX0 PLX_REG_ALT_MBOX(0)
313 #define PLX_REG_ALT_MBOX1 PLX_REG_ALT_MBOX(1)
315 /* PCI-to-Local Doorbell Register */
316 #define PLX_REG_P2LDBELL 0x0060
318 /* Local-to-PCI Doorbell Register */
319 #define PLX_REG_L2PDBELL 0x0064
321 /* Interrupt Control/Status Register */
322 #define PLX_REG_INTCSR 0x0068
324 /* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */
325 #define PLX_INTCSR_LSEABORTEN BIT(0)
326 /* Enable Local Bus LSERR# when PCI parity error occurs */
327 #define PLX_INTCSR_LSEPARITYEN BIT(1)
328 /* Generate PCI Bus SERR# when set to 1 */
329 #define PLX_INTCSR_GENSERR BIT(2)
330 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
331 #define PLX_INTCSR_MBIEN BIT(3)
332 /* PCI Interrupt Enable */
333 #define PLX_INTCSR_PIEN BIT(8)
334 /* PCI Doorbell Interrupt Enable */
335 #define PLX_INTCSR_PDBIEN BIT(9)
336 /* PCI Abort Interrupt Enable */
337 #define PLX_INTCSR_PABORTIEN BIT(10)
338 /* PCI Local Interrupt Enable */
339 #define PLX_INTCSR_PLIEN BIT(11)
340 /* Retry Abort Enable (for diagnostic purposes only) */
341 #define PLX_INTCSR_RAEN BIT(12)
342 /* PCI Doorbell Interrupt Active (read-only) */
343 #define PLX_INTCSR_PDBIA BIT(13)
344 /* PCI Abort Interrupt Active (read-only) */
345 #define PLX_INTCSR_PABORTIA BIT(14)
346 /* Local Interrupt (LINTi#) Active (read-only) */
347 #define PLX_INTCSR_PLIA BIT(15)
348 /* Local Interrupt Output (LINTo#) Enable */
349 #define PLX_INTCSR_LIOEN BIT(16)
350 /* Local Doorbell Interrupt Enable */
351 #define PLX_INTCSR_LDBIEN BIT(17)
352 /* DMA Channel 0 Interrupt Enable */
353 #define PLX_INTCSR_DMA0IEN BIT(18)
354 /* DMA Channel 1 Interrupt Enable */
355 #define PLX_INTCSR_DMA1IEN BIT(19)
356 /* DMA Channel N Interrupt Enable (N <= 1) */
357 #define PLX_INTCSR_DMAIEN(n) ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN)
358 /* Local Doorbell Interrupt Active (read-only) */
359 #define PLX_INTCSR_LDBIA BIT(20)
360 /* DMA Channel 0 Interrupt Active (read-only) */
361 #define PLX_INTCSR_DMA0IA BIT(21)
362 /* DMA Channel 1 Interrupt Active (read-only) */
363 #define PLX_INTCSR_DMA1IA BIT(22)
364 /* DMA Channel N Interrupt Active (N <= 1) (read-only) */
365 #define PLX_INTCSR_DMAIA(n) ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA)
366 /* BIST Interrupt Active (read-only) */
367 #define PLX_INTCSR_BISTIA BIT(23)
368 /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
369 #define PLX_INTCSR_ABNOTDM BIT(24)
370 /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
371 #define PLX_INTCSR_ABNOTDMA0 BIT(25)
372 /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
373 #define PLX_INTCSR_ABNOTDMA1 BIT(26)
374 /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
375 #define PLX_INTCSR_ABNOTDMA(n) ((n) ? PLX_INTCSR_ABNOTDMA1 \
376 : PLX_INTCSR_ABNOTDMA0)
377 /* Target Abort Not Generated After 256 Master Retries (read-only) */
378 #define PLX_INTCSR_ABNOTRETRY BIT(27)
379 /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
380 #define PLX_INTCSR_MB0IA BIT(28)
381 /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
382 #define PLX_INTCSR_MB1IA BIT(29)
383 /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
384 #define PLX_INTCSR_MB2IA BIT(30)
385 /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
386 #define PLX_INTCSR_MB3IA BIT(31)
387 /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
388 #define PLX_INTCSR_MBIA(n) BIT(28 + (n))
391 * Serial EEPROM Control, PCI Command Codes, User I/O Control,
392 * Init Control Register
394 #define PLX_REG_CNTRL 0x006c
396 /* PCI Read Command Code For DMA */
397 #define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf))
398 #define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0)
399 #define PLX_CNTRL_CCRDMA_SHIFT 0
400 #define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14) /* value after reset */
401 /* PCI Write Command Code For DMA 0 */
402 #define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf))
403 #define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4)
404 #define PLX_CNTRL_CCWDMA_SHIFT 4
405 #define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7) /* value after reset */
406 /* PCI Memory Read Command Code For Direct Master */
407 #define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf))
408 #define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8)
409 #define PLX_CNTRL_CCRDM_SHIFT 8
410 #define PLX_CNTRL_CCRDM_NORMAL PLX_CNTRL_CCRDM(6) /* value after reset */
411 /* PCI Memory Write Command Code For Direct Master */
412 #define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf))
413 #define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12)
414 #define PLX_CNTRL_CCWDM_SHIFT 12
415 #define PLX_CNTRL_CCWDM_NORMAL PLX_CNTRL_CCWDM(7) /* value after reset */
416 /* General Purpose Output (USERO) */
417 #define PLX_CNTRL_USERO BIT(16)
418 /* General Purpose Input (USERI) (read-only) */
419 #define PLX_CNTRL_USERI BIT(17)
420 /* Serial EEPROM Clock Output (EESK) */
421 #define PLX_CNTRL_EESK BIT(24)
422 /* Serial EEPROM Chip Select Output (EECS) */
423 #define PLX_CNTRL_EECS BIT(25)
424 /* Serial EEPROM Data Write Bit (EEDI (sic)) */
425 #define PLX_CNTRL_EEWB BIT(26)
426 /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
427 #define PLX_CNTRL_EERB BIT(27)
428 /* Serial EEPROM Present (read-only) */
429 #define PLX_CNTRL_EEPRESENT BIT(28)
430 /* Reload Configuration Registers from EEPROM */
431 #define PLX_CNTRL_EERELOAD BIT(29)
432 /* PCI Adapter Software Reset (asserts LRESETo#) */
433 #define PLX_CNTRL_RESET BIT(30)
434 /* Local Init Status (read-only) */
435 #define PLX_CNTRL_INITDONE BIT(31)
437 * Combined command code stuff for convenience.
439 #define PLX_CNTRL_CC_MASK \
440 (PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \
441 PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK)
442 #define PLX_CNTRL_CC_NORMAL \
443 (PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \
444 PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */
446 /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
447 #define PLX_REG_PCIHIDR 0x0070
449 /* Hard-coded ID for PLX PCI 9080 */
450 #define PLX_PCIHIDR_9080 0x908010b5
452 /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
453 #define PLX_REG_PCIHREV 0x0074
455 /* DMA Channel N Mode Register (N <= 1) */
456 #define PLX_REG_DMAMODE(n) ((n) ? PLX_REG_DMAMODE1 : PLX_REG_DMAMODE0)
457 #define PLX_REG_DMAMODE0 0x0080
458 #define PLX_REG_DMAMODE1 0x0094
460 /* Local Bus Width */
461 #define PLX_DMAMODE_WIDTH8 (BIT(0) * 0) /* 8 bits wide */
462 #define PLX_DMAMODE_WIDTH16 (BIT(0) * 1) /* 16 bits wide */
463 #define PLX_DMAMODE_WIDTH32 (BIT(0) * 2) /* 32 bits wide */
464 #define PLX_DMAMODE_WIDTH32A (BIT(0) * 3) /* 32 bits wide */
465 #define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0)
466 #define PLX_DMAMODE_WIDTH_SHIFT 0
467 /* Internal Wait States */
468 #define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf))
469 #define PLX_DMAMODE_IWS_MASK GENMASK(5, 2)
470 #define PLX_DMAMODE_SHIFT 2
471 /* Ready Input Enable */
472 #define PLX_DMAMODE_READYIEN BIT(6)
473 /* BTERM# Input Enable */
474 #define PLX_DMAMODE_BTERMIEN BIT(7)
475 /* Local Burst Enable */
476 #define PLX_DMAMODE_BURSTEN BIT(8)
477 /* Chaining Enable */
478 #define PLX_DMAMODE_CHAINEN BIT(9)
479 /* Done Interrupt Enable */
480 #define PLX_DMAMODE_DONEIEN BIT(10)
481 /* Hold Local Address Constant */
482 #define PLX_DMAMODE_LACONST BIT(11)
484 #define PLX_DMAMODE_DEMAND BIT(12)
485 /* Write And Invalidate Mode */
486 #define PLX_DMAMODE_WINVALIDATE BIT(13)
487 /* DMA EOT Enable - enables EOT0# or EOT1# input pin */
488 #define PLX_DMAMODE_EOTEN BIT(14)
489 /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
490 #define PLX_DMAMODE_STOP BIT(15)
491 /* DMA Clear Count Mode - count in descriptor cleared on completion */
492 #define PLX_DMAMODE_CLRCOUNT BIT(16)
493 /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
494 #define PLX_DMAMODE_INTRPCI BIT(17)
496 /* DMA Channel N PCI Address Register (N <= 1) */
497 #define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0)
498 #define PLX_REG_DMAPADR0 0x0084
499 #define PLX_REG_DMAPADR1 0x0098
501 /* DMA Channel N Local Address Register (N <= 1) */
502 #define PLX_REG_DMALADR(n) ((n) ? PLX_REG_DMALADR1 : PLX_REG_DMALADR0)
503 #define PLX_REG_DMALADR0 0x0088
504 #define PLX_REG_DMALADR1 0x009c
506 /* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */
507 #define PLX_REG_DMASIZ(n) ((n) ? PLX_REG_DMASIZ1 : PLX_REG_DMASIZ0)
508 #define PLX_REG_DMASIZ0 0x008c
509 #define PLX_REG_DMASIZ1 0x00a0
511 /* DMA Channel N Descriptor Pointer Register (N <= 1) */
512 #define PLX_REG_DMADPR(n) ((n) ? PLX_REG_DMADPR1 : PLX_REG_DMADPR0)
513 #define PLX_REG_DMADPR0 0x0090
514 #define PLX_REG_DMADPR1 0x00a4
516 /* Descriptor Located In PCI Address Space (not local address space) */
517 #define PLX_DMADPR_DESCPCI BIT(0)
519 #define PLX_DMADPR_CHAINEND BIT(1)
520 /* Interrupt After Terminal Count */
521 #define PLX_DMADPR_TCINTR BIT(2)
522 /* Direction Of Transfer Local Bus To PCI (not PCI to local) */
523 #define PLX_DMADPR_XFERL2P BIT(3)
524 /* Next Descriptor Address Bits 31:4 (16 byte boundary) */
525 #define PLX_DMADPR_NEXT_MASK GENMASK(31, 4)
527 /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
528 #define PLX_REG_DMACSR(n) ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0)
529 #define PLX_REG_DMACSR0 0x00a8
530 #define PLX_REG_DMACSR1 0x00a9
533 #define PLX_DMACSR_ENABLE BIT(0)
534 /* Channel Start - write 1 to start transfer (write-only) */
535 #define PLX_DMACSR_START BIT(1)
536 /* Channel Abort - write 1 to abort transfer (write-only) */
537 #define PLX_DMACSR_ABORT BIT(2)
538 /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
539 #define PLX_DMACSR_CLEARINTR BIT(3)
540 /* Channel Done - transfer complete/inactive (read-only) */
541 #define PLX_DMACSR_DONE BIT(4)
543 /* DMA Threshold Register */
544 #define PLX_REG_DMATHR 0x00b0
547 * DMA Threshold constraints:
548 * (C0PLAF + 1) + (C0PLAE + 1) <= 32
549 * (C0LPAF + 1) + (C0LPAE + 1) <= 32
550 * (C1PLAF + 1) + (C1PLAE + 1) <= 16
551 * (C1LPAF + 1) + (C1LPAE + 1) <= 16
554 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
555 #define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf))
556 #define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0)
557 #define PLX_DMATHR_C0PLAF_SHIFT 0
558 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
559 #define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf))
560 #define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4)
561 #define PLX_DMATHR_C0LPAE_SHIFT 4
562 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
563 #define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf))
564 #define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8)
565 #define PLX_DMATHR_C0LPAF_SHIFT 8
566 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
567 #define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf))
568 #define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12)
569 #define PLX_DMATHR_C0PLAE_SHIFT 12
570 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
571 #define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf))
572 #define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16)
573 #define PLX_DMATHR_C1PLAF_SHIFT 16
574 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
575 #define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf))
576 #define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20)
577 #define PLX_DMATHR_C1LPAE_SHIFT 20
578 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
579 #define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf))
580 #define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24)
581 #define PLX_DMATHR_C1LPAF_SHIFT 24
582 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
583 #define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf))
584 #define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28)
585 #define PLX_DMATHR_C1PLAE_SHIFT 28
588 * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR,
589 * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted.
590 * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of
591 * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and
592 * MBOX1 are accessible via alternative offsets.
595 /* Queue Status/Control Register */
596 #define PLX_REG_QSR 0x00e8
598 /* Value of QSR after reset - disables I2O feature completely. */
599 #define PLX_QSR_VALUE_AFTER_RESET 0x00000050
602 * Accesses near the end of memory can cause the PLX chip
603 * to pre-fetch data off of end-of-ram. Limit the size of
604 * memory so host-side accesses cannot occur.
607 #define PLX_PREFETCH 32
609 static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
611 void __iomem *dma_cs_addr;
613 const int timeout = 10000;
616 dma_cs_addr = iobase + PLX_REG_DMACSR(channel);
618 /* abort dma transfer if necessary */
619 dma_status = readb(dma_cs_addr);
620 if ((dma_status & PLX_DMACSR_ENABLE) == 0)
623 /* wait to make sure done bit is zero */
624 for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) {
626 dma_status = readb(dma_cs_addr);
631 /* disable and abort channel */
632 writeb(PLX_DMACSR_ABORT, dma_cs_addr);
633 /* wait for dma done bit */
634 dma_status = readb(dma_cs_addr);
635 for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) {
637 dma_status = readb(dma_cs_addr);
645 #endif /* __COMEDI_PLX9080_H */