drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <addy.ke@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/scatterlist.h>
  25
  26 #define DRIVER_NAME "rockchip-spi"
  27
  28 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
  29                 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
  30 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
  31                 writel_relaxed(readl_relaxed(reg) | (bits), reg)
  32
  33 /* SPI register offsets */
  34 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  35 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  36 #define ROCKCHIP_SPI_SSIENR                     0x0008
  37 #define ROCKCHIP_SPI_SER                        0x000c
  38 #define ROCKCHIP_SPI_BAUDR                      0x0010
  39 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  40 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  41 #define ROCKCHIP_SPI_TXFLR                      0x001c
  42 #define ROCKCHIP_SPI_RXFLR                      0x0020
  43 #define ROCKCHIP_SPI_SR                         0x0024
  44 #define ROCKCHIP_SPI_IPR                        0x0028
  45 #define ROCKCHIP_SPI_IMR                        0x002c
  46 #define ROCKCHIP_SPI_ISR                        0x0030
  47 #define ROCKCHIP_SPI_RISR                       0x0034
  48 #define ROCKCHIP_SPI_ICR                        0x0038
  49 #define ROCKCHIP_SPI_DMACR                      0x003c
  50 #define ROCKCHIP_SPI_DMATDLR            0x0040
  51 #define ROCKCHIP_SPI_DMARDLR            0x0044
  52 #define ROCKCHIP_SPI_TXDR                       0x0400
  53 #define ROCKCHIP_SPI_RXDR                       0x0800
  54
  55 /* Bit fields in CTRLR0 */
  56 #define CR0_DFS_OFFSET                          0
  57
  58 #define CR0_CFS_OFFSET                          2
  59
  60 #define CR0_SCPH_OFFSET                         6
  61
  62 #define CR0_SCPOL_OFFSET                        7
  63
  64 #define CR0_CSM_OFFSET                          8
  65 #define CR0_CSM_KEEP                            0x0
  66 /* ss_n be high for half sclk_out cycles */
  67 #define CR0_CSM_HALF                            0X1
  68 /* ss_n be high for one sclk_out cycle */
  69 #define CR0_CSM_ONE                                     0x2
  70
  71 /* ss_n to sclk_out delay */
  72 #define CR0_SSD_OFFSET                          10
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is half sclk_out cycles
  76  */
  77 #define CR0_SSD_HALF                            0x0
  78 /*
  79  * The period between ss_n active and
  80  * sclk_out active is one sclk_out cycle
  81  */
  82 #define CR0_SSD_ONE                                     0x1
  83
  84 #define CR0_EM_OFFSET                           11
  85 #define CR0_EM_LITTLE                           0x0
  86 #define CR0_EM_BIG                                      0x1
  87
  88 #define CR0_FBM_OFFSET                          12
  89 #define CR0_FBM_MSB                                     0x0
  90 #define CR0_FBM_LSB                                     0x1
  91
  92 #define CR0_BHT_OFFSET                          13
  93 #define CR0_BHT_16BIT                           0x0
  94 #define CR0_BHT_8BIT                            0x1
  95
  96 #define CR0_RSD_OFFSET                          14
  97
  98 #define CR0_FRF_OFFSET                          16
  99 #define CR0_FRF_SPI                                     0x0
 100 #define CR0_FRF_SSP                                     0x1
 101 #define CR0_FRF_MICROWIRE                       0x2
 102
 103 #define CR0_XFM_OFFSET                          18
 104 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 105 #define CR0_XFM_TR                                      0x0
 106 #define CR0_XFM_TO                                      0x1
 107 #define CR0_XFM_RO                                      0x2
 108
 109 #define CR0_OPM_OFFSET                          20
 110 #define CR0_OPM_MASTER                          0x0
 111 #define CR0_OPM_SLAVE                           0x1
 112
 113 #define CR0_MTM_OFFSET                          0x21
 114
 115 /* Bit fields in SER, 2bit */
 116 #define SER_MASK                                        0x3
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 #define RXBUSY                                          (1 << 0)
 146 #define TXBUSY                                          (1 << 1)
 147
 148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 149 #define MAX_SCLK_OUT            50000000
 150
 151 /*
 152  * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
 153  * the controller seems to hang when given 0x10000, so stick with this for now.
 154  */
 155 #define ROCKCHIP_SPI_MAX_TRANLEN                0xffff
 156
 157 #define ROCKCHIP_SPI_MAX_CS_NUM                 2
 158
 159 enum rockchip_ssi_type {
 160         SSI_MOTO_SPI = 0,
 161         SSI_TI_SSP,
 162         SSI_NS_MICROWIRE,
 163 };
 164
 165 struct rockchip_spi_dma_data {
 166         struct dma_chan *ch;
 167         dma_addr_t addr;
 168 };
 169
 170 struct rockchip_spi {
 171         struct device *dev;
 172         struct spi_master *master;
 173
 174         struct clk *spiclk;
 175         struct clk *apb_pclk;
 176
 177         void __iomem *regs;
 178         /*depth of the FIFO buffer */
 179         u32 fifo_len;
 180         /* max bus freq supported */
 181         u32 max_freq;
 182         /* supported slave numbers */
 183         enum rockchip_ssi_type type;
 184
 185         u16 mode;
 186         u8 tmode;
 187         u8 bpw;
 188         u8 n_bytes;
 189         u32 rsd_nsecs;
 190         unsigned len;
 191         u32 speed;
 192
 193         const void *tx;
 194         const void *tx_end;
 195         void *rx;
 196         void *rx_end;
 197
 198         u32 state;
 199         /* protect state */
 200         spinlock_t lock;
 201
 202         bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
 203
 204         bool use_dma;
 205         struct sg_table tx_sg;
 206         struct sg_table rx_sg;
 207         struct rockchip_spi_dma_data dma_rx;
 208         struct rockchip_spi_dma_data dma_tx;
 209 };
 210
 211 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
 212 {
 213         writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
 214 }
 215
 216 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
 217 {
 218         writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
 219 }
 220
 221 static inline void flush_fifo(struct rockchip_spi *rs)
 222 {
 223         while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
 224                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 225 }
 226
 227 static inline void wait_for_idle(struct rockchip_spi *rs)
 228 {
 229         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 230
 231         do {
 232                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 233                         return;
 234         } while (!time_after(jiffies, timeout));
 235
 236         dev_warn(rs->dev, "spi controller is in busy state!\n");
 237 }
 238
 239 static u32 get_fifo_len(struct rockchip_spi *rs)
 240 {
 241         u32 fifo;
 242
 243         for (fifo = 2; fifo < 32; fifo++) {
 244                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 245                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 246                         break;
 247         }
 248
 249         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 250
 251         return (fifo == 31) ? 0 : fifo;
 252 }
 253
 254 static inline u32 tx_max(struct rockchip_spi *rs)
 255 {
 256         u32 tx_left, tx_room;
 257
 258         tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
 259         tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 260
 261         return min(tx_left, tx_room);
 262 }
 263
 264 static inline u32 rx_max(struct rockchip_spi *rs)
 265 {
 266         u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
 267         u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 268
 269         return min(rx_left, rx_room);
 270 }
 271
 272 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 273 {
 274         struct spi_master *master = spi->master;
 275         struct rockchip_spi *rs = spi_master_get_devdata(master);
 276         bool cs_asserted = !enable;
 277
 278         /* Return immediately for no-op */
 279         if (cs_asserted == rs->cs_asserted[spi->chip_select])
 280                 return;
 281
 282         if (cs_asserted) {
 283                 /* Keep things powered as long as CS is asserted */
 284                 pm_runtime_get_sync(rs->dev);
 285
 286                 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
 287                                       BIT(spi->chip_select));
 288         } else {
 289                 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
 290                                       BIT(spi->chip_select));
 291
 292                 /* Drop reference from when we first asserted CS */
 293                 pm_runtime_put(rs->dev);
 294         }
 295
 296         rs->cs_asserted[spi->chip_select] = cs_asserted;
 297 }
 298
 299 static int rockchip_spi_prepare_message(struct spi_master *master,
 300                                         struct spi_message *msg)
 301 {
 302         struct rockchip_spi *rs = spi_master_get_devdata(master);
 303         struct spi_device *spi = msg->spi;
 304
 305         rs->mode = spi->mode;
 306
 307         return 0;
 308 }
 309
 310 static void rockchip_spi_handle_err(struct spi_master *master,
 311                                     struct spi_message *msg)
 312 {
 313         unsigned long flags;
 314         struct rockchip_spi *rs = spi_master_get_devdata(master);
 315
 316         spin_lock_irqsave(&rs->lock, flags);
 317
 318         /*
 319          * For DMA mode, we need terminate DMA channel and flush
 320          * fifo for the next transfer if DMA thansfer timeout.
 321          * handle_err() was called by core if transfer failed.
 322          * Maybe it is reasonable for error handling here.
 323          */
 324         if (rs->use_dma) {
 325                 if (rs->state & RXBUSY) {
 326                         dmaengine_terminate_async(rs->dma_rx.ch);
 327                         flush_fifo(rs);
 328                 }
 329
 330                 if (rs->state & TXBUSY)
 331                         dmaengine_terminate_async(rs->dma_tx.ch);
 332         }
 333
 334         spin_unlock_irqrestore(&rs->lock, flags);
 335 }
 336
 337 static int rockchip_spi_unprepare_message(struct spi_master *master,
 338                                           struct spi_message *msg)
 339 {
 340         struct rockchip_spi *rs = spi_master_get_devdata(master);
 341
 342         spi_enable_chip(rs, 0);
 343
 344         return 0;
 345 }
 346
 347 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 348 {
 349         u32 max = tx_max(rs);
 350         u32 txw = 0;
 351
 352         while (max--) {
 353                 if (rs->n_bytes == 1)
 354                         txw = *(u8 *)(rs->tx);
 355                 else
 356                         txw = *(u16 *)(rs->tx);
 357
 358                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 359                 rs->tx += rs->n_bytes;
 360         }
 361 }
 362
 363 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 364 {
 365         u32 max = rx_max(rs);
 366         u32 rxw;
 367
 368         while (max--) {
 369                 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 370                 if (rs->n_bytes == 1)
 371                         *(u8 *)(rs->rx) = (u8)rxw;
 372                 else
 373                         *(u16 *)(rs->rx) = (u16)rxw;
 374                 rs->rx += rs->n_bytes;
 375         }
 376 }
 377
 378 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
 379 {
 380         int remain = 0;
 381
 382         spi_enable_chip(rs, 1);
 383
 384         do {
 385                 if (rs->tx) {
 386                         remain = rs->tx_end - rs->tx;
 387                         rockchip_spi_pio_writer(rs);
 388                 }
 389
 390                 if (rs->rx) {
 391                         remain = rs->rx_end - rs->rx;
 392                         rockchip_spi_pio_reader(rs);
 393                 }
 394
 395                 cpu_relax();
 396         } while (remain);
 397
 398         /* If tx, wait until the FIFO data completely. */
 399         if (rs->tx)
 400                 wait_for_idle(rs);
 401
 402         spi_enable_chip(rs, 0);
 403
 404         return 0;
 405 }
 406
 407 static void rockchip_spi_dma_rxcb(void *data)
 408 {
 409         unsigned long flags;
 410         struct rockchip_spi *rs = data;
 411
 412         spin_lock_irqsave(&rs->lock, flags);
 413
 414         rs->state &= ~RXBUSY;
 415         if (!(rs->state & TXBUSY)) {
 416                 spi_enable_chip(rs, 0);
 417                 spi_finalize_current_transfer(rs->master);
 418         }
 419
 420         spin_unlock_irqrestore(&rs->lock, flags);
 421 }
 422
 423 static void rockchip_spi_dma_txcb(void *data)
 424 {
 425         unsigned long flags;
 426         struct rockchip_spi *rs = data;
 427
 428         /* Wait until the FIFO data completely. */
 429         wait_for_idle(rs);
 430
 431         spin_lock_irqsave(&rs->lock, flags);
 432
 433         rs->state &= ~TXBUSY;
 434         if (!(rs->state & RXBUSY)) {
 435                 spi_enable_chip(rs, 0);
 436                 spi_finalize_current_transfer(rs->master);
 437         }
 438
 439         spin_unlock_irqrestore(&rs->lock, flags);
 440 }
 441
 442 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
 443 {
 444         unsigned long flags;
 445         struct dma_slave_config rxconf, txconf;
 446         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 447
 448         memset(&rxconf, 0, sizeof(rxconf));
 449         memset(&txconf, 0, sizeof(txconf));
 450
 451         spin_lock_irqsave(&rs->lock, flags);
 452         rs->state &= ~RXBUSY;
 453         rs->state &= ~TXBUSY;
 454         spin_unlock_irqrestore(&rs->lock, flags);
 455
 456         rxdesc = NULL;
 457         if (rs->rx) {
 458                 rxconf.direction = DMA_DEV_TO_MEM;
 459                 rxconf.src_addr = rs->dma_rx.addr;
 460                 rxconf.src_addr_width = rs->n_bytes;
 461                 rxconf.src_maxburst = 1;
 462                 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
 463
 464                 rxdesc = dmaengine_prep_slave_sg(
 465                                 rs->dma_rx.ch,
 466                                 rs->rx_sg.sgl, rs->rx_sg.nents,
 467                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 468                 if (!rxdesc)
 469                         return -EINVAL;
 470
 471                 rxdesc->callback = rockchip_spi_dma_rxcb;
 472                 rxdesc->callback_param = rs;
 473         }
 474
 475         txdesc = NULL;
 476         if (rs->tx) {
 477                 txconf.direction = DMA_MEM_TO_DEV;
 478                 txconf.dst_addr = rs->dma_tx.addr;
 479                 txconf.dst_addr_width = rs->n_bytes;
 480                 txconf.dst_maxburst = rs->fifo_len / 2;
 481                 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
 482
 483                 txdesc = dmaengine_prep_slave_sg(
 484                                 rs->dma_tx.ch,
 485                                 rs->tx_sg.sgl, rs->tx_sg.nents,
 486                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 487                 if (!txdesc) {
 488                         if (rxdesc)
 489                                 dmaengine_terminate_sync(rs->dma_rx.ch);
 490                         return -EINVAL;
 491                 }
 492
 493                 txdesc->callback = rockchip_spi_dma_txcb;
 494                 txdesc->callback_param = rs;
 495         }
 496
 497         /* rx must be started before tx due to spi instinct */
 498         if (rxdesc) {
 499                 spin_lock_irqsave(&rs->lock, flags);
 500                 rs->state |= RXBUSY;
 501                 spin_unlock_irqrestore(&rs->lock, flags);
 502                 dmaengine_submit(rxdesc);
 503                 dma_async_issue_pending(rs->dma_rx.ch);
 504         }
 505
 506         spi_enable_chip(rs, 1);
 507
 508         if (txdesc) {
 509                 spin_lock_irqsave(&rs->lock, flags);
 510                 rs->state |= TXBUSY;
 511                 spin_unlock_irqrestore(&rs->lock, flags);
 512                 dmaengine_submit(txdesc);
 513                 dma_async_issue_pending(rs->dma_tx.ch);
 514         }
 515
 516         /* 1 means the transfer is in progress */
 517         return 1;
 518 }
 519
 520 static void rockchip_spi_config(struct rockchip_spi *rs)
 521 {
 522         u32 div = 0;
 523         u32 dmacr = 0;
 524         int rsd = 0;
 525
 526         u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
 527                 | (CR0_SSD_ONE << CR0_SSD_OFFSET)
 528                 | (CR0_EM_BIG << CR0_EM_OFFSET);
 529
 530         cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
 531         cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
 532         cr0 |= (rs->tmode << CR0_XFM_OFFSET);
 533         cr0 |= (rs->type << CR0_FRF_OFFSET);
 534
 535         if (rs->use_dma) {
 536                 if (rs->tx)
 537                         dmacr |= TF_DMA_EN;
 538                 if (rs->rx)
 539                         dmacr |= RF_DMA_EN;
 540         }
 541
 542         if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 543                 rs->speed = MAX_SCLK_OUT;
 544
 545         /* the minimum divisor is 2 */
 546         if (rs->max_freq < 2 * rs->speed) {
 547                 clk_set_rate(rs->spiclk, 2 * rs->speed);
 548                 rs->max_freq = clk_get_rate(rs->spiclk);
 549         }
 550
 551         /* div doesn't support odd number */
 552         div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 553         div = (div + 1) & 0xfffe;
 554
 555         /* Rx sample delay is expressed in parent clock cycles (max 3) */
 556         rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 557                                 1000000000 >> 8);
 558         if (!rsd && rs->rsd_nsecs) {
 559                 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
 560                              rs->max_freq, rs->rsd_nsecs);
 561         } else if (rsd > 3) {
 562                 rsd = 3;
 563                 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 564                              rs->max_freq, rs->rsd_nsecs,
 565                              rsd * 1000000000U / rs->max_freq);
 566         }
 567         cr0 |= rsd << CR0_RSD_OFFSET;
 568
 569         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 570
 571         if (rs->n_bytes == 1)
 572                 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 573         else if (rs->n_bytes == 2)
 574                 writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 575         else
 576                 writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 577
 578         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
 579         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 580
 581         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
 582         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 583         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 584
 585         spi_set_clk(rs, div);
 586
 587         dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 588 }
 589
 590 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
 591 {
 592         return ROCKCHIP_SPI_MAX_TRANLEN;
 593 }
 594
 595 static int rockchip_spi_transfer_one(
 596                 struct spi_master *master,
 597                 struct spi_device *spi,
 598                 struct spi_transfer *xfer)
 599 {
 600         struct rockchip_spi *rs = spi_master_get_devdata(master);
 601
 602         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 603                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 604
 605         if (!xfer->tx_buf && !xfer->rx_buf) {
 606                 dev_err(rs->dev, "No buffer for transfer\n");
 607                 return -EINVAL;
 608         }
 609
 610         if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
 611                 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
 612                 return -EINVAL;
 613         }
 614
 615         rs->speed = xfer->speed_hz;
 616         rs->bpw = xfer->bits_per_word;
 617         rs->n_bytes = rs->bpw >> 3;
 618
 619         rs->tx = xfer->tx_buf;
 620         rs->tx_end = rs->tx + xfer->len;
 621         rs->rx = xfer->rx_buf;
 622         rs->rx_end = rs->rx + xfer->len;
 623         rs->len = xfer->len;
 624
 625         rs->tx_sg = xfer->tx_sg;
 626         rs->rx_sg = xfer->rx_sg;
 627
 628         if (rs->tx && rs->rx)
 629                 rs->tmode = CR0_XFM_TR;
 630         else if (rs->tx)
 631                 rs->tmode = CR0_XFM_TO;
 632         else if (rs->rx)
 633                 rs->tmode = CR0_XFM_RO;
 634
 635         /* we need prepare dma before spi was enabled */
 636         if (master->can_dma && master->can_dma(master, spi, xfer))
 637                 rs->use_dma = true;
 638         else
 639                 rs->use_dma = false;
 640
 641         rockchip_spi_config(rs);
 642
 643         if (rs->use_dma)
 644                 return rockchip_spi_prepare_dma(rs);
 645
 646         return rockchip_spi_pio_transfer(rs);
 647 }
 648
 649 static bool rockchip_spi_can_dma(struct spi_master *master,
 650                                  struct spi_device *spi,
 651                                  struct spi_transfer *xfer)
 652 {
 653         struct rockchip_spi *rs = spi_master_get_devdata(master);
 654
 655         return (xfer->len > rs->fifo_len);
 656 }
 657
 658 static int rockchip_spi_probe(struct platform_device *pdev)
 659 {
 660         int ret;
 661         struct rockchip_spi *rs;
 662         struct spi_master *master;
 663         struct resource *mem;
 664         u32 rsd_nsecs;
 665
 666         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 667         if (!master)
 668                 return -ENOMEM;
 669
 670         platform_set_drvdata(pdev, master);
 671
 672         rs = spi_master_get_devdata(master);
 673
 674         /* Get basic io resource and map it */
 675         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 676         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 677         if (IS_ERR(rs->regs)) {
 678                 ret =  PTR_ERR(rs->regs);
 679                 goto err_put_master;
 680         }
 681
 682         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 683         if (IS_ERR(rs->apb_pclk)) {
 684                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 685                 ret = PTR_ERR(rs->apb_pclk);
 686                 goto err_put_master;
 687         }
 688
 689         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 690         if (IS_ERR(rs->spiclk)) {
 691                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 692                 ret = PTR_ERR(rs->spiclk);
 693                 goto err_put_master;
 694         }
 695
 696         ret = clk_prepare_enable(rs->apb_pclk);
 697         if (ret < 0) {
 698                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 699                 goto err_put_master;
 700         }
 701
 702         ret = clk_prepare_enable(rs->spiclk);
 703         if (ret < 0) {
 704                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 705                 goto err_disable_apbclk;
 706         }
 707
 708         spi_enable_chip(rs, 0);
 709
 710         rs->type = SSI_MOTO_SPI;
 711         rs->master = master;
 712         rs->dev = &pdev->dev;
 713         rs->max_freq = clk_get_rate(rs->spiclk);
 714
 715         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 716                                   &rsd_nsecs))
 717                 rs->rsd_nsecs = rsd_nsecs;
 718
 719         rs->fifo_len = get_fifo_len(rs);
 720         if (!rs->fifo_len) {
 721                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 722                 ret = -EINVAL;
 723                 goto err_disable_spiclk;
 724         }
 725
 726         spin_lock_init(&rs->lock);
 727
 728         pm_runtime_set_active(&pdev->dev);
 729         pm_runtime_enable(&pdev->dev);
 730
 731         master->auto_runtime_pm = true;
 732         master->bus_num = pdev->id;
 733         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 734         master->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
 735         master->dev.of_node = pdev->dev.of_node;
 736         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
 737
 738         master->set_cs = rockchip_spi_set_cs;
 739         master->prepare_message = rockchip_spi_prepare_message;
 740         master->unprepare_message = rockchip_spi_unprepare_message;
 741         master->transfer_one = rockchip_spi_transfer_one;
 742         master->max_transfer_size = rockchip_spi_max_transfer_size;
 743         master->handle_err = rockchip_spi_handle_err;
 744         master->flags = SPI_MASTER_GPIO_SS;
 745
 746         rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
 747         if (IS_ERR(rs->dma_tx.ch)) {
 748                 /* Check tx to see if we need defer probing driver */
 749                 if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
 750                         ret = -EPROBE_DEFER;
 751                         goto err_disable_pm_runtime;
 752                 }
 753                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 754                 rs->dma_tx.ch = NULL;
 755         }
 756
 757         rs->dma_rx.ch = dma_request_chan(rs->dev, "rx");
 758         if (IS_ERR(rs->dma_rx.ch)) {
 759                 if (PTR_ERR(rs->dma_rx.ch) == -EPROBE_DEFER) {
 760                         ret = -EPROBE_DEFER;
 761                         goto err_free_dma_tx;
 762                 }
 763                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 764                 rs->dma_rx.ch = NULL;
 765         }
 766
 767         if (rs->dma_tx.ch && rs->dma_rx.ch) {
 768                 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
 769                 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
 770
 771                 master->can_dma = rockchip_spi_can_dma;
 772                 master->dma_tx = rs->dma_tx.ch;
 773                 master->dma_rx = rs->dma_rx.ch;
 774         }
 775
 776         ret = devm_spi_register_master(&pdev->dev, master);
 777         if (ret < 0) {
 778                 dev_err(&pdev->dev, "Failed to register master\n");
 779                 goto err_free_dma_rx;
 780         }
 781
 782         return 0;
 783
 784 err_free_dma_rx:
 785         if (rs->dma_rx.ch)
 786                 dma_release_channel(rs->dma_rx.ch);
 787 err_free_dma_tx:
 788         if (rs->dma_tx.ch)
 789                 dma_release_channel(rs->dma_tx.ch);
 790 err_disable_pm_runtime:
 791         pm_runtime_disable(&pdev->dev);
 792 err_disable_spiclk:
 793         clk_disable_unprepare(rs->spiclk);
 794 err_disable_apbclk:
 795         clk_disable_unprepare(rs->apb_pclk);
 796 err_put_master:
 797         spi_master_put(master);
 798
 799         return ret;
 800 }
 801
 802 static int rockchip_spi_remove(struct platform_device *pdev)
 803 {
 804         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 805         struct rockchip_spi *rs = spi_master_get_devdata(master);
 806
 807         pm_runtime_get_sync(&pdev->dev);
 808
 809         clk_disable_unprepare(rs->spiclk);
 810         clk_disable_unprepare(rs->apb_pclk);
 811
 812         pm_runtime_put_noidle(&pdev->dev);
 813         pm_runtime_disable(&pdev->dev);
 814         pm_runtime_set_suspended(&pdev->dev);
 815
 816         if (rs->dma_tx.ch)
 817                 dma_release_channel(rs->dma_tx.ch);
 818         if (rs->dma_rx.ch)
 819                 dma_release_channel(rs->dma_rx.ch);
 820
 821         spi_master_put(master);
 822
 823         return 0;
 824 }
 825
 826 #ifdef CONFIG_PM_SLEEP
 827 static int rockchip_spi_suspend(struct device *dev)
 828 {
 829         int ret;
 830         struct spi_master *master = dev_get_drvdata(dev);
 831         struct rockchip_spi *rs = spi_master_get_devdata(master);
 832
 833         ret = spi_master_suspend(rs->master);
 834         if (ret < 0)
 835                 return ret;
 836
 837         ret = pm_runtime_force_suspend(dev);
 838         if (ret < 0)
 839                 return ret;
 840
 841         pinctrl_pm_select_sleep_state(dev);
 842
 843         return 0;
 844 }
 845
 846 static int rockchip_spi_resume(struct device *dev)
 847 {
 848         int ret;
 849         struct spi_master *master = dev_get_drvdata(dev);
 850         struct rockchip_spi *rs = spi_master_get_devdata(master);
 851
 852         pinctrl_pm_select_default_state(dev);
 853
 854         ret = pm_runtime_force_resume(dev);
 855         if (ret < 0)
 856                 return ret;
 857
 858         ret = spi_master_resume(rs->master);
 859         if (ret < 0) {
 860                 clk_disable_unprepare(rs->spiclk);
 861                 clk_disable_unprepare(rs->apb_pclk);
 862         }
 863
 864         return 0;
 865 }
 866 #endif /* CONFIG_PM_SLEEP */
 867
 868 #ifdef CONFIG_PM
 869 static int rockchip_spi_runtime_suspend(struct device *dev)
 870 {
 871         struct spi_master *master = dev_get_drvdata(dev);
 872         struct rockchip_spi *rs = spi_master_get_devdata(master);
 873
 874         clk_disable_unprepare(rs->spiclk);
 875         clk_disable_unprepare(rs->apb_pclk);
 876
 877         return 0;
 878 }
 879
 880 static int rockchip_spi_runtime_resume(struct device *dev)
 881 {
 882         int ret;
 883         struct spi_master *master = dev_get_drvdata(dev);
 884         struct rockchip_spi *rs = spi_master_get_devdata(master);
 885
 886         ret = clk_prepare_enable(rs->apb_pclk);
 887         if (ret < 0)
 888                 return ret;
 889
 890         ret = clk_prepare_enable(rs->spiclk);
 891         if (ret < 0)
 892                 clk_disable_unprepare(rs->apb_pclk);
 893
 894         return 0;
 895 }
 896 #endif /* CONFIG_PM */
 897
 898 static const struct dev_pm_ops rockchip_spi_pm = {
 899         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 900         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 901                            rockchip_spi_runtime_resume, NULL)
 902 };
 903
 904 static const struct of_device_id rockchip_spi_dt_match[] = {
 905         { .compatible = "rockchip,rv1108-spi", },
 906         { .compatible = "rockchip,rk3036-spi", },
 907         { .compatible = "rockchip,rk3066-spi", },
 908         { .compatible = "rockchip,rk3188-spi", },
 909         { .compatible = "rockchip,rk3228-spi", },
 910         { .compatible = "rockchip,rk3288-spi", },
 911         { .compatible = "rockchip,rk3368-spi", },
 912         { .compatible = "rockchip,rk3399-spi", },
 913         { },
 914 };
 915 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 916
 917 static struct platform_driver rockchip_spi_driver = {
 918         .driver = {
 919                 .name   = DRIVER_NAME,
 920                 .pm = &rockchip_spi_pm,
 921                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 922         },
 923         .probe = rockchip_spi_probe,
 924         .remove = rockchip_spi_remove,
 925 };
 926
 927 module_platform_driver(rockchip_spi_driver);
 928
 929 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 930 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 931 MODULE_LICENSE("GPL v2");