drivers/spi/spi-qup.c

   1 /*
   2  * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License rev 2 and
   6  * only rev 2 as published by the free Software foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/dma-mapping.h>
  27
  28 #define QUP_CONFIG                      0x0000
  29 #define QUP_STATE                       0x0004
  30 #define QUP_IO_M_MODES                  0x0008
  31 #define QUP_SW_RESET                    0x000c
  32 #define QUP_OPERATIONAL                 0x0018
  33 #define QUP_ERROR_FLAGS                 0x001c
  34 #define QUP_ERROR_FLAGS_EN              0x0020
  35 #define QUP_OPERATIONAL_MASK            0x0028
  36 #define QUP_HW_VERSION                  0x0030
  37 #define QUP_MX_OUTPUT_CNT               0x0100
  38 #define QUP_OUTPUT_FIFO                 0x0110
  39 #define QUP_MX_WRITE_CNT                0x0150
  40 #define QUP_MX_INPUT_CNT                0x0200
  41 #define QUP_MX_READ_CNT                 0x0208
  42 #define QUP_INPUT_FIFO                  0x0218
  43
  44 #define SPI_CONFIG                      0x0300
  45 #define SPI_IO_CONTROL                  0x0304
  46 #define SPI_ERROR_FLAGS                 0x0308
  47 #define SPI_ERROR_FLAGS_EN              0x030c
  48
  49 /* QUP_CONFIG fields */
  50 #define QUP_CONFIG_SPI_MODE             (1 << 8)
  51 #define QUP_CONFIG_CLOCK_AUTO_GATE      BIT(13)
  52 #define QUP_CONFIG_NO_INPUT             BIT(7)
  53 #define QUP_CONFIG_NO_OUTPUT            BIT(6)
  54 #define QUP_CONFIG_N                    0x001f
  55
  56 /* QUP_STATE fields */
  57 #define QUP_STATE_VALID                 BIT(2)
  58 #define QUP_STATE_RESET                 0
  59 #define QUP_STATE_RUN                   1
  60 #define QUP_STATE_PAUSE                 3
  61 #define QUP_STATE_MASK                  3
  62 #define QUP_STATE_CLEAR                 2
  63
  64 #define QUP_HW_VERSION_2_1_1            0x20010001
  65
  66 /* QUP_IO_M_MODES fields */
  67 #define QUP_IO_M_PACK_EN                BIT(15)
  68 #define QUP_IO_M_UNPACK_EN              BIT(14)
  69 #define QUP_IO_M_INPUT_MODE_MASK_SHIFT  12
  70 #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
  71 #define QUP_IO_M_INPUT_MODE_MASK        (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
  72 #define QUP_IO_M_OUTPUT_MODE_MASK       (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
  73
  74 #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x)   (((x) & (0x03 << 0)) >> 0)
  75 #define QUP_IO_M_OUTPUT_FIFO_SIZE(x)    (((x) & (0x07 << 2)) >> 2)
  76 #define QUP_IO_M_INPUT_BLOCK_SIZE(x)    (((x) & (0x03 << 5)) >> 5)
  77 #define QUP_IO_M_INPUT_FIFO_SIZE(x)     (((x) & (0x07 << 7)) >> 7)
  78
  79 #define QUP_IO_M_MODE_FIFO              0
  80 #define QUP_IO_M_MODE_BLOCK             1
  81 #define QUP_IO_M_MODE_DMOV              2
  82 #define QUP_IO_M_MODE_BAM               3
  83
  84 /* QUP_OPERATIONAL fields */
  85 #define QUP_OP_IN_BLOCK_READ_REQ        BIT(13)
  86 #define QUP_OP_OUT_BLOCK_WRITE_REQ      BIT(12)
  87 #define QUP_OP_MAX_INPUT_DONE_FLAG      BIT(11)
  88 #define QUP_OP_MAX_OUTPUT_DONE_FLAG     BIT(10)
  89 #define QUP_OP_IN_SERVICE_FLAG          BIT(9)
  90 #define QUP_OP_OUT_SERVICE_FLAG         BIT(8)
  91 #define QUP_OP_IN_FIFO_FULL             BIT(7)
  92 #define QUP_OP_OUT_FIFO_FULL            BIT(6)
  93 #define QUP_OP_IN_FIFO_NOT_EMPTY        BIT(5)
  94 #define QUP_OP_OUT_FIFO_NOT_EMPTY       BIT(4)
  95
  96 /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
  97 #define QUP_ERROR_OUTPUT_OVER_RUN       BIT(5)
  98 #define QUP_ERROR_INPUT_UNDER_RUN       BIT(4)
  99 #define QUP_ERROR_OUTPUT_UNDER_RUN      BIT(3)
 100 #define QUP_ERROR_INPUT_OVER_RUN        BIT(2)
 101
 102 /* SPI_CONFIG fields */
 103 #define SPI_CONFIG_HS_MODE              BIT(10)
 104 #define SPI_CONFIG_INPUT_FIRST          BIT(9)
 105 #define SPI_CONFIG_LOOPBACK             BIT(8)
 106
 107 /* SPI_IO_CONTROL fields */
 108 #define SPI_IO_C_FORCE_CS               BIT(11)
 109 #define SPI_IO_C_CLK_IDLE_HIGH          BIT(10)
 110 #define SPI_IO_C_MX_CS_MODE             BIT(8)
 111 #define SPI_IO_C_CS_N_POLARITY_0        BIT(4)
 112 #define SPI_IO_C_CS_SELECT(x)           (((x) & 3) << 2)
 113 #define SPI_IO_C_CS_SELECT_MASK         0x000c
 114 #define SPI_IO_C_TRISTATE_CS            BIT(1)
 115 #define SPI_IO_C_NO_TRI_STATE           BIT(0)
 116
 117 /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
 118 #define SPI_ERROR_CLK_OVER_RUN          BIT(1)
 119 #define SPI_ERROR_CLK_UNDER_RUN         BIT(0)
 120
 121 #define SPI_NUM_CHIPSELECTS             4
 122
 123 #define SPI_MAX_DMA_XFER                (SZ_64K - 64)
 124
 125 /* high speed mode is when bus rate is greater then 26MHz */
 126 #define SPI_HS_MIN_RATE                 26000000
 127 #define SPI_MAX_RATE                    50000000
 128
 129 #define SPI_DELAY_THRESHOLD             1
 130 #define SPI_DELAY_RETRY                 10
 131
 132 struct spi_qup {
 133         void __iomem            *base;
 134         struct device           *dev;
 135         struct clk              *cclk;  /* core clock */
 136         struct clk              *iclk;  /* interface clock */
 137         int                     irq;
 138         spinlock_t              lock;
 139
 140         int                     in_fifo_sz;
 141         int                     out_fifo_sz;
 142         int                     in_blk_sz;
 143         int                     out_blk_sz;
 144
 145         struct spi_transfer     *xfer;
 146         struct completion       done;
 147         int                     error;
 148         int                     w_size; /* bytes per SPI word */
 149         int                     n_words;
 150         int                     tx_bytes;
 151         int                     rx_bytes;
 152         int                     qup_v1;
 153
 154         int                     mode;
 155         struct dma_slave_config rx_conf;
 156         struct dma_slave_config tx_conf;
 157 };
 158
 159 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
 160
 161 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
 162 {
 163         u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
 164
 165         return (opflag & flag) != 0;
 166 }
 167
 168 static inline bool spi_qup_is_dma_xfer(int mode)
 169 {
 170         if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
 171                 return true;
 172
 173         return false;
 174 }
 175
 176 static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
 177 {
 178         u32 opstate = readl_relaxed(controller->base + QUP_STATE);
 179
 180         return opstate & QUP_STATE_VALID;
 181 }
 182
 183 static int spi_qup_set_state(struct spi_qup *controller, u32 state)
 184 {
 185         unsigned long loop;
 186         u32 cur_state;
 187
 188         loop = 0;
 189         while (!spi_qup_is_valid_state(controller)) {
 190
 191                 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
 192
 193                 if (++loop > SPI_DELAY_RETRY)
 194                         return -EIO;
 195         }
 196
 197         if (loop)
 198                 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
 199                         loop, state);
 200
 201         cur_state = readl_relaxed(controller->base + QUP_STATE);
 202         /*
 203          * Per spec: for PAUSE_STATE to RESET_STATE, two writes
 204          * of (b10) are required
 205          */
 206         if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
 207             (state == QUP_STATE_RESET)) {
 208                 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
 209                 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
 210         } else {
 211                 cur_state &= ~QUP_STATE_MASK;
 212                 cur_state |= state;
 213                 writel_relaxed(cur_state, controller->base + QUP_STATE);
 214         }
 215
 216         loop = 0;
 217         while (!spi_qup_is_valid_state(controller)) {
 218
 219                 usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
 220
 221                 if (++loop > SPI_DELAY_RETRY)
 222                         return -EIO;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void spi_qup_read_from_fifo(struct spi_qup *controller,
 229         struct spi_transfer *xfer, u32 num_words)
 230 {
 231         u8 *rx_buf = xfer->rx_buf;
 232         int i, shift, num_bytes;
 233         u32 word;
 234
 235         for (; num_words; num_words--) {
 236
 237                 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
 238
 239                 num_bytes = min_t(int, xfer->len - controller->rx_bytes,
 240                                         controller->w_size);
 241
 242                 if (!rx_buf) {
 243                         controller->rx_bytes += num_bytes;
 244                         continue;
 245                 }
 246
 247                 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
 248                         /*
 249                          * The data format depends on bytes per SPI word:
 250                          *  4 bytes: 0x12345678
 251                          *  2 bytes: 0x00001234
 252                          *  1 byte : 0x00000012
 253                          */
 254                         shift = BITS_PER_BYTE;
 255                         shift *= (controller->w_size - i - 1);
 256                         rx_buf[controller->rx_bytes] = word >> shift;
 257                 }
 258         }
 259 }
 260
 261 static void spi_qup_read(struct spi_qup *controller,
 262                             struct spi_transfer *xfer)
 263 {
 264         u32 remainder, words_per_block, num_words;
 265         bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
 266
 267         remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes,
 268                                  controller->w_size);
 269         words_per_block = controller->in_blk_sz >> 2;
 270
 271         do {
 272                 /* ACK by clearing service flag */
 273                 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
 274                                controller->base + QUP_OPERATIONAL);
 275
 276                 if (is_block_mode) {
 277                         num_words = (remainder > words_per_block) ?
 278                                         words_per_block : remainder;
 279                 } else {
 280                         if (!spi_qup_is_flag_set(controller,
 281                                                  QUP_OP_IN_FIFO_NOT_EMPTY))
 282                                 break;
 283
 284                         num_words = 1;
 285                 }
 286
 287                 /* read up to the maximum transfer size available */
 288                 spi_qup_read_from_fifo(controller, xfer, num_words);
 289
 290                 remainder -= num_words;
 291
 292                 /* if block mode, check to see if next block is available */
 293                 if (is_block_mode && !spi_qup_is_flag_set(controller,
 294                                         QUP_OP_IN_BLOCK_READ_REQ))
 295                         break;
 296
 297         } while (remainder);
 298
 299         /*
 300          * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
 301          * mode reads, it has to be cleared again at the very end
 302          */
 303         if (is_block_mode && spi_qup_is_flag_set(controller,
 304                                 QUP_OP_MAX_INPUT_DONE_FLAG))
 305                 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
 306                                controller->base + QUP_OPERATIONAL);
 307
 308 }
 309
 310 static void spi_qup_write_to_fifo(struct spi_qup *controller,
 311         struct spi_transfer *xfer, u32 num_words)
 312 {
 313         const u8 *tx_buf = xfer->tx_buf;
 314         int i, num_bytes;
 315         u32 word, data;
 316
 317         for (; num_words; num_words--) {
 318                 word = 0;
 319
 320                 num_bytes = min_t(int, xfer->len - controller->tx_bytes,
 321                                     controller->w_size);
 322                 if (tx_buf)
 323                         for (i = 0; i < num_bytes; i++) {
 324                                 data = tx_buf[controller->tx_bytes + i];
 325                                 word |= data << (BITS_PER_BYTE * (3 - i));
 326                         }
 327
 328                 controller->tx_bytes += num_bytes;
 329
 330                 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
 331         }
 332 }
 333
 334 static void spi_qup_dma_done(void *data)
 335 {
 336         struct spi_qup *qup = data;
 337
 338         complete(&qup->done);
 339 }
 340
 341 static void spi_qup_write(struct spi_qup *controller,
 342                             struct spi_transfer *xfer)
 343 {
 344         bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
 345         u32 remainder, words_per_block, num_words;
 346
 347         remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes,
 348                                  controller->w_size);
 349         words_per_block = controller->out_blk_sz >> 2;
 350
 351         do {
 352                 /* ACK by clearing service flag */
 353                 writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
 354                                controller->base + QUP_OPERATIONAL);
 355
 356                 if (is_block_mode) {
 357                         num_words = (remainder > words_per_block) ?
 358                                 words_per_block : remainder;
 359                 } else {
 360                         if (spi_qup_is_flag_set(controller,
 361                                                 QUP_OP_OUT_FIFO_FULL))
 362                                 break;
 363
 364                         num_words = 1;
 365                 }
 366
 367                 spi_qup_write_to_fifo(controller, xfer, num_words);
 368
 369                 remainder -= num_words;
 370
 371                 /* if block mode, check to see if next block is available */
 372                 if (is_block_mode && !spi_qup_is_flag_set(controller,
 373                                         QUP_OP_OUT_BLOCK_WRITE_REQ))
 374                         break;
 375
 376         } while (remainder);
 377 }
 378
 379 static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
 380                            enum dma_transfer_direction dir,
 381                            dma_async_tx_callback callback)
 382 {
 383         struct spi_qup *qup = spi_master_get_devdata(master);
 384         unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
 385         struct dma_async_tx_descriptor *desc;
 386         struct scatterlist *sgl;
 387         struct dma_chan *chan;
 388         dma_cookie_t cookie;
 389         unsigned int nents;
 390
 391         if (dir == DMA_MEM_TO_DEV) {
 392                 chan = master->dma_tx;
 393                 nents = xfer->tx_sg.nents;
 394                 sgl = xfer->tx_sg.sgl;
 395         } else {
 396                 chan = master->dma_rx;
 397                 nents = xfer->rx_sg.nents;
 398                 sgl = xfer->rx_sg.sgl;
 399         }
 400
 401         desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
 402         if (IS_ERR_OR_NULL(desc))
 403                 return desc ? PTR_ERR(desc) : -EINVAL;
 404
 405         desc->callback = callback;
 406         desc->callback_param = qup;
 407
 408         cookie = dmaengine_submit(desc);
 409
 410         return dma_submit_error(cookie);
 411 }
 412
 413 static void spi_qup_dma_terminate(struct spi_master *master,
 414                                   struct spi_transfer *xfer)
 415 {
 416         if (xfer->tx_buf)
 417                 dmaengine_terminate_all(master->dma_tx);
 418         if (xfer->rx_buf)
 419                 dmaengine_terminate_all(master->dma_rx);
 420 }
 421
 422 static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
 423                           unsigned long timeout)
 424 {
 425         dma_async_tx_callback rx_done = NULL, tx_done = NULL;
 426         struct spi_master *master = spi->master;
 427         struct spi_qup *qup = spi_master_get_devdata(master);
 428         int ret;
 429
 430         if (xfer->rx_buf)
 431                 rx_done = spi_qup_dma_done;
 432         else if (xfer->tx_buf)
 433                 tx_done = spi_qup_dma_done;
 434
 435         ret = spi_qup_io_config(spi, xfer);
 436         if (ret)
 437                 return ret;
 438
 439         /* before issuing the descriptors, set the QUP to run */
 440         ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 441         if (ret) {
 442                 dev_warn(qup->dev, "%s(%d): cannot set RUN state\n",
 443                                 __func__, __LINE__);
 444                 return ret;
 445         }
 446
 447         if (xfer->rx_buf) {
 448                 ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done);
 449                 if (ret)
 450                         return ret;
 451
 452                 dma_async_issue_pending(master->dma_rx);
 453         }
 454
 455         if (xfer->tx_buf) {
 456                 ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done);
 457                 if (ret)
 458                         return ret;
 459
 460                 dma_async_issue_pending(master->dma_tx);
 461         }
 462
 463         if (!wait_for_completion_timeout(&qup->done, timeout))
 464                 return -ETIMEDOUT;
 465
 466         return 0;
 467 }
 468
 469 static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
 470                           unsigned long timeout)
 471 {
 472         struct spi_master *master = spi->master;
 473         struct spi_qup *qup = spi_master_get_devdata(master);
 474         int ret;
 475
 476         ret = spi_qup_io_config(spi, xfer);
 477         if (ret)
 478                 return ret;
 479
 480         ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 481         if (ret) {
 482                 dev_warn(qup->dev, "cannot set RUN state\n");
 483                 return ret;
 484         }
 485
 486         ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
 487         if (ret) {
 488                 dev_warn(qup->dev, "cannot set PAUSE state\n");
 489                 return ret;
 490         }
 491
 492         if (qup->mode == QUP_IO_M_MODE_FIFO)
 493                 spi_qup_write(qup, xfer);
 494
 495         ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 496         if (ret) {
 497                 dev_warn(qup->dev, "%s(%d): cannot set RUN state\n",
 498                                 __func__, __LINE__);
 499                 return ret;
 500         }
 501
 502         if (!wait_for_completion_timeout(&qup->done, timeout))
 503                 return -ETIMEDOUT;
 504
 505         return 0;
 506 }
 507
 508 static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
 509 {
 510         struct spi_qup *controller = dev_id;
 511         struct spi_transfer *xfer = controller->xfer;
 512         u32 opflags, qup_err, spi_err;
 513         int error = 0;
 514
 515         qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
 516         spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
 517         opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
 518
 519         writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
 520         writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
 521
 522         if (qup_err) {
 523                 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
 524                         dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
 525                 if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
 526                         dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
 527                 if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
 528                         dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
 529                 if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
 530                         dev_warn(controller->dev, "INPUT_OVER_RUN\n");
 531
 532                 error = -EIO;
 533         }
 534
 535         if (spi_err) {
 536                 if (spi_err & SPI_ERROR_CLK_OVER_RUN)
 537                         dev_warn(controller->dev, "CLK_OVER_RUN\n");
 538                 if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
 539                         dev_warn(controller->dev, "CLK_UNDER_RUN\n");
 540
 541                 error = -EIO;
 542         }
 543
 544         if (spi_qup_is_dma_xfer(controller->mode)) {
 545                 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
 546         } else {
 547                 if (opflags & QUP_OP_IN_SERVICE_FLAG)
 548                         spi_qup_read(controller, xfer);
 549
 550                 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
 551                         spi_qup_write(controller, xfer);
 552         }
 553
 554         if ((opflags & QUP_OP_MAX_INPUT_DONE_FLAG) || error)
 555                 complete(&controller->done);
 556
 557         return IRQ_HANDLED;
 558 }
 559
 560 /* set clock freq ... bits per word, determine mode */
 561 static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
 562 {
 563         struct spi_qup *controller = spi_master_get_devdata(spi->master);
 564         int ret;
 565
 566         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
 567                 dev_err(controller->dev, "too big size for loopback %d > %d\n",
 568                         xfer->len, controller->in_fifo_sz);
 569                 return -EIO;
 570         }
 571
 572         ret = clk_set_rate(controller->cclk, xfer->speed_hz);
 573         if (ret) {
 574                 dev_err(controller->dev, "fail to set frequency %d",
 575                         xfer->speed_hz);
 576                 return -EIO;
 577         }
 578
 579         controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
 580         controller->n_words = xfer->len / controller->w_size;
 581
 582         if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
 583                 controller->mode = QUP_IO_M_MODE_FIFO;
 584         else if (spi->master->can_dma &&
 585                  spi->master->can_dma(spi->master, spi, xfer) &&
 586                  spi->master->cur_msg_mapped)
 587                 controller->mode = QUP_IO_M_MODE_BAM;
 588         else
 589                 controller->mode = QUP_IO_M_MODE_BLOCK;
 590
 591         return 0;
 592 }
 593
 594 /* prep qup for another spi transaction of specific type */
 595 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 596 {
 597         struct spi_qup *controller = spi_master_get_devdata(spi->master);
 598         u32 config, iomode, control;
 599         unsigned long flags;
 600
 601         spin_lock_irqsave(&controller->lock, flags);
 602         controller->xfer     = xfer;
 603         controller->error    = 0;
 604         controller->rx_bytes = 0;
 605         controller->tx_bytes = 0;
 606         spin_unlock_irqrestore(&controller->lock, flags);
 607
 608
 609         if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 610                 dev_err(controller->dev, "cannot set RESET state\n");
 611                 return -EIO;
 612         }
 613
 614         switch (controller->mode) {
 615         case QUP_IO_M_MODE_FIFO:
 616                 writel_relaxed(controller->n_words,
 617                                controller->base + QUP_MX_READ_CNT);
 618                 writel_relaxed(controller->n_words,
 619                                controller->base + QUP_MX_WRITE_CNT);
 620                 /* must be zero for FIFO */
 621                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 622                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 623                 break;
 624         case QUP_IO_M_MODE_BAM:
 625                 writel_relaxed(controller->n_words,
 626                                controller->base + QUP_MX_INPUT_CNT);
 627                 writel_relaxed(controller->n_words,
 628                                controller->base + QUP_MX_OUTPUT_CNT);
 629                 /* must be zero for BLOCK and BAM */
 630                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 631                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 632
 633                 if (!controller->qup_v1) {
 634                         void __iomem *input_cnt;
 635
 636                         input_cnt = controller->base + QUP_MX_INPUT_CNT;
 637                         /*
 638                          * for DMA transfers, both QUP_MX_INPUT_CNT and
 639                          * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
 640                          * That case is a non-balanced transfer when there is
 641                          * only a rx_buf.
 642                          */
 643                         if (xfer->tx_buf)
 644                                 writel_relaxed(0, input_cnt);
 645                         else
 646                                 writel_relaxed(controller->n_words, input_cnt);
 647
 648                         writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 649                 }
 650                 break;
 651         case QUP_IO_M_MODE_BLOCK:
 652                 reinit_completion(&controller->done);
 653                 writel_relaxed(controller->n_words,
 654                                controller->base + QUP_MX_INPUT_CNT);
 655                 writel_relaxed(controller->n_words,
 656                                controller->base + QUP_MX_OUTPUT_CNT);
 657                 /* must be zero for BLOCK and BAM */
 658                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 659                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 660                 break;
 661         default:
 662                 dev_err(controller->dev, "unknown mode = %d\n",
 663                                 controller->mode);
 664                 return -EIO;
 665         }
 666
 667         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 668         /* Set input and output transfer mode */
 669         iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 670
 671         if (!spi_qup_is_dma_xfer(controller->mode))
 672                 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 673         else
 674                 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 675
 676         iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 677         iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 678
 679         writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
 680
 681         control = readl_relaxed(controller->base + SPI_IO_CONTROL);
 682
 683         if (spi->mode & SPI_CPOL)
 684                 control |= SPI_IO_C_CLK_IDLE_HIGH;
 685         else
 686                 control &= ~SPI_IO_C_CLK_IDLE_HIGH;
 687
 688         writel_relaxed(control, controller->base + SPI_IO_CONTROL);
 689
 690         config = readl_relaxed(controller->base + SPI_CONFIG);
 691
 692         if (spi->mode & SPI_LOOP)
 693                 config |= SPI_CONFIG_LOOPBACK;
 694         else
 695                 config &= ~SPI_CONFIG_LOOPBACK;
 696
 697         if (spi->mode & SPI_CPHA)
 698                 config &= ~SPI_CONFIG_INPUT_FIRST;
 699         else
 700                 config |= SPI_CONFIG_INPUT_FIRST;
 701
 702         /*
 703          * HS_MODE improves signal stability for spi-clk high rates,
 704          * but is invalid in loop back mode.
 705          */
 706         if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
 707                 config |= SPI_CONFIG_HS_MODE;
 708         else
 709                 config &= ~SPI_CONFIG_HS_MODE;
 710
 711         writel_relaxed(config, controller->base + SPI_CONFIG);
 712
 713         config = readl_relaxed(controller->base + QUP_CONFIG);
 714         config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
 715         config |= xfer->bits_per_word - 1;
 716         config |= QUP_CONFIG_SPI_MODE;
 717
 718         if (spi_qup_is_dma_xfer(controller->mode)) {
 719                 if (!xfer->tx_buf)
 720                         config |= QUP_CONFIG_NO_OUTPUT;
 721                 if (!xfer->rx_buf)
 722                         config |= QUP_CONFIG_NO_INPUT;
 723         }
 724
 725         writel_relaxed(config, controller->base + QUP_CONFIG);
 726
 727         /* only write to OPERATIONAL_MASK when register is present */
 728         if (!controller->qup_v1) {
 729                 u32 mask = 0;
 730
 731                 /*
 732                  * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
 733                  * status change in BAM mode
 734                  */
 735
 736                 if (spi_qup_is_dma_xfer(controller->mode))
 737                         mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
 738
 739                 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int spi_qup_transfer_one(struct spi_master *master,
 746                               struct spi_device *spi,
 747                               struct spi_transfer *xfer)
 748 {
 749         struct spi_qup *controller = spi_master_get_devdata(master);
 750         unsigned long timeout, flags;
 751         int ret = -EIO;
 752
 753         ret = spi_qup_io_prep(spi, xfer);
 754         if (ret)
 755                 return ret;
 756
 757         timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
 758         timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
 759         timeout = 100 * msecs_to_jiffies(timeout);
 760
 761         reinit_completion(&controller->done);
 762
 763         spin_lock_irqsave(&controller->lock, flags);
 764         controller->xfer     = xfer;
 765         controller->error    = 0;
 766         controller->rx_bytes = 0;
 767         controller->tx_bytes = 0;
 768         spin_unlock_irqrestore(&controller->lock, flags);
 769
 770         if (spi_qup_is_dma_xfer(controller->mode))
 771                 ret = spi_qup_do_dma(spi, xfer, timeout);
 772         else
 773                 ret = spi_qup_do_pio(spi, xfer, timeout);
 774
 775         if (ret)
 776                 goto exit;
 777
 778 exit:
 779         spi_qup_set_state(controller, QUP_STATE_RESET);
 780         spin_lock_irqsave(&controller->lock, flags);
 781         if (!ret)
 782                 ret = controller->error;
 783         spin_unlock_irqrestore(&controller->lock, flags);
 784
 785         if (ret && spi_qup_is_dma_xfer(controller->mode))
 786                 spi_qup_dma_terminate(master, xfer);
 787
 788         return ret;
 789 }
 790
 791 static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
 792                             struct spi_transfer *xfer)
 793 {
 794         struct spi_qup *qup = spi_master_get_devdata(master);
 795         size_t dma_align = dma_get_cache_alignment();
 796         int n_words;
 797
 798         if (xfer->rx_buf) {
 799                 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
 800                     IS_ERR_OR_NULL(master->dma_rx))
 801                         return false;
 802                 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
 803                         return false;
 804         }
 805
 806         if (xfer->tx_buf) {
 807                 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
 808                     IS_ERR_OR_NULL(master->dma_tx))
 809                         return false;
 810                 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
 811                         return false;
 812         }
 813
 814         n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
 815         if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
 816                 return false;
 817
 818         return true;
 819 }
 820
 821 static void spi_qup_release_dma(struct spi_master *master)
 822 {
 823         if (!IS_ERR_OR_NULL(master->dma_rx))
 824                 dma_release_channel(master->dma_rx);
 825         if (!IS_ERR_OR_NULL(master->dma_tx))
 826                 dma_release_channel(master->dma_tx);
 827 }
 828
 829 static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
 830 {
 831         struct spi_qup *spi = spi_master_get_devdata(master);
 832         struct dma_slave_config *rx_conf = &spi->rx_conf,
 833                                 *tx_conf = &spi->tx_conf;
 834         struct device *dev = spi->dev;
 835         int ret;
 836
 837         /* allocate dma resources, if available */
 838         master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
 839         if (IS_ERR(master->dma_rx))
 840                 return PTR_ERR(master->dma_rx);
 841
 842         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
 843         if (IS_ERR(master->dma_tx)) {
 844                 ret = PTR_ERR(master->dma_tx);
 845                 goto err_tx;
 846         }
 847
 848         /* set DMA parameters */
 849         rx_conf->direction = DMA_DEV_TO_MEM;
 850         rx_conf->device_fc = 1;
 851         rx_conf->src_addr = base + QUP_INPUT_FIFO;
 852         rx_conf->src_maxburst = spi->in_blk_sz;
 853
 854         tx_conf->direction = DMA_MEM_TO_DEV;
 855         tx_conf->device_fc = 1;
 856         tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
 857         tx_conf->dst_maxburst = spi->out_blk_sz;
 858
 859         ret = dmaengine_slave_config(master->dma_rx, rx_conf);
 860         if (ret) {
 861                 dev_err(dev, "failed to configure RX channel\n");
 862                 goto err;
 863         }
 864
 865         ret = dmaengine_slave_config(master->dma_tx, tx_conf);
 866         if (ret) {
 867                 dev_err(dev, "failed to configure TX channel\n");
 868                 goto err;
 869         }
 870
 871         return 0;
 872
 873 err:
 874         dma_release_channel(master->dma_tx);
 875 err_tx:
 876         dma_release_channel(master->dma_rx);
 877         return ret;
 878 }
 879
 880 static void spi_qup_set_cs(struct spi_device *spi, bool val)
 881 {
 882         struct spi_qup *controller;
 883         u32 spi_ioc;
 884         u32 spi_ioc_orig;
 885
 886         controller = spi_master_get_devdata(spi->master);
 887         spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
 888         spi_ioc_orig = spi_ioc;
 889         if (!val)
 890                 spi_ioc |= SPI_IO_C_FORCE_CS;
 891         else
 892                 spi_ioc &= ~SPI_IO_C_FORCE_CS;
 893
 894         if (spi_ioc != spi_ioc_orig)
 895                 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
 896 }
 897
 898 static int spi_qup_probe(struct platform_device *pdev)
 899 {
 900         struct spi_master *master;
 901         struct clk *iclk, *cclk;
 902         struct spi_qup *controller;
 903         struct resource *res;
 904         struct device *dev;
 905         void __iomem *base;
 906         u32 max_freq, iomode, num_cs;
 907         int ret, irq, size;
 908
 909         dev = &pdev->dev;
 910         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 911         base = devm_ioremap_resource(dev, res);
 912         if (IS_ERR(base))
 913                 return PTR_ERR(base);
 914
 915         irq = platform_get_irq(pdev, 0);
 916         if (irq < 0)
 917                 return irq;
 918
 919         cclk = devm_clk_get(dev, "core");
 920         if (IS_ERR(cclk))
 921                 return PTR_ERR(cclk);
 922
 923         iclk = devm_clk_get(dev, "iface");
 924         if (IS_ERR(iclk))
 925                 return PTR_ERR(iclk);
 926
 927         /* This is optional parameter */
 928         if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
 929                 max_freq = SPI_MAX_RATE;
 930
 931         if (!max_freq || max_freq > SPI_MAX_RATE) {
 932                 dev_err(dev, "invalid clock frequency %d\n", max_freq);
 933                 return -ENXIO;
 934         }
 935
 936         ret = clk_prepare_enable(cclk);
 937         if (ret) {
 938                 dev_err(dev, "cannot enable core clock\n");
 939                 return ret;
 940         }
 941
 942         ret = clk_prepare_enable(iclk);
 943         if (ret) {
 944                 clk_disable_unprepare(cclk);
 945                 dev_err(dev, "cannot enable iface clock\n");
 946                 return ret;
 947         }
 948
 949         master = spi_alloc_master(dev, sizeof(struct spi_qup));
 950         if (!master) {
 951                 clk_disable_unprepare(cclk);
 952                 clk_disable_unprepare(iclk);
 953                 dev_err(dev, "cannot allocate master\n");
 954                 return -ENOMEM;
 955         }
 956
 957         /* use num-cs unless not present or out of range */
 958         if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) ||
 959             num_cs > SPI_NUM_CHIPSELECTS)
 960                 master->num_chipselect = SPI_NUM_CHIPSELECTS;
 961         else
 962                 master->num_chipselect = num_cs;
 963
 964         master->bus_num = pdev->id;
 965         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
 966         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 967         master->max_speed_hz = max_freq;
 968         master->transfer_one = spi_qup_transfer_one;
 969         master->dev.of_node = pdev->dev.of_node;
 970         master->auto_runtime_pm = true;
 971         master->dma_alignment = dma_get_cache_alignment();
 972         master->max_dma_len = SPI_MAX_DMA_XFER;
 973
 974         platform_set_drvdata(pdev, master);
 975
 976         controller = spi_master_get_devdata(master);
 977
 978         controller->dev = dev;
 979         controller->base = base;
 980         controller->iclk = iclk;
 981         controller->cclk = cclk;
 982         controller->irq = irq;
 983
 984         ret = spi_qup_init_dma(master, res->start);
 985         if (ret == -EPROBE_DEFER)
 986                 goto error;
 987         else if (!ret)
 988                 master->can_dma = spi_qup_can_dma;
 989
 990         /* set v1 flag if device is version 1 */
 991         if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
 992                 controller->qup_v1 = 1;
 993
 994         if (!controller->qup_v1)
 995                 master->set_cs = spi_qup_set_cs;
 996
 997         spin_lock_init(&controller->lock);
 998         init_completion(&controller->done);
 999
1000         iomode = readl_relaxed(base + QUP_IO_M_MODES);
1001
1002         size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
1003         if (size)
1004                 controller->out_blk_sz = size * 16;
1005         else
1006                 controller->out_blk_sz = 4;
1007
1008         size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
1009         if (size)
1010                 controller->in_blk_sz = size * 16;
1011         else
1012                 controller->in_blk_sz = 4;
1013
1014         size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
1015         controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
1016
1017         size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
1018         controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
1019
1020         dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1021                  controller->in_blk_sz, controller->in_fifo_sz,
1022                  controller->out_blk_sz, controller->out_fifo_sz);
1023
1024         writel_relaxed(1, base + QUP_SW_RESET);
1025
1026         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1027         if (ret) {
1028                 dev_err(dev, "cannot set RESET state\n");
1029                 goto error_dma;
1030         }
1031
1032         writel_relaxed(0, base + QUP_OPERATIONAL);
1033         writel_relaxed(0, base + QUP_IO_M_MODES);
1034
1035         if (!controller->qup_v1)
1036                 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
1037
1038         writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
1039                        base + SPI_ERROR_FLAGS_EN);
1040
1041         /* if earlier version of the QUP, disable INPUT_OVERRUN */
1042         if (controller->qup_v1)
1043                 writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
1044                         QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
1045                         base + QUP_ERROR_FLAGS_EN);
1046
1047         writel_relaxed(0, base + SPI_CONFIG);
1048         writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
1049
1050         ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
1051                                IRQF_TRIGGER_HIGH, pdev->name, controller);
1052         if (ret)
1053                 goto error_dma;
1054
1055         pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
1056         pm_runtime_use_autosuspend(dev);
1057         pm_runtime_set_active(dev);
1058         pm_runtime_enable(dev);
1059
1060         ret = devm_spi_register_master(dev, master);
1061         if (ret)
1062                 goto disable_pm;
1063
1064         return 0;
1065
1066 disable_pm:
1067         pm_runtime_disable(&pdev->dev);
1068 error_dma:
1069         spi_qup_release_dma(master);
1070 error:
1071         clk_disable_unprepare(cclk);
1072         clk_disable_unprepare(iclk);
1073         spi_master_put(master);
1074         return ret;
1075 }
1076
1077 #ifdef CONFIG_PM
1078 static int spi_qup_pm_suspend_runtime(struct device *device)
1079 {
1080         struct spi_master *master = dev_get_drvdata(device);
1081         struct spi_qup *controller = spi_master_get_devdata(master);
1082         u32 config;
1083
1084         /* Enable clocks auto gaiting */
1085         config = readl(controller->base + QUP_CONFIG);
1086         config |= QUP_CONFIG_CLOCK_AUTO_GATE;
1087         writel_relaxed(config, controller->base + QUP_CONFIG);
1088
1089         clk_disable_unprepare(controller->cclk);
1090         clk_disable_unprepare(controller->iclk);
1091
1092         return 0;
1093 }
1094
1095 static int spi_qup_pm_resume_runtime(struct device *device)
1096 {
1097         struct spi_master *master = dev_get_drvdata(device);
1098         struct spi_qup *controller = spi_master_get_devdata(master);
1099         u32 config;
1100         int ret;
1101
1102         ret = clk_prepare_enable(controller->iclk);
1103         if (ret)
1104                 return ret;
1105
1106         ret = clk_prepare_enable(controller->cclk);
1107         if (ret)
1108                 return ret;
1109
1110         /* Disable clocks auto gaiting */
1111         config = readl_relaxed(controller->base + QUP_CONFIG);
1112         config &= ~QUP_CONFIG_CLOCK_AUTO_GATE;
1113         writel_relaxed(config, controller->base + QUP_CONFIG);
1114         return 0;
1115 }
1116 #endif /* CONFIG_PM */
1117
1118 #ifdef CONFIG_PM_SLEEP
1119 static int spi_qup_suspend(struct device *device)
1120 {
1121         struct spi_master *master = dev_get_drvdata(device);
1122         struct spi_qup *controller = spi_master_get_devdata(master);
1123         int ret;
1124
1125         ret = spi_master_suspend(master);
1126         if (ret)
1127                 return ret;
1128
1129         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1130         if (ret)
1131                 return ret;
1132
1133         if (!pm_runtime_suspended(device)) {
1134                 clk_disable_unprepare(controller->cclk);
1135                 clk_disable_unprepare(controller->iclk);
1136         }
1137         return 0;
1138 }
1139
1140 static int spi_qup_resume(struct device *device)
1141 {
1142         struct spi_master *master = dev_get_drvdata(device);
1143         struct spi_qup *controller = spi_master_get_devdata(master);
1144         int ret;
1145
1146         ret = clk_prepare_enable(controller->iclk);
1147         if (ret)
1148                 return ret;
1149
1150         ret = clk_prepare_enable(controller->cclk);
1151         if (ret)
1152                 return ret;
1153
1154         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1155         if (ret)
1156                 return ret;
1157
1158         return spi_master_resume(master);
1159 }
1160 #endif /* CONFIG_PM_SLEEP */
1161
1162 static int spi_qup_remove(struct platform_device *pdev)
1163 {
1164         struct spi_master *master = dev_get_drvdata(&pdev->dev);
1165         struct spi_qup *controller = spi_master_get_devdata(master);
1166         int ret;
1167
1168         ret = pm_runtime_get_sync(&pdev->dev);
1169         if (ret < 0)
1170                 return ret;
1171
1172         ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1173         if (ret)
1174                 return ret;
1175
1176         spi_qup_release_dma(master);
1177
1178         clk_disable_unprepare(controller->cclk);
1179         clk_disable_unprepare(controller->iclk);
1180
1181         pm_runtime_put_noidle(&pdev->dev);
1182         pm_runtime_disable(&pdev->dev);
1183
1184         return 0;
1185 }
1186
1187 static const struct of_device_id spi_qup_dt_match[] = {
1188         { .compatible = "qcom,spi-qup-v1.1.1", },
1189         { .compatible = "qcom,spi-qup-v2.1.1", },
1190         { .compatible = "qcom,spi-qup-v2.2.1", },
1191         { }
1192 };
1193 MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
1194
1195 static const struct dev_pm_ops spi_qup_dev_pm_ops = {
1196         SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
1197         SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
1198                            spi_qup_pm_resume_runtime,
1199                            NULL)
1200 };
1201
1202 static struct platform_driver spi_qup_driver = {
1203         .driver = {
1204                 .name           = "spi_qup",
1205                 .pm             = &spi_qup_dev_pm_ops,
1206                 .of_match_table = spi_qup_dt_match,
1207         },
1208         .probe = spi_qup_probe,
1209         .remove = spi_qup_remove,
1210 };
1211 module_platform_driver(spi_qup_driver);
1212
1213 MODULE_LICENSE("GPL v2");
1214 MODULE_ALIAS("platform:spi_qup");