drivers/spi/spi-dw-mmio.c

   1 /*
   2  * Memory-mapped interface driver for DW SPI Core
   3  *
   4  * Copyright (c) 2010, Octasic semiconductor.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/scatterlist.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/acpi.h>
  24 #include <linux/property.h>
  25 #include <linux/regmap.h>
  26
  27 #include "spi-dw.h"
  28
  29 #define DRIVER_NAME "dw_spi_mmio"
  30
  31 struct dw_spi_mmio {
  32         struct dw_spi  dws;
  33         struct clk     *clk;
  34         void           *priv;
  35 };
  36
  37 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL       0x24
  38 #define OCELOT_IF_SI_OWNER_OFFSET               4
  39 #define JAGUAR2_IF_SI_OWNER_OFFSET              6
  40 #define MSCC_IF_SI_OWNER_MASK                   GENMASK(1, 0)
  41 #define MSCC_IF_SI_OWNER_SISL                   0
  42 #define MSCC_IF_SI_OWNER_SIBM                   1
  43 #define MSCC_IF_SI_OWNER_SIMC                   2
  44
  45 #define MSCC_SPI_MST_SW_MODE                    0x14
  46 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE   BIT(13)
  47 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)       (x << 5)
  48
  49 struct dw_spi_mscc {
  50         struct regmap       *syscon;
  51         void __iomem        *spi_mst;
  52 };
  53
  54 /*
  55  * The Designware SPI controller (referred to as master in the documentation)
  56  * automatically deasserts chip select when the tx fifo is empty. The chip
  57  * selects then needs to be either driven as GPIOs or, for the first 4 using the
  58  * the SPI boot controller registers. the final chip select is an OR gate
  59  * between the Designware SPI controller and the SPI boot controller.
  60  */
  61 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
  62 {
  63         struct dw_spi *dws = spi_master_get_devdata(spi->master);
  64         struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
  65         struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
  66         u32 cs = spi->chip_select;
  67
  68         if (cs < 4) {
  69                 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
  70
  71                 if (!enable)
  72                         sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
  73
  74                 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
  75         }
  76
  77         dw_spi_set_cs(spi, enable);
  78 }
  79
  80 static int dw_spi_mscc_init(struct platform_device *pdev,
  81                             struct dw_spi_mmio *dwsmmio,
  82                             const char *cpu_syscon, u32 if_si_owner_offset)
  83 {
  84         struct dw_spi_mscc *dwsmscc;
  85         struct resource *res;
  86
  87         dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
  88         if (!dwsmscc)
  89                 return -ENOMEM;
  90
  91         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  92         dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
  93         if (IS_ERR(dwsmscc->spi_mst)) {
  94                 dev_err(&pdev->dev, "SPI_MST region map failed\n");
  95                 return PTR_ERR(dwsmscc->spi_mst);
  96         }
  97
  98         dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
  99         if (IS_ERR(dwsmscc->syscon))
 100                 return PTR_ERR(dwsmscc->syscon);
 101
 102         /* Deassert all CS */
 103         writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
 104
 105         /* Select the owner of the SI interface */
 106         regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
 107                            MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
 108                            MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
 109
 110         dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
 111         dwsmmio->priv = dwsmscc;
 112
 113         return 0;
 114 }
 115
 116 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
 117                                    struct dw_spi_mmio *dwsmmio)
 118 {
 119         return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
 120                                 OCELOT_IF_SI_OWNER_OFFSET);
 121 }
 122
 123 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
 124                                     struct dw_spi_mmio *dwsmmio)
 125 {
 126         return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
 127                                 JAGUAR2_IF_SI_OWNER_OFFSET);
 128 }
 129
 130 static int dw_spi_alpine_init(struct platform_device *pdev,
 131                               struct dw_spi_mmio *dwsmmio)
 132 {
 133         dwsmmio->dws.cs_override = 1;
 134
 135         return 0;
 136 }
 137
 138 static int dw_spi_mmio_probe(struct platform_device *pdev)
 139 {
 140         int (*init_func)(struct platform_device *pdev,
 141                          struct dw_spi_mmio *dwsmmio);
 142         struct dw_spi_mmio *dwsmmio;
 143         struct dw_spi *dws;
 144         struct resource *mem;
 145         int ret;
 146         int num_cs;
 147
 148         dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
 149                         GFP_KERNEL);
 150         if (!dwsmmio)
 151                 return -ENOMEM;
 152
 153         dws = &dwsmmio->dws;
 154
 155         /* Get basic io resource and map it */
 156         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 157         dws->regs = devm_ioremap_resource(&pdev->dev, mem);
 158         if (IS_ERR(dws->regs)) {
 159                 dev_err(&pdev->dev, "SPI region map failed\n");
 160                 return PTR_ERR(dws->regs);
 161         }
 162
 163         dws->irq = platform_get_irq(pdev, 0);
 164         if (dws->irq < 0) {
 165                 dev_err(&pdev->dev, "no irq resource?\n");
 166                 return dws->irq; /* -ENXIO */
 167         }
 168
 169         dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
 170         if (IS_ERR(dwsmmio->clk))
 171                 return PTR_ERR(dwsmmio->clk);
 172         ret = clk_prepare_enable(dwsmmio->clk);
 173         if (ret)
 174                 return ret;
 175
 176         dws->bus_num = pdev->id;
 177
 178         dws->max_freq = clk_get_rate(dwsmmio->clk);
 179
 180         device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
 181
 182         num_cs = 4;
 183
 184         device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
 185
 186         dws->num_cs = num_cs;
 187
 188         if (pdev->dev.of_node) {
 189                 int i;
 190
 191                 for (i = 0; i < dws->num_cs; i++) {
 192                         int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
 193                                         "cs-gpios", i);
 194
 195                         if (cs_gpio == -EPROBE_DEFER) {
 196                                 ret = cs_gpio;
 197                                 goto out;
 198                         }
 199
 200                         if (gpio_is_valid(cs_gpio)) {
 201                                 ret = devm_gpio_request(&pdev->dev, cs_gpio,
 202                                                 dev_name(&pdev->dev));
 203                                 if (ret)
 204                                         goto out;
 205                         }
 206                 }
 207         }
 208
 209         init_func = device_get_match_data(&pdev->dev);
 210         if (init_func) {
 211                 ret = init_func(pdev, dwsmmio);
 212                 if (ret)
 213                         goto out;
 214         }
 215
 216         ret = dw_spi_add_host(&pdev->dev, dws);
 217         if (ret)
 218                 goto out;
 219
 220         platform_set_drvdata(pdev, dwsmmio);
 221         return 0;
 222
 223 out:
 224         clk_disable_unprepare(dwsmmio->clk);
 225         return ret;
 226 }
 227
 228 static int dw_spi_mmio_remove(struct platform_device *pdev)
 229 {
 230         struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
 231
 232         dw_spi_remove_host(&dwsmmio->dws);
 233         clk_disable_unprepare(dwsmmio->clk);
 234
 235         return 0;
 236 }
 237
 238 static const struct of_device_id dw_spi_mmio_of_match[] = {
 239         { .compatible = "snps,dw-apb-ssi", },
 240         { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
 241         { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
 242         { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
 243         { /* end of table */}
 244 };
 245 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
 246
 247 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
 248         {"HISI0173", 0},
 249         {},
 250 };
 251 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
 252
 253 static struct platform_driver dw_spi_mmio_driver = {
 254         .probe          = dw_spi_mmio_probe,
 255         .remove         = dw_spi_mmio_remove,
 256         .driver         = {
 257                 .name   = DRIVER_NAME,
 258                 .of_match_table = dw_spi_mmio_of_match,
 259                 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
 260         },
 261 };
 262 module_platform_driver(dw_spi_mmio_driver);
 263
 264 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
 265 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
 266 MODULE_LICENSE("GPL v2");