drivers/spi/spi-dw-mmio.c

   1 /*
   2  * Memory-mapped interface driver for DW SPI Core
   3  *
   4  * Copyright (c) 2010, Octasic semiconductor.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/scatterlist.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/acpi.h>
  23 #include <linux/property.h>
  24 #include <linux/regmap.h>
  25
  26 #include "spi-dw.h"
  27
  28 #define DRIVER_NAME "dw_spi_mmio"
  29
  30 struct dw_spi_mmio {
  31         struct dw_spi  dws;
  32         struct clk     *clk;
  33         void           *priv;
  34 };
  35
  36 #define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL       0x24
  37 #define OCELOT_IF_SI_OWNER_OFFSET               4
  38 #define JAGUAR2_IF_SI_OWNER_OFFSET              6
  39 #define MSCC_IF_SI_OWNER_MASK                   GENMASK(1, 0)
  40 #define MSCC_IF_SI_OWNER_SISL                   0
  41 #define MSCC_IF_SI_OWNER_SIBM                   1
  42 #define MSCC_IF_SI_OWNER_SIMC                   2
  43
  44 #define MSCC_SPI_MST_SW_MODE                    0x14
  45 #define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE   BIT(13)
  46 #define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x)       (x << 5)
  47
  48 struct dw_spi_mscc {
  49         struct regmap       *syscon;
  50         void __iomem        *spi_mst;
  51 };
  52
  53 /*
  54  * The Designware SPI controller (referred to as master in the documentation)
  55  * automatically deasserts chip select when the tx fifo is empty. The chip
  56  * selects then needs to be either driven as GPIOs or, for the first 4 using the
  57  * the SPI boot controller registers. the final chip select is an OR gate
  58  * between the Designware SPI controller and the SPI boot controller.
  59  */
  60 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
  61 {
  62         struct dw_spi *dws = spi_master_get_devdata(spi->master);
  63         struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
  64         struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
  65         u32 cs = spi->chip_select;
  66
  67         if (cs < 4) {
  68                 u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
  69
  70                 if (!enable)
  71                         sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
  72
  73                 writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
  74         }
  75
  76         dw_spi_set_cs(spi, enable);
  77 }
  78
  79 static int dw_spi_mscc_init(struct platform_device *pdev,
  80                             struct dw_spi_mmio *dwsmmio,
  81                             const char *cpu_syscon, u32 if_si_owner_offset)
  82 {
  83         struct dw_spi_mscc *dwsmscc;
  84         struct resource *res;
  85
  86         dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
  87         if (!dwsmscc)
  88                 return -ENOMEM;
  89
  90         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  91         dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
  92         if (IS_ERR(dwsmscc->spi_mst)) {
  93                 dev_err(&pdev->dev, "SPI_MST region map failed\n");
  94                 return PTR_ERR(dwsmscc->spi_mst);
  95         }
  96
  97         dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
  98         if (IS_ERR(dwsmscc->syscon))
  99                 return PTR_ERR(dwsmscc->syscon);
 100
 101         /* Deassert all CS */
 102         writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
 103
 104         /* Select the owner of the SI interface */
 105         regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
 106                            MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
 107                            MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
 108
 109         dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
 110         dwsmmio->priv = dwsmscc;
 111
 112         return 0;
 113 }
 114
 115 static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
 116                                    struct dw_spi_mmio *dwsmmio)
 117 {
 118         return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
 119                                 OCELOT_IF_SI_OWNER_OFFSET);
 120 }
 121
 122 static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
 123                                     struct dw_spi_mmio *dwsmmio)
 124 {
 125         return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
 126                                 JAGUAR2_IF_SI_OWNER_OFFSET);
 127 }
 128
 129 static int dw_spi_alpine_init(struct platform_device *pdev,
 130                               struct dw_spi_mmio *dwsmmio)
 131 {
 132         dwsmmio->dws.cs_override = 1;
 133
 134         return 0;
 135 }
 136
 137 static int dw_spi_mmio_probe(struct platform_device *pdev)
 138 {
 139         int (*init_func)(struct platform_device *pdev,
 140                          struct dw_spi_mmio *dwsmmio);
 141         struct dw_spi_mmio *dwsmmio;
 142         struct dw_spi *dws;
 143         struct resource *mem;
 144         int ret;
 145         int num_cs;
 146
 147         dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
 148                         GFP_KERNEL);
 149         if (!dwsmmio)
 150                 return -ENOMEM;
 151
 152         dws = &dwsmmio->dws;
 153
 154         /* Get basic io resource and map it */
 155         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 156         dws->regs = devm_ioremap_resource(&pdev->dev, mem);
 157         if (IS_ERR(dws->regs)) {
 158                 dev_err(&pdev->dev, "SPI region map failed\n");
 159                 return PTR_ERR(dws->regs);
 160         }
 161
 162         dws->irq = platform_get_irq(pdev, 0);
 163         if (dws->irq < 0) {
 164                 dev_err(&pdev->dev, "no irq resource?\n");
 165                 return dws->irq; /* -ENXIO */
 166         }
 167
 168         dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
 169         if (IS_ERR(dwsmmio->clk))
 170                 return PTR_ERR(dwsmmio->clk);
 171         ret = clk_prepare_enable(dwsmmio->clk);
 172         if (ret)
 173                 return ret;
 174
 175         dws->bus_num = pdev->id;
 176
 177         dws->max_freq = clk_get_rate(dwsmmio->clk);
 178
 179         device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
 180
 181         num_cs = 4;
 182
 183         device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
 184
 185         dws->num_cs = num_cs;
 186
 187         init_func = device_get_match_data(&pdev->dev);
 188         if (init_func) {
 189                 ret = init_func(pdev, dwsmmio);
 190                 if (ret)
 191                         goto out;
 192         }
 193
 194         ret = dw_spi_add_host(&pdev->dev, dws);
 195         if (ret)
 196                 goto out;
 197
 198         platform_set_drvdata(pdev, dwsmmio);
 199         return 0;
 200
 201 out:
 202         clk_disable_unprepare(dwsmmio->clk);
 203         return ret;
 204 }
 205
 206 static int dw_spi_mmio_remove(struct platform_device *pdev)
 207 {
 208         struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
 209
 210         dw_spi_remove_host(&dwsmmio->dws);
 211         clk_disable_unprepare(dwsmmio->clk);
 212
 213         return 0;
 214 }
 215
 216 static const struct of_device_id dw_spi_mmio_of_match[] = {
 217         { .compatible = "snps,dw-apb-ssi", },
 218         { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
 219         { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
 220         { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
 221         { /* end of table */}
 222 };
 223 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
 224
 225 static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
 226         {"HISI0173", 0},
 227         {},
 228 };
 229 MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
 230
 231 static struct platform_driver dw_spi_mmio_driver = {
 232         .probe          = dw_spi_mmio_probe,
 233         .remove         = dw_spi_mmio_remove,
 234         .driver         = {
 235                 .name   = DRIVER_NAME,
 236                 .of_match_table = dw_spi_mmio_of_match,
 237                 .acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
 238         },
 239 };
 240 module_platform_driver(dw_spi_mmio_driver);
 241
 242 MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
 243 MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
 244 MODULE_LICENSE("GPL v2");