drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005, 2006 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/time.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/byteorder.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/scsi_tcq.h>
  35 #include <scsi/scsi_dbg.h>
  36
  37 #define DRV_NAME "stex"
  38 #define ST_DRIVER_VERSION "3.6.0000.1"
  39 #define ST_VER_MAJOR            3
  40 #define ST_VER_MINOR            6
  41 #define ST_OEM                  0
  42 #define ST_BUILD_VER            1
  43
  44 enum {
  45         /* MU register offset */
  46         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  47         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  48         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  49         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  50         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  51         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  52         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  53         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  54         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  55         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  56
  57         /* MU register value */
  58         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  59         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  60         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  61         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  62         MU_INBOUND_DOORBELL_RESET               = 16,
  63
  64         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  65         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  66         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  67         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  68         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  69
  70         /* MU status code */
  71         MU_STATE_STARTING                       = 1,
  72         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  73         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  74         MU_STATE_STARTED                        = 4,
  75         MU_STATE_RESETTING                      = 5,
  76
  77         MU_MAX_DELAY                            = 120,
  78         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  79         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  80         MU_HARD_RESET_WAIT                      = 30000,
  81         HMU_PARTNER_TYPE                        = 2,
  82
  83         /* firmware returned values */
  84         SRB_STATUS_SUCCESS                      = 0x01,
  85         SRB_STATUS_ERROR                        = 0x04,
  86         SRB_STATUS_BUSY                         = 0x05,
  87         SRB_STATUS_INVALID_REQUEST              = 0x06,
  88         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  89         SRB_SEE_SENSE                           = 0x80,
  90
  91         /* task attribute */
  92         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  93         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  94         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  95         TASK_ATTRIBUTE_ACA                      = 0x4,
  96
  97         /* request count, etc. */
  98         MU_MAX_REQUEST                          = 32,
  99
 100         /* one message wasted, use MU_MAX_REQUEST+1
 101                 to handle MU_MAX_REQUEST messages */
 102         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 103         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 104
 105         STEX_CDB_LENGTH                         = MAX_COMMAND_SIZE,
 106         REQ_VARIABLE_LEN                        = 1024,
 107         STATUS_VAR_LEN                          = 128,
 108         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 109         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 110         ST_MAX_SG                               = 32,
 111
 112         /* sg flags */
 113         SG_CF_EOT                               = 0x80, /* end of table */
 114         SG_CF_64B                               = 0x40, /* 64 bit item */
 115         SG_CF_HOST                              = 0x20, /* sg in host memory */
 116
 117         st_shasta                               = 0,
 118         st_vsc                                  = 1,
 119         st_vsc1                                 = 2,
 120         st_yosemite                             = 3,
 121
 122         PASSTHRU_REQ_TYPE                       = 0x00000001,
 123         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 124         ST_INTERNAL_TIMEOUT                     = 30,
 125
 126         ST_TO_CMD                               = 0,
 127         ST_FROM_CMD                             = 1,
 128
 129         /* vendor specific commands of Promise */
 130         MGT_CMD                                 = 0xd8,
 131         SINBAND_MGT_CMD                         = 0xd9,
 132         ARRAY_CMD                               = 0xe0,
 133         CONTROLLER_CMD                          = 0xe1,
 134         DEBUGGING_CMD                           = 0xe2,
 135         PASSTHRU_CMD                            = 0xe3,
 136
 137         PASSTHRU_GET_ADAPTER                    = 0x05,
 138         PASSTHRU_GET_DRVVER                     = 0x10,
 139
 140         CTLR_CONFIG_CMD                         = 0x03,
 141         CTLR_SHUTDOWN                           = 0x0d,
 142
 143         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 144         CTLR_POWER_SAVING                       = 0x01,
 145
 146         PASSTHRU_SIGNATURE                      = 0x4e415041,
 147         MGT_CMD_SIGNATURE                       = 0xba,
 148
 149         INQUIRY_EVPD                            = 0x01,
 150
 151         ST_ADDITIONAL_MEM                       = 0x200000,
 152 };
 153
 154 /* SCSI inquiry data */
 155 typedef struct st_inq {
 156         u8 DeviceType                   :5;
 157         u8 DeviceTypeQualifier          :3;
 158         u8 DeviceTypeModifier           :7;
 159         u8 RemovableMedia               :1;
 160         u8 Versions;
 161         u8 ResponseDataFormat           :4;
 162         u8 HiSupport                    :1;
 163         u8 NormACA                      :1;
 164         u8 ReservedBit                  :1;
 165         u8 AERC                         :1;
 166         u8 AdditionalLength;
 167         u8 Reserved[2];
 168         u8 SoftReset                    :1;
 169         u8 CommandQueue                 :1;
 170         u8 Reserved2                    :1;
 171         u8 LinkedCommands               :1;
 172         u8 Synchronous                  :1;
 173         u8 Wide16Bit                    :1;
 174         u8 Wide32Bit                    :1;
 175         u8 RelativeAddressing           :1;
 176         u8 VendorId[8];
 177         u8 ProductId[16];
 178         u8 ProductRevisionLevel[4];
 179         u8 VendorSpecific[20];
 180         u8 Reserved3[40];
 181 } ST_INQ;
 182
 183 struct st_sgitem {
 184         u8 ctrl;        /* SG_CF_xxx */
 185         u8 reserved[3];
 186         __le32 count;
 187         __le32 addr;
 188         __le32 addr_hi;
 189 };
 190
 191 struct st_sgtable {
 192         __le16 sg_count;
 193         __le16 max_sg_count;
 194         __le32 sz_in_byte;
 195         struct st_sgitem table[ST_MAX_SG];
 196 };
 197
 198 struct handshake_frame {
 199         __le32 rb_phy;          /* request payload queue physical address */
 200         __le32 rb_phy_hi;
 201         __le16 req_sz;          /* size of each request payload */
 202         __le16 req_cnt;         /* count of reqs the buffer can hold */
 203         __le16 status_sz;       /* size of each status payload */
 204         __le16 status_cnt;      /* count of status the buffer can hold */
 205         __le32 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 206         __le32 hosttime_hi;
 207         u8 partner_type;        /* who sends this frame */
 208         u8 reserved0[7];
 209         __le32 partner_ver_major;
 210         __le32 partner_ver_minor;
 211         __le32 partner_ver_oem;
 212         __le32 partner_ver_build;
 213         __le32 extra_offset;    /* NEW */
 214         __le32 extra_size;      /* NEW */
 215         u32 reserved1[2];
 216 };
 217
 218 struct req_msg {
 219         __le16 tag;
 220         u8 lun;
 221         u8 target;
 222         u8 task_attr;
 223         u8 task_manage;
 224         u8 prd_entry;
 225         u8 payload_sz;          /* payload size in 4-byte, not used */
 226         u8 cdb[STEX_CDB_LENGTH];
 227         u8 variable[REQ_VARIABLE_LEN];
 228 };
 229
 230 struct status_msg {
 231         __le16 tag;
 232         u8 lun;
 233         u8 target;
 234         u8 srb_status;
 235         u8 scsi_status;
 236         u8 reserved;
 237         u8 payload_sz;          /* payload size in 4-byte */
 238         u8 variable[STATUS_VAR_LEN];
 239 };
 240
 241 struct ver_info {
 242         u32 major;
 243         u32 minor;
 244         u32 oem;
 245         u32 build;
 246         u32 reserved[2];
 247 };
 248
 249 struct st_frame {
 250         u32 base[6];
 251         u32 rom_addr;
 252
 253         struct ver_info drv_ver;
 254         struct ver_info bios_ver;
 255
 256         u32 bus;
 257         u32 slot;
 258         u32 irq_level;
 259         u32 irq_vec;
 260         u32 id;
 261         u32 subid;
 262
 263         u32 dimm_size;
 264         u8 dimm_type;
 265         u8 reserved[3];
 266
 267         u32 channel;
 268         u32 reserved1;
 269 };
 270
 271 struct st_drvver {
 272         u32 major;
 273         u32 minor;
 274         u32 oem;
 275         u32 build;
 276         u32 signature[2];
 277         u8 console_id;
 278         u8 host_no;
 279         u8 reserved0[2];
 280         u32 reserved[3];
 281 };
 282
 283 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 284 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 285 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 286 #define STEX_EXTRA_SIZE         max(sizeof(struct st_frame), sizeof(ST_INQ))
 287 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
 288
 289 struct st_ccb {
 290         struct req_msg *req;
 291         struct scsi_cmnd *cmd;
 292
 293         void *sense_buffer;
 294         unsigned int sense_bufflen;
 295         int sg_count;
 296
 297         u32 req_type;
 298         u8 srb_status;
 299         u8 scsi_status;
 300 };
 301
 302 struct st_hba {
 303         void __iomem *mmio_base;        /* iomapped PCI memory space */
 304         void *dma_mem;
 305         dma_addr_t dma_handle;
 306         size_t dma_size;
 307
 308         struct Scsi_Host *host;
 309         struct pci_dev *pdev;
 310
 311         u32 req_head;
 312         u32 req_tail;
 313         u32 status_head;
 314         u32 status_tail;
 315
 316         struct status_msg *status_buffer;
 317         void *copy_buffer; /* temp buffer for driver-handled commands */
 318         struct st_ccb ccb[MU_MAX_REQUEST];
 319         struct st_ccb *wait_ccb;
 320         wait_queue_head_t waitq;
 321
 322         unsigned int mu_status;
 323         int out_req_cnt;
 324
 325         unsigned int cardtype;
 326 };
 327
 328 static const char console_inq_page[] =
 329 {
 330         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 331         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 332         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 333         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 334         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 335         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 336         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 337         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 338 };
 339
 340 MODULE_AUTHOR("Ed Lin");
 341 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 342 MODULE_LICENSE("GPL");
 343 MODULE_VERSION(ST_DRIVER_VERSION);
 344
 345 static void stex_gettime(__le32 *time)
 346 {
 347         struct timeval tv;
 348         do_gettimeofday(&tv);
 349
 350         *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
 351         *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
 352 }
 353
 354 static struct status_msg *stex_get_status(struct st_hba *hba)
 355 {
 356         struct status_msg *status =
 357                 hba->status_buffer + hba->status_tail;
 358
 359         ++hba->status_tail;
 360         hba->status_tail %= MU_STATUS_COUNT;
 361
 362         return status;
 363 }
 364
 365 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
 366 {
 367         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 368
 369         cmd->sense_buffer[0] = 0x70;    /* fixed format, current */
 370         cmd->sense_buffer[2] = sk;
 371         cmd->sense_buffer[7] = 18 - 8;  /* additional sense length */
 372         cmd->sense_buffer[12] = asc;
 373         cmd->sense_buffer[13] = ascq;
 374 }
 375
 376 static void stex_invalid_field(struct scsi_cmnd *cmd,
 377                                void (*done)(struct scsi_cmnd *))
 378 {
 379         /* "Invalid field in cbd" */
 380         stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
 381         done(cmd);
 382 }
 383
 384 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 385 {
 386         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 387                 hba->req_head;
 388
 389         ++hba->req_head;
 390         hba->req_head %= MU_REQ_COUNT;
 391
 392         return req;
 393 }
 394
 395 static int stex_map_sg(struct st_hba *hba,
 396         struct req_msg *req, struct st_ccb *ccb)
 397 {
 398         struct scsi_cmnd *cmd;
 399         struct scatterlist *sg;
 400         struct st_sgtable *dst;
 401         int i, nseg;
 402
 403         cmd = ccb->cmd;
 404         dst = (struct st_sgtable *)req->variable;
 405         dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
 406         dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 407
 408         nseg = scsi_dma_map(cmd);
 409         if (nseg < 0)
 410                 return -EIO;
 411         if (nseg) {
 412                 ccb->sg_count = nseg;
 413                 dst->sg_count = cpu_to_le16((u16)nseg);
 414
 415                 scsi_for_each_sg(cmd, sg, nseg, i) {
 416                         dst->table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 417                         dst->table[i].addr =
 418                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 419                         dst->table[i].addr_hi =
 420                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 421                         dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 422                 }
 423                 dst->table[--i].ctrl |= SG_CF_EOT;
 424         }
 425
 426         return 0;
 427 }
 428
 429 static void stex_internal_copy(struct scsi_cmnd *cmd,
 430         const void *src, size_t *count, int sg_count, int direction)
 431 {
 432         size_t lcount;
 433         size_t len;
 434         void *s, *d, *base = NULL;
 435         size_t offset;
 436
 437         if (*count > scsi_bufflen(cmd))
 438                 *count = scsi_bufflen(cmd);
 439         lcount = *count;
 440         while (lcount) {
 441                 len = lcount;
 442                 s = (void *)src;
 443
 444                 offset = *count - lcount;
 445                 s += offset;
 446                 base = scsi_kmap_atomic_sg(scsi_sglist(cmd),
 447                                            sg_count, &offset, &len);
 448                 if (!base) {
 449                         *count -= lcount;
 450                         return;
 451                 }
 452                 d = base + offset;
 453
 454                 if (direction == ST_TO_CMD)
 455                         memcpy(d, s, len);
 456                 else
 457                         memcpy(s, d, len);
 458
 459                 lcount -= len;
 460                 scsi_kunmap_atomic_sg(base);
 461         }
 462 }
 463
 464 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 465 {
 466         struct st_frame *p;
 467         size_t count = sizeof(struct st_frame);
 468
 469         p = hba->copy_buffer;
 470         stex_internal_copy(ccb->cmd, p, &count, scsi_sg_count(ccb->cmd),
 471                            ST_FROM_CMD);
 472         memset(p->base, 0, sizeof(u32)*6);
 473         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 474         p->rom_addr = 0;
 475
 476         p->drv_ver.major = ST_VER_MAJOR;
 477         p->drv_ver.minor = ST_VER_MINOR;
 478         p->drv_ver.oem = ST_OEM;
 479         p->drv_ver.build = ST_BUILD_VER;
 480
 481         p->bus = hba->pdev->bus->number;
 482         p->slot = hba->pdev->devfn;
 483         p->irq_level = 0;
 484         p->irq_vec = hba->pdev->irq;
 485         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 486         p->subid =
 487                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 488
 489         stex_internal_copy(ccb->cmd, p, &count, scsi_sg_count(ccb->cmd),
 490                            ST_TO_CMD);
 491 }
 492
 493 static void
 494 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 495 {
 496         req->tag = cpu_to_le16(tag);
 497         req->task_attr = TASK_ATTRIBUTE_SIMPLE;
 498         req->task_manage = 0; /* not supported yet */
 499
 500         hba->ccb[tag].req = req;
 501         hba->out_req_cnt++;
 502
 503         writel(hba->req_head, hba->mmio_base + IMR0);
 504         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 505         readl(hba->mmio_base + IDBL); /* flush */
 506 }
 507
 508 static int
 509 stex_slave_alloc(struct scsi_device *sdev)
 510 {
 511         /* Cheat: usually extracted from Inquiry data */
 512         sdev->tagged_supported = 1;
 513
 514         scsi_activate_tcq(sdev, sdev->host->can_queue);
 515
 516         return 0;
 517 }
 518
 519 static int
 520 stex_slave_config(struct scsi_device *sdev)
 521 {
 522         sdev->use_10_for_rw = 1;
 523         sdev->use_10_for_ms = 1;
 524         sdev->timeout = 60 * HZ;
 525         sdev->tagged_supported = 1;
 526
 527         return 0;
 528 }
 529
 530 static void
 531 stex_slave_destroy(struct scsi_device *sdev)
 532 {
 533         scsi_deactivate_tcq(sdev, 1);
 534 }
 535
 536 static int
 537 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 538 {
 539         struct st_hba *hba;
 540         struct Scsi_Host *host;
 541         unsigned int id,lun;
 542         struct req_msg *req;
 543         u16 tag;
 544         host = cmd->device->host;
 545         id = cmd->device->id;
 546         lun = cmd->device->lun;
 547         hba = (struct st_hba *) &host->hostdata[0];
 548
 549         switch (cmd->cmnd[0]) {
 550         case MODE_SENSE_10:
 551         {
 552                 static char ms10_caching_page[12] =
 553                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 554                 unsigned char page;
 555                 page = cmd->cmnd[2] & 0x3f;
 556                 if (page == 0x8 || page == 0x3f) {
 557                         size_t cp_len = sizeof(ms10_caching_page);
 558                         stex_internal_copy(cmd, ms10_caching_page,
 559                                            &cp_len, scsi_sg_count(cmd),
 560                                            ST_TO_CMD);
 561                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 562                         done(cmd);
 563                 } else
 564                         stex_invalid_field(cmd, done);
 565                 return 0;
 566         }
 567         case REPORT_LUNS:
 568                 /*
 569                  * The shasta firmware does not report actual luns in the
 570                  * target, so fail the command to force sequential lun scan.
 571                  * Also, the console device does not support this command.
 572                  */
 573                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 574                         stex_invalid_field(cmd, done);
 575                         return 0;
 576                 }
 577                 break;
 578         case TEST_UNIT_READY:
 579                 if (id == host->max_id - 1) {
 580                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 581                         done(cmd);
 582                         return 0;
 583                 }
 584                 break;
 585         case INQUIRY:
 586                 if (id != host->max_id - 1)
 587                         break;
 588                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 589                         size_t cp_len = sizeof(console_inq_page);
 590                         stex_internal_copy(cmd, console_inq_page,
 591                                            &cp_len, scsi_sg_count(cmd),
 592                                            ST_TO_CMD);
 593                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 594                         done(cmd);
 595                 } else
 596                         stex_invalid_field(cmd, done);
 597                 return 0;
 598         case PASSTHRU_CMD:
 599                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 600                         struct st_drvver ver;
 601                         size_t cp_len = sizeof(ver);
 602                         ver.major = ST_VER_MAJOR;
 603                         ver.minor = ST_VER_MINOR;
 604                         ver.oem = ST_OEM;
 605                         ver.build = ST_BUILD_VER;
 606                         ver.signature[0] = PASSTHRU_SIGNATURE;
 607                         ver.console_id = host->max_id - 1;
 608                         ver.host_no = hba->host->host_no;
 609                         stex_internal_copy(cmd, &ver, &cp_len,
 610                                            scsi_sg_count(cmd), ST_TO_CMD);
 611                         cmd->result = sizeof(ver) == cp_len ?
 612                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 613                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 614                         done(cmd);
 615                         return 0;
 616                 }
 617         default:
 618                 break;
 619         }
 620
 621         cmd->scsi_done = done;
 622
 623         tag = cmd->request->tag;
 624
 625         if (unlikely(tag >= host->can_queue))
 626                 return SCSI_MLQUEUE_HOST_BUSY;
 627
 628         req = stex_alloc_req(hba);
 629
 630         req->lun = lun;
 631         req->target = id;
 632
 633         /* cdb */
 634         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 635
 636         hba->ccb[tag].cmd = cmd;
 637         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 638         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 639         hba->ccb[tag].req_type = 0;
 640
 641         if (cmd->sc_data_direction != DMA_NONE)
 642                 stex_map_sg(hba, req, &hba->ccb[tag]);
 643
 644         stex_send_cmd(hba, req, tag);
 645         return 0;
 646 }
 647
 648 static void stex_scsi_done(struct st_ccb *ccb)
 649 {
 650         struct scsi_cmnd *cmd = ccb->cmd;
 651         int result;
 652
 653         if (ccb->srb_status == SRB_STATUS_SUCCESS ||  ccb->srb_status == 0) {
 654                 result = ccb->scsi_status;
 655                 switch (ccb->scsi_status) {
 656                 case SAM_STAT_GOOD:
 657                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 658                         break;
 659                 case SAM_STAT_CHECK_CONDITION:
 660                         result |= DRIVER_SENSE << 24;
 661                         break;
 662                 case SAM_STAT_BUSY:
 663                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 664                         break;
 665                 default:
 666                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 667                         break;
 668                 }
 669         }
 670         else if (ccb->srb_status & SRB_SEE_SENSE)
 671                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 672         else switch (ccb->srb_status) {
 673                 case SRB_STATUS_SELECTION_TIMEOUT:
 674                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 675                         break;
 676                 case SRB_STATUS_BUSY:
 677                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 678                         break;
 679                 case SRB_STATUS_INVALID_REQUEST:
 680                 case SRB_STATUS_ERROR:
 681                 default:
 682                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 683                         break;
 684         }
 685
 686         cmd->result = result;
 687         cmd->scsi_done(cmd);
 688 }
 689
 690 static void stex_copy_data(struct st_ccb *ccb,
 691         struct status_msg *resp, unsigned int variable)
 692 {
 693         size_t count = variable;
 694         if (resp->scsi_status != SAM_STAT_GOOD) {
 695                 if (ccb->sense_buffer != NULL)
 696                         memcpy(ccb->sense_buffer, resp->variable,
 697                                 min(variable, ccb->sense_bufflen));
 698                 return;
 699         }
 700
 701         if (ccb->cmd == NULL)
 702                 return;
 703         stex_internal_copy(ccb->cmd,
 704                 resp->variable, &count, scsi_sg_count(ccb->cmd), ST_TO_CMD);
 705 }
 706
 707 static void stex_ys_commands(struct st_hba *hba,
 708         struct st_ccb *ccb, struct status_msg *resp)
 709 {
 710         size_t count;
 711
 712         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 713                 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
 714                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 715                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 716                 return;
 717         }
 718
 719         if (resp->srb_status != 0)
 720                 return;
 721
 722         /* determine inquiry command status by DeviceTypeQualifier */
 723         if (ccb->cmd->cmnd[0] == INQUIRY &&
 724                 resp->scsi_status == SAM_STAT_GOOD) {
 725                 ST_INQ *inq_data;
 726
 727                 count = STEX_EXTRA_SIZE;
 728                 stex_internal_copy(ccb->cmd, hba->copy_buffer,
 729                         &count, scsi_sg_count(ccb->cmd), ST_FROM_CMD);
 730                 inq_data = (ST_INQ *)hba->copy_buffer;
 731                 if (inq_data->DeviceTypeQualifier != 0)
 732                         ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
 733                 else
 734                         ccb->srb_status = SRB_STATUS_SUCCESS;
 735         }
 736 }
 737
 738 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 739 {
 740         void __iomem *base = hba->mmio_base;
 741         struct status_msg *resp;
 742         struct st_ccb *ccb;
 743         unsigned int size;
 744         u16 tag;
 745
 746         if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
 747                 return;
 748
 749         /* status payloads */
 750         hba->status_head = readl(base + OMR1);
 751         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 752                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 753                         pci_name(hba->pdev));
 754                 return;
 755         }
 756
 757         /*
 758          * it's not a valid status payload if:
 759          * 1. there are no pending requests(e.g. during init stage)
 760          * 2. there are some pending requests, but the controller is in
 761          *     reset status, and its type is not st_yosemite
 762          * firmware of st_yosemite in reset status will return pending requests
 763          * to driver, so we allow it to pass
 764          */
 765         if (unlikely(hba->out_req_cnt <= 0 ||
 766                         (hba->mu_status == MU_STATE_RESETTING &&
 767                          hba->cardtype != st_yosemite))) {
 768                 hba->status_tail = hba->status_head;
 769                 goto update_status;
 770         }
 771
 772         while (hba->status_tail != hba->status_head) {
 773                 resp = stex_get_status(hba);
 774                 tag = le16_to_cpu(resp->tag);
 775                 if (unlikely(tag >= hba->host->can_queue)) {
 776                         printk(KERN_WARNING DRV_NAME
 777                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 778                         continue;
 779                 }
 780
 781                 ccb = &hba->ccb[tag];
 782                 if (hba->wait_ccb == ccb)
 783                         hba->wait_ccb = NULL;
 784                 if (unlikely(ccb->req == NULL)) {
 785                         printk(KERN_WARNING DRV_NAME
 786                                 "(%s): lagging req\n", pci_name(hba->pdev));
 787                         hba->out_req_cnt--;
 788                         continue;
 789                 }
 790
 791                 size = resp->payload_sz * sizeof(u32); /* payload size */
 792                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 793                         size > sizeof(*resp))) {
 794                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 795                                 pci_name(hba->pdev));
 796                 } else {
 797                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 798                         if (size)
 799                                 stex_copy_data(ccb, resp, size);
 800                 }
 801
 802                 ccb->srb_status = resp->srb_status;
 803                 ccb->scsi_status = resp->scsi_status;
 804
 805                 if (likely(ccb->cmd != NULL)) {
 806                         if (hba->cardtype == st_yosemite)
 807                                 stex_ys_commands(hba, ccb, resp);
 808
 809                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 810                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 811                                 stex_controller_info(hba, ccb);
 812
 813                         scsi_dma_unmap(ccb->cmd);
 814                         stex_scsi_done(ccb);
 815                         hba->out_req_cnt--;
 816                 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
 817                         hba->out_req_cnt--;
 818                         if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
 819                                 ccb->req_type = 0;
 820                                 continue;
 821                         }
 822                         ccb->req_type = 0;
 823                         if (waitqueue_active(&hba->waitq))
 824                                 wake_up(&hba->waitq);
 825                 }
 826         }
 827
 828 update_status:
 829         writel(hba->status_head, base + IMR1);
 830         readl(base + IMR1); /* flush */
 831 }
 832
 833 static irqreturn_t stex_intr(int irq, void *__hba)
 834 {
 835         struct st_hba *hba = __hba;
 836         void __iomem *base = hba->mmio_base;
 837         u32 data;
 838         unsigned long flags;
 839         int handled = 0;
 840
 841         spin_lock_irqsave(hba->host->host_lock, flags);
 842
 843         data = readl(base + ODBL);
 844
 845         if (data && data != 0xffffffff) {
 846                 /* clear the interrupt */
 847                 writel(data, base + ODBL);
 848                 readl(base + ODBL); /* flush */
 849                 stex_mu_intr(hba, data);
 850                 handled = 1;
 851         }
 852
 853         spin_unlock_irqrestore(hba->host->host_lock, flags);
 854
 855         return IRQ_RETVAL(handled);
 856 }
 857
 858 static int stex_handshake(struct st_hba *hba)
 859 {
 860         void __iomem *base = hba->mmio_base;
 861         struct handshake_frame *h;
 862         dma_addr_t status_phys;
 863         u32 data;
 864         unsigned long before;
 865
 866         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 867                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 868                 readl(base + IDBL);
 869                 before = jiffies;
 870                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 871                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 872                                 printk(KERN_ERR DRV_NAME
 873                                         "(%s): no handshake signature\n",
 874                                         pci_name(hba->pdev));
 875                                 return -1;
 876                         }
 877                         rmb();
 878                         msleep(1);
 879                 }
 880         }
 881
 882         udelay(10);
 883
 884         data = readl(base + OMR1);
 885         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 886                 data &= 0x0000ffff;
 887                 if (hba->host->can_queue > data)
 888                         hba->host->can_queue = data;
 889         }
 890
 891         h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
 892         h->rb_phy = cpu_to_le32(hba->dma_handle);
 893         h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
 894         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 895         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 896         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 897         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 898         stex_gettime(&h->hosttime);
 899         h->partner_type = HMU_PARTNER_TYPE;
 900         if (hba->dma_size > STEX_BUFFER_SIZE) {
 901                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
 902                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
 903         } else
 904                 h->extra_offset = h->extra_size = 0;
 905
 906         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 907         writel(status_phys, base + IMR0);
 908         readl(base + IMR0);
 909         writel((status_phys >> 16) >> 16, base + IMR1);
 910         readl(base + IMR1);
 911
 912         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 913         readl(base + OMR0);
 914         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 915         readl(base + IDBL); /* flush */
 916
 917         udelay(10);
 918         before = jiffies;
 919         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 920                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 921                         printk(KERN_ERR DRV_NAME
 922                                 "(%s): no signature after handshake frame\n",
 923                                 pci_name(hba->pdev));
 924                         return -1;
 925                 }
 926                 rmb();
 927                 msleep(1);
 928         }
 929
 930         writel(0, base + IMR0);
 931         readl(base + IMR0);
 932         writel(0, base + OMR0);
 933         readl(base + OMR0);
 934         writel(0, base + IMR1);
 935         readl(base + IMR1);
 936         writel(0, base + OMR1);
 937         readl(base + OMR1); /* flush */
 938         hba->mu_status = MU_STATE_STARTED;
 939         return 0;
 940 }
 941
 942 static int stex_abort(struct scsi_cmnd *cmd)
 943 {
 944         struct Scsi_Host *host = cmd->device->host;
 945         struct st_hba *hba = (struct st_hba *)host->hostdata;
 946         u16 tag = cmd->request->tag;
 947         void __iomem *base;
 948         u32 data;
 949         int result = SUCCESS;
 950         unsigned long flags;
 951
 952         printk(KERN_INFO DRV_NAME
 953                 "(%s): aborting command\n", pci_name(hba->pdev));
 954         scsi_print_command(cmd);
 955
 956         base = hba->mmio_base;
 957         spin_lock_irqsave(host->host_lock, flags);
 958         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
 959                 hba->wait_ccb = &hba->ccb[tag];
 960         else {
 961                 for (tag = 0; tag < host->can_queue; tag++)
 962                         if (hba->ccb[tag].cmd == cmd) {
 963                                 hba->wait_ccb = &hba->ccb[tag];
 964                                 break;
 965                         }
 966                 if (tag >= host->can_queue)
 967                         goto out;
 968         }
 969
 970         data = readl(base + ODBL);
 971         if (data == 0 || data == 0xffffffff)
 972                 goto fail_out;
 973
 974         writel(data, base + ODBL);
 975         readl(base + ODBL); /* flush */
 976
 977         stex_mu_intr(hba, data);
 978
 979         if (hba->wait_ccb == NULL) {
 980                 printk(KERN_WARNING DRV_NAME
 981                         "(%s): lost interrupt\n", pci_name(hba->pdev));
 982                 goto out;
 983         }
 984
 985 fail_out:
 986         scsi_dma_unmap(cmd);
 987         hba->wait_ccb->req = NULL; /* nullify the req's future return */
 988         hba->wait_ccb = NULL;
 989         result = FAILED;
 990 out:
 991         spin_unlock_irqrestore(host->host_lock, flags);
 992         return result;
 993 }
 994
 995 static void stex_hard_reset(struct st_hba *hba)
 996 {
 997         struct pci_bus *bus;
 998         int i;
 999         u16 pci_cmd;
1000         u8 pci_bctl;
1001
1002         for (i = 0; i < 16; i++)
1003                 pci_read_config_dword(hba->pdev, i * 4,
1004                         &hba->pdev->saved_config_space[i]);
1005
1006         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1007            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1008         bus = hba->pdev->bus;
1009         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1010         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1011         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1012
1013         /*
1014          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1015          * require more time to finish bus reset. Use 100 ms here for safety
1016          */
1017         msleep(100);
1018         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1019         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1020
1021         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1022                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1023                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1024                         break;
1025                 msleep(1);
1026         }
1027
1028         ssleep(5);
1029         for (i = 0; i < 16; i++)
1030                 pci_write_config_dword(hba->pdev, i * 4,
1031                         hba->pdev->saved_config_space[i]);
1032 }
1033
1034 static int stex_reset(struct scsi_cmnd *cmd)
1035 {
1036         struct st_hba *hba;
1037         unsigned long flags;
1038         unsigned long before;
1039         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1040
1041         printk(KERN_INFO DRV_NAME
1042                 "(%s): resetting host\n", pci_name(hba->pdev));
1043         scsi_print_command(cmd);
1044
1045         hba->mu_status = MU_STATE_RESETTING;
1046
1047         if (hba->cardtype == st_shasta)
1048                 stex_hard_reset(hba);
1049
1050         if (hba->cardtype != st_yosemite) {
1051                 if (stex_handshake(hba)) {
1052                         printk(KERN_WARNING DRV_NAME
1053                                 "(%s): resetting: handshake failed\n",
1054                                 pci_name(hba->pdev));
1055                         return FAILED;
1056                 }
1057                 spin_lock_irqsave(hba->host->host_lock, flags);
1058                 hba->req_head = 0;
1059                 hba->req_tail = 0;
1060                 hba->status_head = 0;
1061                 hba->status_tail = 0;
1062                 hba->out_req_cnt = 0;
1063                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1064                 return SUCCESS;
1065         }
1066
1067         /* st_yosemite */
1068         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1069         readl(hba->mmio_base + IDBL); /* flush */
1070         before = jiffies;
1071         while (hba->out_req_cnt > 0) {
1072                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1073                         printk(KERN_WARNING DRV_NAME
1074                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1075                         return FAILED;
1076                 }
1077                 msleep(1);
1078         }
1079
1080         hba->mu_status = MU_STATE_STARTED;
1081         return SUCCESS;
1082 }
1083
1084 static int stex_biosparam(struct scsi_device *sdev,
1085         struct block_device *bdev, sector_t capacity, int geom[])
1086 {
1087         int heads = 255, sectors = 63;
1088
1089         if (capacity < 0x200000) {
1090                 heads = 64;
1091                 sectors = 32;
1092         }
1093
1094         sector_div(capacity, heads * sectors);
1095
1096         geom[0] = heads;
1097         geom[1] = sectors;
1098         geom[2] = capacity;
1099
1100         return 0;
1101 }
1102
1103 static struct scsi_host_template driver_template = {
1104         .module                         = THIS_MODULE,
1105         .name                           = DRV_NAME,
1106         .proc_name                      = DRV_NAME,
1107         .bios_param                     = stex_biosparam,
1108         .queuecommand                   = stex_queuecommand,
1109         .slave_alloc                    = stex_slave_alloc,
1110         .slave_configure                = stex_slave_config,
1111         .slave_destroy                  = stex_slave_destroy,
1112         .eh_abort_handler               = stex_abort,
1113         .eh_host_reset_handler          = stex_reset,
1114         .can_queue                      = ST_CAN_QUEUE,
1115         .this_id                        = -1,
1116         .sg_tablesize                   = ST_MAX_SG,
1117         .cmd_per_lun                    = ST_CMD_PER_LUN,
1118 };
1119
1120 static int stex_set_dma_mask(struct pci_dev * pdev)
1121 {
1122         int ret;
1123         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1124                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1125                 return 0;
1126         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1127         if (!ret)
1128                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1129         return ret;
1130 }
1131
1132 static int __devinit
1133 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1134 {
1135         struct st_hba *hba;
1136         struct Scsi_Host *host;
1137         int err;
1138
1139         err = pci_enable_device(pdev);
1140         if (err)
1141                 return err;
1142
1143         pci_set_master(pdev);
1144
1145         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1146
1147         if (!host) {
1148                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1149                         pci_name(pdev));
1150                 err = -ENOMEM;
1151                 goto out_disable;
1152         }
1153
1154         hba = (struct st_hba *)host->hostdata;
1155         memset(hba, 0, sizeof(struct st_hba));
1156
1157         err = pci_request_regions(pdev, DRV_NAME);
1158         if (err < 0) {
1159                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1160                         pci_name(pdev));
1161                 goto out_scsi_host_put;
1162         }
1163
1164         hba->mmio_base = ioremap_nocache(pci_resource_start(pdev, 0),
1165                 pci_resource_len(pdev, 0));
1166         if ( !hba->mmio_base) {
1167                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1168                         pci_name(pdev));
1169                 err = -ENOMEM;
1170                 goto out_release_regions;
1171         }
1172
1173         err = stex_set_dma_mask(pdev);
1174         if (err) {
1175                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1176                         pci_name(pdev));
1177                 goto out_iounmap;
1178         }
1179
1180         hba->cardtype = (unsigned int) id->driver_data;
1181         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1182                 hba->cardtype = st_vsc1;
1183         hba->dma_size = (hba->cardtype == st_vsc1) ?
1184                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1185         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1186                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1187         if (!hba->dma_mem) {
1188                 err = -ENOMEM;
1189                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1190                         pci_name(pdev));
1191                 goto out_iounmap;
1192         }
1193
1194         hba->status_buffer =
1195                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1196         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1197         hba->mu_status = MU_STATE_STARTING;
1198
1199         if (hba->cardtype == st_shasta) {
1200                 host->max_lun = 8;
1201                 host->max_id = 16 + 1;
1202         } else if (hba->cardtype == st_yosemite) {
1203                 host->max_lun = 128;
1204                 host->max_id = 1 + 1;
1205         } else {
1206                 /* st_vsc and st_vsc1 */
1207                 host->max_lun = 1;
1208                 host->max_id = 128 + 1;
1209         }
1210         host->max_channel = 0;
1211         host->unique_id = host->host_no;
1212         host->max_cmd_len = STEX_CDB_LENGTH;
1213
1214         hba->host = host;
1215         hba->pdev = pdev;
1216         init_waitqueue_head(&hba->waitq);
1217
1218         err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1219         if (err) {
1220                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1221                         pci_name(pdev));
1222                 goto out_pci_free;
1223         }
1224
1225         err = stex_handshake(hba);
1226         if (err)
1227                 goto out_free_irq;
1228
1229         err = scsi_init_shared_tag_map(host, host->can_queue);
1230         if (err) {
1231                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1232                         pci_name(pdev));
1233                 goto out_free_irq;
1234         }
1235
1236         pci_set_drvdata(pdev, hba);
1237
1238         err = scsi_add_host(host, &pdev->dev);
1239         if (err) {
1240                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1241                         pci_name(pdev));
1242                 goto out_free_irq;
1243         }
1244
1245         scsi_scan_host(host);
1246
1247         return 0;
1248
1249 out_free_irq:
1250         free_irq(pdev->irq, hba);
1251 out_pci_free:
1252         dma_free_coherent(&pdev->dev, hba->dma_size,
1253                           hba->dma_mem, hba->dma_handle);
1254 out_iounmap:
1255         iounmap(hba->mmio_base);
1256 out_release_regions:
1257         pci_release_regions(pdev);
1258 out_scsi_host_put:
1259         scsi_host_put(host);
1260 out_disable:
1261         pci_disable_device(pdev);
1262
1263         return err;
1264 }
1265
1266 static void stex_hba_stop(struct st_hba *hba)
1267 {
1268         struct req_msg *req;
1269         unsigned long flags;
1270         unsigned long before;
1271         u16 tag = 0;
1272
1273         spin_lock_irqsave(hba->host->host_lock, flags);
1274         req = stex_alloc_req(hba);
1275         memset(req->cdb, 0, STEX_CDB_LENGTH);
1276
1277         if (hba->cardtype == st_yosemite) {
1278                 req->cdb[0] = MGT_CMD;
1279                 req->cdb[1] = MGT_CMD_SIGNATURE;
1280                 req->cdb[2] = CTLR_CONFIG_CMD;
1281                 req->cdb[3] = CTLR_SHUTDOWN;
1282         } else {
1283                 req->cdb[0] = CONTROLLER_CMD;
1284                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1285                 req->cdb[2] = CTLR_POWER_SAVING;
1286         }
1287
1288         hba->ccb[tag].cmd = NULL;
1289         hba->ccb[tag].sg_count = 0;
1290         hba->ccb[tag].sense_bufflen = 0;
1291         hba->ccb[tag].sense_buffer = NULL;
1292         hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1293
1294         stex_send_cmd(hba, req, tag);
1295         spin_unlock_irqrestore(hba->host->host_lock, flags);
1296
1297         before = jiffies;
1298         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1299                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1300                         return;
1301                 msleep(10);
1302         }
1303 }
1304
1305 static void stex_hba_free(struct st_hba *hba)
1306 {
1307         free_irq(hba->pdev->irq, hba);
1308
1309         iounmap(hba->mmio_base);
1310
1311         pci_release_regions(hba->pdev);
1312
1313         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1314                           hba->dma_mem, hba->dma_handle);
1315 }
1316
1317 static void stex_remove(struct pci_dev *pdev)
1318 {
1319         struct st_hba *hba = pci_get_drvdata(pdev);
1320
1321         scsi_remove_host(hba->host);
1322
1323         pci_set_drvdata(pdev, NULL);
1324
1325         stex_hba_stop(hba);
1326
1327         stex_hba_free(hba);
1328
1329         scsi_host_put(hba->host);
1330
1331         pci_disable_device(pdev);
1332 }
1333
1334 static void stex_shutdown(struct pci_dev *pdev)
1335 {
1336         struct st_hba *hba = pci_get_drvdata(pdev);
1337
1338         stex_hba_stop(hba);
1339 }
1340
1341 static struct pci_device_id stex_pci_tbl[] = {
1342         /* st_shasta */
1343         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1344                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1345         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1346                 st_shasta }, /* SuperTrak EX12350 */
1347         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1348                 st_shasta }, /* SuperTrak EX4350 */
1349         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1350                 st_shasta }, /* SuperTrak EX24350 */
1351
1352         /* st_vsc */
1353         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1354
1355         /* st_yosemite */
1356         { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1357                 st_yosemite }, /* SuperTrak EX4650 */
1358         { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1359                 st_yosemite }, /* SuperTrak EX4650o */
1360         { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1361                 st_yosemite }, /* SuperTrak EX8650EL */
1362         { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1363                 st_yosemite }, /* SuperTrak EX8650 */
1364         { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1365                 st_yosemite }, /* SuperTrak EX8654 */
1366         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1367                 st_yosemite }, /* generic st_yosemite */
1368         { }     /* terminate list */
1369 };
1370 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1371
1372 static struct pci_driver stex_pci_driver = {
1373         .name           = DRV_NAME,
1374         .id_table       = stex_pci_tbl,
1375         .probe          = stex_probe,
1376         .remove         = __devexit_p(stex_remove),
1377         .shutdown       = stex_shutdown,
1378 };
1379
1380 static int __init stex_init(void)
1381 {
1382         printk(KERN_INFO DRV_NAME
1383                 ": Promise SuperTrak EX Driver version: %s\n",
1384                  ST_DRIVER_VERSION);
1385
1386         return pci_register_driver(&stex_pci_driver);
1387 }
1388
1389 static void __exit stex_exit(void)
1390 {
1391         pci_unregister_driver(&stex_pci_driver);
1392 }
1393
1394 module_init(stex_init);
1395 module_exit(stex_exit);