drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_INVLD_DQE_INFO              0x148
  59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  62 #define INT_COAL_EN                     0x19c
  63 #define OQ_INT_COAL_TIME                0x1a0
  64 #define OQ_INT_COAL_CNT                 0x1a4
  65 #define ENT_INT_COAL_TIME               0x1a8
  66 #define ENT_INT_COAL_CNT                0x1ac
  67 #define OQ_INT_SRC                      0x1b0
  68 #define OQ_INT_SRC_MSK                  0x1b4
  69 #define ENT_INT_SRC1                    0x1b8
  70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  74 #define ENT_INT_SRC2                    0x1bc
  75 #define ENT_INT_SRC3                    0x1c0
  76 #define ENT_INT_SRC3_ITC_INT_OFF        15
  77 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  78 #define ENT_INT_SRC_MSK1                0x1c4
  79 #define ENT_INT_SRC_MSK2                0x1c8
  80 #define ENT_INT_SRC_MSK3                0x1cc
  81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  83 #define SAS_ECC_INTR_MSK                0x1ec
  84 #define HGC_ERR_STAT_EN                 0x238
  85 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  86 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  87 #define DLVRY_Q_0_DEPTH                 0x268
  88 #define DLVRY_Q_0_WR_PTR                0x26c
  89 #define DLVRY_Q_0_RD_PTR                0x270
  90 #define HYPER_STREAM_ID_EN_CFG          0xc80
  91 #define OQ0_INT_SRC_MSK                 0xc90
  92 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
  93 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
  94 #define COMPL_Q_0_DEPTH                 0x4e8
  95 #define COMPL_Q_0_WR_PTR                0x4ec
  96 #define COMPL_Q_0_RD_PTR                0x4f0
  97
  98 /* phy registers need init */
  99 #define PORT_BASE                       (0x2000)
 100
 101 #define PHY_CFG                         (PORT_BASE + 0x0)
 102 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 103 #define PHY_CFG_ENA_OFF                 0
 104 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 105 #define PHY_CFG_DC_OPT_OFF              2
 106 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 107 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 108 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 109 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 110 #define PHY_CTRL                        (PORT_BASE + 0x14)
 111 #define PHY_CTRL_RESET_OFF              0
 112 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 113 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 114 #define SL_CFG                          (PORT_BASE + 0x84)
 115 #define PHY_PCN                         (PORT_BASE + 0x44)
 116 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 117 #define SL_CONTROL                      (PORT_BASE + 0x94)
 118 #define SL_CONTROL_NOTIFY_EN_OFF        0
 119 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 120 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 121 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 122 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 123 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 124 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 125 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 126 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 127 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 128 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 129 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 130 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 131 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 132 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 133 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 134 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 135 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 136 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 137 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 138 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 139 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 140 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 141 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 142 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 143 #define CHL_INT0_NOT_RDY_OFF            4
 144 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 145 #define CHL_INT0_PHY_RDY_OFF            5
 146 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 147 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 148 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 149 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 150 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 151 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 152 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 153 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 154 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 155 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 156 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 157 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 158 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 159 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 160 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 161 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 162 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 163 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 164 #define DMA_TX_STATUS_BUSY_OFF          0
 165 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 166 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 167 #define DMA_RX_STATUS_BUSY_OFF          0
 168 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 169
 170 #define AXI_CFG                         (0x5100)
 171 #define AM_CFG_MAX_TRANS                (0x5010)
 172 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 173
 174 /* HW dma structures */
 175 /* Delivery queue header */
 176 /* dw0 */
 177 #define CMD_HDR_RESP_REPORT_OFF         5
 178 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 179 #define CMD_HDR_TLR_CTRL_OFF            6
 180 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 181 #define CMD_HDR_PORT_OFF                18
 182 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 183 #define CMD_HDR_PRIORITY_OFF            27
 184 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 185 #define CMD_HDR_CMD_OFF                 29
 186 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 187 /* dw1 */
 188 #define CMD_HDR_DIR_OFF                 5
 189 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 190 #define CMD_HDR_RESET_OFF               7
 191 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 192 #define CMD_HDR_VDTL_OFF                10
 193 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 194 #define CMD_HDR_FRAME_TYPE_OFF          11
 195 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 196 #define CMD_HDR_DEV_ID_OFF              16
 197 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 198 /* dw2 */
 199 #define CMD_HDR_CFL_OFF                 0
 200 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 201 #define CMD_HDR_NCQ_TAG_OFF             10
 202 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 203 #define CMD_HDR_MRFL_OFF                15
 204 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 205 #define CMD_HDR_SG_MOD_OFF              24
 206 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 207 #define CMD_HDR_FIRST_BURST_OFF         26
 208 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 209 /* dw3 */
 210 #define CMD_HDR_IPTT_OFF                0
 211 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 212 /* dw6 */
 213 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 214 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 215 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 216 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 217
 218 /* Completion header */
 219 /* dw0 */
 220 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 221 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 222 #define CMPLT_HDR_ERX_OFF               12
 223 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 224 /* dw1 */
 225 #define CMPLT_HDR_IPTT_OFF              0
 226 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 227 #define CMPLT_HDR_DEV_ID_OFF            16
 228 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 229
 230 /* ITCT header */
 231 /* qw0 */
 232 #define ITCT_HDR_DEV_TYPE_OFF           0
 233 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 234 #define ITCT_HDR_VALID_OFF              2
 235 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 236 #define ITCT_HDR_MCR_OFF                5
 237 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 238 #define ITCT_HDR_VLN_OFF                9
 239 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 240 #define ITCT_HDR_PORT_ID_OFF            28
 241 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 242 /* qw2 */
 243 #define ITCT_HDR_INLT_OFF               0
 244 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 245 #define ITCT_HDR_BITLT_OFF              16
 246 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 247 #define ITCT_HDR_MCTLT_OFF              32
 248 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 249 #define ITCT_HDR_RTOLT_OFF              48
 250 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 251
 252 struct hisi_sas_complete_v2_hdr {
 253         __le32 dw0;
 254         __le32 dw1;
 255         __le32 act;
 256         __le32 dw3;
 257 };
 258
 259 enum {
 260         HISI_SAS_PHY_PHY_UPDOWN,
 261         HISI_SAS_PHY_CHNL_INT,
 262         HISI_SAS_PHY_INT_NR
 263 };
 264
 265 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 266
 267 #define DIR_NO_DATA 0
 268 #define DIR_TO_INI 1
 269 #define DIR_TO_DEVICE 2
 270 #define DIR_RESERVED 3
 271
 272 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 273 {
 274         void __iomem *regs = hisi_hba->regs + off;
 275
 276         return readl(regs);
 277 }
 278
 279 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 280 {
 281         void __iomem *regs = hisi_hba->regs + off;
 282
 283         return readl_relaxed(regs);
 284 }
 285
 286 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 287 {
 288         void __iomem *regs = hisi_hba->regs + off;
 289
 290         writel(val, regs);
 291 }
 292
 293 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 294                                  u32 off, u32 val)
 295 {
 296         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 297
 298         writel(val, regs);
 299 }
 300
 301 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 302                                       int phy_no, u32 off)
 303 {
 304         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 305
 306         return readl(regs);
 307 }
 308
 309 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 310 {
 311         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 312
 313         cfg &= ~PHY_CFG_DC_OPT_MSK;
 314         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 315         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 316 }
 317
 318 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 319 {
 320         struct sas_identify_frame identify_frame;
 321         u32 *identify_buffer;
 322
 323         memset(&identify_frame, 0, sizeof(identify_frame));
 324         identify_frame.dev_type = SAS_END_DEVICE;
 325         identify_frame.frame_type = 0;
 326         identify_frame._un1 = 1;
 327         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 328         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 329         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 330         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 331         identify_frame.phy_id = phy_no;
 332         identify_buffer = (u32 *)(&identify_frame);
 333
 334         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 335                         __swab32(identify_buffer[0]));
 336         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 337                         identify_buffer[2]);
 338         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 339                         identify_buffer[1]);
 340         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 341                         identify_buffer[4]);
 342         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 343                         identify_buffer[3]);
 344         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 345                         __swab32(identify_buffer[5]));
 346 }
 347
 348 static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
 349 {
 350         int i;
 351
 352         for (i = 0; i < hisi_hba->n_phy; i++)
 353                 config_id_frame_v2_hw(hisi_hba, i);
 354 }
 355
 356 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
 357 {
 358         int i, reset_val;
 359         u32 val;
 360         unsigned long end_time;
 361         struct device *dev = &hisi_hba->pdev->dev;
 362
 363         /* The mask needs to be set depending on the number of phys */
 364         if (hisi_hba->n_phy == 9)
 365                 reset_val = 0x1fffff;
 366         else
 367                 reset_val = 0x7ffff;
 368
 369         /* Disable all of the DQ */
 370         for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
 371                 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 372
 373         /* Disable all of the PHYs */
 374         for (i = 0; i < hisi_hba->n_phy; i++) {
 375                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
 376
 377                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
 378                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
 379         }
 380         udelay(50);
 381
 382         /* Ensure DMA tx & rx idle */
 383         for (i = 0; i < hisi_hba->n_phy; i++) {
 384                 u32 dma_tx_status, dma_rx_status;
 385
 386                 end_time = jiffies + msecs_to_jiffies(1000);
 387
 388                 while (1) {
 389                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 390                                                             DMA_TX_STATUS);
 391                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 392                                                             DMA_RX_STATUS);
 393
 394                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 395                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 396                                 break;
 397
 398                         msleep(20);
 399                         if (time_after(jiffies, end_time))
 400                                 return -EIO;
 401                 }
 402         }
 403
 404         /* Ensure axi bus idle */
 405         end_time = jiffies + msecs_to_jiffies(1000);
 406         while (1) {
 407                 u32 axi_status =
 408                         hisi_sas_read32(hisi_hba, AXI_CFG);
 409
 410                 if (axi_status == 0)
 411                         break;
 412
 413                 msleep(20);
 414                 if (time_after(jiffies, end_time))
 415                         return -EIO;
 416         }
 417
 418         /* reset and disable clock*/
 419         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 420                         reset_val);
 421         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 422                         reset_val);
 423         msleep(1);
 424         regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 425         if (reset_val != (val & reset_val)) {
 426                 dev_err(dev, "SAS reset fail.\n");
 427                 return -EIO;
 428         }
 429
 430         /* De-reset and enable clock*/
 431         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 432                         reset_val);
 433         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 434                         reset_val);
 435         msleep(1);
 436         regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
 437                         &val);
 438         if (val & reset_val) {
 439                 dev_err(dev, "SAS de-reset fail.\n");
 440                 return -EIO;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
 447 {
 448         struct device *dev = &hisi_hba->pdev->dev;
 449         struct device_node *np = dev->of_node;
 450         int i;
 451
 452         /* Global registers init */
 453
 454         /* Deal with am-max-transmissions quirk */
 455         if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
 456                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
 457                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
 458                                  0x2020);
 459         } /* Else, use defaults -> do nothing */
 460
 461         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 462                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 463         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
 464         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
 465         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 466         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
 467         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
 468         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
 469         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
 470         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
 471         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 472         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
 473         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 474         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 475         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 476         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 477         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 478         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 479         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
 480         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 481         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 482         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 483         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
 484         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
 485         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
 486         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
 487         for (i = 0; i < hisi_hba->queue_count; i++)
 488                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 489
 490         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
 491         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 492
 493         for (i = 0; i < hisi_hba->n_phy; i++) {
 494                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
 495                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
 496                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 497                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
 498                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 499                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 500                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 501                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 502                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
 503                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
 504                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
 505                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 506                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 507                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 508                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 509                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 510                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
 511                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
 512                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
 513         }
 514
 515         for (i = 0; i < hisi_hba->queue_count; i++) {
 516                 /* Delivery queue */
 517                 hisi_sas_write32(hisi_hba,
 518                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 519                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 520
 521                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 522                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 523
 524                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 525                                  HISI_SAS_QUEUE_SLOTS);
 526
 527                 /* Completion queue */
 528                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 529                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 530
 531                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 532                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 533
 534                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 535                                  HISI_SAS_QUEUE_SLOTS);
 536         }
 537
 538         /* itct */
 539         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 540                          lower_32_bits(hisi_hba->itct_dma));
 541
 542         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 543                          upper_32_bits(hisi_hba->itct_dma));
 544
 545         /* iost */
 546         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 547                          lower_32_bits(hisi_hba->iost_dma));
 548
 549         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 550                          upper_32_bits(hisi_hba->iost_dma));
 551
 552         /* breakpoint */
 553         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 554                          lower_32_bits(hisi_hba->breakpoint_dma));
 555
 556         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 557                          upper_32_bits(hisi_hba->breakpoint_dma));
 558
 559         /* SATA broken msg */
 560         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 561                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 562
 563         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 564                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 565
 566         /* SATA initial fis */
 567         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 568                          lower_32_bits(hisi_hba->initial_fis_dma));
 569
 570         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 571                          upper_32_bits(hisi_hba->initial_fis_dma));
 572 }
 573
 574 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
 575 {
 576         struct device *dev = &hisi_hba->pdev->dev;
 577         int rc;
 578
 579         rc = reset_hw_v2_hw(hisi_hba);
 580         if (rc) {
 581                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 582                 return rc;
 583         }
 584
 585         msleep(100);
 586         init_reg_v2_hw(hisi_hba);
 587
 588         init_id_frame_v2_hw(hisi_hba);
 589
 590         return 0;
 591 }
 592
 593 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 594 {
 595         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 596
 597         cfg |= PHY_CFG_ENA_MSK;
 598         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 599 }
 600
 601 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 602 {
 603         config_id_frame_v2_hw(hisi_hba, phy_no);
 604         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
 605         enable_phy_v2_hw(hisi_hba, phy_no);
 606 }
 607
 608 static void start_phys_v2_hw(unsigned long data)
 609 {
 610         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
 611         int i;
 612
 613         for (i = 0; i < hisi_hba->n_phy; i++)
 614                 start_phy_v2_hw(hisi_hba, i);
 615 }
 616
 617 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
 618 {
 619         int i;
 620         struct timer_list *timer = &hisi_hba->timer;
 621
 622         for (i = 0; i < hisi_hba->n_phy; i++) {
 623                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
 624                 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
 625         }
 626
 627         setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
 628         mod_timer(timer, jiffies + HZ);
 629 }
 630
 631 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 632 {
 633         u32 sl_control;
 634
 635         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 636         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 637         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 638         msleep(1);
 639         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 640         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 641         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 642 }
 643
 644 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
 645 {
 646         int i, bitmap = 0;
 647         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 648         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 649
 650         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
 651                 if (phy_state & 1 << i)
 652                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 653                                 bitmap |= 1 << i;
 654
 655         if (hisi_hba->n_phy == 9) {
 656                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
 657
 658                 if (phy_state & 1 << 8)
 659                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
 660                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
 661                                 bitmap |= 1 << 9;
 662         }
 663
 664         return bitmap;
 665 }
 666
 667 /**
 668  * This function allocates across all queues to load balance.
 669  * Slots are allocated from queues in a round-robin fashion.
 670  *
 671  * The callpath to this function and upto writing the write
 672  * queue pointer should be safe from interruption.
 673  */
 674 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
 675 {
 676         struct device *dev = &hisi_hba->pdev->dev;
 677         u32 r, w;
 678         int queue = hisi_hba->queue;
 679
 680         while (1) {
 681                 w = hisi_sas_read32_relaxed(hisi_hba,
 682                                             DLVRY_Q_0_WR_PTR + (queue * 0x14));
 683                 r = hisi_sas_read32_relaxed(hisi_hba,
 684                                             DLVRY_Q_0_RD_PTR + (queue * 0x14));
 685                 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 686                         queue = (queue + 1) % hisi_hba->queue_count;
 687                         if (queue == hisi_hba->queue) {
 688                                 dev_warn(dev, "could not find free slot\n");
 689                                 return -EAGAIN;
 690                         }
 691                         continue;
 692                 }
 693                 break;
 694         }
 695         hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
 696         *q = queue;
 697         *s = w;
 698         return 0;
 699 }
 700
 701 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
 702 {
 703         int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
 704         int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
 705
 706         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
 707                          ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
 708 }
 709
 710 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
 711                               struct hisi_sas_slot *slot,
 712                               struct hisi_sas_cmd_hdr *hdr,
 713                               struct scatterlist *scatter,
 714                               int n_elem)
 715 {
 716         struct device *dev = &hisi_hba->pdev->dev;
 717         struct scatterlist *sg;
 718         int i;
 719
 720         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
 721                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
 722                         n_elem);
 723                 return -EINVAL;
 724         }
 725
 726         slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
 727                                         &slot->sge_page_dma);
 728         if (!slot->sge_page)
 729                 return -ENOMEM;
 730
 731         for_each_sg(scatter, sg, n_elem, i) {
 732                 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
 733
 734                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 735                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 736                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 737                 entry->data_off = 0;
 738         }
 739
 740         hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
 741
 742         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 743
 744         return 0;
 745 }
 746
 747 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
 748                           struct hisi_sas_slot *slot, int is_tmf,
 749                           struct hisi_sas_tmf_task *tmf)
 750 {
 751         struct sas_task *task = slot->task;
 752         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 753         struct domain_device *device = task->dev;
 754         struct hisi_sas_device *sas_dev = device->lldd_dev;
 755         struct hisi_sas_port *port = slot->port;
 756         struct sas_ssp_task *ssp_task = &task->ssp_task;
 757         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
 758         int has_data = 0, rc, priority = is_tmf;
 759         u8 *buf_cmd;
 760         u32 dw1 = 0, dw2 = 0;
 761
 762         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
 763                                (2 << CMD_HDR_TLR_CTRL_OFF) |
 764                                (port->id << CMD_HDR_PORT_OFF) |
 765                                (priority << CMD_HDR_PRIORITY_OFF) |
 766                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
 767
 768         dw1 = 1 << CMD_HDR_VDTL_OFF;
 769         if (is_tmf) {
 770                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
 771                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
 772         } else {
 773                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
 774                 switch (scsi_cmnd->sc_data_direction) {
 775                 case DMA_TO_DEVICE:
 776                         has_data = 1;
 777                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
 778                         break;
 779                 case DMA_FROM_DEVICE:
 780                         has_data = 1;
 781                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
 782                         break;
 783                 default:
 784                         dw1 &= ~CMD_HDR_DIR_MSK;
 785                 }
 786         }
 787
 788         /* map itct entry */
 789         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
 790         hdr->dw1 = cpu_to_le32(dw1);
 791
 792         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
 793               + 3) / 4) << CMD_HDR_CFL_OFF) |
 794               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
 795               (2 << CMD_HDR_SG_MOD_OFF);
 796         hdr->dw2 = cpu_to_le32(dw2);
 797
 798         hdr->transfer_tags = cpu_to_le32(slot->idx);
 799
 800         if (has_data) {
 801                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
 802                                         slot->n_elem);
 803                 if (rc)
 804                         return rc;
 805         }
 806
 807         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
 808         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
 809         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
 810
 811         buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
 812
 813         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
 814         if (!is_tmf) {
 815                 buf_cmd[9] = task->ssp_task.task_attr |
 816                                 (task->ssp_task.task_prio << 3);
 817                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
 818                                 task->ssp_task.cmd->cmd_len);
 819         } else {
 820                 buf_cmd[10] = tmf->tmf;
 821                 switch (tmf->tmf) {
 822                 case TMF_ABORT_TASK:
 823                 case TMF_QUERY_TASK:
 824                         buf_cmd[12] =
 825                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
 826                         buf_cmd[13] =
 827                                 tmf->tag_of_task_to_be_managed & 0xff;
 828                         break;
 829                 default:
 830                         break;
 831                 }
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int
 838 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
 839                     int abort)
 840 {
 841         struct sas_task *task = slot->task;
 842         struct hisi_sas_device *sas_dev;
 843         struct device *dev = &hisi_hba->pdev->dev;
 844         struct task_status_struct *ts;
 845         struct domain_device *device;
 846         enum exec_status sts;
 847         struct hisi_sas_complete_v2_hdr *complete_queue =
 848                         hisi_hba->complete_hdr[slot->cmplt_queue];
 849         struct hisi_sas_complete_v2_hdr *complete_hdr =
 850                         &complete_queue[slot->cmplt_queue_slot];
 851
 852         if (unlikely(!task || !task->lldd_task || !task->dev))
 853                 return -EINVAL;
 854
 855         ts = &task->task_status;
 856         device = task->dev;
 857         sas_dev = device->lldd_dev;
 858
 859         task->task_state_flags &=
 860                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
 861         task->task_state_flags |= SAS_TASK_STATE_DONE;
 862
 863         memset(ts, 0, sizeof(*ts));
 864         ts->resp = SAS_TASK_COMPLETE;
 865
 866         if (unlikely(!sas_dev || abort)) {
 867                 if (!sas_dev)
 868                         dev_dbg(dev, "slot complete: port has not device\n");
 869                 ts->stat = SAS_PHY_DOWN;
 870                 goto out;
 871         }
 872
 873         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
 874                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
 875                 dev_dbg(dev, "%s slot %d has error info 0x%x\n",
 876                         __func__, slot->cmplt_queue_slot,
 877                         complete_hdr->dw0 & CMPLT_HDR_ERX_MSK);
 878
 879                 goto out;
 880         }
 881
 882         switch (task->task_proto) {
 883         case SAS_PROTOCOL_SSP:
 884         {
 885                 struct ssp_response_iu *iu = slot->status_buffer +
 886                         sizeof(struct hisi_sas_err_record);
 887
 888                 sas_ssp_task_response(dev, task, iu);
 889                 break;
 890         }
 891         case SAS_PROTOCOL_SMP:
 892         {
 893                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
 894                 void *to;
 895
 896                 ts->stat = SAM_STAT_GOOD;
 897                 to = kmap_atomic(sg_page(sg_resp));
 898
 899                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
 900                              DMA_FROM_DEVICE);
 901                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
 902                              DMA_TO_DEVICE);
 903                 memcpy(to + sg_resp->offset,
 904                        slot->status_buffer +
 905                        sizeof(struct hisi_sas_err_record),
 906                        sg_dma_len(sg_resp));
 907                 kunmap_atomic(to);
 908                 break;
 909         }
 910         case SAS_PROTOCOL_SATA:
 911         case SAS_PROTOCOL_STP:
 912         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
 913         default:
 914                 ts->stat = SAM_STAT_CHECK_CONDITION;
 915                 break;
 916         }
 917
 918         if (!slot->port->port_attached) {
 919                 dev_err(dev, "slot complete: port %d has removed\n",
 920                         slot->port->sas_port.id);
 921                 ts->stat = SAS_PHY_DOWN;
 922         }
 923
 924 out:
 925         if (sas_dev && sas_dev->running_req)
 926                 sas_dev->running_req--;
 927
 928         hisi_sas_slot_task_free(hisi_hba, task, slot);
 929         sts = ts->stat;
 930
 931         if (task->task_done)
 932                 task->task_done(task);
 933
 934         return sts;
 935 }
 936
 937 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
 938 {
 939         int i, res = 0;
 940         u32 context, port_id, link_rate, hard_phy_linkrate;
 941         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
 942         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 943         struct device *dev = &hisi_hba->pdev->dev;
 944         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
 945         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
 946
 947         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
 948
 949         /* Check for SATA dev */
 950         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
 951         if (context & (1 << phy_no))
 952                 goto end;
 953
 954         if (phy_no == 8) {
 955                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
 956
 957                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
 958                           PORT_STATE_PHY8_PORT_NUM_OFF;
 959                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
 960                             PORT_STATE_PHY8_CONN_RATE_OFF;
 961         } else {
 962                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 963                 port_id = (port_id >> (4 * phy_no)) & 0xf;
 964                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
 965                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
 966         }
 967
 968         if (port_id == 0xf) {
 969                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
 970                 res = IRQ_NONE;
 971                 goto end;
 972         }
 973
 974         for (i = 0; i < 6; i++) {
 975                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
 976                                                RX_IDAF_DWORD0 + (i * 4));
 977                 frame_rcvd[i] = __swab32(idaf);
 978         }
 979
 980         /* Get the linkrates */
 981         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
 982         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
 983         sas_phy->linkrate = link_rate;
 984         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
 985                                                 HARD_PHY_LINKRATE);
 986         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
 987         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
 988
 989         sas_phy->oob_mode = SAS_OOB_MODE;
 990         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
 991         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
 992         phy->port_id = port_id;
 993         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
 994         phy->phy_type |= PORT_TYPE_SAS;
 995         phy->phy_attached = 1;
 996         phy->identify.device_type = id->dev_type;
 997         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
 998         if (phy->identify.device_type == SAS_END_DEVICE)
 999                 phy->identify.target_port_protocols =
1000                         SAS_PROTOCOL_SSP;
1001         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1002                 phy->identify.target_port_protocols =
1003                         SAS_PROTOCOL_SMP;
1004         queue_work(hisi_hba->wq, &phy->phyup_ws);
1005
1006 end:
1007         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1008                              CHL_INT0_SL_PHY_ENABLE_MSK);
1009         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1010
1011         return res;
1012 }
1013
1014 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1015 {
1016         int res = 0;
1017         u32 phy_cfg, phy_state;
1018
1019         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1020
1021         phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1022
1023         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1024
1025         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1026
1027         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1028         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1029
1030         return res;
1031 }
1032
1033 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1034 {
1035         struct hisi_hba *hisi_hba = p;
1036         u32 irq_msk;
1037         int phy_no = 0;
1038         irqreturn_t res = IRQ_HANDLED;
1039
1040         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1041                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1042         while (irq_msk) {
1043                 if (irq_msk  & 1) {
1044                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1045                                                             CHL_INT0);
1046
1047                         if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1048                                 /* phy up */
1049                                 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1050                                         res = IRQ_NONE;
1051                                         goto end;
1052                                 }
1053
1054                         if (irq_value & CHL_INT0_NOT_RDY_MSK)
1055                                 /* phy down */
1056                                 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1057                                         res = IRQ_NONE;
1058                                         goto end;
1059                                 }
1060                 }
1061                 irq_msk >>= 1;
1062                 phy_no++;
1063         }
1064
1065 end:
1066         return res;
1067 }
1068
1069 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1070 {
1071         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1072         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1073         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1074         unsigned long flags;
1075
1076         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1077
1078         spin_lock_irqsave(&hisi_hba->lock, flags);
1079         sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1080         spin_unlock_irqrestore(&hisi_hba->lock, flags);
1081
1082         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1083                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1084         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1085 }
1086
1087 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1088 {
1089         struct hisi_hba *hisi_hba = p;
1090         struct device *dev = &hisi_hba->pdev->dev;
1091         u32 ent_msk, ent_tmp, irq_msk;
1092         int phy_no = 0;
1093
1094         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1095         ent_tmp = ent_msk;
1096         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1097         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1098
1099         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1100                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1101
1102         while (irq_msk) {
1103                 if (irq_msk & (1 << phy_no)) {
1104                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1105                                                              CHL_INT0);
1106                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1107                                                              CHL_INT1);
1108                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1109                                                              CHL_INT2);
1110
1111                         if (irq_value1) {
1112                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1113                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1114                                         panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1115                                                 dev_name(dev), irq_value1);
1116
1117                                 hisi_sas_phy_write32(hisi_hba, phy_no,
1118                                                      CHL_INT1, irq_value1);
1119                         }
1120
1121                         if (irq_value2)
1122                                 hisi_sas_phy_write32(hisi_hba, phy_no,
1123                                                      CHL_INT2, irq_value2);
1124
1125
1126                         if (irq_value0) {
1127                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
1128                                         phy_bcast_v2_hw(phy_no, hisi_hba);
1129
1130                                 hisi_sas_phy_write32(hisi_hba, phy_no,
1131                                                 CHL_INT0, irq_value0
1132                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1133                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1134                                                 & (~CHL_INT0_NOT_RDY_MSK));
1135                         }
1136                 }
1137                 irq_msk &= ~(1 << phy_no);
1138                 phy_no++;
1139         }
1140
1141         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1142
1143         return IRQ_HANDLED;
1144 }
1145
1146 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
1147 {
1148         struct hisi_sas_cq *cq = p;
1149         struct hisi_hba *hisi_hba = cq->hisi_hba;
1150         struct hisi_sas_slot *slot;
1151         struct hisi_sas_itct *itct;
1152         struct hisi_sas_complete_v2_hdr *complete_queue;
1153         u32 irq_value, rd_point, wr_point, dev_id;
1154         int queue = cq->id;
1155
1156         complete_queue = hisi_hba->complete_hdr[queue];
1157         irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1158
1159         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1160
1161         rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR +
1162                                    (0x14 * queue));
1163         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1164                                    (0x14 * queue));
1165
1166         while (rd_point != wr_point) {
1167                 struct hisi_sas_complete_v2_hdr *complete_hdr;
1168                 int iptt;
1169
1170                 complete_hdr = &complete_queue[rd_point];
1171
1172                 /* Check for NCQ completion */
1173                 if (complete_hdr->act) {
1174                         u32 act_tmp = complete_hdr->act;
1175                         int ncq_tag_count = ffs(act_tmp);
1176
1177                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1178                                  CMPLT_HDR_DEV_ID_OFF;
1179                         itct = &hisi_hba->itct[dev_id];
1180
1181                         /* The NCQ tags are held in the itct header */
1182                         while (ncq_tag_count) {
1183                                 __le64 *ncq_tag = &itct->qw4_15[0];
1184
1185                                 ncq_tag_count -= 1;
1186                                 iptt = (ncq_tag[ncq_tag_count / 5]
1187                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
1188
1189                                 slot = &hisi_hba->slot_info[iptt];
1190                                 slot->cmplt_queue_slot = rd_point;
1191                                 slot->cmplt_queue = queue;
1192                                 slot_complete_v2_hw(hisi_hba, slot, 0);
1193
1194                                 act_tmp &= ~(1 << ncq_tag_count);
1195                                 ncq_tag_count = ffs(act_tmp);
1196                         }
1197                 } else {
1198                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1199                         slot = &hisi_hba->slot_info[iptt];
1200                         slot->cmplt_queue_slot = rd_point;
1201                         slot->cmplt_queue = queue;
1202                         slot_complete_v2_hw(hisi_hba, slot, 0);
1203                 }
1204
1205                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1206                         rd_point = 0;
1207         }
1208
1209         /* update rd_point */
1210         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1211         return IRQ_HANDLED;
1212 }
1213
1214 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
1215 {
1216         struct hisi_sas_phy *phy = p;
1217         struct hisi_hba *hisi_hba = phy->hisi_hba;
1218         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1219         struct device *dev = &hisi_hba->pdev->dev;
1220         struct  hisi_sas_initial_fis *initial_fis;
1221         struct dev_to_host_fis *fis;
1222         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
1223         irqreturn_t res = IRQ_HANDLED;
1224         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1225         int phy_no;
1226
1227         phy_no = sas_phy->id;
1228         initial_fis = &hisi_hba->initial_fis[phy_no];
1229         fis = &initial_fis->fis;
1230
1231         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1);
1232         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk | 1 << phy_no);
1233
1234         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1);
1235         ent_tmp = ent_int;
1236         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
1237         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
1238                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
1239                 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1240                 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1241                 res = IRQ_NONE;
1242                 goto end;
1243         }
1244
1245         if (unlikely(phy_no == 8)) {
1246                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1247
1248                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1249                           PORT_STATE_PHY8_PORT_NUM_OFF;
1250                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1251                             PORT_STATE_PHY8_CONN_RATE_OFF;
1252         } else {
1253                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1254                 port_id = (port_id >> (4 * phy_no)) & 0xf;
1255                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1256                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1257         }
1258
1259         if (port_id == 0xf) {
1260                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
1261                 res = IRQ_NONE;
1262                 goto end;
1263         }
1264
1265         sas_phy->linkrate = link_rate;
1266         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1267                                                 HARD_PHY_LINKRATE);
1268         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1269         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1270
1271         sas_phy->oob_mode = SATA_OOB_MODE;
1272         /* Make up some unique SAS address */
1273         attached_sas_addr[0] = 0x50;
1274         attached_sas_addr[7] = phy_no;
1275         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
1276         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
1277         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1278         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1279         phy->port_id = port_id;
1280         phy->phy_type |= PORT_TYPE_SATA;
1281         phy->phy_attached = 1;
1282         phy->identify.device_type = SAS_SATA_DEV;
1283         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1284         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1285         queue_work(hisi_hba->wq, &phy->phyup_ws);
1286
1287 end:
1288         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1289         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1290
1291         return res;
1292 }
1293
1294 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1295         int_phy_updown_v2_hw,
1296         int_chnl_int_v2_hw,
1297 };
1298
1299 /**
1300  * There is a limitation in the hip06 chipset that we need
1301  * to map in all mbigen interrupts, even if they are not used.
1302  */
1303 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
1304 {
1305         struct platform_device *pdev = hisi_hba->pdev;
1306         struct device *dev = &pdev->dev;
1307         int i, irq, rc, irq_map[128];
1308
1309
1310         for (i = 0; i < 128; i++)
1311                 irq_map[i] = platform_get_irq(pdev, i);
1312
1313         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
1314                 int idx = i;
1315
1316                 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
1317                 if (!irq) {
1318                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
1319                                 idx);
1320                         return -ENOENT;
1321                 }
1322
1323                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
1324                                       DRV_NAME " phy", hisi_hba);
1325                 if (rc) {
1326                         dev_err(dev, "irq init: could not request "
1327                                 "phy interrupt %d, rc=%d\n",
1328                                 irq, rc);
1329                         return -ENOENT;
1330                 }
1331         }
1332
1333         for (i = 0; i < hisi_hba->n_phy; i++) {
1334                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1335                 int idx = i + 72; /* First SATA interrupt is irq72 */
1336
1337                 irq = irq_map[idx];
1338                 if (!irq) {
1339                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
1340                                 idx);
1341                         return -ENOENT;
1342                 }
1343
1344                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
1345                                       DRV_NAME " sata", phy);
1346                 if (rc) {
1347                         dev_err(dev, "irq init: could not request "
1348                                 "sata interrupt %d, rc=%d\n",
1349                                 irq, rc);
1350                         return -ENOENT;
1351                 }
1352         }
1353
1354         for (i = 0; i < hisi_hba->queue_count; i++) {
1355                 int idx = i + 96; /* First cq interrupt is irq96 */
1356
1357                 irq = irq_map[idx];
1358                 if (!irq) {
1359                         dev_err(dev,
1360                                 "irq init: could not map cq interrupt %d\n",
1361                                 idx);
1362                         return -ENOENT;
1363                 }
1364                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
1365                                       DRV_NAME " cq", &hisi_hba->cq[i]);
1366                 if (rc) {
1367                         dev_err(dev,
1368                                 "irq init: could not request cq interrupt %d, rc=%d\n",
1369                                 irq, rc);
1370                         return -ENOENT;
1371                 }
1372         }
1373
1374         return 0;
1375 }
1376
1377 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
1378 {
1379         int rc;
1380
1381         rc = hw_init_v2_hw(hisi_hba);
1382         if (rc)
1383                 return rc;
1384
1385         rc = interrupt_init_v2_hw(hisi_hba);
1386         if (rc)
1387                 return rc;
1388
1389         phys_init_v2_hw(hisi_hba);
1390
1391         return 0;
1392 }
1393
1394 static const struct hisi_sas_hw hisi_sas_v2_hw = {
1395         .hw_init = hisi_sas_v2_init,
1396         .sl_notify = sl_notify_v2_hw,
1397         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
1398         .prep_ssp = prep_ssp_v2_hw,
1399         .get_free_slot = get_free_slot_v2_hw,
1400         .start_delivery = start_delivery_v2_hw,
1401         .slot_complete = slot_complete_v2_hw,
1402         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
1403         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
1404 };
1405
1406 static int hisi_sas_v2_probe(struct platform_device *pdev)
1407 {
1408         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
1409 }
1410
1411 static int hisi_sas_v2_remove(struct platform_device *pdev)
1412 {
1413         return hisi_sas_remove(pdev);
1414 }
1415
1416 static const struct of_device_id sas_v2_of_match[] = {
1417         { .compatible = "hisilicon,hip06-sas-v2",},
1418         {},
1419 };
1420 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
1421
1422 static struct platform_driver hisi_sas_v2_driver = {
1423         .probe = hisi_sas_v2_probe,
1424         .remove = hisi_sas_v2_remove,
1425         .driver = {
1426                 .name = DRV_NAME,
1427                 .of_match_table = sas_v2_of_match,
1428         },
1429 };
1430
1431 module_platform_driver(hisi_sas_v2_driver);
1432
1433 MODULE_LICENSE("GPL");
1434 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1435 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
1436 MODULE_ALIAS("platform:" DRV_NAME);