drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

   1 /*
   2  * Copyright (c) 2015 Linaro Ltd.
   3  * Copyright (c) 2015 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v1_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define BROKEN_MSG_ADDR_LO              0x18
  22 #define BROKEN_MSG_ADDR_HI              0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PHY_CONN_RATE                   0x30
  28 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  29 #define AXI_AHB_CLK_CFG                 0x3c
  30 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x84
  31 #define HGC_GET_ITV_TIME                0x90
  32 #define DEVICE_MSG_WORK_MODE            0x94
  33 #define I_T_NEXUS_LOSS_TIME             0xa0
  34 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  35 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  36 #define CFG_AGING_TIME                  0xbc
  37 #define CFG_AGING_TIME_ITCT_REL_OFF     0
  38 #define CFG_AGING_TIME_ITCT_REL_MSK     (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
  39 #define HGC_DFX_CFG2                    0xc0
  40 #define FIS_LIST_BADDR_L                0xc4
  41 #define CFG_1US_TIMER_TRSH              0xcc
  42 #define CFG_SAS_CONFIG                  0xd4
  43 #define HGC_IOST_ECC_ADDR               0x140
  44 #define HGC_IOST_ECC_ADDR_BAD_OFF       16
  45 #define HGC_IOST_ECC_ADDR_BAD_MSK       (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
  46 #define HGC_DQ_ECC_ADDR                 0x144
  47 #define HGC_DQ_ECC_ADDR_BAD_OFF         16
  48 #define HGC_DQ_ECC_ADDR_BAD_MSK         (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
  49 #define HGC_INVLD_DQE_INFO              0x148
  50 #define HGC_INVLD_DQE_INFO_DQ_OFF       0
  51 #define HGC_INVLD_DQE_INFO_DQ_MSK       (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
  52 #define HGC_INVLD_DQE_INFO_TYPE_OFF     16
  53 #define HGC_INVLD_DQE_INFO_TYPE_MSK     (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
  54 #define HGC_INVLD_DQE_INFO_FORCE_OFF    17
  55 #define HGC_INVLD_DQE_INFO_FORCE_MSK    (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
  56 #define HGC_INVLD_DQE_INFO_PHY_OFF      18
  57 #define HGC_INVLD_DQE_INFO_PHY_MSK      (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
  58 #define HGC_INVLD_DQE_INFO_ABORT_OFF    19
  59 #define HGC_INVLD_DQE_INFO_ABORT_MSK    (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
  60 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF  20
  61 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK  (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
  62 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF  21
  63 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK  (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
  64 #define HGC_INVLD_DQE_INFO_OFL_OFF      22
  65 #define HGC_INVLD_DQE_INFO_OFL_MSK      (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
  66 #define HGC_ITCT_ECC_ADDR               0x150
  67 #define HGC_ITCT_ECC_ADDR_BAD_OFF       16
  68 #define HGC_ITCT_ECC_ADDR_BAD_MSK       (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
  69 #define HGC_AXI_FIFO_ERR_INFO           0x154
  70 #define INT_COAL_EN                     0x1bc
  71 #define OQ_INT_COAL_TIME                0x1c0
  72 #define OQ_INT_COAL_CNT                 0x1c4
  73 #define ENT_INT_COAL_TIME               0x1c8
  74 #define ENT_INT_COAL_CNT                0x1cc
  75 #define OQ_INT_SRC                      0x1d0
  76 #define OQ_INT_SRC_MSK                  0x1d4
  77 #define ENT_INT_SRC1                    0x1d8
  78 #define ENT_INT_SRC2                    0x1dc
  79 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF     25
  80 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK     (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
  81 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF     27
  82 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK     (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
  83 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF  28
  84 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK  (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
  85 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
  86 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
  87 #define ENT_INT_SRC_MSK1                0x1e0
  88 #define ENT_INT_SRC_MSK2                0x1e4
  89 #define SAS_ECC_INTR                    0x1e8
  90 #define SAS_ECC_INTR_DQ_ECC1B_OFF       0
  91 #define SAS_ECC_INTR_DQ_ECC1B_MSK       (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
  92 #define SAS_ECC_INTR_DQ_ECCBAD_OFF      1
  93 #define SAS_ECC_INTR_DQ_ECCBAD_MSK      (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
  94 #define SAS_ECC_INTR_IOST_ECC1B_OFF     2
  95 #define SAS_ECC_INTR_IOST_ECC1B_MSK     (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
  96 #define SAS_ECC_INTR_IOST_ECCBAD_OFF    3
  97 #define SAS_ECC_INTR_IOST_ECCBAD_MSK    (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
  98 #define SAS_ECC_INTR_ITCT_ECC1B_OFF     4
  99 #define SAS_ECC_INTR_ITCT_ECC1B_MSK     (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
 100 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF    5
 101 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK    (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
 102 #define SAS_ECC_INTR_MSK                0x1ec
 103 #define HGC_ERR_STAT_EN                 0x238
 104 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 105 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 106 #define DLVRY_Q_0_DEPTH                 0x268
 107 #define DLVRY_Q_0_WR_PTR                0x26c
 108 #define DLVRY_Q_0_RD_PTR                0x270
 109 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 110 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 111 #define COMPL_Q_0_DEPTH                 0x4e8
 112 #define COMPL_Q_0_WR_PTR                0x4ec
 113 #define COMPL_Q_0_RD_PTR                0x4f0
 114 #define HGC_ECC_ERR                     0x7d0
 115
 116 /* phy registers need init */
 117 #define PORT_BASE                       (0x800)
 118
 119 #define PHY_CFG                         (PORT_BASE + 0x0)
 120 #define PHY_CFG_ENA_OFF                 0
 121 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 122 #define PHY_CFG_DC_OPT_OFF              2
 123 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 124 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0xc)
 125 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 126 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
 127 #define PROG_PHY_LINK_RATE_MIN_OFF      4
 128 #define PROG_PHY_LINK_RATE_MIN_MSK      (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
 129 #define PROG_PHY_LINK_RATE_OOB_OFF      8
 130 #define PROG_PHY_LINK_RATE_OOB_MSK      (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
 131 #define PHY_CTRL                        (PORT_BASE + 0x14)
 132 #define PHY_CTRL_RESET_OFF              0
 133 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 134 #define PHY_RATE_NEGO                   (PORT_BASE + 0x30)
 135 #define PHY_PCN                         (PORT_BASE + 0x44)
 136 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 137 #define SL_CONTROL                      (PORT_BASE + 0x94)
 138 #define SL_CONTROL_NOTIFY_EN_OFF        0
 139 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 140 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 141 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 142 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 143 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 144 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 145 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 146 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 147 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 148 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 149 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 150 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 151 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 152 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 153 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 154 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 155 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x12c)
 156 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
 157 #define PHY_CONFIG2                     (PORT_BASE + 0x1a8)
 158 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF  3
 159 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK  (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
 160 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF   24
 161 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK   (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
 162 #define CHL_INT0                        (PORT_BASE + 0x1b0)
 163 #define CHL_INT0_PHYCTRL_NOTRDY_OFF     0
 164 #define CHL_INT0_PHYCTRL_NOTRDY_MSK     (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
 165 #define CHL_INT0_SN_FAIL_NGR_OFF        2
 166 #define CHL_INT0_SN_FAIL_NGR_MSK        (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
 167 #define CHL_INT0_DWS_LOST_OFF           4
 168 #define CHL_INT0_DWS_LOST_MSK           (0x1 << CHL_INT0_DWS_LOST_OFF)
 169 #define CHL_INT0_SL_IDAF_FAIL_OFF       10
 170 #define CHL_INT0_SL_IDAF_FAIL_MSK       (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
 171 #define CHL_INT0_ID_TIMEOUT_OFF         11
 172 #define CHL_INT0_ID_TIMEOUT_MSK         (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
 173 #define CHL_INT0_SL_OPAF_FAIL_OFF       12
 174 #define CHL_INT0_SL_OPAF_FAIL_MSK       (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
 175 #define CHL_INT0_SL_PS_FAIL_OFF         21
 176 #define CHL_INT0_SL_PS_FAIL_MSK         (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
 177 #define CHL_INT1                        (PORT_BASE + 0x1b4)
 178 #define CHL_INT2                        (PORT_BASE + 0x1b8)
 179 #define CHL_INT2_SL_RX_BC_ACK_OFF       2
 180 #define CHL_INT2_SL_RX_BC_ACK_MSK       (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
 181 #define CHL_INT2_SL_PHY_ENA_OFF         6
 182 #define CHL_INT2_SL_PHY_ENA_MSK         (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
 183 #define CHL_INT0_MSK                    (PORT_BASE + 0x1bc)
 184 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
 185 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
 186 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c0)
 187 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c4)
 188 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 189 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 190 #define DMA_TX_STATUS_BUSY_OFF          0
 191 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 192 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 193 #define DMA_RX_STATUS_BUSY_OFF          0
 194 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 195
 196 #define AXI_CFG                         0x5100
 197 #define RESET_VALUE                     0x7ffff
 198
 199 /* HW dma structures */
 200 /* Delivery queue header */
 201 /* dw0 */
 202 #define CMD_HDR_RESP_REPORT_OFF         5
 203 #define CMD_HDR_RESP_REPORT_MSK         0x20
 204 #define CMD_HDR_TLR_CTRL_OFF            6
 205 #define CMD_HDR_TLR_CTRL_MSK            0xc0
 206 #define CMD_HDR_PORT_OFF                17
 207 #define CMD_HDR_PORT_MSK                0xe0000
 208 #define CMD_HDR_PRIORITY_OFF            27
 209 #define CMD_HDR_PRIORITY_MSK            0x8000000
 210 #define CMD_HDR_MODE_OFF                28
 211 #define CMD_HDR_MODE_MSK                0x10000000
 212 #define CMD_HDR_CMD_OFF                 29
 213 #define CMD_HDR_CMD_MSK                 0xe0000000
 214 /* dw1 */
 215 #define CMD_HDR_VERIFY_DTL_OFF          10
 216 #define CMD_HDR_VERIFY_DTL_MSK          0x400
 217 #define CMD_HDR_SSP_FRAME_TYPE_OFF      13
 218 #define CMD_HDR_SSP_FRAME_TYPE_MSK      0xe000
 219 #define CMD_HDR_DEVICE_ID_OFF           16
 220 #define CMD_HDR_DEVICE_ID_MSK           0xffff0000
 221 /* dw2 */
 222 #define CMD_HDR_CFL_OFF                 0
 223 #define CMD_HDR_CFL_MSK                 0x1ff
 224 #define CMD_HDR_MRFL_OFF                15
 225 #define CMD_HDR_MRFL_MSK                0xff8000
 226 #define CMD_HDR_FIRST_BURST_OFF         25
 227 #define CMD_HDR_FIRST_BURST_MSK         0x2000000
 228 /* dw3 */
 229 #define CMD_HDR_IPTT_OFF                0
 230 #define CMD_HDR_IPTT_MSK                0xffff
 231 /* dw6 */
 232 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 233 #define CMD_HDR_DATA_SGL_LEN_MSK        0xffff0000
 234
 235 /* Completion header */
 236 #define CMPLT_HDR_IPTT_OFF              0
 237 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 238 #define CMPLT_HDR_CMD_CMPLT_OFF         17
 239 #define CMPLT_HDR_CMD_CMPLT_MSK         (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
 240 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF     18
 241 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK     (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
 242 #define CMPLT_HDR_RSPNS_XFRD_OFF        19
 243 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 244 #define CMPLT_HDR_IO_CFG_ERR_OFF        27
 245 #define CMPLT_HDR_IO_CFG_ERR_MSK        (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
 246
 247 /* ITCT header */
 248 /* qw0 */
 249 #define ITCT_HDR_DEV_TYPE_OFF           0
 250 #define ITCT_HDR_DEV_TYPE_MSK           (0x3ULL << ITCT_HDR_DEV_TYPE_OFF)
 251 #define ITCT_HDR_VALID_OFF              2
 252 #define ITCT_HDR_VALID_MSK              (0x1ULL << ITCT_HDR_VALID_OFF)
 253 #define ITCT_HDR_AWT_CONTROL_OFF        4
 254 #define ITCT_HDR_AWT_CONTROL_MSK        (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)
 255 #define ITCT_HDR_MAX_CONN_RATE_OFF      5
 256 #define ITCT_HDR_MAX_CONN_RATE_MSK      (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)
 257 #define ITCT_HDR_VALID_LINK_NUM_OFF     9
 258 #define ITCT_HDR_VALID_LINK_NUM_MSK     (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)
 259 #define ITCT_HDR_PORT_ID_OFF            13
 260 #define ITCT_HDR_PORT_ID_MSK            (0x7ULL << ITCT_HDR_PORT_ID_OFF)
 261 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 262 #define ITCT_HDR_SMP_TIMEOUT_MSK        (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)
 263 /* qw1 */
 264 #define ITCT_HDR_MAX_SAS_ADDR_OFF       0
 265 #define ITCT_HDR_MAX_SAS_ADDR_MSK       (0xffffffffffffffff << \
 266                                         ITCT_HDR_MAX_SAS_ADDR_OFF)
 267 /* qw2 */
 268 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF   0
 269 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK   (0xffffULL << \
 270                                         ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
 271 #define ITCT_HDR_BUS_INACTIVE_TL_OFF    16
 272 #define ITCT_HDR_BUS_INACTIVE_TL_MSK    (0xffffULL << \
 273                                         ITCT_HDR_BUS_INACTIVE_TL_OFF)
 274 #define ITCT_HDR_MAX_CONN_TL_OFF        32
 275 #define ITCT_HDR_MAX_CONN_TL_MSK        (0xffffULL << \
 276                                         ITCT_HDR_MAX_CONN_TL_OFF)
 277 #define ITCT_HDR_REJ_OPEN_TL_OFF        48
 278 #define ITCT_HDR_REJ_OPEN_TL_MSK        (0xffffULL << \
 279                                         ITCT_HDR_REJ_OPEN_TL_OFF)
 280
 281 /* Err record header */
 282 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF     0
 283 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK     (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
 284 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF     16
 285 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK     (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
 286
 287 struct hisi_sas_complete_v1_hdr {
 288         __le32 data;
 289 };
 290
 291 struct hisi_sas_err_record_v1 {
 292         /* dw0 */
 293         __le32 dma_err_type;
 294
 295         /* dw1 */
 296         __le32 trans_tx_fail_type;
 297
 298         /* dw2 */
 299         __le32 trans_rx_fail_type;
 300
 301         /* dw3 */
 302         u32 rsvd;
 303 };
 304
 305 enum {
 306         HISI_SAS_PHY_BCAST_ACK = 0,
 307         HISI_SAS_PHY_SL_PHY_ENABLED,
 308         HISI_SAS_PHY_INT_ABNORMAL,
 309         HISI_SAS_PHY_INT_NR
 310 };
 311
 312 enum {
 313         DMA_TX_ERR_BASE = 0x0,
 314         DMA_RX_ERR_BASE = 0x100,
 315         TRANS_TX_FAIL_BASE = 0x200,
 316         TRANS_RX_FAIL_BASE = 0x300,
 317
 318         /* dma tx */
 319         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
 320         DMA_TX_DIF_APP_ERR, /* 0x1 */
 321         DMA_TX_DIF_RPP_ERR, /* 0x2 */
 322         DMA_TX_AXI_BUS_ERR, /* 0x3 */
 323         DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
 324         DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
 325         DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
 326         DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
 327         DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
 328         DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
 329
 330         /* dma rx */
 331         DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
 332         DMA_RX_DIF_CRC_ERR, /* 0x101 */
 333         DMA_RX_DIF_APP_ERR, /* 0x102 */
 334         DMA_RX_DIF_RPP_ERR, /* 0x103 */
 335         DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
 336         DMA_RX_AXI_BUS_ERR, /* 0x105 */
 337         DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
 338         DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
 339         DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
 340         DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
 341         DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
 342         DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
 343         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
 344
 345         /* trans tx */
 346         TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
 347         TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
 348         TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
 349         TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
 350         TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
 351         TRANS_TX_RSVD1_ERR, /* 0x205 */
 352         TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
 353         TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
 354         TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
 355         TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
 356         TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
 357         TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
 358         TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
 359         TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
 360         TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
 361         TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
 362         TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
 363         TRANS_TX_RSVD2_ERR, /* 0x211 */
 364         TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
 365         TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
 366         TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
 367         TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
 368         TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
 369         TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
 370         TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
 371         TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
 372         TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
 373         TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
 374         TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
 375         TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
 376         TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
 377         TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
 378
 379         /* trans rx */
 380         TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
 381         TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
 382         TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
 383         TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
 384         TRANS_RX_RSVD0_ERR, /* 0x304 */
 385         TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
 386         TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
 387         TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
 388         TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
 389         TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
 390         TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
 391         TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
 392         TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
 393         TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
 394         TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
 395         TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
 396         TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
 397         TRANS_RX_BAD_HASH_ERR, /* 0x311 */
 398         TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
 399         TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
 400         TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
 401         TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
 402         TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
 403         TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
 404         TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
 405         TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
 406         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
 407 };
 408
 409 #define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192
 410
 411 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
 412 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
 413 #define HISI_SAS_FATAL_INT_NR (2)
 414
 415 #define HISI_SAS_MAX_INT_NR \
 416         (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
 417         HISI_SAS_FATAL_INT_NR)
 418
 419 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 420 {
 421         void __iomem *regs = hisi_hba->regs + off;
 422
 423         return readl(regs);
 424 }
 425
 426 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 427 {
 428         void __iomem *regs = hisi_hba->regs + off;
 429
 430         return readl_relaxed(regs);
 431 }
 432
 433 static void hisi_sas_write32(struct hisi_hba *hisi_hba,
 434                                     u32 off, u32 val)
 435 {
 436         void __iomem *regs = hisi_hba->regs + off;
 437
 438         writel(val, regs);
 439 }
 440
 441 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
 442                                         int phy_no, u32 off, u32 val)
 443 {
 444         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 445
 446         writel(val, regs);
 447 }
 448
 449 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 450                                       int phy_no, u32 off)
 451 {
 452         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 453
 454         return readl(regs);
 455 }
 456
 457 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 458 {
 459         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 460
 461         cfg &= ~PHY_CFG_DC_OPT_MSK;
 462         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 463         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 464 }
 465
 466 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 467 {
 468         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
 469
 470         cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
 471         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
 472 }
 473
 474 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 475 {
 476         struct sas_identify_frame identify_frame;
 477         u32 *identify_buffer;
 478
 479         memset(&identify_frame, 0, sizeof(identify_frame));
 480         identify_frame.dev_type = SAS_END_DEVICE;
 481         identify_frame.frame_type = 0;
 482         identify_frame._un1 = 1;
 483         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 484         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 485         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 486         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 487         identify_frame.phy_id = phy_no;
 488         identify_buffer = (u32 *)(&identify_frame);
 489
 490         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 491                         __swab32(identify_buffer[0]));
 492         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 493                         __swab32(identify_buffer[1]));
 494         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 495                         __swab32(identify_buffer[2]));
 496         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 497                         __swab32(identify_buffer[3]));
 498         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 499                         __swab32(identify_buffer[4]));
 500         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 501                         __swab32(identify_buffer[5]));
 502 }
 503
 504 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
 505                              struct hisi_sas_device *sas_dev)
 506 {
 507         struct domain_device *device = sas_dev->sas_device;
 508         struct device *dev = hisi_hba->dev;
 509         u64 qw0, device_id = sas_dev->device_id;
 510         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 511         struct asd_sas_port *sas_port = device->port;
 512         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 513         u64 sas_addr;
 514
 515         memset(itct, 0, sizeof(*itct));
 516
 517         /* qw0 */
 518         qw0 = 0;
 519         switch (sas_dev->dev_type) {
 520         case SAS_END_DEVICE:
 521         case SAS_EDGE_EXPANDER_DEVICE:
 522         case SAS_FANOUT_EXPANDER_DEVICE:
 523                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 524                 break;
 525         default:
 526                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 527                          sas_dev->dev_type);
 528         }
 529
 530         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 531                 (1 << ITCT_HDR_AWT_CONTROL_OFF) |
 532                 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
 533                 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
 534                 (port->id << ITCT_HDR_PORT_ID_OFF));
 535         itct->qw0 = cpu_to_le64(qw0);
 536
 537         /* qw1 */
 538         memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 539         itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
 540
 541         /* qw2 */
 542         itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
 543                                 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) |
 544                                 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) |
 545                                 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
 546 }
 547
 548 static void clear_itct_v1_hw(struct hisi_hba *hisi_hba,
 549                               struct hisi_sas_device *sas_dev)
 550 {
 551         u64 dev_id = sas_dev->device_id;
 552         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 553         u64 qw0;
 554         u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
 555
 556         reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
 557         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 558
 559         /* free itct */
 560         udelay(1);
 561         reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
 562         reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
 563         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 564
 565         qw0 = le64_to_cpu(itct->qw0);
 566         qw0 &= ~ITCT_HDR_VALID_MSK;
 567         itct->qw0 = cpu_to_le64(qw0);
 568 }
 569
 570 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
 571 {
 572         int i;
 573         unsigned long end_time;
 574         u32 val;
 575         struct device *dev = hisi_hba->dev;
 576
 577         for (i = 0; i < hisi_hba->n_phy; i++) {
 578                 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
 579
 580                 phy_ctrl |= PHY_CTRL_RESET_MSK;
 581                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
 582         }
 583         msleep(1); /* It is safe to wait for 50us */
 584
 585         /* Ensure DMA tx & rx idle */
 586         for (i = 0; i < hisi_hba->n_phy; i++) {
 587                 u32 dma_tx_status, dma_rx_status;
 588
 589                 end_time = jiffies + msecs_to_jiffies(1000);
 590
 591                 while (1) {
 592                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 593                                                             DMA_TX_STATUS);
 594                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 595                                                             DMA_RX_STATUS);
 596
 597                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 598                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 599                                 break;
 600
 601                         msleep(20);
 602                         if (time_after(jiffies, end_time))
 603                                 return -EIO;
 604                 }
 605         }
 606
 607         /* Ensure axi bus idle */
 608         end_time = jiffies + msecs_to_jiffies(1000);
 609         while (1) {
 610                 u32 axi_status =
 611                         hisi_sas_read32(hisi_hba, AXI_CFG);
 612
 613                 if (axi_status == 0)
 614                         break;
 615
 616                 msleep(20);
 617                 if (time_after(jiffies, end_time))
 618                         return -EIO;
 619         }
 620
 621         if (ACPI_HANDLE(dev)) {
 622                 acpi_status s;
 623
 624                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 625                 if (ACPI_FAILURE(s)) {
 626                         dev_err(dev, "Reset failed\n");
 627                         return -EIO;
 628                 }
 629         } else if (hisi_hba->ctrl) {
 630                 /* Apply reset and disable clock */
 631                 /* clk disable reg is offset by +4 bytes from clk enable reg */
 632                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 633                              RESET_VALUE);
 634                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 635                              RESET_VALUE);
 636                 msleep(1);
 637                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 638                 if (RESET_VALUE != (val & RESET_VALUE)) {
 639                         dev_err(dev, "Reset failed\n");
 640                         return -EIO;
 641                 }
 642
 643                 /* De-reset and enable clock */
 644                 /* deassert rst reg is offset by +4 bytes from assert reg */
 645                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 646                              RESET_VALUE);
 647                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 648                              RESET_VALUE);
 649                 msleep(1);
 650                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 651                 if (val & RESET_VALUE) {
 652                         dev_err(dev, "De-reset failed\n");
 653                         return -EIO;
 654                 }
 655         } else {
 656                 dev_warn(dev, "no reset method\n");
 657                 return -EINVAL;
 658         }
 659
 660         return 0;
 661 }
 662
 663 static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
 664 {
 665         int i;
 666
 667         /* Global registers init*/
 668         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 669                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 670         hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
 671         hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
 672         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
 673         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
 674         hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
 675         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 676         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
 677         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
 678         hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
 679         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
 680         hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
 681         hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
 682         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
 683         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
 684         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
 685         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 686         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 687         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
 688         hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
 689         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 690         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
 691         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 692         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
 693         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
 694         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
 695         hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
 696
 697         for (i = 0; i < hisi_hba->n_phy; i++) {
 698                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
 699                 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
 700                 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
 701                 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
 702                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 703                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
 704                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 705                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
 706                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
 707                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
 708                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
 709         }
 710
 711         for (i = 0; i < hisi_hba->queue_count; i++) {
 712                 /* Delivery queue */
 713                 hisi_sas_write32(hisi_hba,
 714                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 715                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 716
 717                 hisi_sas_write32(hisi_hba,
 718                                  DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 719                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 720
 721                 hisi_sas_write32(hisi_hba,
 722                                  DLVRY_Q_0_DEPTH + (i * 0x14),
 723                                  HISI_SAS_QUEUE_SLOTS);
 724
 725                 /* Completion queue */
 726                 hisi_sas_write32(hisi_hba,
 727                                  COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 728                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 729
 730                 hisi_sas_write32(hisi_hba,
 731                                  COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 732                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 733
 734                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 735                                  HISI_SAS_QUEUE_SLOTS);
 736         }
 737
 738         /* itct */
 739         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 740                          lower_32_bits(hisi_hba->itct_dma));
 741
 742         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 743                          upper_32_bits(hisi_hba->itct_dma));
 744
 745         /* iost */
 746         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 747                          lower_32_bits(hisi_hba->iost_dma));
 748
 749         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 750                          upper_32_bits(hisi_hba->iost_dma));
 751
 752         /* breakpoint */
 753         hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
 754                          lower_32_bits(hisi_hba->breakpoint_dma));
 755
 756         hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
 757                          upper_32_bits(hisi_hba->breakpoint_dma));
 758 }
 759
 760 static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
 761 {
 762         struct device *dev = hisi_hba->dev;
 763         int rc;
 764
 765         rc = reset_hw_v1_hw(hisi_hba);
 766         if (rc) {
 767                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 768                 return rc;
 769         }
 770
 771         msleep(100);
 772         init_reg_v1_hw(hisi_hba);
 773
 774         return 0;
 775 }
 776
 777 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 778 {
 779         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 780
 781         cfg |= PHY_CFG_ENA_MSK;
 782         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 783 }
 784
 785 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 786 {
 787         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 788
 789         cfg &= ~PHY_CFG_ENA_MSK;
 790         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 791 }
 792
 793 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 794 {
 795         config_id_frame_v1_hw(hisi_hba, phy_no);
 796         config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
 797         config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
 798         enable_phy_v1_hw(hisi_hba, phy_no);
 799 }
 800
 801 static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 802 {
 803         disable_phy_v1_hw(hisi_hba, phy_no);
 804 }
 805
 806 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 807 {
 808         stop_phy_v1_hw(hisi_hba, phy_no);
 809         msleep(100);
 810         start_phy_v1_hw(hisi_hba, phy_no);
 811 }
 812
 813 static void start_phys_v1_hw(struct timer_list *t)
 814 {
 815         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
 816         int i;
 817
 818         for (i = 0; i < hisi_hba->n_phy; i++) {
 819                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
 820                 start_phy_v1_hw(hisi_hba, i);
 821         }
 822 }
 823
 824 static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
 825 {
 826         int i;
 827         struct timer_list *timer = &hisi_hba->timer;
 828
 829         for (i = 0; i < hisi_hba->n_phy; i++) {
 830                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
 831                 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
 832         }
 833
 834         timer_setup(timer, start_phys_v1_hw, 0);
 835         mod_timer(timer, jiffies + HZ);
 836 }
 837
 838 static void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 839 {
 840         u32 sl_control;
 841
 842         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 843         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 844         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 845         msleep(1);
 846         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 847         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 848         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 849 }
 850
 851 static enum sas_linkrate phy_get_max_linkrate_v1_hw(void)
 852 {
 853         return SAS_LINK_RATE_6_0_GBPS;
 854 }
 855
 856 static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no,
 857                 struct sas_phy_linkrates *r)
 858 {
 859         enum sas_linkrate max = r->maximum_linkrate;
 860         u32 prog_phy_link_rate = 0x800;
 861
 862         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
 863         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
 864                              prog_phy_link_rate);
 865 }
 866
 867 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
 868 {
 869         int i, bitmap = 0;
 870         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 871
 872         for (i = 0; i < hisi_hba->n_phy; i++)
 873                 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 874                         bitmap |= 1 << i;
 875
 876         return bitmap;
 877 }
 878
 879 /*
 880  * The callpath to this function and upto writing the write
 881  * queue pointer should be safe from interruption.
 882  */
 883 static int
 884 get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
 885 {
 886         struct device *dev = hisi_hba->dev;
 887         int queue = dq->id;
 888         u32 r, w;
 889
 890         w = dq->wr_point;
 891         r = hisi_sas_read32_relaxed(hisi_hba,
 892                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
 893         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 894                 dev_warn(dev, "could not find free slot\n");
 895                 return -EAGAIN;
 896         }
 897
 898         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
 899
 900         return w;
 901 }
 902
 903 /* DQ lock must be taken here */
 904 static void start_delivery_v1_hw(struct hisi_sas_dq *dq)
 905 {
 906         struct hisi_hba *hisi_hba = dq->hisi_hba;
 907         struct hisi_sas_slot *s, *s1, *s2 = NULL;
 908         int dlvry_queue = dq->id;
 909         int wp;
 910
 911         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
 912                 if (!s->ready)
 913                         break;
 914                 s2 = s;
 915                 list_del(&s->delivery);
 916         }
 917
 918         if (!s2)
 919                 return;
 920
 921         /*
 922          * Ensure that memories for slots built on other CPUs is observed.
 923          */
 924         smp_rmb();
 925         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
 926
 927         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
 928 }
 929
 930 static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
 931                               struct hisi_sas_slot *slot,
 932                               struct hisi_sas_cmd_hdr *hdr,
 933                               struct scatterlist *scatter,
 934                               int n_elem)
 935 {
 936         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
 937         struct scatterlist *sg;
 938         int i;
 939
 940         for_each_sg(scatter, sg, n_elem, i) {
 941                 struct hisi_sas_sge *entry = &sge_page->sge[i];
 942
 943                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 944                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 945                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 946                 entry->data_off = 0;
 947         }
 948
 949         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
 950
 951         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 952 }
 953
 954 static void prep_smp_v1_hw(struct hisi_hba *hisi_hba,
 955                           struct hisi_sas_slot *slot)
 956 {
 957         struct sas_task *task = slot->task;
 958         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 959         struct domain_device *device = task->dev;
 960         struct hisi_sas_port *port = slot->port;
 961         struct scatterlist *sg_req;
 962         struct hisi_sas_device *sas_dev = device->lldd_dev;
 963         dma_addr_t req_dma_addr;
 964         unsigned int req_len;
 965
 966         /* req */
 967         sg_req = &task->smp_task.smp_req;
 968         req_len = sg_dma_len(sg_req);
 969         req_dma_addr = sg_dma_address(sg_req);
 970
 971         /* create header */
 972         /* dw0 */
 973         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
 974                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
 975                                (1 << CMD_HDR_MODE_OFF) | /* ini mode */
 976                                (2 << CMD_HDR_CMD_OFF)); /* smp */
 977
 978         /* map itct entry */
 979         hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
 980
 981         /* dw2 */
 982         hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
 983                                (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
 984                                CMD_HDR_MRFL_OFF));
 985
 986         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
 987
 988         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
 989         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
 990 }
 991
 992 static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 993                           struct hisi_sas_slot *slot)
 994 {
 995         struct sas_task *task = slot->task;
 996         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 997         struct domain_device *device = task->dev;
 998         struct hisi_sas_device *sas_dev = device->lldd_dev;
 999         struct hisi_sas_port *port = slot->port;
1000         struct sas_ssp_task *ssp_task = &task->ssp_task;
1001         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1002         struct hisi_sas_tmf_task *tmf = slot->tmf;
1003         int has_data = 0, priority = !!tmf;
1004         u8 *buf_cmd, fburst = 0;
1005         u32 dw1, dw2;
1006
1007         /* create header */
1008         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1009                                (0x2 << CMD_HDR_TLR_CTRL_OFF) |
1010                                (port->id << CMD_HDR_PORT_OFF) |
1011                                (priority << CMD_HDR_PRIORITY_OFF) |
1012                                (1 << CMD_HDR_MODE_OFF) | /* ini mode */
1013                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1014
1015         dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
1016
1017         if (tmf) {
1018                 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1019         } else {
1020                 switch (scsi_cmnd->sc_data_direction) {
1021                 case DMA_TO_DEVICE:
1022                         dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1023                         has_data = 1;
1024                         break;
1025                 case DMA_FROM_DEVICE:
1026                         dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1027                         has_data = 1;
1028                         break;
1029                 default:
1030                         dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1031                 }
1032         }
1033
1034         /* map itct entry */
1035         dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
1036         hdr->dw1 = cpu_to_le32(dw1);
1037
1038         if (tmf) {
1039                 dw2 = ((sizeof(struct ssp_tmf_iu) +
1040                         sizeof(struct ssp_frame_hdr)+3)/4) <<
1041                         CMD_HDR_CFL_OFF;
1042         } else {
1043                 dw2 = ((sizeof(struct ssp_command_iu) +
1044                         sizeof(struct ssp_frame_hdr)+3)/4) <<
1045                         CMD_HDR_CFL_OFF;
1046         }
1047
1048         dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
1049
1050         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1051
1052         if (has_data)
1053                 prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
1054                                         slot->n_elem);
1055
1056         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1057         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1058         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1059
1060         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1061                 sizeof(struct ssp_frame_hdr);
1062         if (task->ssp_task.enable_first_burst) {
1063                 fburst = (1 << 7);
1064                 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
1065         }
1066         hdr->dw2 = cpu_to_le32(dw2);
1067
1068         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1069         if (!tmf) {
1070                 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1071                                 (task->ssp_task.task_prio << 3);
1072                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1073                                 task->ssp_task.cmd->cmd_len);
1074         } else {
1075                 buf_cmd[10] = tmf->tmf;
1076                 switch (tmf->tmf) {
1077                 case TMF_ABORT_TASK:
1078                 case TMF_QUERY_TASK:
1079                         buf_cmd[12] =
1080                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1081                         buf_cmd[13] =
1082                                 tmf->tag_of_task_to_be_managed & 0xff;
1083                         break;
1084                 default:
1085                         break;
1086                 }
1087         }
1088 }
1089
1090 /* by default, task resp is complete */
1091 static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
1092                            struct sas_task *task,
1093                            struct hisi_sas_slot *slot)
1094 {
1095         struct task_status_struct *ts = &task->task_status;
1096         struct hisi_sas_err_record_v1 *err_record =
1097                         hisi_sas_status_buf_addr_mem(slot);
1098         struct device *dev = hisi_hba->dev;
1099
1100         switch (task->task_proto) {
1101         case SAS_PROTOCOL_SSP:
1102         {
1103                 int error = -1;
1104                 u32 dma_err_type = le32_to_cpu(err_record->dma_err_type);
1105                 u32 dma_tx_err_type = ((dma_err_type &
1106                                         ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
1107                                         ERR_HDR_DMA_TX_ERR_TYPE_OFF;
1108                 u32 dma_rx_err_type = ((dma_err_type &
1109                                         ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
1110                                         ERR_HDR_DMA_RX_ERR_TYPE_OFF;
1111                 u32 trans_tx_fail_type =
1112                                 le32_to_cpu(err_record->trans_tx_fail_type);
1113                 u32 trans_rx_fail_type =
1114                                 le32_to_cpu(err_record->trans_rx_fail_type);
1115
1116                 if (dma_tx_err_type) {
1117                         /* dma tx err */
1118                         error = ffs(dma_tx_err_type)
1119                                 - 1 + DMA_TX_ERR_BASE;
1120                 } else if (dma_rx_err_type) {
1121                         /* dma rx err */
1122                         error = ffs(dma_rx_err_type)
1123                                 - 1 + DMA_RX_ERR_BASE;
1124                 } else if (trans_tx_fail_type) {
1125                         /* trans tx err */
1126                         error = ffs(trans_tx_fail_type)
1127                                 - 1 + TRANS_TX_FAIL_BASE;
1128                 } else if (trans_rx_fail_type) {
1129                         /* trans rx err */
1130                         error = ffs(trans_rx_fail_type)
1131                                 - 1 + TRANS_RX_FAIL_BASE;
1132                 }
1133
1134                 switch (error) {
1135                 case DMA_TX_DATA_UNDERFLOW_ERR:
1136                 case DMA_RX_DATA_UNDERFLOW_ERR:
1137                 {
1138                         ts->residual = 0;
1139                         ts->stat = SAS_DATA_UNDERRUN;
1140                         break;
1141                 }
1142                 case DMA_TX_DATA_SGL_OVERFLOW_ERR:
1143                 case DMA_TX_DIF_SGL_OVERFLOW_ERR:
1144                 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
1145                 case DMA_RX_DATA_OVERFLOW_ERR:
1146                 case TRANS_RX_FRAME_OVERRUN_ERR:
1147                 case TRANS_RX_LINK_BUF_OVERRUN_ERR:
1148                 {
1149                         ts->stat = SAS_DATA_OVERRUN;
1150                         ts->residual = 0;
1151                         break;
1152                 }
1153                 case TRANS_TX_PHY_NOT_ENABLE_ERR:
1154                 {
1155                         ts->stat = SAS_PHY_DOWN;
1156                         break;
1157                 }
1158                 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
1159                 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
1160                 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
1161                 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
1162                 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
1163                 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
1164                 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
1165                 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
1166                 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
1167                 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
1168                 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
1169                 case TRANS_TX_OPEN_RETRY_ERR:
1170                 {
1171                         ts->stat = SAS_OPEN_REJECT;
1172                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1173                         break;
1174                 }
1175                 case TRANS_TX_OPEN_TIMEOUT_ERR:
1176                 {
1177                         ts->stat = SAS_OPEN_TO;
1178                         break;
1179                 }
1180                 case TRANS_TX_NAK_RECEIVE_ERR:
1181                 case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
1182                 {
1183                         ts->stat = SAS_NAK_R_ERR;
1184                         break;
1185                 }
1186                 case TRANS_TX_CREDIT_TIMEOUT_ERR:
1187                 case TRANS_TX_CLOSE_NORMAL_ERR:
1188                 {
1189                         /* This will request a retry */
1190                         ts->stat = SAS_QUEUE_FULL;
1191                         slot->abort = 1;
1192                         break;
1193                 }
1194                 default:
1195                 {
1196                         ts->stat = SAM_STAT_CHECK_CONDITION;
1197                         break;
1198                 }
1199                 }
1200         }
1201                 break;
1202         case SAS_PROTOCOL_SMP:
1203                 ts->stat = SAM_STAT_CHECK_CONDITION;
1204                 break;
1205
1206         case SAS_PROTOCOL_SATA:
1207         case SAS_PROTOCOL_STP:
1208         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1209         {
1210                 dev_err(dev, "slot err: SATA/STP not supported");
1211         }
1212                 break;
1213         default:
1214                 break;
1215         }
1216
1217 }
1218
1219 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1220                                struct hisi_sas_slot *slot)
1221 {
1222         struct sas_task *task = slot->task;
1223         struct hisi_sas_device *sas_dev;
1224         struct device *dev = hisi_hba->dev;
1225         struct task_status_struct *ts;
1226         struct domain_device *device;
1227         enum exec_status sts;
1228         struct hisi_sas_complete_v1_hdr *complete_queue =
1229                         hisi_hba->complete_hdr[slot->cmplt_queue];
1230         struct hisi_sas_complete_v1_hdr *complete_hdr;
1231         unsigned long flags;
1232         u32 cmplt_hdr_data;
1233
1234         complete_hdr = &complete_queue[slot->cmplt_queue_slot];
1235         cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1236
1237         if (unlikely(!task || !task->lldd_task || !task->dev))
1238                 return -EINVAL;
1239
1240         ts = &task->task_status;
1241         device = task->dev;
1242         sas_dev = device->lldd_dev;
1243
1244         spin_lock_irqsave(&task->task_state_lock, flags);
1245         task->task_state_flags &=
1246                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1247         task->task_state_flags |= SAS_TASK_STATE_DONE;
1248         spin_unlock_irqrestore(&task->task_state_lock, flags);
1249
1250         memset(ts, 0, sizeof(*ts));
1251         ts->resp = SAS_TASK_COMPLETE;
1252
1253         if (unlikely(!sas_dev)) {
1254                 dev_dbg(dev, "slot complete: port has no device\n");
1255                 ts->stat = SAS_PHY_DOWN;
1256                 goto out;
1257         }
1258
1259         if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
1260                 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
1261
1262                 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
1263                         dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
1264                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1265
1266                 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
1267                         dev_err(dev, "slot complete: [%d:%d] has dq type err",
1268                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1269
1270                 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
1271                         dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
1272                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1273
1274                 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
1275                         dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
1276                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1277
1278                 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
1279                         dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
1280                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1281
1282                 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
1283                         dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
1284                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1285
1286                 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
1287                         dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
1288                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1289
1290                 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
1291                         dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
1292                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1293
1294                 ts->stat = SAS_OPEN_REJECT;
1295                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1296                 goto out;
1297         }
1298
1299         if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK &&
1300                 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
1301
1302                 slot_err_v1_hw(hisi_hba, task, slot);
1303                 if (unlikely(slot->abort))
1304                         return ts->stat;
1305                 goto out;
1306         }
1307
1308         switch (task->task_proto) {
1309         case SAS_PROTOCOL_SSP:
1310         {
1311                 struct hisi_sas_status_buffer *status_buffer =
1312                                 hisi_sas_status_buf_addr_mem(slot);
1313                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
1314                                 &status_buffer->iu[0];
1315
1316                 sas_ssp_task_response(dev, task, iu);
1317                 break;
1318         }
1319         case SAS_PROTOCOL_SMP:
1320         {
1321                 void *to;
1322                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1323
1324                 ts->stat = SAM_STAT_GOOD;
1325                 to = kmap_atomic(sg_page(sg_resp));
1326
1327                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1328                              DMA_FROM_DEVICE);
1329                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1330                              DMA_TO_DEVICE);
1331                 memcpy(to + sg_resp->offset,
1332                        hisi_sas_status_buf_addr_mem(slot) +
1333                        sizeof(struct hisi_sas_err_record),
1334                        sg_dma_len(sg_resp));
1335                 kunmap_atomic(to);
1336                 break;
1337         }
1338         case SAS_PROTOCOL_SATA:
1339         case SAS_PROTOCOL_STP:
1340         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1341                 dev_err(dev, "slot complete: SATA/STP not supported");
1342                 break;
1343
1344         default:
1345                 ts->stat = SAM_STAT_CHECK_CONDITION;
1346                 break;
1347         }
1348
1349         if (!slot->port->port_attached) {
1350                 dev_err(dev, "slot complete: port %d has removed\n",
1351                         slot->port->sas_port.id);
1352                 ts->stat = SAS_PHY_DOWN;
1353         }
1354
1355 out:
1356         hisi_sas_slot_task_free(hisi_hba, task, slot);
1357         sts = ts->stat;
1358
1359         if (task->task_done)
1360                 task->task_done(task);
1361
1362         return sts;
1363 }
1364
1365 /* Interrupts */
1366 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
1367 {
1368         struct hisi_sas_phy *phy = p;
1369         struct hisi_hba *hisi_hba = phy->hisi_hba;
1370         struct device *dev = hisi_hba->dev;
1371         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1372         int i, phy_no = sas_phy->id;
1373         u32 irq_value, context, port_id, link_rate;
1374         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1375         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1376         irqreturn_t res = IRQ_HANDLED;
1377         unsigned long flags;
1378
1379         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1380         if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
1381                 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
1382                         irq_value);
1383                 res = IRQ_NONE;
1384                 goto end;
1385         }
1386
1387         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1388         if (context & 1 << phy_no) {
1389                 dev_err(dev, "phyup: phy%d SATA attached equipment\n",
1390                         phy_no);
1391                 goto end;
1392         }
1393
1394         port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
1395                   & 0xf;
1396         if (port_id == 0xf) {
1397                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1398                 res = IRQ_NONE;
1399                 goto end;
1400         }
1401
1402         for (i = 0; i < 6; i++) {
1403                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1404                                         RX_IDAF_DWORD0 + (i * 4));
1405                 frame_rcvd[i] = __swab32(idaf);
1406         }
1407
1408         /* Get the linkrate */
1409         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1410         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1411         sas_phy->linkrate = link_rate;
1412         sas_phy->oob_mode = SAS_OOB_MODE;
1413         memcpy(sas_phy->attached_sas_addr,
1414                 &id->sas_addr, SAS_ADDR_SIZE);
1415         dev_info(dev, "phyup: phy%d link_rate=%d\n",
1416                  phy_no, link_rate);
1417         phy->port_id = port_id;
1418         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1419         phy->phy_type |= PORT_TYPE_SAS;
1420         phy->phy_attached = 1;
1421         phy->identify.device_type = id->dev_type;
1422         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
1423         if (phy->identify.device_type == SAS_END_DEVICE)
1424                 phy->identify.target_port_protocols =
1425                         SAS_PROTOCOL_SSP;
1426         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1427                 phy->identify.target_port_protocols =
1428                         SAS_PROTOCOL_SMP;
1429         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1430
1431         spin_lock_irqsave(&phy->lock, flags);
1432         if (phy->reset_completion) {
1433                 phy->in_reset = 0;
1434                 complete(phy->reset_completion);
1435         }
1436         spin_unlock_irqrestore(&phy->lock, flags);
1437
1438 end:
1439         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1440                              CHL_INT2_SL_PHY_ENA_MSK);
1441
1442         if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
1443                 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1444
1445                 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
1446                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
1447                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
1448         }
1449
1450         return res;
1451 }
1452
1453 static irqreturn_t int_bcast_v1_hw(int irq, void *p)
1454 {
1455         struct hisi_sas_phy *phy = p;
1456         struct hisi_hba *hisi_hba = phy->hisi_hba;
1457         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1458         struct sas_ha_struct *sha = &hisi_hba->sha;
1459         struct device *dev = hisi_hba->dev;
1460         int phy_no = sas_phy->id;
1461         u32 irq_value;
1462         irqreturn_t res = IRQ_HANDLED;
1463
1464         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1465
1466         if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1467                 dev_err(dev, "bcast: irq_value = %x not set enable bit",
1468                         irq_value);
1469                 res = IRQ_NONE;
1470                 goto end;
1471         }
1472
1473         if (!test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1474                 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1475
1476 end:
1477         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1478                              CHL_INT2_SL_RX_BC_ACK_MSK);
1479
1480         return res;
1481 }
1482
1483 static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
1484 {
1485         struct hisi_sas_phy *phy = p;
1486         struct hisi_hba *hisi_hba = phy->hisi_hba;
1487         struct device *dev = hisi_hba->dev;
1488         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1489         u32 irq_value, irq_mask_old;
1490         int phy_no = sas_phy->id;
1491
1492         /* mask_int0 */
1493         irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
1494         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
1495
1496         /* read int0 */
1497         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1498
1499         if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
1500                 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1501
1502                 hisi_sas_phy_down(hisi_hba, phy_no,
1503                                   (phy_state & 1 << phy_no) ? 1 : 0);
1504         }
1505
1506         if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
1507                 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
1508                         phy_no);
1509
1510         if (irq_value & CHL_INT0_DWS_LOST_MSK)
1511                 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
1512
1513         if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
1514                 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
1515                         phy_no);
1516
1517         if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
1518                 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
1519                 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
1520                         phy_no);
1521
1522         if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
1523                 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
1524
1525         /* write to zero */
1526         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
1527
1528         if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
1529                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1530                                 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1531         else
1532                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1533                                 irq_mask_old);
1534
1535         return IRQ_HANDLED;
1536 }
1537
1538 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
1539 {
1540         struct hisi_sas_cq *cq = p;
1541         struct hisi_hba *hisi_hba = cq->hisi_hba;
1542         struct hisi_sas_slot *slot;
1543         int queue = cq->id;
1544         struct hisi_sas_complete_v1_hdr *complete_queue =
1545                         (struct hisi_sas_complete_v1_hdr *)
1546                         hisi_hba->complete_hdr[queue];
1547         u32 irq_value, rd_point = cq->rd_point, wr_point;
1548
1549         spin_lock(&hisi_hba->lock);
1550         irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1551
1552         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1553         wr_point = hisi_sas_read32(hisi_hba,
1554                         COMPL_Q_0_WR_PTR + (0x14 * queue));
1555
1556         while (rd_point != wr_point) {
1557                 struct hisi_sas_complete_v1_hdr *complete_hdr;
1558                 int idx;
1559                 u32 cmplt_hdr_data;
1560
1561                 complete_hdr = &complete_queue[rd_point];
1562                 cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1563                 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
1564                       CMPLT_HDR_IPTT_OFF;
1565                 slot = &hisi_hba->slot_info[idx];
1566
1567                 /* The completion queue and queue slot index are not
1568                  * necessarily the same as the delivery queue and
1569                  * queue slot index.
1570                  */
1571                 slot->cmplt_queue_slot = rd_point;
1572                 slot->cmplt_queue = queue;
1573                 slot_complete_v1_hw(hisi_hba, slot);
1574
1575                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1576                         rd_point = 0;
1577         }
1578
1579         /* update rd_point */
1580         cq->rd_point = rd_point;
1581         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1582         spin_unlock(&hisi_hba->lock);
1583
1584         return IRQ_HANDLED;
1585 }
1586
1587 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
1588 {
1589         struct hisi_hba *hisi_hba = p;
1590         struct device *dev = hisi_hba->dev;
1591         u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1592
1593         if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
1594                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1595
1596                 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
1597                       dev_name(dev), ecc_err);
1598         }
1599
1600         if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
1601                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
1602                                 HGC_DQ_ECC_ADDR_BAD_MSK) >>
1603                                 HGC_DQ_ECC_ADDR_BAD_OFF;
1604
1605                 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
1606                       dev_name(dev), addr);
1607         }
1608
1609         if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
1610                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1611
1612                 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
1613                       dev_name(dev), ecc_err);
1614         }
1615
1616         if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
1617                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
1618                                 HGC_IOST_ECC_ADDR_BAD_MSK) >>
1619                                 HGC_IOST_ECC_ADDR_BAD_OFF;
1620
1621                 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
1622                       dev_name(dev), addr);
1623         }
1624
1625         if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
1626                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
1627                                 HGC_ITCT_ECC_ADDR_BAD_MSK) >>
1628                                 HGC_ITCT_ECC_ADDR_BAD_OFF;
1629
1630                 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
1631                       dev_name(dev), addr);
1632         }
1633
1634         if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
1635                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1636
1637                 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
1638                       dev_name(dev), ecc_err);
1639         }
1640
1641         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
1642
1643         return IRQ_HANDLED;
1644 }
1645
1646 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
1647 {
1648         struct hisi_hba *hisi_hba = p;
1649         struct device *dev = hisi_hba->dev;
1650         u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
1651         u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
1652
1653         if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
1654                 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
1655                       dev_name(dev), axi_info);
1656
1657         if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
1658                 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
1659                       dev_name(dev), axi_info);
1660
1661         if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
1662                 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
1663                       dev_name(dev), axi_info);
1664
1665         if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
1666                 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
1667                       dev_name(dev), axi_info);
1668
1669         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
1670
1671         return IRQ_HANDLED;
1672 }
1673
1674 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1675         int_bcast_v1_hw,
1676         int_phyup_v1_hw,
1677         int_abnormal_v1_hw
1678 };
1679
1680 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
1681         fatal_ecc_int_v1_hw,
1682         fatal_axi_int_v1_hw
1683 };
1684
1685 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
1686 {
1687         struct platform_device *pdev = hisi_hba->platform_dev;
1688         struct device *dev = &pdev->dev;
1689         int i, j, irq, rc, idx;
1690
1691         for (i = 0; i < hisi_hba->n_phy; i++) {
1692                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1693
1694                 idx = i * HISI_SAS_PHY_INT_NR;
1695                 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
1696                         irq = platform_get_irq(pdev, idx);
1697                         if (!irq) {
1698                                 dev_err(dev,
1699                                         "irq init: fail map phy interrupt %d\n",
1700                                         idx);
1701                                 return -ENOENT;
1702                         }
1703
1704                         rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
1705                                               DRV_NAME " phy", phy);
1706                         if (rc) {
1707                                 dev_err(dev, "irq init: could not request "
1708                                         "phy interrupt %d, rc=%d\n",
1709                                         irq, rc);
1710                                 return -ENOENT;
1711                         }
1712                 }
1713         }
1714
1715         idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
1716         for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
1717                 irq = platform_get_irq(pdev, idx);
1718                 if (!irq) {
1719                         dev_err(dev, "irq init: could not map cq interrupt %d\n",
1720                                 idx);
1721                         return -ENOENT;
1722                 }
1723
1724                 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
1725                                       DRV_NAME " cq", &hisi_hba->cq[i]);
1726                 if (rc) {
1727                         dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
1728                                 irq, rc);
1729                         return -ENOENT;
1730                 }
1731         }
1732
1733         idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
1734         for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
1735                 irq = platform_get_irq(pdev, idx);
1736                 if (!irq) {
1737                         dev_err(dev, "irq init: could not map fatal interrupt %d\n",
1738                                 idx);
1739                         return -ENOENT;
1740                 }
1741
1742                 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
1743                                       DRV_NAME " fatal", hisi_hba);
1744                 if (rc) {
1745                         dev_err(dev,
1746                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
1747                                 irq, rc);
1748                         return -ENOENT;
1749                 }
1750         }
1751
1752         return 0;
1753 }
1754
1755 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
1756 {
1757         int i;
1758         u32 val;
1759
1760         for (i = 0; i < hisi_hba->n_phy; i++) {
1761                 /* Clear interrupt status */
1762                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
1763                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
1764                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
1765                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
1766                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
1767                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
1768
1769                 /* Unmask interrupt */
1770                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
1771                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
1772                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
1773
1774                 /* bypass chip bug mask abnormal intr */
1775                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK,
1776                                 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1777         }
1778
1779         return 0;
1780 }
1781
1782 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
1783 {
1784         int rc;
1785
1786         rc = hw_init_v1_hw(hisi_hba);
1787         if (rc)
1788                 return rc;
1789
1790         rc = interrupt_init_v1_hw(hisi_hba);
1791         if (rc)
1792                 return rc;
1793
1794         rc = interrupt_openall_v1_hw(hisi_hba);
1795         if (rc)
1796                 return rc;
1797
1798         return 0;
1799 }
1800
1801 static struct device_attribute *host_attrs_v1_hw[] = {
1802         &dev_attr_phy_event_threshold,
1803         NULL
1804 };
1805
1806 static struct scsi_host_template sht_v1_hw = {
1807         .name                   = DRV_NAME,
1808         .module                 = THIS_MODULE,
1809         .queuecommand           = sas_queuecommand,
1810         .target_alloc           = sas_target_alloc,
1811         .slave_configure        = hisi_sas_slave_configure,
1812         .scan_finished          = hisi_sas_scan_finished,
1813         .scan_start             = hisi_sas_scan_start,
1814         .change_queue_depth     = sas_change_queue_depth,
1815         .bios_param             = sas_bios_param,
1816         .this_id                = -1,
1817         .sg_tablesize           = HISI_SAS_SGE_PAGE_CNT,
1818         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
1819         .eh_device_reset_handler = sas_eh_device_reset_handler,
1820         .eh_target_reset_handler = sas_eh_target_reset_handler,
1821         .target_destroy         = sas_target_destroy,
1822         .ioctl                  = sas_ioctl,
1823         .shost_attrs            = host_attrs_v1_hw,
1824 };
1825
1826 static const struct hisi_sas_hw hisi_sas_v1_hw = {
1827         .hw_init = hisi_sas_v1_init,
1828         .setup_itct = setup_itct_v1_hw,
1829         .sl_notify = sl_notify_v1_hw,
1830         .clear_itct = clear_itct_v1_hw,
1831         .prep_smp = prep_smp_v1_hw,
1832         .prep_ssp = prep_ssp_v1_hw,
1833         .get_free_slot = get_free_slot_v1_hw,
1834         .start_delivery = start_delivery_v1_hw,
1835         .slot_complete = slot_complete_v1_hw,
1836         .phys_init = phys_init_v1_hw,
1837         .phy_start = start_phy_v1_hw,
1838         .phy_disable = disable_phy_v1_hw,
1839         .phy_hard_reset = phy_hard_reset_v1_hw,
1840         .phy_set_linkrate = phy_set_linkrate_v1_hw,
1841         .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw,
1842         .get_wideport_bitmap = get_wideport_bitmap_v1_hw,
1843         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW,
1844         .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
1845         .sht = &sht_v1_hw,
1846 };
1847
1848 static int hisi_sas_v1_probe(struct platform_device *pdev)
1849 {
1850         return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
1851 }
1852
1853 static int hisi_sas_v1_remove(struct platform_device *pdev)
1854 {
1855         return hisi_sas_remove(pdev);
1856 }
1857
1858 static const struct of_device_id sas_v1_of_match[] = {
1859         { .compatible = "hisilicon,hip05-sas-v1",},
1860         {},
1861 };
1862 MODULE_DEVICE_TABLE(of, sas_v1_of_match);
1863
1864 static const struct acpi_device_id sas_v1_acpi_match[] = {
1865         { "HISI0161", 0 },
1866         { }
1867 };
1868
1869 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match);
1870
1871 static struct platform_driver hisi_sas_v1_driver = {
1872         .probe = hisi_sas_v1_probe,
1873         .remove = hisi_sas_v1_remove,
1874         .driver = {
1875                 .name = DRV_NAME,
1876                 .of_match_table = sas_v1_of_match,
1877                 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match),
1878         },
1879 };
1880
1881 module_platform_driver(hisi_sas_v1_driver);
1882
1883 MODULE_LICENSE("GPL");
1884 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1885 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
1886 MODULE_ALIAS("platform:" DRV_NAME);