2 * Copyright IBM Corp. 2016
3 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
5 * Adjunct processor bus inline assemblies.
14 * ap_intructions_available() - Test if AP instructions are available.
16 * Returns 0 if the AP instructions are installed.
18 static inline int ap_instructions_available(void)
20 register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
21 register unsigned long reg1 asm ("1") = -ENODEV;
22 register unsigned long reg2 asm ("2") = 0UL;
25 " .long 0xb2af0000\n" /* PQAP(TAPQ) */
29 : "+d" (reg0), "+d" (reg1), "+d" (reg2) : : "cc");
34 * ap_tapq(): Test adjunct processor queue.
35 * @qid: The AP queue number
36 * @info: Pointer to queue descriptor
38 * Returns AP queue status structure.
40 static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
42 register unsigned long reg0 asm ("0") = qid;
43 register struct ap_queue_status reg1 asm ("1");
44 register unsigned long reg2 asm ("2") = 0UL;
46 asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
47 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
54 * ap_pqap_rapq(): Reset adjunct processor queue.
55 * @qid: The AP queue number
57 * Returns AP queue status structure.
59 static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
61 register unsigned long reg0 asm ("0") = qid | 0x01000000UL;
62 register struct ap_queue_status reg1 asm ("1");
63 register unsigned long reg2 asm ("2") = 0UL;
66 ".long 0xb2af0000" /* PQAP(RAPQ) */
67 : "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
72 * ap_aqic(): Control interruption for a specific AP.
73 * @qid: The AP queue number
74 * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
75 * @ind: The notification indicator byte
77 * Returns AP queue status.
79 static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
80 struct ap_qirq_ctrl qirqctrl,
83 register unsigned long reg0 asm ("0") = qid | (3UL << 24);
84 register struct ap_qirq_ctrl reg1_in asm ("1") = qirqctrl;
85 register struct ap_queue_status reg1_out asm ("1");
86 register void *reg2 asm ("2") = ind;
89 ".long 0xb2af0000" /* PQAP(AQIC) */
90 : "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2)
97 * ap_qci(): Get AP configuration data
99 * Returns 0 on success, or -EOPNOTSUPP.
101 static inline int ap_qci(void *config)
103 register unsigned long reg0 asm ("0") = 0x04000000UL;
104 register unsigned long reg1 asm ("1") = -EINVAL;
105 register void *reg2 asm ("2") = (void *) config;
108 ".long 0xb2af0000\n" /* PQAP(QCI) */
112 : "+d" (reg0), "+d" (reg1), "+d" (reg2)
120 * ap_nqap(): Send message to adjunct processor queue.
121 * @qid: The AP queue number
122 * @psmid: The program supplied message identifier
123 * @msg: The message text
124 * @length: The message length
126 * Returns AP queue status structure.
127 * Condition code 1 on NQAP can't happen because the L bit is 1.
128 * Condition code 2 on NQAP also means the send is incomplete,
129 * because a segment boundary was reached. The NQAP is repeated.
131 static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
132 unsigned long long psmid,
133 void *msg, size_t length)
135 register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
136 register struct ap_queue_status reg1 asm ("1");
137 register unsigned long reg2 asm ("2") = (unsigned long) msg;
138 register unsigned long reg3 asm ("3") = (unsigned long) length;
139 register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
140 register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
143 "0: .long 0xb2ad0042\n" /* NQAP */
145 : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
146 : "d" (reg4), "d" (reg5)
152 * ap_dqap(): Receive message from adjunct processor queue.
153 * @qid: The AP queue number
154 * @psmid: Pointer to program supplied message identifier
155 * @msg: The message text
156 * @length: The message length
158 * Returns AP queue status structure.
159 * Condition code 1 on DQAP means the receive has taken place
160 * but only partially. The response is incomplete, hence the
162 * Condition code 2 on DQAP also means the receive is incomplete,
163 * this time because a segment boundary was reached. Again, the
165 * Note that gpr2 is used by the DQAP instruction to keep track of
166 * any 'residual' length, in case the instruction gets interrupted.
167 * Hence it gets zeroed before the instruction.
169 static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
170 unsigned long long *psmid,
171 void *msg, size_t length)
173 register unsigned long reg0 asm("0") = qid | 0x80000000UL;
174 register struct ap_queue_status reg1 asm ("1");
175 register unsigned long reg2 asm("2") = 0UL;
176 register unsigned long reg4 asm("4") = (unsigned long) msg;
177 register unsigned long reg5 asm("5") = (unsigned long) length;
178 register unsigned long reg6 asm("6") = 0UL;
179 register unsigned long reg7 asm("7") = 0UL;
183 "0: .long 0xb2ae0064\n" /* DQAP */
185 : "+d" (reg0), "=d" (reg1), "+d" (reg2),
186 "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
188 *psmid = (((unsigned long long) reg6) << 32) + reg7;
192 #endif /* _AP_ASM_H_ */