drivers/rtc/rtc-omap.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI OMAP Real Time Clock interface for Linux
   4  *
   5  * Copyright (C) 2003 MontaVista Software, Inc.
   6  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
   7  *
   8  * Copyright (C) 2006 David Brownell (new RTC framework)
   9  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <linux/bcd.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/ioport.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/pinctrl/pinctrl.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/rtc.h>
  29
  30 /*
  31  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
  32  * with century-range alarm matching, driven by the 32kHz clock.
  33  *
  34  * The main user-visible ways it differs from PC RTCs are by omitting
  35  * "don't care" alarm fields and sub-second periodic IRQs, and having
  36  * an autoadjust mechanism to calibrate to the true oscillator rate.
  37  *
  38  * Board-specific wiring options include using split power mode with
  39  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
  40  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
  41  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
  42  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
  43  */
  44
  45 /* RTC registers */
  46 #define OMAP_RTC_SECONDS_REG            0x00
  47 #define OMAP_RTC_MINUTES_REG            0x04
  48 #define OMAP_RTC_HOURS_REG              0x08
  49 #define OMAP_RTC_DAYS_REG               0x0C
  50 #define OMAP_RTC_MONTHS_REG             0x10
  51 #define OMAP_RTC_YEARS_REG              0x14
  52 #define OMAP_RTC_WEEKS_REG              0x18
  53
  54 #define OMAP_RTC_ALARM_SECONDS_REG      0x20
  55 #define OMAP_RTC_ALARM_MINUTES_REG      0x24
  56 #define OMAP_RTC_ALARM_HOURS_REG        0x28
  57 #define OMAP_RTC_ALARM_DAYS_REG         0x2c
  58 #define OMAP_RTC_ALARM_MONTHS_REG       0x30
  59 #define OMAP_RTC_ALARM_YEARS_REG        0x34
  60
  61 #define OMAP_RTC_CTRL_REG               0x40
  62 #define OMAP_RTC_STATUS_REG             0x44
  63 #define OMAP_RTC_INTERRUPTS_REG         0x48
  64
  65 #define OMAP_RTC_COMP_LSB_REG           0x4c
  66 #define OMAP_RTC_COMP_MSB_REG           0x50
  67 #define OMAP_RTC_OSC_REG                0x54
  68
  69 #define OMAP_RTC_SCRATCH0_REG           0x60
  70 #define OMAP_RTC_SCRATCH1_REG           0x64
  71 #define OMAP_RTC_SCRATCH2_REG           0x68
  72
  73 #define OMAP_RTC_KICK0_REG              0x6c
  74 #define OMAP_RTC_KICK1_REG              0x70
  75
  76 #define OMAP_RTC_IRQWAKEEN              0x7c
  77
  78 #define OMAP_RTC_ALARM2_SECONDS_REG     0x80
  79 #define OMAP_RTC_ALARM2_MINUTES_REG     0x84
  80 #define OMAP_RTC_ALARM2_HOURS_REG       0x88
  81 #define OMAP_RTC_ALARM2_DAYS_REG        0x8c
  82 #define OMAP_RTC_ALARM2_MONTHS_REG      0x90
  83 #define OMAP_RTC_ALARM2_YEARS_REG       0x94
  84
  85 #define OMAP_RTC_PMIC_REG               0x98
  86
  87 /* OMAP_RTC_CTRL_REG bit fields: */
  88 #define OMAP_RTC_CTRL_SPLIT             BIT(7)
  89 #define OMAP_RTC_CTRL_DISABLE           BIT(6)
  90 #define OMAP_RTC_CTRL_SET_32_COUNTER    BIT(5)
  91 #define OMAP_RTC_CTRL_TEST              BIT(4)
  92 #define OMAP_RTC_CTRL_MODE_12_24        BIT(3)
  93 #define OMAP_RTC_CTRL_AUTO_COMP         BIT(2)
  94 #define OMAP_RTC_CTRL_ROUND_30S         BIT(1)
  95 #define OMAP_RTC_CTRL_STOP              BIT(0)
  96
  97 /* OMAP_RTC_STATUS_REG bit fields: */
  98 #define OMAP_RTC_STATUS_POWER_UP        BIT(7)
  99 #define OMAP_RTC_STATUS_ALARM2          BIT(7)
 100 #define OMAP_RTC_STATUS_ALARM           BIT(6)
 101 #define OMAP_RTC_STATUS_1D_EVENT        BIT(5)
 102 #define OMAP_RTC_STATUS_1H_EVENT        BIT(4)
 103 #define OMAP_RTC_STATUS_1M_EVENT        BIT(3)
 104 #define OMAP_RTC_STATUS_1S_EVENT        BIT(2)
 105 #define OMAP_RTC_STATUS_RUN             BIT(1)
 106 #define OMAP_RTC_STATUS_BUSY            BIT(0)
 107
 108 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
 109 #define OMAP_RTC_INTERRUPTS_IT_ALARM2   BIT(4)
 110 #define OMAP_RTC_INTERRUPTS_IT_ALARM    BIT(3)
 111 #define OMAP_RTC_INTERRUPTS_IT_TIMER    BIT(2)
 112
 113 /* OMAP_RTC_OSC_REG bit fields: */
 114 #define OMAP_RTC_OSC_32KCLK_EN          BIT(6)
 115 #define OMAP_RTC_OSC_SEL_32KCLK_SRC     BIT(3)
 116 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE  BIT(4)
 117
 118 /* OMAP_RTC_IRQWAKEEN bit fields: */
 119 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
 120
 121 /* OMAP_RTC_PMIC bit fields: */
 122 #define OMAP_RTC_PMIC_POWER_EN_EN       BIT(16)
 123 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x)    BIT(x)
 124 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x)   BIT(4 + x)
 125
 126 /* OMAP_RTC_KICKER values */
 127 #define KICK0_VALUE                     0x83e70b13
 128 #define KICK1_VALUE                     0x95a4f1e0
 129
 130 struct omap_rtc;
 131
 132 struct omap_rtc_device_type {
 133         bool has_32kclk_en;
 134         bool has_irqwakeen;
 135         bool has_pmic_mode;
 136         bool has_power_up_reset;
 137         void (*lock)(struct omap_rtc *rtc);
 138         void (*unlock)(struct omap_rtc *rtc);
 139 };
 140
 141 struct omap_rtc {
 142         struct rtc_device *rtc;
 143         void __iomem *base;
 144         struct clk *clk;
 145         int irq_alarm;
 146         int irq_timer;
 147         u8 interrupts_reg;
 148         bool is_pmic_controller;
 149         bool has_ext_clk;
 150         bool is_suspending;
 151         const struct omap_rtc_device_type *type;
 152         struct pinctrl_dev *pctldev;
 153 };
 154
 155 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
 156 {
 157         return readb(rtc->base + reg);
 158 }
 159
 160 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
 161 {
 162         return readl(rtc->base + reg);
 163 }
 164
 165 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
 166 {
 167         writeb(val, rtc->base + reg);
 168 }
 169
 170 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
 171 {
 172         writel(val, rtc->base + reg);
 173 }
 174
 175 static void am3352_rtc_unlock(struct omap_rtc *rtc)
 176 {
 177         rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
 178         rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
 179 }
 180
 181 static void am3352_rtc_lock(struct omap_rtc *rtc)
 182 {
 183         rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
 184         rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0);
 185 }
 186
 187 static void default_rtc_unlock(struct omap_rtc *rtc)
 188 {
 189 }
 190
 191 static void default_rtc_lock(struct omap_rtc *rtc)
 192 {
 193 }
 194
 195 /*
 196  * We rely on the rtc framework to handle locking (rtc->ops_lock),
 197  * so the only other requirement is that register accesses which
 198  * require BUSY to be clear are made with IRQs locally disabled
 199  */
 200 static void rtc_wait_not_busy(struct omap_rtc *rtc)
 201 {
 202         int count;
 203         u8 status;
 204
 205         /* BUSY may stay active for 1/32768 second (~30 usec) */
 206         for (count = 0; count < 50; count++) {
 207                 status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 208                 if (!(status & OMAP_RTC_STATUS_BUSY))
 209                         break;
 210                 udelay(1);
 211         }
 212         /* now we have ~15 usec to read/write various registers */
 213 }
 214
 215 static irqreturn_t rtc_irq(int irq, void *dev_id)
 216 {
 217         struct omap_rtc *rtc = dev_id;
 218         unsigned long events = 0;
 219         u8 irq_data;
 220
 221         irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 222
 223         /* alarm irq? */
 224         if (irq_data & OMAP_RTC_STATUS_ALARM) {
 225                 rtc->type->unlock(rtc);
 226                 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
 227                 rtc->type->lock(rtc);
 228                 events |= RTC_IRQF | RTC_AF;
 229         }
 230
 231         /* 1/sec periodic/update irq? */
 232         if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
 233                 events |= RTC_IRQF | RTC_UF;
 234
 235         rtc_update_irq(rtc->rtc, 1, events);
 236
 237         return IRQ_HANDLED;
 238 }
 239
 240 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 241 {
 242         struct omap_rtc *rtc = dev_get_drvdata(dev);
 243         u8 reg, irqwake_reg = 0;
 244
 245         local_irq_disable();
 246         rtc_wait_not_busy(rtc);
 247         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 248         if (rtc->type->has_irqwakeen)
 249                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 250
 251         if (enabled) {
 252                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 253                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 254         } else {
 255                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 256                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 257         }
 258         rtc_wait_not_busy(rtc);
 259         rtc->type->unlock(rtc);
 260         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 261         if (rtc->type->has_irqwakeen)
 262                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 263         rtc->type->lock(rtc);
 264         local_irq_enable();
 265
 266         return 0;
 267 }
 268
 269 /* this hardware doesn't support "don't care" alarm fields */
 270 static void tm2bcd(struct rtc_time *tm)
 271 {
 272         tm->tm_sec = bin2bcd(tm->tm_sec);
 273         tm->tm_min = bin2bcd(tm->tm_min);
 274         tm->tm_hour = bin2bcd(tm->tm_hour);
 275         tm->tm_mday = bin2bcd(tm->tm_mday);
 276
 277         tm->tm_mon = bin2bcd(tm->tm_mon + 1);
 278         tm->tm_year = bin2bcd(tm->tm_year - 100);
 279 }
 280
 281 static void bcd2tm(struct rtc_time *tm)
 282 {
 283         tm->tm_sec = bcd2bin(tm->tm_sec);
 284         tm->tm_min = bcd2bin(tm->tm_min);
 285         tm->tm_hour = bcd2bin(tm->tm_hour);
 286         tm->tm_mday = bcd2bin(tm->tm_mday);
 287         tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
 288         /* epoch == 1900 */
 289         tm->tm_year = bcd2bin(tm->tm_year) + 100;
 290 }
 291
 292 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
 293 {
 294         tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
 295         tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
 296         tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
 297         tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
 298         tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
 299         tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
 300 }
 301
 302 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
 303 {
 304         struct omap_rtc *rtc = dev_get_drvdata(dev);
 305
 306         /* we don't report wday/yday/isdst ... */
 307         local_irq_disable();
 308         rtc_wait_not_busy(rtc);
 309         omap_rtc_read_time_raw(rtc, tm);
 310         local_irq_enable();
 311
 312         bcd2tm(tm);
 313
 314         return 0;
 315 }
 316
 317 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
 318 {
 319         struct omap_rtc *rtc = dev_get_drvdata(dev);
 320
 321         tm2bcd(tm);
 322
 323         local_irq_disable();
 324         rtc_wait_not_busy(rtc);
 325
 326         rtc->type->unlock(rtc);
 327         rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
 328         rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
 329         rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
 330         rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
 331         rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
 332         rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
 333         rtc->type->lock(rtc);
 334
 335         local_irq_enable();
 336
 337         return 0;
 338 }
 339
 340 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 341 {
 342         struct omap_rtc *rtc = dev_get_drvdata(dev);
 343         u8 interrupts;
 344
 345         local_irq_disable();
 346         rtc_wait_not_busy(rtc);
 347
 348         alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
 349         alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
 350         alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
 351         alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
 352         alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
 353         alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
 354
 355         local_irq_enable();
 356
 357         bcd2tm(&alm->time);
 358
 359         interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 360         alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
 361
 362         return 0;
 363 }
 364
 365 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 366 {
 367         struct omap_rtc *rtc = dev_get_drvdata(dev);
 368         u8 reg, irqwake_reg = 0;
 369
 370         tm2bcd(&alm->time);
 371
 372         local_irq_disable();
 373         rtc_wait_not_busy(rtc);
 374
 375         rtc->type->unlock(rtc);
 376         rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
 377         rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
 378         rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
 379         rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
 380         rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
 381         rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
 382
 383         reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 384         if (rtc->type->has_irqwakeen)
 385                 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
 386
 387         if (alm->enabled) {
 388                 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
 389                 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 390         } else {
 391                 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
 392                 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
 393         }
 394         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
 395         if (rtc->type->has_irqwakeen)
 396                 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
 397         rtc->type->lock(rtc);
 398
 399         local_irq_enable();
 400
 401         return 0;
 402 }
 403
 404 static struct omap_rtc *omap_rtc_power_off_rtc;
 405
 406 /*
 407  * omap_rtc_poweroff: RTC-controlled power off
 408  *
 409  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
 410  * which can be configured to transition to OFF on ALARM2 events.
 411  *
 412  * Called with local interrupts disabled.
 413  */
 414 static void omap_rtc_power_off(void)
 415 {
 416         struct omap_rtc *rtc = omap_rtc_power_off_rtc;
 417         struct rtc_time tm;
 418         unsigned long now;
 419         int seconds;
 420         u32 val;
 421
 422         rtc->type->unlock(rtc);
 423         /* enable pmic_power_en control */
 424         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 425         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
 426
 427 again:
 428         /* set alarm one second from now */
 429         omap_rtc_read_time_raw(rtc, &tm);
 430         seconds = tm.tm_sec;
 431         bcd2tm(&tm);
 432         now = rtc_tm_to_time64(&tm);
 433         rtc_time64_to_tm(now + 1, &tm);
 434
 435         tm2bcd(&tm);
 436
 437         rtc_wait_not_busy(rtc);
 438
 439         rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
 440         rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
 441         rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
 442         rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
 443         rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
 444         rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
 445
 446         /*
 447          * enable ALARM2 interrupt
 448          *
 449          * NOTE: this fails on AM3352 if rtc_write (writeb) is used
 450          */
 451         val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 452         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
 453                         val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
 454
 455         /* Retry in case roll over happened before alarm was armed. */
 456         if (rtc_read(rtc, OMAP_RTC_SECONDS_REG) != seconds) {
 457                 val = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 458                 if (!(val & OMAP_RTC_STATUS_ALARM2))
 459                         goto again;
 460         }
 461
 462         rtc->type->lock(rtc);
 463
 464         /*
 465          * Wait for alarm to trigger (within one second) and external PMIC to
 466          * power off the system. Add a 500 ms margin for external latencies
 467          * (e.g. debounce circuits).
 468          */
 469         mdelay(1500);
 470 }
 471
 472 static const struct rtc_class_ops omap_rtc_ops = {
 473         .read_time      = omap_rtc_read_time,
 474         .set_time       = omap_rtc_set_time,
 475         .read_alarm     = omap_rtc_read_alarm,
 476         .set_alarm      = omap_rtc_set_alarm,
 477         .alarm_irq_enable = omap_rtc_alarm_irq_enable,
 478 };
 479
 480 static const struct omap_rtc_device_type omap_rtc_default_type = {
 481         .has_power_up_reset = true,
 482         .lock           = default_rtc_lock,
 483         .unlock         = default_rtc_unlock,
 484 };
 485
 486 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
 487         .has_32kclk_en  = true,
 488         .has_irqwakeen  = true,
 489         .has_pmic_mode  = true,
 490         .lock           = am3352_rtc_lock,
 491         .unlock         = am3352_rtc_unlock,
 492 };
 493
 494 static const struct omap_rtc_device_type omap_rtc_da830_type = {
 495         .lock           = am3352_rtc_lock,
 496         .unlock         = am3352_rtc_unlock,
 497 };
 498
 499 static const struct platform_device_id omap_rtc_id_table[] = {
 500         {
 501                 .name   = "omap_rtc",
 502                 .driver_data = (kernel_ulong_t)&omap_rtc_default_type,
 503         }, {
 504                 .name   = "am3352-rtc",
 505                 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
 506         }, {
 507                 .name   = "da830-rtc",
 508                 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
 509         }, {
 510                 /* sentinel */
 511         }
 512 };
 513 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
 514
 515 static const struct of_device_id omap_rtc_of_match[] = {
 516         {
 517                 .compatible     = "ti,am3352-rtc",
 518                 .data           = &omap_rtc_am3352_type,
 519         }, {
 520                 .compatible     = "ti,da830-rtc",
 521                 .data           = &omap_rtc_da830_type,
 522         }, {
 523                 /* sentinel */
 524         }
 525 };
 526 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
 527
 528 static const struct pinctrl_pin_desc rtc_pins_desc[] = {
 529         PINCTRL_PIN(0, "ext_wakeup0"),
 530         PINCTRL_PIN(1, "ext_wakeup1"),
 531         PINCTRL_PIN(2, "ext_wakeup2"),
 532         PINCTRL_PIN(3, "ext_wakeup3"),
 533 };
 534
 535 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 536 {
 537         return 0;
 538 }
 539
 540 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 541                                         unsigned int group)
 542 {
 543         return NULL;
 544 }
 545
 546 static const struct pinctrl_ops rtc_pinctrl_ops = {
 547         .get_groups_count = rtc_pinctrl_get_groups_count,
 548         .get_group_name = rtc_pinctrl_get_group_name,
 549         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 550         .dt_free_map = pinconf_generic_dt_free_map,
 551 };
 552
 553 #define PIN_CONFIG_ACTIVE_HIGH          (PIN_CONFIG_END + 1)
 554
 555 static const struct pinconf_generic_params rtc_params[] = {
 556         {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0},
 557 };
 558
 559 #ifdef CONFIG_DEBUG_FS
 560 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = {
 561         PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false),
 562 };
 563 #endif
 564
 565 static int rtc_pinconf_get(struct pinctrl_dev *pctldev,
 566                         unsigned int pin, unsigned long *config)
 567 {
 568         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
 569         unsigned int param = pinconf_to_config_param(*config);
 570         u32 val;
 571         u16 arg = 0;
 572
 573         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 574
 575         switch (param) {
 576         case PIN_CONFIG_INPUT_ENABLE:
 577                 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin)))
 578                         return -EINVAL;
 579                 break;
 580         case PIN_CONFIG_ACTIVE_HIGH:
 581                 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin))
 582                         return -EINVAL;
 583                 break;
 584         default:
 585                 return -ENOTSUPP;
 586         };
 587
 588         *config = pinconf_to_config_packed(param, arg);
 589
 590         return 0;
 591 }
 592
 593 static int rtc_pinconf_set(struct pinctrl_dev *pctldev,
 594                         unsigned int pin, unsigned long *configs,
 595                         unsigned int num_configs)
 596 {
 597         struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev);
 598         u32 val;
 599         unsigned int param;
 600         u32 param_val;
 601         int i;
 602
 603         val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
 604
 605         /* active low by default */
 606         val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
 607
 608         for (i = 0; i < num_configs; i++) {
 609                 param = pinconf_to_config_param(configs[i]);
 610                 param_val = pinconf_to_config_argument(configs[i]);
 611
 612                 switch (param) {
 613                 case PIN_CONFIG_INPUT_ENABLE:
 614                         if (param_val)
 615                                 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
 616                         else
 617                                 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin);
 618                         break;
 619                 case PIN_CONFIG_ACTIVE_HIGH:
 620                         val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin);
 621                         break;
 622                 default:
 623                         dev_err(&rtc->rtc->dev, "Property %u not supported\n",
 624                                 param);
 625                         return -ENOTSUPP;
 626                 }
 627         }
 628
 629         rtc->type->unlock(rtc);
 630         rtc_writel(rtc, OMAP_RTC_PMIC_REG, val);
 631         rtc->type->lock(rtc);
 632
 633         return 0;
 634 }
 635
 636 static const struct pinconf_ops rtc_pinconf_ops = {
 637         .is_generic = true,
 638         .pin_config_get = rtc_pinconf_get,
 639         .pin_config_set = rtc_pinconf_set,
 640 };
 641
 642 static struct pinctrl_desc rtc_pinctrl_desc = {
 643         .pins = rtc_pins_desc,
 644         .npins = ARRAY_SIZE(rtc_pins_desc),
 645         .pctlops = &rtc_pinctrl_ops,
 646         .confops = &rtc_pinconf_ops,
 647         .custom_params = rtc_params,
 648         .num_custom_params = ARRAY_SIZE(rtc_params),
 649 #ifdef CONFIG_DEBUG_FS
 650         .custom_conf_items = rtc_conf_items,
 651 #endif
 652         .owner = THIS_MODULE,
 653 };
 654
 655 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val,
 656                                  size_t bytes)
 657 {
 658         struct omap_rtc *rtc = priv;
 659         u32 *val = _val;
 660         int i;
 661
 662         for (i = 0; i < bytes / 4; i++)
 663                 val[i] = rtc_readl(rtc,
 664                                    OMAP_RTC_SCRATCH0_REG + offset + (i * 4));
 665
 666         return 0;
 667 }
 668
 669 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val,
 670                                   size_t bytes)
 671 {
 672         struct omap_rtc *rtc = priv;
 673         u32 *val = _val;
 674         int i;
 675
 676         rtc->type->unlock(rtc);
 677         for (i = 0; i < bytes / 4; i++)
 678                 rtc_writel(rtc,
 679                            OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]);
 680         rtc->type->lock(rtc);
 681
 682         return 0;
 683 }
 684
 685 static struct nvmem_config omap_rtc_nvmem_config = {
 686         .name = "omap_rtc_scratch",
 687         .word_size = 4,
 688         .stride = 4,
 689         .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG,
 690         .reg_read = omap_rtc_scratch_read,
 691         .reg_write = omap_rtc_scratch_write,
 692 };
 693
 694 static int omap_rtc_probe(struct platform_device *pdev)
 695 {
 696         struct omap_rtc *rtc;
 697         struct resource *res;
 698         u8 reg, mask, new_ctrl;
 699         const struct platform_device_id *id_entry;
 700         const struct of_device_id *of_id;
 701         int ret;
 702
 703         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 704         if (!rtc)
 705                 return -ENOMEM;
 706
 707         of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
 708         if (of_id) {
 709                 rtc->type = of_id->data;
 710                 rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
 711                         of_device_is_system_power_controller(pdev->dev.of_node);
 712         } else {
 713                 id_entry = platform_get_device_id(pdev);
 714                 rtc->type = (void *)id_entry->driver_data;
 715         }
 716
 717         rtc->irq_timer = platform_get_irq(pdev, 0);
 718         if (rtc->irq_timer <= 0)
 719                 return -ENOENT;
 720
 721         rtc->irq_alarm = platform_get_irq(pdev, 1);
 722         if (rtc->irq_alarm <= 0)
 723                 return -ENOENT;
 724
 725         rtc->clk = devm_clk_get(&pdev->dev, "ext-clk");
 726         if (!IS_ERR(rtc->clk))
 727                 rtc->has_ext_clk = true;
 728         else
 729                 rtc->clk = devm_clk_get(&pdev->dev, "int-clk");
 730
 731         if (!IS_ERR(rtc->clk))
 732                 clk_prepare_enable(rtc->clk);
 733
 734         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 735         rtc->base = devm_ioremap_resource(&pdev->dev, res);
 736         if (IS_ERR(rtc->base)) {
 737                 clk_disable_unprepare(rtc->clk);
 738                 return PTR_ERR(rtc->base);
 739         }
 740
 741         platform_set_drvdata(pdev, rtc);
 742
 743         /* Enable the clock/module so that we can access the registers */
 744         pm_runtime_enable(&pdev->dev);
 745         pm_runtime_get_sync(&pdev->dev);
 746
 747         rtc->type->unlock(rtc);
 748
 749         /*
 750          * disable interrupts
 751          *
 752          * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
 753          */
 754         rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 755
 756         /* enable RTC functional clock */
 757         if (rtc->type->has_32kclk_en) {
 758                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 759                 rtc_writel(rtc, OMAP_RTC_OSC_REG,
 760                                 reg | OMAP_RTC_OSC_32KCLK_EN);
 761         }
 762
 763         /* clear old status */
 764         reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
 765
 766         mask = OMAP_RTC_STATUS_ALARM;
 767
 768         if (rtc->type->has_pmic_mode)
 769                 mask |= OMAP_RTC_STATUS_ALARM2;
 770
 771         if (rtc->type->has_power_up_reset) {
 772                 mask |= OMAP_RTC_STATUS_POWER_UP;
 773                 if (reg & OMAP_RTC_STATUS_POWER_UP)
 774                         dev_info(&pdev->dev, "RTC power up reset detected\n");
 775         }
 776
 777         if (reg & mask)
 778                 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
 779
 780         /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
 781         reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
 782         if (reg & OMAP_RTC_CTRL_STOP)
 783                 dev_info(&pdev->dev, "already running\n");
 784
 785         /* force to 24 hour mode */
 786         new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
 787         new_ctrl |= OMAP_RTC_CTRL_STOP;
 788
 789         /*
 790          * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
 791          *
 792          *  - Device wake-up capability setting should come through chip
 793          *    init logic. OMAP1 boards should initialize the "wakeup capable"
 794          *    flag in the platform device if the board is wired right for
 795          *    being woken up by RTC alarm. For OMAP-L138, this capability
 796          *    is built into the SoC by the "Deep Sleep" capability.
 797          *
 798          *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
 799          *    rather than nPWRON_RESET, should forcibly enable split
 800          *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
 801          *    is write-only, and always reads as zero...)
 802          */
 803
 804         if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
 805                 dev_info(&pdev->dev, "split power mode\n");
 806
 807         if (reg != new_ctrl)
 808                 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
 809
 810         /*
 811          * If we have the external clock then switch to it so we can keep
 812          * ticking across suspend.
 813          */
 814         if (rtc->has_ext_clk) {
 815                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 816                 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
 817                 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
 818                 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg);
 819         }
 820
 821         rtc->type->lock(rtc);
 822
 823         device_init_wakeup(&pdev->dev, true);
 824
 825         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
 826         if (IS_ERR(rtc->rtc)) {
 827                 ret = PTR_ERR(rtc->rtc);
 828                 goto err;
 829         }
 830
 831         rtc->rtc->ops = &omap_rtc_ops;
 832         rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
 833         rtc->rtc->range_max = RTC_TIMESTAMP_END_2099;
 834         omap_rtc_nvmem_config.priv = rtc;
 835
 836         /* handle periodic and alarm irqs */
 837         ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
 838                         dev_name(&rtc->rtc->dev), rtc);
 839         if (ret)
 840                 goto err;
 841
 842         if (rtc->irq_timer != rtc->irq_alarm) {
 843                 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
 844                                 dev_name(&rtc->rtc->dev), rtc);
 845                 if (ret)
 846                         goto err;
 847         }
 848
 849         /* Support ext_wakeup pinconf */
 850         rtc_pinctrl_desc.name = dev_name(&pdev->dev);
 851
 852         rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc);
 853         if (IS_ERR(rtc->pctldev)) {
 854                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 855                 ret = PTR_ERR(rtc->pctldev);
 856                 goto err;
 857         }
 858
 859         ret = rtc_register_device(rtc->rtc);
 860         if (ret)
 861                 goto err_deregister_pinctrl;
 862
 863         rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config);
 864
 865         if (rtc->is_pmic_controller) {
 866                 if (!pm_power_off) {
 867                         omap_rtc_power_off_rtc = rtc;
 868                         pm_power_off = omap_rtc_power_off;
 869                 }
 870         }
 871
 872         return 0;
 873
 874 err_deregister_pinctrl:
 875         pinctrl_unregister(rtc->pctldev);
 876 err:
 877         clk_disable_unprepare(rtc->clk);
 878         device_init_wakeup(&pdev->dev, false);
 879         rtc->type->lock(rtc);
 880         pm_runtime_put_sync(&pdev->dev);
 881         pm_runtime_disable(&pdev->dev);
 882
 883         return ret;
 884 }
 885
 886 static int omap_rtc_remove(struct platform_device *pdev)
 887 {
 888         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 889         u8 reg;
 890
 891         if (pm_power_off == omap_rtc_power_off &&
 892                         omap_rtc_power_off_rtc == rtc) {
 893                 pm_power_off = NULL;
 894                 omap_rtc_power_off_rtc = NULL;
 895         }
 896
 897         device_init_wakeup(&pdev->dev, 0);
 898
 899         if (!IS_ERR(rtc->clk))
 900                 clk_disable_unprepare(rtc->clk);
 901
 902         rtc->type->unlock(rtc);
 903         /* leave rtc running, but disable irqs */
 904         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 905
 906         if (rtc->has_ext_clk) {
 907                 reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
 908                 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
 909                 rtc_write(rtc, OMAP_RTC_OSC_REG, reg);
 910         }
 911
 912         rtc->type->lock(rtc);
 913
 914         /* Disable the clock/module */
 915         pm_runtime_put_sync(&pdev->dev);
 916         pm_runtime_disable(&pdev->dev);
 917
 918         /* Remove ext_wakeup pinconf */
 919         pinctrl_unregister(rtc->pctldev);
 920
 921         return 0;
 922 }
 923
 924 static int __maybe_unused omap_rtc_suspend(struct device *dev)
 925 {
 926         struct omap_rtc *rtc = dev_get_drvdata(dev);
 927
 928         rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 929
 930         rtc->type->unlock(rtc);
 931         /*
 932          * FIXME: the RTC alarm is not currently acting as a wakeup event
 933          * source on some platforms, and in fact this enable() call is just
 934          * saving a flag that's never used...
 935          */
 936         if (device_may_wakeup(dev))
 937                 enable_irq_wake(rtc->irq_alarm);
 938         else
 939                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
 940         rtc->type->lock(rtc);
 941
 942         rtc->is_suspending = true;
 943
 944         return 0;
 945 }
 946
 947 static int __maybe_unused omap_rtc_resume(struct device *dev)
 948 {
 949         struct omap_rtc *rtc = dev_get_drvdata(dev);
 950
 951         rtc->type->unlock(rtc);
 952         if (device_may_wakeup(dev))
 953                 disable_irq_wake(rtc->irq_alarm);
 954         else
 955                 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
 956         rtc->type->lock(rtc);
 957
 958         rtc->is_suspending = false;
 959
 960         return 0;
 961 }
 962
 963 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev)
 964 {
 965         struct omap_rtc *rtc = dev_get_drvdata(dev);
 966
 967         if (rtc->is_suspending && !rtc->has_ext_clk)
 968                 return -EBUSY;
 969
 970         return 0;
 971 }
 972
 973 static const struct dev_pm_ops omap_rtc_pm_ops = {
 974         SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume)
 975         SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL)
 976 };
 977
 978 static void omap_rtc_shutdown(struct platform_device *pdev)
 979 {
 980         struct omap_rtc *rtc = platform_get_drvdata(pdev);
 981         u8 mask;
 982
 983         /*
 984          * Keep the ALARM interrupt enabled to allow the system to power up on
 985          * alarm events.
 986          */
 987         rtc->type->unlock(rtc);
 988         mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
 989         mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
 990         rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
 991         rtc->type->lock(rtc);
 992 }
 993
 994 static struct platform_driver omap_rtc_driver = {
 995         .probe          = omap_rtc_probe,
 996         .remove         = omap_rtc_remove,
 997         .shutdown       = omap_rtc_shutdown,
 998         .driver         = {
 999                 .name   = "omap_rtc",
1000                 .pm     = &omap_rtc_pm_ops,
1001                 .of_match_table = omap_rtc_of_match,
1002         },
1003         .id_table       = omap_rtc_id_table,
1004 };
1005
1006 module_platform_driver(omap_rtc_driver);
1007
1008 MODULE_ALIAS("platform:omap_rtc");
1009 MODULE_AUTHOR("George G. Davis (and others)");
1010 MODULE_LICENSE("GPL");