drivers/pwm/pwm-mtk-disp.c

   1 /*
   2  * MediaTek display pulse-width-modulation controller driver.
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: YH Huang <yh.huang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pwm.h>
  24 #include <linux/slab.h>
  25
  26 #define DISP_PWM_EN             0x00
  27
  28 #define PWM_CLKDIV_SHIFT        16
  29 #define PWM_CLKDIV_MAX          0x3ff
  30 #define PWM_CLKDIV_MASK         (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
  31
  32 #define PWM_PERIOD_BIT_WIDTH    12
  33 #define PWM_PERIOD_MASK         ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
  34
  35 #define PWM_HIGH_WIDTH_SHIFT    16
  36 #define PWM_HIGH_WIDTH_MASK     (0x1fff << PWM_HIGH_WIDTH_SHIFT)
  37
  38 struct mtk_pwm_data {
  39         u32 enable_mask;
  40         unsigned int con0;
  41         u32 con0_sel;
  42         unsigned int con1;
  43
  44         bool has_commit;
  45         unsigned int commit;
  46         unsigned int commit_mask;
  47
  48         unsigned int bls_debug;
  49         u32 bls_debug_mask;
  50 };
  51
  52 struct mtk_disp_pwm {
  53         struct pwm_chip chip;
  54         const struct mtk_pwm_data *data;
  55         struct clk *clk_main;
  56         struct clk *clk_mm;
  57         void __iomem *base;
  58 };
  59
  60 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
  61 {
  62         return container_of(chip, struct mtk_disp_pwm, chip);
  63 }
  64
  65 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
  66                                      u32 mask, u32 data)
  67 {
  68         void __iomem *address = mdp->base + offset;
  69         u32 value;
  70
  71         value = readl(address);
  72         value &= ~mask;
  73         value |= data;
  74         writel(value, address);
  75 }
  76
  77 static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  78                                int duty_ns, int period_ns)
  79 {
  80         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  81         u32 clk_div, period, high_width, value;
  82         u64 div, rate;
  83         int err;
  84
  85         /*
  86          * Find period, high_width and clk_div to suit duty_ns and period_ns.
  87          * Calculate proper div value to keep period value in the bound.
  88          *
  89          * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
  90          * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
  91          *
  92          * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
  93          * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
  94          */
  95         rate = clk_get_rate(mdp->clk_main);
  96         clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
  97                           PWM_PERIOD_BIT_WIDTH;
  98         if (clk_div > PWM_CLKDIV_MAX)
  99                 return -EINVAL;
 100
 101         div = NSEC_PER_SEC * (clk_div + 1);
 102         period = div64_u64(rate * period_ns, div);
 103         if (period > 0)
 104                 period--;
 105
 106         high_width = div64_u64(rate * duty_ns, div);
 107         value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
 108
 109         err = clk_enable(mdp->clk_main);
 110         if (err < 0)
 111                 return err;
 112
 113         err = clk_enable(mdp->clk_mm);
 114         if (err < 0) {
 115                 clk_disable(mdp->clk_main);
 116                 return err;
 117         }
 118
 119         mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 120                                  PWM_CLKDIV_MASK,
 121                                  clk_div << PWM_CLKDIV_SHIFT);
 122         mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
 123                                  PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
 124                                  value);
 125
 126         if (mdp->data->has_commit) {
 127                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 128                                          mdp->data->commit_mask,
 129                                          mdp->data->commit_mask);
 130                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 131                                          mdp->data->commit_mask,
 132                                          0x0);
 133         }
 134
 135         clk_disable(mdp->clk_mm);
 136         clk_disable(mdp->clk_main);
 137
 138         return 0;
 139 }
 140
 141 static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 142 {
 143         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
 144         int err;
 145
 146         err = clk_enable(mdp->clk_main);
 147         if (err < 0)
 148                 return err;
 149
 150         err = clk_enable(mdp->clk_mm);
 151         if (err < 0) {
 152                 clk_disable(mdp->clk_main);
 153                 return err;
 154         }
 155
 156         mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
 157                                  mdp->data->enable_mask);
 158
 159         return 0;
 160 }
 161
 162 static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 163 {
 164         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
 165
 166         mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
 167                                  0x0);
 168
 169         clk_disable(mdp->clk_mm);
 170         clk_disable(mdp->clk_main);
 171 }
 172
 173 static const struct pwm_ops mtk_disp_pwm_ops = {
 174         .config = mtk_disp_pwm_config,
 175         .enable = mtk_disp_pwm_enable,
 176         .disable = mtk_disp_pwm_disable,
 177         .owner = THIS_MODULE,
 178 };
 179
 180 static int mtk_disp_pwm_probe(struct platform_device *pdev)
 181 {
 182         struct mtk_disp_pwm *mdp;
 183         struct resource *r;
 184         int ret;
 185
 186         mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
 187         if (!mdp)
 188                 return -ENOMEM;
 189
 190         mdp->data = of_device_get_match_data(&pdev->dev);
 191
 192         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 193         mdp->base = devm_ioremap_resource(&pdev->dev, r);
 194         if (IS_ERR(mdp->base))
 195                 return PTR_ERR(mdp->base);
 196
 197         mdp->clk_main = devm_clk_get(&pdev->dev, "main");
 198         if (IS_ERR(mdp->clk_main))
 199                 return PTR_ERR(mdp->clk_main);
 200
 201         mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
 202         if (IS_ERR(mdp->clk_mm))
 203                 return PTR_ERR(mdp->clk_mm);
 204
 205         ret = clk_prepare(mdp->clk_main);
 206         if (ret < 0)
 207                 return ret;
 208
 209         ret = clk_prepare(mdp->clk_mm);
 210         if (ret < 0)
 211                 goto disable_clk_main;
 212
 213         mdp->chip.dev = &pdev->dev;
 214         mdp->chip.ops = &mtk_disp_pwm_ops;
 215         mdp->chip.base = -1;
 216         mdp->chip.npwm = 1;
 217
 218         ret = pwmchip_add(&mdp->chip);
 219         if (ret < 0) {
 220                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 221                 goto disable_clk_mm;
 222         }
 223
 224         platform_set_drvdata(pdev, mdp);
 225
 226         /*
 227          * For MT2701, disable double buffer before writing register
 228          * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
 229          */
 230         if (!mdp->data->has_commit) {
 231                 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
 232                                          mdp->data->bls_debug_mask,
 233                                          mdp->data->bls_debug_mask);
 234                 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 235                                          mdp->data->con0_sel,
 236                                          mdp->data->con0_sel);
 237         }
 238
 239         return 0;
 240
 241 disable_clk_mm:
 242         clk_unprepare(mdp->clk_mm);
 243 disable_clk_main:
 244         clk_unprepare(mdp->clk_main);
 245         return ret;
 246 }
 247
 248 static int mtk_disp_pwm_remove(struct platform_device *pdev)
 249 {
 250         struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
 251         int ret;
 252
 253         ret = pwmchip_remove(&mdp->chip);
 254         clk_unprepare(mdp->clk_mm);
 255         clk_unprepare(mdp->clk_main);
 256
 257         return ret;
 258 }
 259
 260 static const struct mtk_pwm_data mt2701_pwm_data = {
 261         .enable_mask = BIT(16),
 262         .con0 = 0xa8,
 263         .con0_sel = 0x2,
 264         .con1 = 0xac,
 265         .has_commit = false,
 266         .bls_debug = 0xb0,
 267         .bls_debug_mask = 0x3,
 268 };
 269
 270 static const struct mtk_pwm_data mt8173_pwm_data = {
 271         .enable_mask = BIT(0),
 272         .con0 = 0x10,
 273         .con0_sel = 0x0,
 274         .con1 = 0x14,
 275         .has_commit = true,
 276         .commit = 0x8,
 277         .commit_mask = 0x1,
 278 };
 279
 280 static const struct mtk_pwm_data mt8183_pwm_data = {
 281         .enable_mask = BIT(0),
 282         .con0 = 0x18,
 283         .con0_sel = 0x0,
 284         .con1 = 0x1c,
 285         .has_commit = false,
 286         .bls_debug = 0x80,
 287         .bls_debug_mask = 0x3,
 288 };
 289
 290 static const struct of_device_id mtk_disp_pwm_of_match[] = {
 291         { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
 292         { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
 293         { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
 294         { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
 295         { }
 296 };
 297 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
 298
 299 static struct platform_driver mtk_disp_pwm_driver = {
 300         .driver = {
 301                 .name = "mediatek-disp-pwm",
 302                 .of_match_table = mtk_disp_pwm_of_match,
 303         },
 304         .probe = mtk_disp_pwm_probe,
 305         .remove = mtk_disp_pwm_remove,
 306 };
 307 module_platform_driver(mtk_disp_pwm_driver);
 308
 309 MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
 310 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
 311 MODULE_LICENSE("GPL v2");