drivers/pwm/pwm-atmel.c

   1 /*
   2  * Driver for Atmel Pulse Width Modulation Controller
   3  *
   4  * Copyright (C) 2013 Atmel Corporation
   5  *               Bo Shen <voice.shen@atmel.com>
   6  *
   7  * Licensed under GPLv2.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pwm.h>
  20 #include <linux/slab.h>
  21
  22 /* The following is global registers for PWM controller */
  23 #define PWM_ENA                 0x04
  24 #define PWM_DIS                 0x08
  25 #define PWM_SR                  0x0C
  26 #define PWM_ISR                 0x1C
  27 /* Bit field in SR */
  28 #define PWM_SR_ALL_CH_ON        0x0F
  29
  30 /* The following register is PWM channel related registers */
  31 #define PWM_CH_REG_OFFSET       0x200
  32 #define PWM_CH_REG_SIZE         0x20
  33
  34 #define PWM_CMR                 0x0
  35 /* Bit field in CMR */
  36 #define PWM_CMR_CPOL            (1 << 9)
  37 #define PWM_CMR_UPD_CDTY        (1 << 10)
  38 #define PWM_CMR_CPRE_MSK        0xF
  39
  40 /* The following registers for PWM v1 */
  41 #define PWMV1_CDTY              0x04
  42 #define PWMV1_CPRD              0x08
  43 #define PWMV1_CUPD              0x10
  44
  45 /* The following registers for PWM v2 */
  46 #define PWMV2_CDTY              0x04
  47 #define PWMV2_CDTYUPD           0x08
  48 #define PWMV2_CPRD              0x0C
  49 #define PWMV2_CPRDUPD           0x10
  50
  51 /*
  52  * Max value for duty and period
  53  *
  54  * Although the duty and period register is 32 bit,
  55  * however only the LSB 16 bits are significant.
  56  */
  57 #define PWM_MAX_DTY             0xFFFF
  58 #define PWM_MAX_PRD             0xFFFF
  59 #define PRD_MAX_PRES            10
  60
  61 struct atmel_pwm_registers {
  62         u8 period;
  63         u8 period_upd;
  64         u8 duty;
  65         u8 duty_upd;
  66 };
  67
  68 struct atmel_pwm_chip {
  69         struct pwm_chip chip;
  70         struct clk *clk;
  71         void __iomem *base;
  72         const struct atmel_pwm_registers *regs;
  73
  74         unsigned int updated_pwms;
  75         /* ISR is cleared when read, ensure only one thread does that */
  76         struct mutex isr_lock;
  77 };
  78
  79 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
  80 {
  81         return container_of(chip, struct atmel_pwm_chip, chip);
  82 }
  83
  84 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
  85                                   unsigned long offset)
  86 {
  87         return readl_relaxed(chip->base + offset);
  88 }
  89
  90 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
  91                                     unsigned long offset, unsigned long val)
  92 {
  93         writel_relaxed(val, chip->base + offset);
  94 }
  95
  96 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
  97                                      unsigned int ch, unsigned long offset)
  98 {
  99         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 100
 101         return readl_relaxed(chip->base + base + offset);
 102 }
 103
 104 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
 105                                        unsigned int ch, unsigned long offset,
 106                                        unsigned long val)
 107 {
 108         unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
 109
 110         writel_relaxed(val, chip->base + base + offset);
 111 }
 112
 113 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
 114                                              const struct pwm_state *state,
 115                                              unsigned long *cprd, u32 *pres)
 116 {
 117         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 118         unsigned long long cycles = state->period;
 119
 120         /* Calculate the period cycles and prescale value */
 121         cycles *= clk_get_rate(atmel_pwm->clk);
 122         do_div(cycles, NSEC_PER_SEC);
 123
 124         for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
 125                 (*pres)++;
 126
 127         if (*pres > PRD_MAX_PRES) {
 128                 dev_err(chip->dev, "pres exceeds the maximum value\n");
 129                 return -EINVAL;
 130         }
 131
 132         *cprd = cycles;
 133
 134         return 0;
 135 }
 136
 137 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
 138                                      unsigned long cprd, unsigned long *cdty)
 139 {
 140         unsigned long long cycles = state->duty_cycle;
 141
 142         cycles *= cprd;
 143         do_div(cycles, state->period);
 144         *cdty = cprd - cycles;
 145 }
 146
 147 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
 148                                   unsigned long cdty)
 149 {
 150         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 151         u32 val;
 152
 153         if (atmel_pwm->regs->duty_upd ==
 154             atmel_pwm->regs->period_upd) {
 155                 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 156                 val &= ~PWM_CMR_UPD_CDTY;
 157                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 158         }
 159
 160         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 161                             atmel_pwm->regs->duty_upd, cdty);
 162 }
 163
 164 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
 165                                     struct pwm_device *pwm,
 166                                     unsigned long cprd, unsigned long cdty)
 167 {
 168         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 169
 170         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 171                             atmel_pwm->regs->duty, cdty);
 172         atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
 173                             atmel_pwm->regs->period, cprd);
 174 }
 175
 176 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
 177                               bool disable_clk)
 178 {
 179         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 180         unsigned long timeout = jiffies + 2 * HZ;
 181
 182         /*
 183          * Wait for at least a complete period to have passed before disabling a
 184          * channel to be sure that CDTY has been updated
 185          */
 186         mutex_lock(&atmel_pwm->isr_lock);
 187         atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 188
 189         while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
 190                time_before(jiffies, timeout)) {
 191                 usleep_range(10, 100);
 192                 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 193         }
 194
 195         mutex_unlock(&atmel_pwm->isr_lock);
 196         atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
 197
 198         /*
 199          * Wait for the PWM channel disable operation to be effective before
 200          * stopping the clock.
 201          */
 202         timeout = jiffies + 2 * HZ;
 203
 204         while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
 205                time_before(jiffies, timeout))
 206                 usleep_range(10, 100);
 207
 208         if (disable_clk)
 209                 clk_disable(atmel_pwm->clk);
 210 }
 211
 212 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 213                            struct pwm_state *state)
 214 {
 215         struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
 216         struct pwm_state cstate;
 217         unsigned long cprd, cdty;
 218         u32 pres, val;
 219         int ret;
 220
 221         pwm_get_state(pwm, &cstate);
 222
 223         if (state->enabled) {
 224                 if (cstate.enabled &&
 225                     cstate.polarity == state->polarity &&
 226                     cstate.period == state->period) {
 227                         cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
 228                                                   atmel_pwm->regs->period);
 229                         atmel_pwm_calculate_cdty(state, cprd, &cdty);
 230                         atmel_pwm_update_cdty(chip, pwm, cdty);
 231                         return 0;
 232                 }
 233
 234                 ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
 235                                                         &pres);
 236                 if (ret) {
 237                         dev_err(chip->dev,
 238                                 "failed to calculate cprd and prescaler\n");
 239                         return ret;
 240                 }
 241
 242                 atmel_pwm_calculate_cdty(state, cprd, &cdty);
 243
 244                 if (cstate.enabled) {
 245                         atmel_pwm_disable(chip, pwm, false);
 246                 } else {
 247                         ret = clk_enable(atmel_pwm->clk);
 248                         if (ret) {
 249                                 dev_err(chip->dev, "failed to enable clock\n");
 250                                 return ret;
 251                         }
 252                 }
 253
 254                 /* It is necessary to preserve CPOL, inside CMR */
 255                 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
 256                 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
 257                 if (state->polarity == PWM_POLARITY_NORMAL)
 258                         val &= ~PWM_CMR_CPOL;
 259                 else
 260                         val |= PWM_CMR_CPOL;
 261                 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
 262                 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
 263                 mutex_lock(&atmel_pwm->isr_lock);
 264                 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
 265                 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
 266                 mutex_unlock(&atmel_pwm->isr_lock);
 267                 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
 268         } else if (cstate.enabled) {
 269                 atmel_pwm_disable(chip, pwm, true);
 270         }
 271
 272         return 0;
 273 }
 274
 275 static const struct pwm_ops atmel_pwm_ops = {
 276         .apply = atmel_pwm_apply,
 277         .owner = THIS_MODULE,
 278 };
 279
 280 static const struct atmel_pwm_registers atmel_pwm_regs_v1 = {
 281         .period         = PWMV1_CPRD,
 282         .period_upd     = PWMV1_CUPD,
 283         .duty           = PWMV1_CDTY,
 284         .duty_upd       = PWMV1_CUPD,
 285 };
 286
 287 static const struct atmel_pwm_registers atmel_pwm_regs_v2 = {
 288         .period         = PWMV2_CPRD,
 289         .period_upd     = PWMV2_CPRDUPD,
 290         .duty           = PWMV2_CDTY,
 291         .duty_upd       = PWMV2_CDTYUPD,
 292 };
 293
 294 static const struct platform_device_id atmel_pwm_devtypes[] = {
 295         {
 296                 .name = "at91sam9rl-pwm",
 297                 .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v1,
 298         }, {
 299                 .name = "sama5d3-pwm",
 300                 .driver_data = (kernel_ulong_t)&atmel_pwm_regs_v2,
 301         }, {
 302                 /* sentinel */
 303         },
 304 };
 305 MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
 306
 307 static const struct of_device_id atmel_pwm_dt_ids[] = {
 308         {
 309                 .compatible = "atmel,at91sam9rl-pwm",
 310                 .data = &atmel_pwm_regs_v1,
 311         }, {
 312                 .compatible = "atmel,sama5d3-pwm",
 313                 .data = &atmel_pwm_regs_v2,
 314         }, {
 315                 .compatible = "atmel,sama5d2-pwm",
 316                 .data = &atmel_pwm_regs_v2,
 317         }, {
 318                 /* sentinel */
 319         },
 320 };
 321 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
 322
 323 static inline const struct atmel_pwm_registers *
 324 atmel_pwm_get_driver_data(struct platform_device *pdev)
 325 {
 326         const struct platform_device_id *id;
 327
 328         if (pdev->dev.of_node)
 329                 return of_device_get_match_data(&pdev->dev);
 330
 331         id = platform_get_device_id(pdev);
 332
 333         return (struct atmel_pwm_registers *)id->driver_data;
 334 }
 335
 336 static int atmel_pwm_probe(struct platform_device *pdev)
 337 {
 338         const struct atmel_pwm_registers *regs;
 339         struct atmel_pwm_chip *atmel_pwm;
 340         struct resource *res;
 341         int ret;
 342
 343         regs = atmel_pwm_get_driver_data(pdev);
 344         if (!regs)
 345                 return -ENODEV;
 346
 347         atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
 348         if (!atmel_pwm)
 349                 return -ENOMEM;
 350
 351         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 352         atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
 353         if (IS_ERR(atmel_pwm->base))
 354                 return PTR_ERR(atmel_pwm->base);
 355
 356         atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
 357         if (IS_ERR(atmel_pwm->clk))
 358                 return PTR_ERR(atmel_pwm->clk);
 359
 360         ret = clk_prepare(atmel_pwm->clk);
 361         if (ret) {
 362                 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
 363                 return ret;
 364         }
 365
 366         atmel_pwm->chip.dev = &pdev->dev;
 367         atmel_pwm->chip.ops = &atmel_pwm_ops;
 368
 369         if (pdev->dev.of_node) {
 370                 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
 371                 atmel_pwm->chip.of_pwm_n_cells = 3;
 372         }
 373
 374         atmel_pwm->chip.base = -1;
 375         atmel_pwm->chip.npwm = 4;
 376         atmel_pwm->regs = regs;
 377         atmel_pwm->updated_pwms = 0;
 378         mutex_init(&atmel_pwm->isr_lock);
 379
 380         ret = pwmchip_add(&atmel_pwm->chip);
 381         if (ret < 0) {
 382                 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
 383                 goto unprepare_clk;
 384         }
 385
 386         platform_set_drvdata(pdev, atmel_pwm);
 387
 388         return ret;
 389
 390 unprepare_clk:
 391         clk_unprepare(atmel_pwm->clk);
 392         return ret;
 393 }
 394
 395 static int atmel_pwm_remove(struct platform_device *pdev)
 396 {
 397         struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
 398
 399         clk_unprepare(atmel_pwm->clk);
 400         mutex_destroy(&atmel_pwm->isr_lock);
 401
 402         return pwmchip_remove(&atmel_pwm->chip);
 403 }
 404
 405 static struct platform_driver atmel_pwm_driver = {
 406         .driver = {
 407                 .name = "atmel-pwm",
 408                 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
 409         },
 410         .id_table = atmel_pwm_devtypes,
 411         .probe = atmel_pwm_probe,
 412         .remove = atmel_pwm_remove,
 413 };
 414 module_platform_driver(atmel_pwm_driver);
 415
 416 MODULE_ALIAS("platform:atmel-pwm");
 417 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
 418 MODULE_DESCRIPTION("Atmel PWM driver");
 419 MODULE_LICENSE("GPL v2");