drivers/ptp/ptp_pch.c

   1 /*
   2  * PTP 1588 clock using the EG20T PCH
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
   6  *
   7  * This code was derived from the IXP46X driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  21  */
  22
  23 #include <linux/device.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/pci.h>
  32 #include <linux/ptp_clock_kernel.h>
  33 #include <linux/slab.h>
  34
  35 #define STATION_ADDR_LEN        20
  36 #define PCI_DEVICE_ID_PCH_1588  0x8819
  37 #define IO_MEM_BAR 1
  38
  39 #define DEFAULT_ADDEND 0xA0000000
  40 #define TICKS_NS_SHIFT  5
  41 #define N_EXT_TS        2
  42
  43 enum pch_status {
  44         PCH_SUCCESS,
  45         PCH_INVALIDPARAM,
  46         PCH_NOTIMESTAMP,
  47         PCH_INTERRUPTMODEINUSE,
  48         PCH_FAILED,
  49         PCH_UNSUPPORTED,
  50 };
  51 /**
  52  * struct pch_ts_regs - IEEE 1588 registers
  53  */
  54 struct pch_ts_regs {
  55         u32 control;
  56         u32 event;
  57         u32 addend;
  58         u32 accum;
  59         u32 test;
  60         u32 ts_compare;
  61         u32 rsystime_lo;
  62         u32 rsystime_hi;
  63         u32 systime_lo;
  64         u32 systime_hi;
  65         u32 trgt_lo;
  66         u32 trgt_hi;
  67         u32 asms_lo;
  68         u32 asms_hi;
  69         u32 amms_lo;
  70         u32 amms_hi;
  71         u32 ch_control;
  72         u32 ch_event;
  73         u32 tx_snap_lo;
  74         u32 tx_snap_hi;
  75         u32 rx_snap_lo;
  76         u32 rx_snap_hi;
  77         u32 src_uuid_lo;
  78         u32 src_uuid_hi;
  79         u32 can_status;
  80         u32 can_snap_lo;
  81         u32 can_snap_hi;
  82         u32 ts_sel;
  83         u32 ts_st[6];
  84         u32 reserve1[14];
  85         u32 stl_max_set_en;
  86         u32 stl_max_set;
  87         u32 reserve2[13];
  88         u32 srst;
  89 };
  90
  91 #define PCH_TSC_RESET           (1 << 0)
  92 #define PCH_TSC_TTM_MASK        (1 << 1)
  93 #define PCH_TSC_ASMS_MASK       (1 << 2)
  94 #define PCH_TSC_AMMS_MASK       (1 << 3)
  95 #define PCH_TSC_PPSM_MASK       (1 << 4)
  96 #define PCH_TSE_TTIPEND         (1 << 1)
  97 #define PCH_TSE_SNS             (1 << 2)
  98 #define PCH_TSE_SNM             (1 << 3)
  99 #define PCH_TSE_PPS             (1 << 4)
 100 #define PCH_CC_MM               (1 << 0)
 101 #define PCH_CC_TA               (1 << 1)
 102
 103 #define PCH_CC_MODE_SHIFT       16
 104 #define PCH_CC_MODE_MASK        0x001F0000
 105 #define PCH_CC_VERSION          (1 << 31)
 106 #define PCH_CE_TXS              (1 << 0)
 107 #define PCH_CE_RXS              (1 << 1)
 108 #define PCH_CE_OVR              (1 << 0)
 109 #define PCH_CE_VAL              (1 << 1)
 110 #define PCH_ECS_ETH             (1 << 0)
 111
 112 #define PCH_ECS_CAN             (1 << 1)
 113 #define PCH_STATION_BYTES       6
 114
 115 #define PCH_IEEE1588_ETH        (1 << 0)
 116 #define PCH_IEEE1588_CAN        (1 << 1)
 117 /**
 118  * struct pch_dev - Driver private data
 119  */
 120 struct pch_dev {
 121         struct pch_ts_regs __iomem *regs;
 122         struct ptp_clock *ptp_clock;
 123         struct ptp_clock_info caps;
 124         int exts0_enabled;
 125         int exts1_enabled;
 126
 127         u32 mem_base;
 128         u32 mem_size;
 129         u32 irq;
 130         struct pci_dev *pdev;
 131         spinlock_t register_lock;
 132 };
 133
 134 /**
 135  * struct pch_params - 1588 module parameter
 136  */
 137 struct pch_params {
 138         u8 station[STATION_ADDR_LEN];
 139 };
 140
 141 /* structure to hold the module parameters */
 142 static struct pch_params pch_param = {
 143         "00:00:00:00:00:00"
 144 };
 145
 146 /*
 147  * Register access functions
 148  */
 149 static inline void pch_eth_enable_set(struct pch_dev *chip)
 150 {
 151         u32 val;
 152         /* SET the eth_enable bit */
 153         val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
 154         iowrite32(val, (&chip->regs->ts_sel));
 155 }
 156
 157 static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
 158 {
 159         u64 ns;
 160         u32 lo, hi;
 161
 162         lo = ioread32(&regs->systime_lo);
 163         hi = ioread32(&regs->systime_hi);
 164
 165         ns = ((u64) hi) << 32;
 166         ns |= lo;
 167         ns <<= TICKS_NS_SHIFT;
 168
 169         return ns;
 170 }
 171
 172 static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
 173 {
 174         u32 hi, lo;
 175
 176         ns >>= TICKS_NS_SHIFT;
 177         hi = ns >> 32;
 178         lo = ns & 0xffffffff;
 179
 180         iowrite32(lo, &regs->systime_lo);
 181         iowrite32(hi, &regs->systime_hi);
 182 }
 183
 184 static inline void pch_block_reset(struct pch_dev *chip)
 185 {
 186         u32 val;
 187         /* Reset Hardware Assist block */
 188         val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
 189         iowrite32(val, (&chip->regs->control));
 190         val = val & ~PCH_TSC_RESET;
 191         iowrite32(val, (&chip->regs->control));
 192 }
 193
 194 u32 pch_ch_control_read(struct pci_dev *pdev)
 195 {
 196         struct pch_dev *chip = pci_get_drvdata(pdev);
 197         u32 val;
 198
 199         val = ioread32(&chip->regs->ch_control);
 200
 201         return val;
 202 }
 203 EXPORT_SYMBOL(pch_ch_control_read);
 204
 205 void pch_ch_control_write(struct pci_dev *pdev, u32 val)
 206 {
 207         struct pch_dev *chip = pci_get_drvdata(pdev);
 208
 209         iowrite32(val, (&chip->regs->ch_control));
 210 }
 211 EXPORT_SYMBOL(pch_ch_control_write);
 212
 213 u32 pch_ch_event_read(struct pci_dev *pdev)
 214 {
 215         struct pch_dev *chip = pci_get_drvdata(pdev);
 216         u32 val;
 217
 218         val = ioread32(&chip->regs->ch_event);
 219
 220         return val;
 221 }
 222 EXPORT_SYMBOL(pch_ch_event_read);
 223
 224 void pch_ch_event_write(struct pci_dev *pdev, u32 val)
 225 {
 226         struct pch_dev *chip = pci_get_drvdata(pdev);
 227
 228         iowrite32(val, (&chip->regs->ch_event));
 229 }
 230 EXPORT_SYMBOL(pch_ch_event_write);
 231
 232 u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
 233 {
 234         struct pch_dev *chip = pci_get_drvdata(pdev);
 235         u32 val;
 236
 237         val = ioread32(&chip->regs->src_uuid_lo);
 238
 239         return val;
 240 }
 241 EXPORT_SYMBOL(pch_src_uuid_lo_read);
 242
 243 u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
 244 {
 245         struct pch_dev *chip = pci_get_drvdata(pdev);
 246         u32 val;
 247
 248         val = ioread32(&chip->regs->src_uuid_hi);
 249
 250         return val;
 251 }
 252 EXPORT_SYMBOL(pch_src_uuid_hi_read);
 253
 254 u64 pch_rx_snap_read(struct pci_dev *pdev)
 255 {
 256         struct pch_dev *chip = pci_get_drvdata(pdev);
 257         u64 ns;
 258         u32 lo, hi;
 259
 260         lo = ioread32(&chip->regs->rx_snap_lo);
 261         hi = ioread32(&chip->regs->rx_snap_hi);
 262
 263         ns = ((u64) hi) << 32;
 264         ns |= lo;
 265         ns <<= TICKS_NS_SHIFT;
 266
 267         return ns;
 268 }
 269 EXPORT_SYMBOL(pch_rx_snap_read);
 270
 271 u64 pch_tx_snap_read(struct pci_dev *pdev)
 272 {
 273         struct pch_dev *chip = pci_get_drvdata(pdev);
 274         u64 ns;
 275         u32 lo, hi;
 276
 277         lo = ioread32(&chip->regs->tx_snap_lo);
 278         hi = ioread32(&chip->regs->tx_snap_hi);
 279
 280         ns = ((u64) hi) << 32;
 281         ns |= lo;
 282         ns <<= TICKS_NS_SHIFT;
 283
 284         return ns;
 285 }
 286 EXPORT_SYMBOL(pch_tx_snap_read);
 287
 288 /* This function enables all 64 bits in system time registers [high & low].
 289 This is a work-around for non continuous value in the SystemTime Register*/
 290 static void pch_set_system_time_count(struct pch_dev *chip)
 291 {
 292         iowrite32(0x01, &chip->regs->stl_max_set_en);
 293         iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
 294         iowrite32(0x00, &chip->regs->stl_max_set_en);
 295 }
 296
 297 static void pch_reset(struct pch_dev *chip)
 298 {
 299         /* Reset Hardware Assist */
 300         pch_block_reset(chip);
 301
 302         /* enable all 32 bits in system time registers */
 303         pch_set_system_time_count(chip);
 304 }
 305
 306 /**
 307  * pch_set_station_address() - This API sets the station address used by
 308  *                                  IEEE 1588 hardware when looking at PTP
 309  *                                  traffic on the  ethernet interface
 310  * @addr:       dress which contain the column separated address to be used.
 311  */
 312 int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
 313 {
 314         s32 i;
 315         struct pch_dev *chip = pci_get_drvdata(pdev);
 316
 317         /* Verify the parameter */
 318         if ((chip->regs == NULL) || addr == (u8 *)NULL) {
 319                 dev_err(&pdev->dev,
 320                         "invalid params returning PCH_INVALIDPARAM\n");
 321                 return PCH_INVALIDPARAM;
 322         }
 323         /* For all station address bytes */
 324         for (i = 0; i < PCH_STATION_BYTES; i++) {
 325                 u32 val;
 326                 s32 tmp;
 327
 328                 tmp = hex_to_bin(addr[i * 3]);
 329                 if (tmp < 0) {
 330                         dev_err(&pdev->dev,
 331                                 "invalid params returning PCH_INVALIDPARAM\n");
 332                         return PCH_INVALIDPARAM;
 333                 }
 334                 val = tmp * 16;
 335                 tmp = hex_to_bin(addr[(i * 3) + 1]);
 336                 if (tmp < 0) {
 337                         dev_err(&pdev->dev,
 338                                 "invalid params returning PCH_INVALIDPARAM\n");
 339                         return PCH_INVALIDPARAM;
 340                 }
 341                 val += tmp;
 342                 /* Expects ':' separated addresses */
 343                 if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
 344                         dev_err(&pdev->dev,
 345                                 "invalid params returning PCH_INVALIDPARAM\n");
 346                         return PCH_INVALIDPARAM;
 347                 }
 348
 349                 /* Ideally we should set the address only after validating
 350                                                          entire string */
 351                 dev_dbg(&pdev->dev, "invoking pch_station_set\n");
 352                 iowrite32(val, &chip->regs->ts_st[i]);
 353         }
 354         return 0;
 355 }
 356 EXPORT_SYMBOL(pch_set_station_address);
 357
 358 /*
 359  * Interrupt service routine
 360  */
 361 static irqreturn_t isr(int irq, void *priv)
 362 {
 363         struct pch_dev *pch_dev = priv;
 364         struct pch_ts_regs __iomem *regs = pch_dev->regs;
 365         struct ptp_clock_event event;
 366         u32 ack = 0, lo, hi, val;
 367
 368         val = ioread32(&regs->event);
 369
 370         if (val & PCH_TSE_SNS) {
 371                 ack |= PCH_TSE_SNS;
 372                 if (pch_dev->exts0_enabled) {
 373                         hi = ioread32(&regs->asms_hi);
 374                         lo = ioread32(&regs->asms_lo);
 375                         event.type = PTP_CLOCK_EXTTS;
 376                         event.index = 0;
 377                         event.timestamp = ((u64) hi) << 32;
 378                         event.timestamp |= lo;
 379                         event.timestamp <<= TICKS_NS_SHIFT;
 380                         ptp_clock_event(pch_dev->ptp_clock, &event);
 381                 }
 382         }
 383
 384         if (val & PCH_TSE_SNM) {
 385                 ack |= PCH_TSE_SNM;
 386                 if (pch_dev->exts1_enabled) {
 387                         hi = ioread32(&regs->amms_hi);
 388                         lo = ioread32(&regs->amms_lo);
 389                         event.type = PTP_CLOCK_EXTTS;
 390                         event.index = 1;
 391                         event.timestamp = ((u64) hi) << 32;
 392                         event.timestamp |= lo;
 393                         event.timestamp <<= TICKS_NS_SHIFT;
 394                         ptp_clock_event(pch_dev->ptp_clock, &event);
 395                 }
 396         }
 397
 398         if (val & PCH_TSE_TTIPEND)
 399                 ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
 400
 401         if (ack) {
 402                 iowrite32(ack, &regs->event);
 403                 return IRQ_HANDLED;
 404         } else
 405                 return IRQ_NONE;
 406 }
 407
 408 /*
 409  * PTP clock operations
 410  */
 411
 412 static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 413 {
 414         u64 adj;
 415         u32 diff, addend;
 416         int neg_adj = 0;
 417         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 418         struct pch_ts_regs __iomem *regs = pch_dev->regs;
 419
 420         if (ppb < 0) {
 421                 neg_adj = 1;
 422                 ppb = -ppb;
 423         }
 424         addend = DEFAULT_ADDEND;
 425         adj = addend;
 426         adj *= ppb;
 427         diff = div_u64(adj, 1000000000ULL);
 428
 429         addend = neg_adj ? addend - diff : addend + diff;
 430
 431         iowrite32(addend, &regs->addend);
 432
 433         return 0;
 434 }
 435
 436 static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
 437 {
 438         s64 now;
 439         unsigned long flags;
 440         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 441         struct pch_ts_regs __iomem *regs = pch_dev->regs;
 442
 443         spin_lock_irqsave(&pch_dev->register_lock, flags);
 444         now = pch_systime_read(regs);
 445         now += delta;
 446         pch_systime_write(regs, now);
 447         spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 448
 449         return 0;
 450 }
 451
 452 static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 453 {
 454         u64 ns;
 455         unsigned long flags;
 456         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 457         struct pch_ts_regs __iomem *regs = pch_dev->regs;
 458
 459         spin_lock_irqsave(&pch_dev->register_lock, flags);
 460         ns = pch_systime_read(regs);
 461         spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 462
 463         *ts = ns_to_timespec64(ns);
 464         return 0;
 465 }
 466
 467 static int ptp_pch_settime(struct ptp_clock_info *ptp,
 468                            const struct timespec64 *ts)
 469 {
 470         u64 ns;
 471         unsigned long flags;
 472         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 473         struct pch_ts_regs __iomem *regs = pch_dev->regs;
 474
 475         ns = timespec64_to_ns(ts);
 476
 477         spin_lock_irqsave(&pch_dev->register_lock, flags);
 478         pch_systime_write(regs, ns);
 479         spin_unlock_irqrestore(&pch_dev->register_lock, flags);
 480
 481         return 0;
 482 }
 483
 484 static int ptp_pch_enable(struct ptp_clock_info *ptp,
 485                           struct ptp_clock_request *rq, int on)
 486 {
 487         struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
 488
 489         switch (rq->type) {
 490         case PTP_CLK_REQ_EXTTS:
 491                 switch (rq->extts.index) {
 492                 case 0:
 493                         pch_dev->exts0_enabled = on ? 1 : 0;
 494                         break;
 495                 case 1:
 496                         pch_dev->exts1_enabled = on ? 1 : 0;
 497                         break;
 498                 default:
 499                         return -EINVAL;
 500                 }
 501                 return 0;
 502         default:
 503                 break;
 504         }
 505
 506         return -EOPNOTSUPP;
 507 }
 508
 509 static const struct ptp_clock_info ptp_pch_caps = {
 510         .owner          = THIS_MODULE,
 511         .name           = "PCH timer",
 512         .max_adj        = 50000000,
 513         .n_ext_ts       = N_EXT_TS,
 514         .n_pins         = 0,
 515         .pps            = 0,
 516         .adjfreq        = ptp_pch_adjfreq,
 517         .adjtime        = ptp_pch_adjtime,
 518         .gettime64      = ptp_pch_gettime,
 519         .settime64      = ptp_pch_settime,
 520         .enable         = ptp_pch_enable,
 521 };
 522
 523
 524 #ifdef CONFIG_PM
 525 static s32 pch_suspend(struct pci_dev *pdev, pm_message_t state)
 526 {
 527         pci_disable_device(pdev);
 528         pci_enable_wake(pdev, PCI_D3hot, 0);
 529
 530         if (pci_save_state(pdev) != 0) {
 531                 dev_err(&pdev->dev, "could not save PCI config state\n");
 532                 return -ENOMEM;
 533         }
 534         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 535
 536         return 0;
 537 }
 538
 539 static s32 pch_resume(struct pci_dev *pdev)
 540 {
 541         s32 ret;
 542
 543         pci_set_power_state(pdev, PCI_D0);
 544         pci_restore_state(pdev);
 545         ret = pci_enable_device(pdev);
 546         if (ret) {
 547                 dev_err(&pdev->dev, "pci_enable_device failed\n");
 548                 return ret;
 549         }
 550         pci_enable_wake(pdev, PCI_D3hot, 0);
 551         return 0;
 552 }
 553 #else
 554 #define pch_suspend NULL
 555 #define pch_resume NULL
 556 #endif
 557
 558 static void pch_remove(struct pci_dev *pdev)
 559 {
 560         struct pch_dev *chip = pci_get_drvdata(pdev);
 561
 562         ptp_clock_unregister(chip->ptp_clock);
 563         /* free the interrupt */
 564         if (pdev->irq != 0)
 565                 free_irq(pdev->irq, chip);
 566
 567         /* unmap the virtual IO memory space */
 568         if (chip->regs != NULL) {
 569                 iounmap(chip->regs);
 570                 chip->regs = NULL;
 571         }
 572         /* release the reserved IO memory space */
 573         if (chip->mem_base != 0) {
 574                 release_mem_region(chip->mem_base, chip->mem_size);
 575                 chip->mem_base = 0;
 576         }
 577         pci_disable_device(pdev);
 578         kfree(chip);
 579         dev_info(&pdev->dev, "complete\n");
 580 }
 581
 582 static s32
 583 pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 584 {
 585         s32 ret;
 586         unsigned long flags;
 587         struct pch_dev *chip;
 588
 589         chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
 590         if (chip == NULL)
 591                 return -ENOMEM;
 592
 593         /* enable the 1588 pci device */
 594         ret = pci_enable_device(pdev);
 595         if (ret != 0) {
 596                 dev_err(&pdev->dev, "could not enable the pci device\n");
 597                 goto err_pci_en;
 598         }
 599
 600         chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
 601         if (!chip->mem_base) {
 602                 dev_err(&pdev->dev, "could not locate IO memory address\n");
 603                 ret = -ENODEV;
 604                 goto err_pci_start;
 605         }
 606
 607         /* retrieve the available length of the IO memory space */
 608         chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
 609
 610         /* allocate the memory for the device registers */
 611         if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
 612                 dev_err(&pdev->dev,
 613                         "could not allocate register memory space\n");
 614                 ret = -EBUSY;
 615                 goto err_req_mem_region;
 616         }
 617
 618         /* get the virtual address to the 1588 registers */
 619         chip->regs = ioremap(chip->mem_base, chip->mem_size);
 620
 621         if (!chip->regs) {
 622                 dev_err(&pdev->dev, "Could not get virtual address\n");
 623                 ret = -ENOMEM;
 624                 goto err_ioremap;
 625         }
 626
 627         chip->caps = ptp_pch_caps;
 628         chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
 629         if (IS_ERR(chip->ptp_clock)) {
 630                 ret = PTR_ERR(chip->ptp_clock);
 631                 goto err_ptp_clock_reg;
 632         }
 633
 634         spin_lock_init(&chip->register_lock);
 635
 636         ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
 637         if (ret != 0) {
 638                 dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
 639                 goto err_req_irq;
 640         }
 641
 642         /* indicate success */
 643         chip->irq = pdev->irq;
 644         chip->pdev = pdev;
 645         pci_set_drvdata(pdev, chip);
 646
 647         spin_lock_irqsave(&chip->register_lock, flags);
 648         /* reset the ieee1588 h/w */
 649         pch_reset(chip);
 650
 651         iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
 652         iowrite32(1, &chip->regs->trgt_lo);
 653         iowrite32(0, &chip->regs->trgt_hi);
 654         iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
 655
 656         pch_eth_enable_set(chip);
 657
 658         if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
 659                 if (pch_set_station_address(pch_param.station, pdev) != 0) {
 660                         dev_err(&pdev->dev,
 661                         "Invalid station address parameter\n"
 662                         "Module loaded but station address not set correctly\n"
 663                         );
 664                 }
 665         }
 666         spin_unlock_irqrestore(&chip->register_lock, flags);
 667         return 0;
 668
 669 err_req_irq:
 670         ptp_clock_unregister(chip->ptp_clock);
 671 err_ptp_clock_reg:
 672         iounmap(chip->regs);
 673         chip->regs = NULL;
 674
 675 err_ioremap:
 676         release_mem_region(chip->mem_base, chip->mem_size);
 677
 678 err_req_mem_region:
 679         chip->mem_base = 0;
 680
 681 err_pci_start:
 682         pci_disable_device(pdev);
 683
 684 err_pci_en:
 685         kfree(chip);
 686         dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
 687
 688         return ret;
 689 }
 690
 691 static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
 692         {
 693           .vendor = PCI_VENDOR_ID_INTEL,
 694           .device = PCI_DEVICE_ID_PCH_1588
 695          },
 696         {0}
 697 };
 698
 699 static struct pci_driver pch_driver = {
 700         .name = KBUILD_MODNAME,
 701         .id_table = pch_ieee1588_pcidev_id,
 702         .probe = pch_probe,
 703         .remove = pch_remove,
 704         .suspend = pch_suspend,
 705         .resume = pch_resume,
 706 };
 707
 708 static void __exit ptp_pch_exit(void)
 709 {
 710         pci_unregister_driver(&pch_driver);
 711 }
 712
 713 static s32 __init ptp_pch_init(void)
 714 {
 715         s32 ret;
 716
 717         /* register the driver with the pci core */
 718         ret = pci_register_driver(&pch_driver);
 719
 720         return ret;
 721 }
 722
 723 module_init(ptp_pch_init);
 724 module_exit(ptp_pch_exit);
 725
 726 module_param_string(station,
 727                     pch_param.station, sizeof(pch_param.station), 0444);
 728 MODULE_PARM_DESC(station,
 729          "IEEE 1588 station address to use - colon separated hex values");
 730
 731 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
 732 MODULE_DESCRIPTION("PTP clock using the EG20T timer");
 733 MODULE_LICENSE("GPL");