drivers/platform/x86/intel_pmc_core.c

   1 /*
   2  * Intel Core SoC Power Management Controller Driver
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   8  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/acpi.h>
  24 #include <linux/debugfs.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/uaccess.h>
  30
  31 #include <asm/cpu_device_id.h>
  32 #include <asm/intel-family.h>
  33
  34 #include "intel_pmc_core.h"
  35
  36 #define ICPU(model, data) \
  37         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
  38
  39 static struct pmc_dev pmc;
  40
  41 static const struct pmc_bit_map spt_pll_map[] = {
  42         {"MIPI PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE0},
  43         {"GEN2 USB2PCIE2 PLL",          SPT_PMC_BIT_MPHY_CMN_LANE1},
  44         {"DMIPCIE3 PLL",                SPT_PMC_BIT_MPHY_CMN_LANE2},
  45         {"SATA PLL",                    SPT_PMC_BIT_MPHY_CMN_LANE3},
  46         {},
  47 };
  48
  49 static const struct pmc_bit_map spt_mphy_map[] = {
  50         {"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
  51         {"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
  52         {"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
  53         {"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
  54         {"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
  55         {"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
  56         {"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
  57         {"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
  58         {"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
  59         {"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
  60         {"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
  61         {"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
  62         {"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
  63         {"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
  64         {"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
  65         {"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
  66         {},
  67 };
  68
  69 static const struct pmc_bit_map spt_pfear_map[] = {
  70         {"PMC",                         SPT_PMC_BIT_PMC},
  71         {"OPI-DMI",                     SPT_PMC_BIT_OPI},
  72         {"SPI / eSPI",                  SPT_PMC_BIT_SPI},
  73         {"XHCI",                        SPT_PMC_BIT_XHCI},
  74         {"SPA",                         SPT_PMC_BIT_SPA},
  75         {"SPB",                         SPT_PMC_BIT_SPB},
  76         {"SPC",                         SPT_PMC_BIT_SPC},
  77         {"GBE",                         SPT_PMC_BIT_GBE},
  78         {"SATA",                        SPT_PMC_BIT_SATA},
  79         {"HDA-PGD0",                    SPT_PMC_BIT_HDA_PGD0},
  80         {"HDA-PGD1",                    SPT_PMC_BIT_HDA_PGD1},
  81         {"HDA-PGD2",                    SPT_PMC_BIT_HDA_PGD2},
  82         {"HDA-PGD3",                    SPT_PMC_BIT_HDA_PGD3},
  83         {"RSVD",                        SPT_PMC_BIT_RSVD_0B},
  84         {"LPSS",                        SPT_PMC_BIT_LPSS},
  85         {"LPC",                         SPT_PMC_BIT_LPC},
  86         {"SMB",                         SPT_PMC_BIT_SMB},
  87         {"ISH",                         SPT_PMC_BIT_ISH},
  88         {"P2SB",                        SPT_PMC_BIT_P2SB},
  89         {"DFX",                         SPT_PMC_BIT_DFX},
  90         {"SCC",                         SPT_PMC_BIT_SCC},
  91         {"RSVD",                        SPT_PMC_BIT_RSVD_0C},
  92         {"FUSE",                        SPT_PMC_BIT_FUSE},
  93         {"CAMERA",                      SPT_PMC_BIT_CAMREA},
  94         {"RSVD",                        SPT_PMC_BIT_RSVD_0D},
  95         {"USB3-OTG",                    SPT_PMC_BIT_USB3_OTG},
  96         {"EXI",                         SPT_PMC_BIT_EXI},
  97         {"CSE",                         SPT_PMC_BIT_CSE},
  98         {"CSME_KVM",                    SPT_PMC_BIT_CSME_KVM},
  99         {"CSME_PMT",                    SPT_PMC_BIT_CSME_PMT},
 100         {"CSME_CLINK",                  SPT_PMC_BIT_CSME_CLINK},
 101         {"CSME_PTIO",                   SPT_PMC_BIT_CSME_PTIO},
 102         {"CSME_USBR",                   SPT_PMC_BIT_CSME_USBR},
 103         {"CSME_SUSRAM",                 SPT_PMC_BIT_CSME_SUSRAM},
 104         {"CSME_SMT",                    SPT_PMC_BIT_CSME_SMT},
 105         {"RSVD",                        SPT_PMC_BIT_RSVD_1A},
 106         {"CSME_SMS2",                   SPT_PMC_BIT_CSME_SMS2},
 107         {"CSME_SMS1",                   SPT_PMC_BIT_CSME_SMS1},
 108         {"CSME_RTC",                    SPT_PMC_BIT_CSME_RTC},
 109         {"CSME_PSF",                    SPT_PMC_BIT_CSME_PSF},
 110         {},
 111 };
 112
 113 static const struct pmc_reg_map spt_reg_map = {
 114         .pfear_sts = spt_pfear_map,
 115         .mphy_sts = spt_mphy_map,
 116         .pll_sts = spt_pll_map,
 117         .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
 118         .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
 119         .regmap_length = SPT_PMC_MMIO_REG_LEN,
 120         .ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
 121         .ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
 122         .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
 123         .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
 124 };
 125
 126 /* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
 127 static const struct pmc_bit_map cnp_pfear_map[] = {
 128         {"PMC",                 BIT(0)},
 129         {"OPI-DMI",             BIT(1)},
 130         {"SPI/eSPI",            BIT(2)},
 131         {"XHCI",                BIT(3)},
 132         {"SPA",                 BIT(4)},
 133         {"SPB",                 BIT(5)},
 134         {"SPC",                 BIT(6)},
 135         {"GBE",                 BIT(7)},
 136
 137         {"SATA",                BIT(0)},
 138         {"HDA_PGD0",            BIT(1)},
 139         {"HDA_PGD1",            BIT(2)},
 140         {"HDA_PGD2",            BIT(3)},
 141         {"HDA_PGD3",            BIT(4)},
 142         {"SPD",                 BIT(5)},
 143         {"LPSS",                BIT(6)},
 144         {"LPC",                 BIT(7)},
 145
 146         {"SMB",                 BIT(0)},
 147         {"ISH",                 BIT(1)},
 148         {"P2SB",                BIT(2)},
 149         {"NPK_VNN",             BIT(3)},
 150         {"SDX",                 BIT(4)},
 151         {"SPE",                 BIT(5)},
 152         {"Fuse",                BIT(6)},
 153         {"Res_23",              BIT(7)},
 154
 155         {"CSME_FSC",            BIT(0)},
 156         {"USB3_OTG",            BIT(1)},
 157         {"EXI",                 BIT(2)},
 158         {"CSE",                 BIT(3)},
 159         {"csme_kvm",            BIT(4)},
 160         {"csme_pmt",            BIT(5)},
 161         {"csme_clink",          BIT(6)},
 162         {"csme_ptio",           BIT(7)},
 163
 164         {"csme_usbr",           BIT(0)},
 165         {"csme_susram",         BIT(1)},
 166         {"csme_smt1",           BIT(2)},
 167         {"CSME_SMT4",           BIT(3)},
 168         {"csme_sms2",           BIT(4)},
 169         {"csme_sms1",           BIT(5)},
 170         {"csme_rtc",            BIT(6)},
 171         {"csme_psf",            BIT(7)},
 172
 173         {"SBR0",                BIT(0)},
 174         {"SBR1",                BIT(1)},
 175         {"SBR2",                BIT(2)},
 176         {"SBR3",                BIT(3)},
 177         {"SBR4",                BIT(4)},
 178         {"SBR5",                BIT(5)},
 179         {"CSME_PECI",           BIT(6)},
 180         {"PSF1",                BIT(7)},
 181
 182         {"PSF2",                BIT(0)},
 183         {"PSF3",                BIT(1)},
 184         {"PSF4",                BIT(2)},
 185         {"CNVI",                BIT(3)},
 186         {"UFS0",                BIT(4)},
 187         {"EMMC",                BIT(5)},
 188         {"Res_6",               BIT(6)},
 189         {"SBR6",                BIT(7)},
 190
 191         {"SBR7",                BIT(0)},
 192         {"NPK_AON",             BIT(1)},
 193         {"HDA_PGD4",            BIT(2)},
 194         {"HDA_PGD5",            BIT(3)},
 195         {"HDA_PGD6",            BIT(4)},
 196         {}
 197 };
 198
 199 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
 200         {"AUDIO_D3",            BIT(0)},
 201         {"OTG_D3",              BIT(1)},
 202         {"XHCI_D3",             BIT(2)},
 203         {"LPIO_D3",             BIT(3)},
 204         {"SDX_D3",              BIT(4)},
 205         {"SATA_D3",             BIT(5)},
 206         {"UFS0_D3",             BIT(6)},
 207         {"UFS1_D3",             BIT(7)},
 208         {"EMMC_D3",             BIT(8)},
 209         {}
 210 };
 211
 212 static const struct pmc_bit_map cnp_slps0_dbg1_map[] = {
 213         {"SDIO_PLL_OFF",        BIT(0)},
 214         {"USB2_PLL_OFF",        BIT(1)},
 215         {"AUDIO_PLL_OFF",       BIT(2)},
 216         {"OC_PLL_OFF",          BIT(3)},
 217         {"MAIN_PLL_OFF",        BIT(4)},
 218         {"XOSC_OFF",            BIT(5)},
 219         {"LPC_CLKS_GATED",      BIT(6)},
 220         {"PCIE_CLKREQS_IDLE",   BIT(7)},
 221         {"AUDIO_ROSC_OFF",      BIT(8)},
 222         {"HPET_XOSC_CLK_REQ",   BIT(9)},
 223         {"PMC_ROSC_SLOW_CLK",   BIT(10)},
 224         {"AON2_ROSC_GATED",     BIT(11)},
 225         {"CLKACKS_DEASSERTED",  BIT(12)},
 226         {}
 227 };
 228
 229 static const struct pmc_bit_map cnp_slps0_dbg2_map[] = {
 230         {"MPHY_CORE_GATED",     BIT(0)},
 231         {"CSME_GATED",          BIT(1)},
 232         {"USB2_SUS_GATED",      BIT(2)},
 233         {"DYN_FLEX_IO_IDLE",    BIT(3)},
 234         {"GBE_NO_LINK",         BIT(4)},
 235         {"THERM_SEN_DISABLED",  BIT(5)},
 236         {"PCIE_LOW_POWER",      BIT(6)},
 237         {"ISH_VNNAON_REQ_ACT",  BIT(7)},
 238         {"ISH_VNN_REQ_ACT",     BIT(8)},
 239         {"CNV_VNNAON_REQ_ACT",  BIT(9)},
 240         {"CNV_VNN_REQ_ACT",     BIT(10)},
 241         {"NPK_VNNON_REQ_ACT",   BIT(11)},
 242         {"PMSYNC_STATE_IDLE",   BIT(12)},
 243         {"ALST_GT_THRES",       BIT(13)},
 244         {"PMC_ARC_PG_READY",    BIT(14)},
 245         {}
 246 };
 247
 248 static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
 249         cnp_slps0_dbg0_map,
 250         cnp_slps0_dbg1_map,
 251         cnp_slps0_dbg2_map,
 252         NULL,
 253 };
 254
 255 static const struct pmc_reg_map cnp_reg_map = {
 256         .pfear_sts = cnp_pfear_map,
 257         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 258         .slps0_dbg_maps = cnp_slps0_dbg_maps,
 259         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
 260         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 261         .regmap_length = CNP_PMC_MMIO_REG_LEN,
 262         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
 263         .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
 264         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
 265         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
 266 };
 267
 268 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 269 {
 270         return readb(pmcdev->regbase + offset);
 271 }
 272
 273 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
 274 {
 275         return readl(pmcdev->regbase + reg_offset);
 276 }
 277
 278 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
 279                                                         reg_offset, u32 val)
 280 {
 281         writel(val, pmcdev->regbase + reg_offset);
 282 }
 283
 284 static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
 285 {
 286         return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
 287 }
 288
 289 static int pmc_core_dev_state_get(void *data, u64 *val)
 290 {
 291         struct pmc_dev *pmcdev = data;
 292         const struct pmc_reg_map *map = pmcdev->map;
 293         u32 value;
 294
 295         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 296         *val = pmc_core_adjust_slp_s0_step(value);
 297
 298         return 0;
 299 }
 300
 301 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 302
 303 static int pmc_core_check_read_lock_bit(void)
 304 {
 305         struct pmc_dev *pmcdev = &pmc;
 306         u32 value;
 307
 308         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 309         return value & BIT(pmcdev->map->pm_read_disable_bit);
 310 }
 311
 312 #if IS_ENABLED(CONFIG_DEBUG_FS)
 313 static bool slps0_dbg_latch;
 314
 315 static void pmc_core_display_map(struct seq_file *s, int index,
 316                                  u8 pf_reg, const struct pmc_bit_map *pf_map)
 317 {
 318         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 319                    index, pf_map[index].name,
 320                    pf_map[index].bit_mask & pf_reg ? "Off" : "On");
 321 }
 322
 323 static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
 324 {
 325         struct pmc_dev *pmcdev = s->private;
 326         const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
 327         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 328         int index, iter;
 329
 330         iter = pmcdev->map->ppfear0_offset;
 331
 332         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 333              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 334                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 335
 336         for (index = 0; map[index].name; index++)
 337                 pmc_core_display_map(s, index, pf_regs[index / 8], map);
 338
 339         return 0;
 340 }
 341
 342 static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
 343 {
 344         return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
 345 }
 346
 347 static const struct file_operations pmc_core_ppfear_ops = {
 348         .open           = pmc_core_ppfear_sts_open,
 349         .read           = seq_read,
 350         .llseek         = seq_lseek,
 351         .release        = single_release,
 352 };
 353
 354 /* This function should return link status, 0 means ready */
 355 static int pmc_core_mtpmc_link_status(void)
 356 {
 357         struct pmc_dev *pmcdev = &pmc;
 358         u32 value;
 359
 360         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 361         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 362 }
 363
 364 static int pmc_core_send_msg(u32 *addr_xram)
 365 {
 366         struct pmc_dev *pmcdev = &pmc;
 367         u32 dest;
 368         int timeout;
 369
 370         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 371                 if (pmc_core_mtpmc_link_status() == 0)
 372                         break;
 373                 msleep(5);
 374         }
 375
 376         if (timeout <= 0 && pmc_core_mtpmc_link_status())
 377                 return -EBUSY;
 378
 379         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 380         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 381         return 0;
 382 }
 383
 384 static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
 385 {
 386         struct pmc_dev *pmcdev = s->private;
 387         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 388         u32 mphy_core_reg_low, mphy_core_reg_high;
 389         u32 val_low, val_high;
 390         int index, err = 0;
 391
 392         if (pmcdev->pmc_xram_read_bit) {
 393                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 394                 return 0;
 395         }
 396
 397         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 398         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 399
 400         mutex_lock(&pmcdev->lock);
 401
 402         if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
 403                 err = -EBUSY;
 404                 goto out_unlock;
 405         }
 406
 407         msleep(10);
 408         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 409
 410         if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
 411                 err = -EBUSY;
 412                 goto out_unlock;
 413         }
 414
 415         msleep(10);
 416         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 417
 418         for (index = 0; map[index].name && index < 8; index++) {
 419                 seq_printf(s, "%-32s\tState: %s\n",
 420                            map[index].name,
 421                            map[index].bit_mask & val_low ? "Not power gated" :
 422                            "Power gated");
 423         }
 424
 425         for (index = 8; map[index].name; index++) {
 426                 seq_printf(s, "%-32s\tState: %s\n",
 427                            map[index].name,
 428                            map[index].bit_mask & val_high ? "Not power gated" :
 429                            "Power gated");
 430         }
 431
 432 out_unlock:
 433         mutex_unlock(&pmcdev->lock);
 434         return err;
 435 }
 436
 437 static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
 438 {
 439         return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
 440 }
 441
 442 static const struct file_operations pmc_core_mphy_pg_ops = {
 443         .open           = pmc_core_mphy_pg_sts_open,
 444         .read           = seq_read,
 445         .llseek         = seq_lseek,
 446         .release        = single_release,
 447 };
 448
 449 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 450 {
 451         struct pmc_dev *pmcdev = s->private;
 452         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 453         u32 mphy_common_reg, val;
 454         int index, err = 0;
 455
 456         if (pmcdev->pmc_xram_read_bit) {
 457                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 458                 return 0;
 459         }
 460
 461         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 462         mutex_lock(&pmcdev->lock);
 463
 464         if (pmc_core_send_msg(&mphy_common_reg) != 0) {
 465                 err = -EBUSY;
 466                 goto out_unlock;
 467         }
 468
 469         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 470         msleep(10);
 471         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 472
 473         for (index = 0; map[index].name ; index++) {
 474                 seq_printf(s, "%-32s\tState: %s\n",
 475                            map[index].name,
 476                            map[index].bit_mask & val ? "Active" : "Idle");
 477         }
 478
 479 out_unlock:
 480         mutex_unlock(&pmcdev->lock);
 481         return err;
 482 }
 483
 484 static int pmc_core_pll_open(struct inode *inode, struct file *file)
 485 {
 486         return single_open(file, pmc_core_pll_show, inode->i_private);
 487 }
 488
 489 static const struct file_operations pmc_core_pll_ops = {
 490         .open           = pmc_core_pll_open,
 491         .read           = seq_read,
 492         .llseek         = seq_lseek,
 493         .release        = single_release,
 494 };
 495
 496 static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
 497 *userbuf, size_t count, loff_t *ppos)
 498 {
 499         struct pmc_dev *pmcdev = &pmc;
 500         const struct pmc_reg_map *map = pmcdev->map;
 501         u32 val, buf_size, fd;
 502         int err = 0;
 503
 504         buf_size = count < 64 ? count : 64;
 505         mutex_lock(&pmcdev->lock);
 506
 507         if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
 508                 err = -EFAULT;
 509                 goto out_unlock;
 510         }
 511
 512         if (val > NUM_IP_IGN_ALLOWED) {
 513                 err = -EINVAL;
 514                 goto out_unlock;
 515         }
 516
 517         fd = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
 518         fd |= (1U << val);
 519         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
 520
 521 out_unlock:
 522         mutex_unlock(&pmcdev->lock);
 523         return err == 0 ? count : err;
 524 }
 525
 526 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 527 {
 528         return 0;
 529 }
 530
 531 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
 532 {
 533         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
 534 }
 535
 536 static const struct file_operations pmc_core_ltr_ignore_ops = {
 537         .open           = pmc_core_ltr_ignore_open,
 538         .read           = seq_read,
 539         .write          = pmc_core_ltr_ignore_write,
 540         .llseek         = seq_lseek,
 541         .release        = single_release,
 542 };
 543
 544 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
 545 {
 546         const struct pmc_reg_map *map = pmcdev->map;
 547         u32 fd;
 548
 549         mutex_lock(&pmcdev->lock);
 550
 551         if (!reset && !slps0_dbg_latch)
 552                 goto out_unlock;
 553
 554         fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
 555         if (reset)
 556                 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
 557         else
 558                 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
 559         pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
 560
 561         slps0_dbg_latch = 0;
 562
 563 out_unlock:
 564         mutex_unlock(&pmcdev->lock);
 565 }
 566
 567 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
 568 {
 569         struct pmc_dev *pmcdev = s->private;
 570         const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
 571         const struct pmc_bit_map *map;
 572         int offset;
 573         u32 data;
 574
 575         pmc_core_slps0_dbg_latch(pmcdev, false);
 576         offset = pmcdev->map->slps0_dbg_offset;
 577         while (*maps) {
 578                 map = *maps;
 579                 data = pmc_core_reg_read(pmcdev, offset);
 580                 offset += 4;
 581                 while (map->name) {
 582                         seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
 583                                    map->name,
 584                                    data & map->bit_mask ?
 585                                    "Yes" : "No");
 586                         ++map;
 587                 }
 588                 ++maps;
 589         }
 590         pmc_core_slps0_dbg_latch(pmcdev, true);
 591         return 0;
 592 }
 593 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
 594
 595 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 596 {
 597         debugfs_remove_recursive(pmcdev->dbgfs_dir);
 598 }
 599
 600 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 601 {
 602         struct dentry *dir;
 603
 604         dir = debugfs_create_dir("pmc_core", NULL);
 605         if (!dir)
 606                 return -ENOMEM;
 607
 608         pmcdev->dbgfs_dir = dir;
 609
 610         debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
 611                             &pmc_core_dev_state);
 612
 613         debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
 614                             &pmc_core_ppfear_ops);
 615
 616         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
 617                             &pmc_core_ltr_ignore_ops);
 618
 619         if (pmcdev->map->pll_sts)
 620                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
 621                                     &pmc_core_pll_ops);
 622
 623         if (pmcdev->map->mphy_sts)
 624                 debugfs_create_file("mphy_core_lanes_power_gating_status",
 625                                     0444, dir, pmcdev,
 626                                     &pmc_core_mphy_pg_ops);
 627
 628         if (pmcdev->map->slps0_dbg_maps) {
 629                 debugfs_create_file("slp_s0_debug_status", 0444,
 630                                     dir, pmcdev,
 631                                     &pmc_core_slps0_dbg_fops);
 632
 633                 debugfs_create_bool("slp_s0_dbg_latch", 0644,
 634                                     dir, &slps0_dbg_latch);
 635         }
 636
 637         return 0;
 638 }
 639 #else
 640 static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 641 {
 642         return 0;
 643 }
 644
 645 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 646 {
 647 }
 648 #endif /* CONFIG_DEBUG_FS */
 649
 650 static const struct x86_cpu_id intel_pmc_core_ids[] = {
 651         ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
 652         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
 653         ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
 654         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
 655         ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map),
 656         {}
 657 };
 658
 659 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
 660
 661 static const struct pci_device_id pmc_pci_ids[] = {
 662         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
 663         { 0, },
 664 };
 665
 666 static int __init pmc_core_probe(void)
 667 {
 668         struct pmc_dev *pmcdev = &pmc;
 669         const struct x86_cpu_id *cpu_id;
 670         u64 slp_s0_addr;
 671         int err;
 672
 673         cpu_id = x86_match_cpu(intel_pmc_core_ids);
 674         if (!cpu_id)
 675                 return -ENODEV;
 676
 677         pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
 678
 679         /*
 680          * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
 681          * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
 682          * in this case.
 683          */
 684         if (!pci_dev_present(pmc_pci_ids))
 685                 pmcdev->map = &cnp_reg_map;
 686
 687         if (lpit_read_residency_count_address(&slp_s0_addr))
 688                 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
 689         else
 690                 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
 691
 692         pmcdev->regbase = ioremap(pmcdev->base_addr,
 693                                   pmcdev->map->regmap_length);
 694         if (!pmcdev->regbase)
 695                 return -ENOMEM;
 696
 697         mutex_init(&pmcdev->lock);
 698         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
 699
 700         err = pmc_core_dbgfs_register(pmcdev);
 701         if (err < 0) {
 702                 pr_warn(" debugfs register failed.\n");
 703                 iounmap(pmcdev->regbase);
 704                 return err;
 705         }
 706
 707         pr_info(" initialized\n");
 708         return 0;
 709 }
 710 module_init(pmc_core_probe)
 711
 712 static void __exit pmc_core_remove(void)
 713 {
 714         struct pmc_dev *pmcdev = &pmc;
 715
 716         pmc_core_dbgfs_unregister(pmcdev);
 717         mutex_destroy(&pmcdev->lock);
 718         iounmap(pmcdev->regbase);
 719 }
 720 module_exit(pmc_core_remove)
 721
 722 MODULE_LICENSE("GPL v2");
 723 MODULE_DESCRIPTION("Intel PMC Core Driver");