2 * cros_ec_lpc_mec - LPC variant I/O for Microchip EC
4 * Copyright (C) 2016 Google, Inc
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * This driver uses the Chrome OS EC byte-level message-based protocol for
16 * communicating the keyboard state (which keys are pressed) from a keyboard EC
17 * to the AP over some bus (such as i2c, lpc, spi). The EC does debouncing,
18 * but everything else (including deghosting) is done here. The main
19 * motivation for this is to keep the EC firmware as simple as possible, since
20 * it cannot be easily upgraded and EC flash/IRAM space is relatively
24 #include <linux/delay.h>
26 #include <linux/mfd/cros_ec_commands.h>
27 #include <linux/mutex.h>
28 #include <linux/types.h>
30 #include "cros_ec_lpc_mec.h"
33 * This mutex must be held while accessing the EMI unit. We can't rely on the
34 * EC mutex because memmap data may be accessed without it being held.
36 static struct mutex io_mutex;
39 * cros_ec_lpc_mec_emi_write_address
41 * Initialize EMI read / write at a given address.
43 * @addr: Starting read / write address
44 * @access_type: Type of access, typically 32-bit auto-increment
46 static void cros_ec_lpc_mec_emi_write_address(u16 addr,
47 enum cros_ec_lpc_mec_emi_access_mode access_type)
49 /* Address relative to start of EMI range */
50 addr -= MEC_EMI_RANGE_START;
51 outb((addr & 0xfc) | access_type, MEC_EMI_EC_ADDRESS_B0);
52 outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1);
56 * cros_ec_lpc_io_bytes_mec - Read / write bytes to MEC EMI port
58 * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request
59 * @offset: Base read / write address
60 * @length: Number of bytes to read / write
61 * @buf: Destination / source buffer
63 * @return 8-bit checksum of all bytes read / written
65 u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,
66 unsigned int offset, unsigned int length,
72 enum cros_ec_lpc_mec_emi_access_mode access, new_access;
75 * Long access cannot be used on misaligned data since reading B0 loads
76 * the data register and writing B3 flushes.
78 if (offset & 0x3 || length < 4)
79 access = ACCESS_TYPE_BYTE;
81 access = ACCESS_TYPE_LONG_AUTO_INCREMENT;
83 mutex_lock(&io_mutex);
85 /* Initialize I/O at desired address */
86 cros_ec_lpc_mec_emi_write_address(offset, access);
88 /* Skip bytes in case of misaligned offset */
89 io_addr = MEC_EMI_EC_DATA_B0 + (offset & 0x3);
91 while (io_addr <= MEC_EMI_EC_DATA_B3) {
92 if (io_type == MEC_IO_READ)
93 buf[i] = inb(io_addr++);
95 outb(buf[i], io_addr++);
100 /* Extra bounds check in case of misaligned length */
106 * Use long auto-increment access except for misaligned write,
107 * since writing B3 triggers the flush.
109 if (length - i < 4 && io_type == MEC_IO_WRITE)
110 new_access = ACCESS_TYPE_BYTE;
112 new_access = ACCESS_TYPE_LONG_AUTO_INCREMENT;
114 if (new_access != access ||
115 access != ACCESS_TYPE_LONG_AUTO_INCREMENT) {
117 cros_ec_lpc_mec_emi_write_address(offset, access);
120 /* Access [B0, B3] on each loop pass */
121 io_addr = MEC_EMI_EC_DATA_B0;
125 mutex_unlock(&io_mutex);
129 EXPORT_SYMBOL(cros_ec_lpc_io_bytes_mec);
131 void cros_ec_lpc_mec_init(void)
133 mutex_init(&io_mutex);
135 EXPORT_SYMBOL(cros_ec_lpc_mec_init);
137 void cros_ec_lpc_mec_destroy(void)
139 mutex_destroy(&io_mutex);
141 EXPORT_SYMBOL(cros_ec_lpc_mec_destroy);