drivers/pinctrl/sh-pfc/pfc-r8a7794.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7794/r8a7745 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   6  * Copyright (C) 2015 Renesas Solutions Corp.
   7  * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/sys_soc.h>
  12
  13 #include "core.h"
  14 #include "sh_pfc.h"
  15
  16 #define CPU_ALL_PORT(fn, sfx)                                           \
  17         PORT_GP_32(0, fn, sfx),                                         \
  18         PORT_GP_26(1, fn, sfx),                                         \
  19         PORT_GP_32(2, fn, sfx),                                         \
  20         PORT_GP_32(3, fn, sfx),                                         \
  21         PORT_GP_32(4, fn, sfx),                                         \
  22         PORT_GP_28(5, fn, sfx),                                         \
  23         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  24         PORT_GP_1(6, 24, fn, sfx),                                      \
  25         PORT_GP_1(6, 25, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  39         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  40         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  41         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  42         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  43         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  44         FN_IP2_17_16,
  45
  46         /* GPSR1 */
  47         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  48         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  49         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  50         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  51         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  52
  53         /* GPSR2 */
  54         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  55         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  56         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  57         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  58         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  59         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  60         FN_IP6_5_4, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  64         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  65         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  66         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  67         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  68         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  69         FN_IP8_22_20,
  70
  71         /* GPSR4 */
  72         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  73         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  74         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  75         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  76         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  77         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  78         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  79
  80         /* GPSR5 */
  81         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  82         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  83         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  84         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  85         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  86         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  87
  88         /* GPSR6 */
  89         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  90         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  91         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  92         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  93         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  94
  95         /* IPSR0 */
  96         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  97         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
  98         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
  99         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 100         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 101         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 102         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 103         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 104
 105         /* IPSR1 */
 106         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
 107         FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
 108         FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
 109         FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
 110         FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
 111         FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 112         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
 113         FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
 114         FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
 115         FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
 116         FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
 117         FN_A1, FN_SCIFB1_TXD,
 118         FN_A3, FN_SCIFB0_SCK,
 119         FN_A4, FN_SCIFB0_TXD,
 120         FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 121         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 122
 123         /* IPSR2 */
 124         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
 125         FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
 126         FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
 127         FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
 128         FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
 129         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
 130         FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
 131         FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 132         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
 133         FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
 134         FN_TPUTO2_B,
 135         FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 136         FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
 137         FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
 138         FN_A20, FN_SPCLK,
 139
 140         /* IPSR3 */
 141         FN_A21, FN_MOSI_IO0,
 142         FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
 143         FN_A23, FN_IO2, FN_ATAWR1_N,
 144         FN_A24, FN_IO3, FN_EX_WAIT2,
 145         FN_A25, FN_SSL, FN_ATARD1_N,
 146         FN_CS0_N, FN_VI1_DATA8,
 147         FN_CS1_N_A26, FN_VI1_DATA9,
 148         FN_EX_CS0_N, FN_VI1_DATA10,
 149         FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
 150         FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
 151         FN_SCIFB2_TXD,
 152         FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
 153         FN_SCIFB2_SCK,
 154         FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
 155         FN_SCIFB2_CTS_N,
 156         FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
 157         FN_SCIFB2_RTS_N,
 158         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
 159         FN_RD_N, FN_ATACS11_N,
 160         FN_RD_WR_N, FN_ATAG1_N,
 161
 162         /* IPSR4 */
 163         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
 164         FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
 165         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
 166         FN_DU0_DR2, FN_LCDOUT18,
 167         FN_DU0_DR3, FN_LCDOUT19,
 168         FN_DU0_DR4, FN_LCDOUT20,
 169         FN_DU0_DR5, FN_LCDOUT21,
 170         FN_DU0_DR6, FN_LCDOUT22,
 171         FN_DU0_DR7, FN_LCDOUT23,
 172         FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
 173         FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
 174         FN_DU0_DG2, FN_LCDOUT10,
 175         FN_DU0_DG3, FN_LCDOUT11,
 176         FN_DU0_DG4, FN_LCDOUT12,
 177
 178         /* IPSR5 */
 179         FN_DU0_DG5, FN_LCDOUT13,
 180         FN_DU0_DG6, FN_LCDOUT14,
 181         FN_DU0_DG7, FN_LCDOUT15,
 182         FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 183         FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
 184         FN_DU0_DB2, FN_LCDOUT2,
 185         FN_DU0_DB3, FN_LCDOUT3,
 186         FN_DU0_DB4, FN_LCDOUT4,
 187         FN_DU0_DB5, FN_LCDOUT5,
 188         FN_DU0_DB6, FN_LCDOUT6,
 189         FN_DU0_DB7, FN_LCDOUT7,
 190         FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 191         FN_DU0_DOTCLKOUT0, FN_QCLK,
 192         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 193         FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
 194
 195         /* IPSR6 */
 196         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 197         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
 198         FN_DU0_DISP, FN_QPOLA,
 199         FN_DU0_CDE, FN_QPOLB,
 200         FN_VI0_CLK, FN_AVB_RX_CLK,
 201         FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
 202         FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
 203         FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
 204         FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
 205         FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
 206         FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
 207         FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
 208         FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
 209         FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
 210         FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
 211         FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
 212         FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
 213         FN_AVB_TX_EN,
 214         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
 215         FN_ADIDATA,
 216
 217         /* IPSR7 */
 218         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
 219         FN_ADICS_SAMP,
 220         FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
 221         FN_ADICLK,
 222         FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
 223         FN_ADICHS0,
 224         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 225         FN_ADICHS1,
 226         FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
 227         FN_ADICHS2,
 228         FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
 229         FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
 230         FN_SSI_WS5_B,
 231         FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
 232         FN_SSI_SDATA5_B,
 233         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 234         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 235         FN_SSI_WS6_B,
 236         FN_DREQ0_N, FN_SCIFB1_RXD,
 237
 238         /* IPSR8 */
 239         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 240         FN_SSI_SDATA6_B,
 241         FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
 242         FN_SSI_SCK78_B,
 243         FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
 244         FN_SSI_WS78_B,
 245         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 246         FN_AVB_MAGIC, FN_SSI_SDATA7_B,
 247         FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
 248         FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 249         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 250         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 251         FN_CAN1_RX_D, FN_TPUTO0_B,
 252         FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
 253         FN_CAN1_TX_D,
 254         FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
 255         FN_TPUTO1_B,
 256         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
 257         FN_BPFCLK_C,
 258         FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
 259         FN_FMCLK_C,
 260
 261         /* IPSR9 */
 262         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
 263         FN_FMIN_C,
 264         FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
 265         FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
 266         FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
 267         FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
 268         FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
 269         FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 270         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 271         FN_SPEEDIN_B,
 272         FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
 273         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 274         FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
 275
 276         /* IPSR10 */
 277         FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
 278         FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 279         FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
 280         FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 281         FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
 282         FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
 283         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 284         FN_SSI_SCK4_B,
 285         FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
 286         FN_SSI_WS4_B,
 287         FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
 288         FN_SSI_SDATA4_B,
 289         FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
 290         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
 291
 292         /* IPSR11 */
 293         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 294         FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
 295         FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
 296         FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 297         FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 298         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
 299         FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
 300         FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
 301         FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
 302         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 303         FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
 304         FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
 305
 306         /* IPSR12 */
 307         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 308         FN_DREQ1_N_B,
 309         FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
 310         FN_CAN1_RX_C, FN_DACK1_B,
 311         FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
 312         FN_CAN1_TX_C, FN_DREQ2_N,
 313         FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
 314         FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
 315         FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
 316         FN_DACK2, FN_ETH_MDIO_B,
 317         FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 318         FN_ETH_CRS_DV_B,
 319         FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
 320         FN_ETH_RX_ER_B,
 321         FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
 322         FN_ETH_RXD0_B,
 323         FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
 324
 325         /* IPSR13 */
 326         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
 327         FN_ATACS00_N, FN_ETH_LINK_B,
 328         FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
 329         FN_ATACS10_N, FN_ETH_REFCLK_B,
 330         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
 331         FN_ETH_TXD1_B,
 332         FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
 333         FN_ETH_TX_EN_B,
 334         FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
 335         FN_ATADIR0_N, FN_ETH_MAGIC_B,
 336         FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
 337         FN_TS_SDATA_C, FN_ETH_TXD0_B,
 338         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 339         FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
 340         FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
 341         FN_TS_SDEN_C, FN_FMCLK_E,
 342         FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
 343         FN_TS_SPSYNC_C, FN_FMIN_E,
 344
 345         /* MOD_SEL */
 346         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 347         FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
 348         FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
 349         FN_SEL_DARC_4,
 350         FN_SEL_ETH_0, FN_SEL_ETH_1,
 351         FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
 352         FN_SEL_I2C00_4,
 353         FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
 354         FN_SEL_I2C01_4,
 355         FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
 356         FN_SEL_I2C02_4,
 357         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 358         FN_SEL_I2C03_4,
 359         FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
 360         FN_SEL_I2C04_4,
 361         FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
 362
 363         /* MOD_SEL2 */
 364         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 365         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
 366         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
 367         FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
 368         FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
 369         FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
 370         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 371         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
 372         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
 373         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
 374         FN_SEL_TMU_0, FN_SEL_TMU_1,
 375         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 376         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 377         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 378         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 379
 380         /* MOD_SEL3 */
 381         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 382         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 383         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 384         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 385         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 386         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 387         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 388         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 389         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 390         FN_SEL_SSI9_1,
 391         PINMUX_FUNCTION_END,
 392
 393         PINMUX_MARK_BEGIN,
 394         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 395
 396         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 397
 398         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 399         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 400
 401         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 402         SD1_DATA2_MARK, SD1_DATA3_MARK,
 403
 404         /* IPSR0 */
 405         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 406         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 407         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 408         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 409         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 410         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 411         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 412         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 413         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 414         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 415
 416         /* IPSR1 */
 417         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
 418         D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
 419         D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 420         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
 421         D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 422         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 423         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 424         D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 425         D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
 426         D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
 427         A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
 428         A1_MARK, SCIFB1_TXD_MARK,
 429         A3_MARK, SCIFB0_SCK_MARK,
 430         A4_MARK, SCIFB0_TXD_MARK,
 431         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
 432         A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 433
 434         /* IPSR2 */
 435         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
 436         A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
 437         A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 438         A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
 439         A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
 440         A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 441         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
 442         A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
 443         A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
 444         A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
 445         CAN_CLK_C_MARK, TPUTO2_B_MARK,
 446         A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
 447         A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
 448         A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
 449         A20_MARK, SPCLK_MARK,
 450
 451         /* IPSR3 */
 452         A21_MARK, MOSI_IO0_MARK,
 453         A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
 454         A23_MARK, IO2_MARK, ATAWR1_N_MARK,
 455         A24_MARK, IO3_MARK, EX_WAIT2_MARK,
 456         A25_MARK, SSL_MARK, ATARD1_N_MARK,
 457         CS0_N_MARK, VI1_DATA8_MARK,
 458         CS1_N_A26_MARK, VI1_DATA9_MARK,
 459         EX_CS0_N_MARK, VI1_DATA10_MARK,
 460         EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
 461         EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
 462         TPUTO3_MARK, SCIFB2_TXD_MARK,
 463         EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
 464         BPFCLK_MARK, SCIFB2_SCK_MARK,
 465         EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
 466         FMCLK_MARK, SCIFB2_CTS_N_MARK,
 467         EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
 468         FMIN_MARK, SCIFB2_RTS_N_MARK,
 469         BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
 470         RD_N_MARK, ATACS11_N_MARK,
 471         RD_WR_N_MARK, ATAG1_N_MARK,
 472
 473         /* IPSR4 */
 474         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
 475         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 476         DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
 477         DU0_DR2_MARK, LCDOUT18_MARK,
 478         DU0_DR3_MARK, LCDOUT19_MARK,
 479         DU0_DR4_MARK, LCDOUT20_MARK,
 480         DU0_DR5_MARK, LCDOUT21_MARK,
 481         DU0_DR6_MARK, LCDOUT22_MARK,
 482         DU0_DR7_MARK, LCDOUT23_MARK,
 483         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 484         DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
 485         DU0_DG2_MARK, LCDOUT10_MARK,
 486         DU0_DG3_MARK, LCDOUT11_MARK,
 487         DU0_DG4_MARK, LCDOUT12_MARK,
 488
 489         /* IPSR5 */
 490         DU0_DG5_MARK, LCDOUT13_MARK,
 491         DU0_DG6_MARK, LCDOUT14_MARK,
 492         DU0_DG7_MARK, LCDOUT15_MARK,
 493         DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
 494         CAN0_RX_C_MARK,
 495         DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
 496         CAN0_TX_C_MARK,
 497         DU0_DB2_MARK, LCDOUT2_MARK,
 498         DU0_DB3_MARK, LCDOUT3_MARK,
 499         DU0_DB4_MARK, LCDOUT4_MARK,
 500         DU0_DB5_MARK, LCDOUT5_MARK,
 501         DU0_DB6_MARK, LCDOUT6_MARK,
 502         DU0_DB7_MARK, LCDOUT7_MARK,
 503         DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 504         DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 505         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 506         DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 507
 508         /* IPSR6 */
 509         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 510         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 511         DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
 512         VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
 513         VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 514         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
 515         VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
 516         VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 517         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
 518         VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
 519         VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
 520         VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
 521         AVB_RXD7_MARK,
 522         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 523         AVB_RX_ER_MARK,
 524         VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
 525         AVB_COL_MARK,
 526         VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
 527         AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
 528         ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
 529         AVB_TX_CLK_MARK, ADIDATA_MARK,
 530
 531         /* IPSR7 */
 532         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
 533         AVB_TXD0_MARK, ADICS_SAMP_MARK,
 534         ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
 535         AVB_TXD1_MARK, ADICLK_MARK,
 536         ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
 537         AVB_TXD2_MARK, ADICHS0_MARK,
 538         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 539         AVB_TXD3_MARK, ADICHS1_MARK,
 540         ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
 541         AVB_TXD4_MARK, ADICHS2_MARK,
 542         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 543         SSI_SCK5_B_MARK,
 544         ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
 545         AVB_TXD6_MARK, SSI_WS5_B_MARK,
 546         ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
 547         AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
 548         ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
 549         SSI_SCK6_B_MARK,
 550         ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
 551         AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 552         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 553
 554         /* IPSR8 */
 555         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 556         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 557         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 558         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 559         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 560         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 561         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 562         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 563         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 564         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 565         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 566         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 567         CAN1_TX_D_MARK,
 568         I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
 569         TS_SDATA_D_MARK, TPUTO1_B_MARK,
 570         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
 571         BPFCLK_C_MARK,
 572         MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
 573         TS_SDEN_D_MARK, FMCLK_C_MARK,
 574
 575         /* IPSR9 */
 576         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 577         TS_SPSYNC_D_MARK, FMIN_C_MARK,
 578         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
 579         MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
 580         MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
 581         FMCLK_B_MARK,
 582         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 583         FMIN_B_MARK,
 584         HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
 585         HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
 586         HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
 587         SPEEDIN_B_MARK,
 588         HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
 589         SSI_SCK1_B_MARK,
 590         HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
 591         SSI_WS1_B_MARK,
 592         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 593         CAN_TXCLK_MARK,
 594
 595         /* IPSR10 */
 596         SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 597         SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
 598         SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 599         SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
 600         SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
 601         SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
 602         SSI_SDATA9_B_MARK,
 603         SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
 604         AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
 605         SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
 606         AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
 607         I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
 608         SSI_SDATA4_B_MARK,
 609         I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
 610         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
 611
 612         /* IPSR11 */
 613         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 614         SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
 615         SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 616         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 617         DU1_EXVSYNC_DU1_VSYNC_MARK,
 618         SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
 619         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 620         SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
 621         SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
 622         SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
 623         CAN_CLK_D_MARK,
 624         SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
 625         SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
 626         SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
 627
 628         /* IPSR12 */
 629         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 630         DREQ1_N_B_MARK,
 631         SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
 632         CAN1_RX_C_MARK, DACK1_B_MARK,
 633         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 634         CAN1_TX_C_MARK, DREQ2_N_MARK,
 635         SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 636         SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
 637         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
 638         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 639         DACK2_MARK, ETH_MDIO_B_MARK,
 640         SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
 641         CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
 642         SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
 643         CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
 644         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
 645         ETH_RXD0_B_MARK,
 646         SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
 647         ETH_RXD1_B_MARK,
 648
 649         /* IPSR13 */
 650         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 651         ATACS00_N_MARK, ETH_LINK_B_MARK,
 652         SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
 653         VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
 654         SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
 655         EX_WAIT1_MARK, ETH_TXD1_B_MARK,
 656         SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
 657         ATARD0_N_MARK, ETH_TX_EN_B_MARK,
 658         SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
 659         ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
 660         AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
 661         TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
 662         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 663         TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 664         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 665         TS_SDEN_C_MARK, FMCLK_E_MARK,
 666         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 667         TS_SPSYNC_C_MARK, FMIN_E_MARK,
 668         PINMUX_MARK_END,
 669 };
 670
 671 static const u16 pinmux_data[] = {
 672         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 673
 674         PINMUX_SINGLE(A2),
 675         PINMUX_SINGLE(WE0_N),
 676         PINMUX_SINGLE(WE1_N),
 677         PINMUX_SINGLE(DACK0),
 678         PINMUX_SINGLE(USB0_PWEN),
 679         PINMUX_SINGLE(USB0_OVC),
 680         PINMUX_SINGLE(USB1_PWEN),
 681         PINMUX_SINGLE(USB1_OVC),
 682         PINMUX_SINGLE(SD0_CLK),
 683         PINMUX_SINGLE(SD0_CMD),
 684         PINMUX_SINGLE(SD0_DATA0),
 685         PINMUX_SINGLE(SD0_DATA1),
 686         PINMUX_SINGLE(SD0_DATA2),
 687         PINMUX_SINGLE(SD0_DATA3),
 688         PINMUX_SINGLE(SD0_CD),
 689         PINMUX_SINGLE(SD0_WP),
 690         PINMUX_SINGLE(SD1_CLK),
 691         PINMUX_SINGLE(SD1_CMD),
 692         PINMUX_SINGLE(SD1_DATA0),
 693         PINMUX_SINGLE(SD1_DATA1),
 694         PINMUX_SINGLE(SD1_DATA2),
 695         PINMUX_SINGLE(SD1_DATA3),
 696
 697         /* IPSR0 */
 698         PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
 699         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
 700         PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
 701         PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
 702         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 703         PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
 704         PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
 705         PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
 706         PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
 707         PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
 708         PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
 709         PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
 710         PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
 711         PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
 712         PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
 713         PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
 714         PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
 715         PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
 716         PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
 717         PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
 718         PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
 719         PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
 720         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 721         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 722         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 723         PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
 724         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 725         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 726         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 727         PINMUX_IPSR_GPSR(IP0_23_22, D0),
 728         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 729         PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
 730         PINMUX_IPSR_GPSR(IP0_24, D1),
 731         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 732         PINMUX_IPSR_GPSR(IP0_25, D2),
 733         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 734         PINMUX_IPSR_GPSR(IP0_27_26, D3),
 735         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 736         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 737         PINMUX_IPSR_GPSR(IP0_29_28, D4),
 738         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 739         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 740         PINMUX_IPSR_GPSR(IP0_31_30, D5),
 741         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 742         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 743
 744         /* IPSR1 */
 745         PINMUX_IPSR_GPSR(IP1_1_0, D6),
 746         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 747         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 748         PINMUX_IPSR_GPSR(IP1_3_2, D7),
 749         PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
 750         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
 751         PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
 752         PINMUX_IPSR_GPSR(IP1_5_4, D8),
 753         PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
 754         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 755         PINMUX_IPSR_GPSR(IP1_7_6, D9),
 756         PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
 757         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 758         PINMUX_IPSR_GPSR(IP1_10_8, D10),
 759         PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
 760         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 761         PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
 762         PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
 763         PINMUX_IPSR_GPSR(IP1_12_11, D11),
 764         PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
 765         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 766         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 767         PINMUX_IPSR_GPSR(IP1_14_13, D12),
 768         PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
 769         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 770         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 771         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 772         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 773         PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 774         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 775         PINMUX_IPSR_GPSR(IP1_19_18, D14),
 776         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 777         PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
 778         PINMUX_IPSR_GPSR(IP1_21_20, D15),
 779         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 780         PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
 781         PINMUX_IPSR_GPSR(IP1_23_22, A0),
 782         PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
 783         PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
 784         PINMUX_IPSR_GPSR(IP1_24, A1),
 785         PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
 786         PINMUX_IPSR_GPSR(IP1_26, A3),
 787         PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
 788         PINMUX_IPSR_GPSR(IP1_27, A4),
 789         PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
 790         PINMUX_IPSR_GPSR(IP1_29_28, A5),
 791         PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
 792         PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
 793         PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
 794         PINMUX_IPSR_GPSR(IP1_31_30, A6),
 795         PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
 796         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 797         PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 798
 799         /* IPSR2 */
 800         PINMUX_IPSR_GPSR(IP2_1_0, A7),
 801         PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
 802         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 803         PINMUX_IPSR_GPSR(IP2_3_2, A8),
 804         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 805         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 806         PINMUX_IPSR_GPSR(IP2_5_4, A9),
 807         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 808         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 809         PINMUX_IPSR_GPSR(IP2_7_6, A10),
 810         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 811         PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
 812         PINMUX_IPSR_GPSR(IP2_9_8, A11),
 813         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 814         PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
 815         PINMUX_IPSR_GPSR(IP2_11_10, A12),
 816         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 817         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 818         PINMUX_IPSR_GPSR(IP2_13_12, A13),
 819         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 820         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 821         PINMUX_IPSR_GPSR(IP2_15_14, A14),
 822         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 823         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 824         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
 825         PINMUX_IPSR_GPSR(IP2_17_16, A15),
 826         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 827         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 828         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
 829         PINMUX_IPSR_GPSR(IP2_20_18, A16),
 830         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 831         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 832         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
 833         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 834         PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 835         PINMUX_IPSR_GPSR(IP2_23_21, A17),
 836         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 837         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 838         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 839         PINMUX_IPSR_GPSR(IP2_26_24, A18),
 840         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 841         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 842         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 843         PINMUX_IPSR_GPSR(IP2_29_27, A19),
 844         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 845         PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 846         PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
 847         PINMUX_IPSR_GPSR(IP2_31_30, A20),
 848         PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
 849
 850         /* IPSR3 */
 851         PINMUX_IPSR_GPSR(IP3_1_0, A21),
 852         PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
 853         PINMUX_IPSR_GPSR(IP3_3_2, A22),
 854         PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
 855         PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 856         PINMUX_IPSR_GPSR(IP3_5_4, A23),
 857         PINMUX_IPSR_GPSR(IP3_5_4, IO2),
 858         PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 859         PINMUX_IPSR_GPSR(IP3_7_6, A24),
 860         PINMUX_IPSR_GPSR(IP3_7_6, IO3),
 861         PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
 862         PINMUX_IPSR_GPSR(IP3_9_8, A25),
 863         PINMUX_IPSR_GPSR(IP3_9_8, SSL),
 864         PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
 865         PINMUX_IPSR_GPSR(IP3_10, CS0_N),
 866         PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
 867         PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
 868         PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
 869         PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
 870         PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
 871         PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
 872         PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
 873         PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
 874         PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
 875         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 876         PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 877         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 878         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 879         PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 880         PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
 881         PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 882         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 883         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 884         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 885         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
 886         PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
 887         PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 888         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 889         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 890         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 891         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
 892         PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
 893         PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 894         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 895         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 896         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 897         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
 898         PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
 899         PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 900         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 901         PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 902         PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 903         PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
 904         PINMUX_IPSR_GPSR(IP3_30, RD_N),
 905         PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 906         PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
 907         PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 908
 909         /* IPSR4 */
 910         PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 911         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 912         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 913         PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
 914         PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
 915         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 916         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 917         PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
 918         PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
 919         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 920         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 921         PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
 922         PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
 923         PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
 924         PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
 925         PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
 926         PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
 927         PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
 928         PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
 929         PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
 930         PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
 931         PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
 932         PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
 933         PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
 934         PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
 935         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 936         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 937         PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
 938         PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
 939         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 940         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 941         PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
 942         PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
 943         PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
 944         PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
 945         PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
 946         PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
 947
 948         /* IPSR5 */
 949         PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
 950         PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
 951         PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
 952         PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
 953         PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
 954         PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
 955         PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
 956         PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
 957         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 958         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 959         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 960         PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
 961         PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
 962         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 963         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 964         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 965         PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
 966         PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
 967         PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
 968         PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
 969         PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
 970         PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
 971         PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
 972         PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
 973         PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
 974         PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
 975         PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
 976         PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
 977         PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
 978         PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
 979         PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
 980         PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
 981         PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
 982         PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
 983         PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 984         PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
 985
 986         /* IPSR6 */
 987         PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 988         PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
 989         PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 990         PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
 991         PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
 992         PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
 993         PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
 994         PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
 995         PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 996         PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 997         PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
 998         PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
 999         PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
1000         PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
1001         PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
1002         PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
1003         PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
1004         PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
1005         PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
1006         PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
1007         PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
1008         PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
1009         PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
1010         PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
1011         PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
1012         PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
1013         PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
1014         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1015         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1016         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1017         PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
1018         PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1019         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1020         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1021         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1022         PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1023         PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1024         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1025         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1026         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1027         PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1028         PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1029         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1030         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1031         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1032         PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1033         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1034         PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1035         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1036         PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
1037         PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1038         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1039
1040         /* IPSR7 */
1041         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1042         PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1043         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1044         PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
1045         PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1046         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1047         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1048         PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1049         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1050         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1051         PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1052         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1053         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1054         PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1055         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1056         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1057         PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1058         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1059         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1060         PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1061         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1062         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1063         PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1064         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1065         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1066         PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1067         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1068         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1069         PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1070         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1071         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1072         PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1073         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1074         PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1075         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1076         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1077         PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1078         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1079         PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
1080         PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1081         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1082         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1083         PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1084         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1085         PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
1086         PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1087         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1088         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1089         PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1090         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1091         PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1092         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1093         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1094         PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1095         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1096         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1097         PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1098         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1099         PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1100         PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1101
1102         /* IPSR8 */
1103         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1104         PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1105         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1106         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1107         PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1108         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1109         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1110         PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1111         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1112         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1113         PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1114         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1115         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1116         PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1117         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1118         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1119         PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1120         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1121         PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1122         PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1123         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1124         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1125         PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1126         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1127         PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1128         PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1129         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1130         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1131         PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1132         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1133         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1134         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1135         PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1136         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1137         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1138         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1139         PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1140         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1141         PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1142         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1143         PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1144         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1145         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1146         PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1147         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1148         PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1149         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1150         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1151         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1152         PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1153         PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1154         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1155         PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1156         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1157         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1158         PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1159         PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1160         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1161         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1162         PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1163         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1164         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1165         PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1166         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1167         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1168
1169         /* IPSR9 */
1170         PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1171         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1172         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1173         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1174         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1175         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1176         PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1177         PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1178         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1179         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1180         PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1181         PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1182         PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1183         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1184         PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1185         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1186         PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1187         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1188         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1189         PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1190         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1191         PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1192         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1193         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1194         PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1195         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1196         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1197         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1198         PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1199         PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1200         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1201         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1202         PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1203         PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1204         PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1205         PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1206         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1207         PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1208         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1209         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1210         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1211         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1212         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1213         PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1214         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1215         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1216         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1217         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1218         PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1219         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1220         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1221         PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1222         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1223         PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1224         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1225
1226         /* IPSR10 */
1227         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1228         PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
1229         PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1230         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1231         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1232         PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
1233         PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1234         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1235         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1236         PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
1237         PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1238         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1239         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1240         PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
1241         PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1242         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1243         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1244         PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1245         PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1246         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1247         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1248         PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1249         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1250         PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1251         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1252         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1253         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1254         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1255         PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1256         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1257         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1258         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1259         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1260         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1261         PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1262         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1263         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1264         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1265         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1266         PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1267         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1268         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1269         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1270         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1271         PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1272         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1273         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1274         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1275         PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1276
1277         /* IPSR11 */
1278         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1279         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1280         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1281         PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1282         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1283         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1284         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1285         PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1286         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1287         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1288         PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1289         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1290         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1291         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1292         PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1293         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1294         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1295         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1296         PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1297         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1298         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1299         PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
1300         PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1301         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1302         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1303         PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
1304         PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1305         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1306         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1307         PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1308         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1309         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1310         PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1311         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1312         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1313         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1314         PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1315         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1316         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1317         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1318         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1319         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1320         PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1321         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1322
1323         /* IPSR12 */
1324         PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1325         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1326         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1327         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1328         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1329         PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1330         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1331         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1332         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1333         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1334         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1335         PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1336         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1337         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1338         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1339         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1340         PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1341         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1342         PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1343         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1344         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1345         PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1346         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1347         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1348         PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1349         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1350         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1351         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1352         PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1353         PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1354         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1355         PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1356         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1357         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1358         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1359         PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
1360         PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1361         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1362         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1363         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1364         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1365         PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
1366         PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1367         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1368         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1369         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1370         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1371         PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1372         PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
1373         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1374         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1375         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1376         PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1377         PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
1378         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1379
1380         /* IPSR13 */
1381         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1382         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1383         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1384         PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1385         PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1386         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1387         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1388         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1389         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1390         PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1391         PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1392         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1393         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1394         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1395         PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1396         PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1397         PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1398         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1399         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1400         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1401         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1402         PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1403         PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1404         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1405         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1406         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1407         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1408         PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1409         PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1410         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1411         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1412         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1413         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1414         PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1415         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1416         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1417         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1418         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1419         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1420         PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1421         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1422         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1423         PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1424         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1425         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1426         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1427         PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1428         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1429         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1430         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1431         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1432         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1433         PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1434         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1435         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1436 };
1437
1438 static const struct sh_pfc_pin pinmux_pins[] = {
1439         PINMUX_GPIO_GP_ALL(),
1440 };
1441
1442 /* - Audio Clock ------------------------------------------------------------ */
1443 static const unsigned int audio_clka_pins[] = {
1444         /* CLKA */
1445         RCAR_GP_PIN(5, 20),
1446 };
1447 static const unsigned int audio_clka_mux[] = {
1448         AUDIO_CLKA_MARK,
1449 };
1450 static const unsigned int audio_clka_b_pins[] = {
1451         /* CLKA */
1452         RCAR_GP_PIN(3, 25),
1453 };
1454 static const unsigned int audio_clka_b_mux[] = {
1455         AUDIO_CLKA_B_MARK,
1456 };
1457 static const unsigned int audio_clka_c_pins[] = {
1458         /* CLKA */
1459         RCAR_GP_PIN(4, 20),
1460 };
1461 static const unsigned int audio_clka_c_mux[] = {
1462         AUDIO_CLKA_C_MARK,
1463 };
1464 static const unsigned int audio_clka_d_pins[] = {
1465         /* CLKA */
1466         RCAR_GP_PIN(5, 0),
1467 };
1468 static const unsigned int audio_clka_d_mux[] = {
1469         AUDIO_CLKA_D_MARK,
1470 };
1471 static const unsigned int audio_clkb_pins[] = {
1472         /* CLKB */
1473         RCAR_GP_PIN(5, 21),
1474 };
1475 static const unsigned int audio_clkb_mux[] = {
1476         AUDIO_CLKB_MARK,
1477 };
1478 static const unsigned int audio_clkb_b_pins[] = {
1479         /* CLKB */
1480         RCAR_GP_PIN(3, 26),
1481 };
1482 static const unsigned int audio_clkb_b_mux[] = {
1483         AUDIO_CLKB_B_MARK,
1484 };
1485 static const unsigned int audio_clkb_c_pins[] = {
1486         /* CLKB */
1487         RCAR_GP_PIN(4, 21),
1488 };
1489 static const unsigned int audio_clkb_c_mux[] = {
1490         AUDIO_CLKB_C_MARK,
1491 };
1492 static const unsigned int audio_clkc_pins[] = {
1493         /* CLKC */
1494         RCAR_GP_PIN(5, 22),
1495 };
1496 static const unsigned int audio_clkc_mux[] = {
1497         AUDIO_CLKC_MARK,
1498 };
1499 static const unsigned int audio_clkc_b_pins[] = {
1500         /* CLKC */
1501         RCAR_GP_PIN(3, 29),
1502 };
1503 static const unsigned int audio_clkc_b_mux[] = {
1504         AUDIO_CLKC_B_MARK,
1505 };
1506 static const unsigned int audio_clkc_c_pins[] = {
1507         /* CLKC */
1508         RCAR_GP_PIN(4, 22),
1509 };
1510 static const unsigned int audio_clkc_c_mux[] = {
1511         AUDIO_CLKC_C_MARK,
1512 };
1513 static const unsigned int audio_clkout_pins[] = {
1514         /* CLKOUT */
1515         RCAR_GP_PIN(5, 23),
1516 };
1517 static const unsigned int audio_clkout_mux[] = {
1518         AUDIO_CLKOUT_MARK,
1519 };
1520 static const unsigned int audio_clkout_b_pins[] = {
1521         /* CLKOUT */
1522         RCAR_GP_PIN(3, 12),
1523 };
1524 static const unsigned int audio_clkout_b_mux[] = {
1525         AUDIO_CLKOUT_B_MARK,
1526 };
1527 static const unsigned int audio_clkout_c_pins[] = {
1528         /* CLKOUT */
1529         RCAR_GP_PIN(4, 23),
1530 };
1531 static const unsigned int audio_clkout_c_mux[] = {
1532         AUDIO_CLKOUT_C_MARK,
1533 };
1534 /* - AVB -------------------------------------------------------------------- */
1535 static const unsigned int avb_link_pins[] = {
1536         RCAR_GP_PIN(3, 26),
1537 };
1538 static const unsigned int avb_link_mux[] = {
1539         AVB_LINK_MARK,
1540 };
1541 static const unsigned int avb_magic_pins[] = {
1542         RCAR_GP_PIN(3, 27),
1543 };
1544 static const unsigned int avb_magic_mux[] = {
1545         AVB_MAGIC_MARK,
1546 };
1547 static const unsigned int avb_phy_int_pins[] = {
1548         RCAR_GP_PIN(3, 28),
1549 };
1550 static const unsigned int avb_phy_int_mux[] = {
1551         AVB_PHY_INT_MARK,
1552 };
1553 static const unsigned int avb_mdio_pins[] = {
1554         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1555 };
1556 static const unsigned int avb_mdio_mux[] = {
1557         AVB_MDC_MARK, AVB_MDIO_MARK,
1558 };
1559 static const unsigned int avb_mii_pins[] = {
1560         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1561         RCAR_GP_PIN(3, 17),
1562
1563         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1564         RCAR_GP_PIN(3, 5),
1565
1566         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1567         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1568         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1569 };
1570 static const unsigned int avb_mii_mux[] = {
1571         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1572         AVB_TXD3_MARK,
1573
1574         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1575         AVB_RXD3_MARK,
1576
1577         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1578         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1579         AVB_TX_CLK_MARK, AVB_COL_MARK,
1580 };
1581 static const unsigned int avb_gmii_pins[] = {
1582         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1583         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1584         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1585
1586         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1587         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1588         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1589
1590         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1591         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1592         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1593         RCAR_GP_PIN(3, 11),
1594 };
1595 static const unsigned int avb_gmii_mux[] = {
1596         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1597         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1598         AVB_TXD6_MARK, AVB_TXD7_MARK,
1599
1600         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1601         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1602         AVB_RXD6_MARK, AVB_RXD7_MARK,
1603
1604         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1605         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1606         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1607         AVB_COL_MARK,
1608 };
1609
1610 /* - CAN -------------------------------------------------------------------- */
1611 static const unsigned int can0_data_pins[] = {
1612         /* TX, RX */
1613         RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1614 };
1615
1616 static const unsigned int can0_data_mux[] = {
1617         CAN0_TX_MARK, CAN0_RX_MARK,
1618 };
1619
1620 static const unsigned int can0_data_b_pins[] = {
1621         /* TX, RX */
1622         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1623 };
1624
1625 static const unsigned int can0_data_b_mux[] = {
1626         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1627 };
1628
1629 static const unsigned int can0_data_c_pins[] = {
1630         /* TX, RX */
1631         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1632 };
1633
1634 static const unsigned int can0_data_c_mux[] = {
1635         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1636 };
1637
1638 static const unsigned int can0_data_d_pins[] = {
1639         /* TX, RX */
1640         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1641 };
1642
1643 static const unsigned int can0_data_d_mux[] = {
1644         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1645 };
1646
1647 static const unsigned int can1_data_pins[] = {
1648         /* TX, RX */
1649         RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
1650 };
1651
1652 static const unsigned int can1_data_mux[] = {
1653         CAN1_TX_MARK, CAN1_RX_MARK,
1654 };
1655
1656 static const unsigned int can1_data_b_pins[] = {
1657         /* TX, RX */
1658         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1659 };
1660
1661 static const unsigned int can1_data_b_mux[] = {
1662         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1663 };
1664
1665 static const unsigned int can1_data_c_pins[] = {
1666         /* TX, RX */
1667         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1668 };
1669
1670 static const unsigned int can1_data_c_mux[] = {
1671         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1672 };
1673
1674 static const unsigned int can1_data_d_pins[] = {
1675         /* TX, RX */
1676         RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1677 };
1678
1679 static const unsigned int can1_data_d_mux[] = {
1680         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1681 };
1682
1683 static const unsigned int can_clk_pins[] = {
1684         /* CLK */
1685         RCAR_GP_PIN(3, 31),
1686 };
1687
1688 static const unsigned int can_clk_mux[] = {
1689         CAN_CLK_MARK,
1690 };
1691
1692 static const unsigned int can_clk_b_pins[] = {
1693         /* CLK */
1694         RCAR_GP_PIN(1, 23),
1695 };
1696
1697 static const unsigned int can_clk_b_mux[] = {
1698         CAN_CLK_B_MARK,
1699 };
1700
1701 static const unsigned int can_clk_c_pins[] = {
1702         /* CLK */
1703         RCAR_GP_PIN(1, 0),
1704 };
1705
1706 static const unsigned int can_clk_c_mux[] = {
1707         CAN_CLK_C_MARK,
1708 };
1709
1710 static const unsigned int can_clk_d_pins[] = {
1711         /* CLK */
1712         RCAR_GP_PIN(5, 0),
1713 };
1714
1715 static const unsigned int can_clk_d_mux[] = {
1716         CAN_CLK_D_MARK,
1717 };
1718
1719 /* - DU --------------------------------------------------------------------- */
1720 static const unsigned int du0_rgb666_pins[] = {
1721         /* R[7:2], G[7:2], B[7:2] */
1722         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1723         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1724         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1725         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1726         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1727         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1728 };
1729 static const unsigned int du0_rgb666_mux[] = {
1730         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1731         DU0_DR3_MARK, DU0_DR2_MARK,
1732         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1733         DU0_DG3_MARK, DU0_DG2_MARK,
1734         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1735         DU0_DB3_MARK, DU0_DB2_MARK,
1736 };
1737 static const unsigned int du0_rgb888_pins[] = {
1738         /* R[7:0], G[7:0], B[7:0] */
1739         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1740         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1741         RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
1742         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1743         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1744         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
1745         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1746         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1747         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1748 };
1749 static const unsigned int du0_rgb888_mux[] = {
1750         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1751         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1752         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1753         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1754         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1755         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1756 };
1757 static const unsigned int du0_clk0_out_pins[] = {
1758         /* DOTCLKOUT0 */
1759         RCAR_GP_PIN(2, 25),
1760 };
1761 static const unsigned int du0_clk0_out_mux[] = {
1762         DU0_DOTCLKOUT0_MARK
1763 };
1764 static const unsigned int du0_clk1_out_pins[] = {
1765         /* DOTCLKOUT1 */
1766         RCAR_GP_PIN(2, 26),
1767 };
1768 static const unsigned int du0_clk1_out_mux[] = {
1769         DU0_DOTCLKOUT1_MARK
1770 };
1771 static const unsigned int du0_clk_in_pins[] = {
1772         /* CLKIN */
1773         RCAR_GP_PIN(2, 24),
1774 };
1775 static const unsigned int du0_clk_in_mux[] = {
1776         DU0_DOTCLKIN_MARK
1777 };
1778 static const unsigned int du0_sync_pins[] = {
1779         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1780         RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1781 };
1782 static const unsigned int du0_sync_mux[] = {
1783         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1784 };
1785 static const unsigned int du0_oddf_pins[] = {
1786         /* EXODDF/ODDF/DISP/CDE */
1787         RCAR_GP_PIN(2, 29),
1788 };
1789 static const unsigned int du0_oddf_mux[] = {
1790         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1791 };
1792 static const unsigned int du0_cde_pins[] = {
1793         /* CDE */
1794         RCAR_GP_PIN(2, 31),
1795 };
1796 static const unsigned int du0_cde_mux[] = {
1797         DU0_CDE_MARK,
1798 };
1799 static const unsigned int du0_disp_pins[] = {
1800         /* DISP */
1801         RCAR_GP_PIN(2, 30),
1802 };
1803 static const unsigned int du0_disp_mux[] = {
1804         DU0_DISP_MARK
1805 };
1806 static const unsigned int du1_rgb666_pins[] = {
1807         /* R[7:2], G[7:2], B[7:2] */
1808         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1809         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1810         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1811         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1812         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1813         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1814 };
1815 static const unsigned int du1_rgb666_mux[] = {
1816         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1817         DU1_DR3_MARK, DU1_DR2_MARK,
1818         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1819         DU1_DG3_MARK, DU1_DG2_MARK,
1820         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1821         DU1_DB3_MARK, DU1_DB2_MARK,
1822 };
1823 static const unsigned int du1_rgb888_pins[] = {
1824         /* R[7:0], G[7:0], B[7:0] */
1825         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1826         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1827         RCAR_GP_PIN(4, 1),  RCAR_GP_PIN(4, 0),
1828         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1829         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1830         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),
1831         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1832         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1833         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1834 };
1835 static const unsigned int du1_rgb888_mux[] = {
1836         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1837         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1838         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1839         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1840         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1841         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1842 };
1843 static const unsigned int du1_clk0_out_pins[] = {
1844         /* DOTCLKOUT0 */
1845         RCAR_GP_PIN(4, 25),
1846 };
1847 static const unsigned int du1_clk0_out_mux[] = {
1848         DU1_DOTCLKOUT0_MARK
1849 };
1850 static const unsigned int du1_clk1_out_pins[] = {
1851         /* DOTCLKOUT1 */
1852         RCAR_GP_PIN(4, 26),
1853 };
1854 static const unsigned int du1_clk1_out_mux[] = {
1855         DU1_DOTCLKOUT1_MARK
1856 };
1857 static const unsigned int du1_clk_in_pins[] = {
1858         /* DOTCLKIN */
1859         RCAR_GP_PIN(4, 24),
1860 };
1861 static const unsigned int du1_clk_in_mux[] = {
1862         DU1_DOTCLKIN_MARK
1863 };
1864 static const unsigned int du1_sync_pins[] = {
1865         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1866         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1867 };
1868 static const unsigned int du1_sync_mux[] = {
1869         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1870 };
1871 static const unsigned int du1_oddf_pins[] = {
1872         /* EXODDF/ODDF/DISP/CDE */
1873         RCAR_GP_PIN(4, 29),
1874 };
1875 static const unsigned int du1_oddf_mux[] = {
1876         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1877 };
1878 static const unsigned int du1_cde_pins[] = {
1879         /* CDE */
1880         RCAR_GP_PIN(4, 31),
1881 };
1882 static const unsigned int du1_cde_mux[] = {
1883         DU1_CDE_MARK
1884 };
1885 static const unsigned int du1_disp_pins[] = {
1886         /* DISP */
1887         RCAR_GP_PIN(4, 30),
1888 };
1889 static const unsigned int du1_disp_mux[] = {
1890         DU1_DISP_MARK
1891 };
1892 /* - ETH -------------------------------------------------------------------- */
1893 static const unsigned int eth_link_pins[] = {
1894         /* LINK */
1895         RCAR_GP_PIN(3, 18),
1896 };
1897 static const unsigned int eth_link_mux[] = {
1898         ETH_LINK_MARK,
1899 };
1900 static const unsigned int eth_magic_pins[] = {
1901         /* MAGIC */
1902         RCAR_GP_PIN(3, 22),
1903 };
1904 static const unsigned int eth_magic_mux[] = {
1905         ETH_MAGIC_MARK,
1906 };
1907 static const unsigned int eth_mdio_pins[] = {
1908         /* MDC, MDIO */
1909         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1910 };
1911 static const unsigned int eth_mdio_mux[] = {
1912         ETH_MDC_MARK, ETH_MDIO_MARK,
1913 };
1914 static const unsigned int eth_rmii_pins[] = {
1915         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1916         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1917         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1918         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1919 };
1920 static const unsigned int eth_rmii_mux[] = {
1921         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1922         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1923 };
1924 static const unsigned int eth_link_b_pins[] = {
1925         /* LINK */
1926         RCAR_GP_PIN(5, 15),
1927 };
1928 static const unsigned int eth_link_b_mux[] = {
1929         ETH_LINK_B_MARK,
1930 };
1931 static const unsigned int eth_magic_b_pins[] = {
1932         /* MAGIC */
1933         RCAR_GP_PIN(5, 19),
1934 };
1935 static const unsigned int eth_magic_b_mux[] = {
1936         ETH_MAGIC_B_MARK,
1937 };
1938 static const unsigned int eth_mdio_b_pins[] = {
1939         /* MDC, MDIO */
1940         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1941 };
1942 static const unsigned int eth_mdio_b_mux[] = {
1943         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1944 };
1945 static const unsigned int eth_rmii_b_pins[] = {
1946         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1947         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1948         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1949         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1950 };
1951 static const unsigned int eth_rmii_b_mux[] = {
1952         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1953         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1954 };
1955 /* - HSCIF0 ----------------------------------------------------------------- */
1956 static const unsigned int hscif0_data_pins[] = {
1957         /* RX, TX */
1958         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1959 };
1960 static const unsigned int hscif0_data_mux[] = {
1961         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1962 };
1963 static const unsigned int hscif0_clk_pins[] = {
1964         /* SCK */
1965         RCAR_GP_PIN(3, 29),
1966 };
1967 static const unsigned int hscif0_clk_mux[] = {
1968         HSCIF0_HSCK_MARK,
1969 };
1970 static const unsigned int hscif0_ctrl_pins[] = {
1971         /* RTS, CTS */
1972         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1973 };
1974 static const unsigned int hscif0_ctrl_mux[] = {
1975         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1976 };
1977 static const unsigned int hscif0_data_b_pins[] = {
1978         /* RX, TX */
1979         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1980 };
1981 static const unsigned int hscif0_data_b_mux[] = {
1982         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1983 };
1984 static const unsigned int hscif0_clk_b_pins[] = {
1985         /* SCK */
1986         RCAR_GP_PIN(1, 0),
1987 };
1988 static const unsigned int hscif0_clk_b_mux[] = {
1989         HSCIF0_HSCK_B_MARK,
1990 };
1991 /* - HSCIF1 ----------------------------------------------------------------- */
1992 static const unsigned int hscif1_data_pins[] = {
1993         /* RX, TX */
1994         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1995 };
1996 static const unsigned int hscif1_data_mux[] = {
1997         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1998 };
1999 static const unsigned int hscif1_clk_pins[] = {
2000         /* SCK */
2001         RCAR_GP_PIN(4, 10),
2002 };
2003 static const unsigned int hscif1_clk_mux[] = {
2004         HSCIF1_HSCK_MARK,
2005 };
2006 static const unsigned int hscif1_ctrl_pins[] = {
2007         /* RTS, CTS */
2008         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2009 };
2010 static const unsigned int hscif1_ctrl_mux[] = {
2011         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
2012 };
2013 static const unsigned int hscif1_data_b_pins[] = {
2014         /* RX, TX */
2015         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2016 };
2017 static const unsigned int hscif1_data_b_mux[] = {
2018         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
2019 };
2020 static const unsigned int hscif1_ctrl_b_pins[] = {
2021         /* RTS, CTS */
2022         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2023 };
2024 static const unsigned int hscif1_ctrl_b_mux[] = {
2025         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
2026 };
2027 /* - HSCIF2 ----------------------------------------------------------------- */
2028 static const unsigned int hscif2_data_pins[] = {
2029         /* RX, TX */
2030         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2031 };
2032 static const unsigned int hscif2_data_mux[] = {
2033         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
2034 };
2035 static const unsigned int hscif2_clk_pins[] = {
2036         /* SCK */
2037         RCAR_GP_PIN(0, 10),
2038 };
2039 static const unsigned int hscif2_clk_mux[] = {
2040         HSCIF2_HSCK_MARK,
2041 };
2042 static const unsigned int hscif2_ctrl_pins[] = {
2043         /* RTS, CTS */
2044         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2045 };
2046 static const unsigned int hscif2_ctrl_mux[] = {
2047         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
2048 };
2049 /* - I2C0 ------------------------------------------------------------------- */
2050 static const unsigned int i2c0_pins[] = {
2051         /* SCL, SDA */
2052         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2053 };
2054 static const unsigned int i2c0_mux[] = {
2055         I2C0_SCL_MARK, I2C0_SDA_MARK,
2056 };
2057 static const unsigned int i2c0_b_pins[] = {
2058         /* SCL, SDA */
2059         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2060 };
2061 static const unsigned int i2c0_b_mux[] = {
2062         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2063 };
2064 static const unsigned int i2c0_c_pins[] = {
2065         /* SCL, SDA */
2066         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2067 };
2068 static const unsigned int i2c0_c_mux[] = {
2069         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2070 };
2071 static const unsigned int i2c0_d_pins[] = {
2072         /* SCL, SDA */
2073         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2074 };
2075 static const unsigned int i2c0_d_mux[] = {
2076         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
2077 };
2078 static const unsigned int i2c0_e_pins[] = {
2079         /* SCL, SDA */
2080         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2081 };
2082 static const unsigned int i2c0_e_mux[] = {
2083         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
2084 };
2085 /* - I2C1 ------------------------------------------------------------------- */
2086 static const unsigned int i2c1_pins[] = {
2087         /* SCL, SDA */
2088         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2089 };
2090 static const unsigned int i2c1_mux[] = {
2091         I2C1_SCL_MARK, I2C1_SDA_MARK,
2092 };
2093 static const unsigned int i2c1_b_pins[] = {
2094         /* SCL, SDA */
2095         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2096 };
2097 static const unsigned int i2c1_b_mux[] = {
2098         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2099 };
2100 static const unsigned int i2c1_c_pins[] = {
2101         /* SCL, SDA */
2102         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2103 };
2104 static const unsigned int i2c1_c_mux[] = {
2105         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2106 };
2107 static const unsigned int i2c1_d_pins[] = {
2108         /* SCL, SDA */
2109         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2110 };
2111 static const unsigned int i2c1_d_mux[] = {
2112         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2113 };
2114 static const unsigned int i2c1_e_pins[] = {
2115         /* SCL, SDA */
2116         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2117 };
2118 static const unsigned int i2c1_e_mux[] = {
2119         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2120 };
2121 /* - I2C2 ------------------------------------------------------------------- */
2122 static const unsigned int i2c2_pins[] = {
2123         /* SCL, SDA */
2124         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2125 };
2126 static const unsigned int i2c2_mux[] = {
2127         I2C2_SCL_MARK, I2C2_SDA_MARK,
2128 };
2129 static const unsigned int i2c2_b_pins[] = {
2130         /* SCL, SDA */
2131         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2132 };
2133 static const unsigned int i2c2_b_mux[] = {
2134         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2135 };
2136 static const unsigned int i2c2_c_pins[] = {
2137         /* SCL, SDA */
2138         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2139 };
2140 static const unsigned int i2c2_c_mux[] = {
2141         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2142 };
2143 static const unsigned int i2c2_d_pins[] = {
2144         /* SCL, SDA */
2145         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2146 };
2147 static const unsigned int i2c2_d_mux[] = {
2148         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2149 };
2150 static const unsigned int i2c2_e_pins[] = {
2151         /* SCL, SDA */
2152         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2153 };
2154 static const unsigned int i2c2_e_mux[] = {
2155         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2156 };
2157 /* - I2C3 ------------------------------------------------------------------- */
2158 static const unsigned int i2c3_pins[] = {
2159         /* SCL, SDA */
2160         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2161 };
2162 static const unsigned int i2c3_mux[] = {
2163         I2C3_SCL_MARK, I2C3_SDA_MARK,
2164 };
2165 static const unsigned int i2c3_b_pins[] = {
2166         /* SCL, SDA */
2167         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2168 };
2169 static const unsigned int i2c3_b_mux[] = {
2170         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2171 };
2172 static const unsigned int i2c3_c_pins[] = {
2173         /* SCL, SDA */
2174         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2175 };
2176 static const unsigned int i2c3_c_mux[] = {
2177         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2178 };
2179 static const unsigned int i2c3_d_pins[] = {
2180         /* SCL, SDA */
2181         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2182 };
2183 static const unsigned int i2c3_d_mux[] = {
2184         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2185 };
2186 static const unsigned int i2c3_e_pins[] = {
2187         /* SCL, SDA */
2188         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2189 };
2190 static const unsigned int i2c3_e_mux[] = {
2191         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2192 };
2193 /* - I2C4 ------------------------------------------------------------------- */
2194 static const unsigned int i2c4_pins[] = {
2195         /* SCL, SDA */
2196         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2197 };
2198 static const unsigned int i2c4_mux[] = {
2199         I2C4_SCL_MARK, I2C4_SDA_MARK,
2200 };
2201 static const unsigned int i2c4_b_pins[] = {
2202         /* SCL, SDA */
2203         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2204 };
2205 static const unsigned int i2c4_b_mux[] = {
2206         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2207 };
2208 static const unsigned int i2c4_c_pins[] = {
2209         /* SCL, SDA */
2210         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2211 };
2212 static const unsigned int i2c4_c_mux[] = {
2213         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2214 };
2215 static const unsigned int i2c4_d_pins[] = {
2216         /* SCL, SDA */
2217         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2218 };
2219 static const unsigned int i2c4_d_mux[] = {
2220         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2221 };
2222 static const unsigned int i2c4_e_pins[] = {
2223         /* SCL, SDA */
2224         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2225 };
2226 static const unsigned int i2c4_e_mux[] = {
2227         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2228 };
2229 /* - I2C5 ------------------------------------------------------------------- */
2230 static const unsigned int i2c5_pins[] = {
2231         /* SCL, SDA */
2232         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2233 };
2234 static const unsigned int i2c5_mux[] = {
2235         I2C5_SCL_MARK, I2C5_SDA_MARK,
2236 };
2237 static const unsigned int i2c5_b_pins[] = {
2238         /* SCL, SDA */
2239         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2240 };
2241 static const unsigned int i2c5_b_mux[] = {
2242         I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
2243 };
2244 static const unsigned int i2c5_c_pins[] = {
2245         /* SCL, SDA */
2246         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2247 };
2248 static const unsigned int i2c5_c_mux[] = {
2249         I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
2250 };
2251 static const unsigned int i2c5_d_pins[] = {
2252         /* SCL, SDA */
2253         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2254 };
2255 static const unsigned int i2c5_d_mux[] = {
2256         I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
2257 };
2258 /* - INTC ------------------------------------------------------------------- */
2259 static const unsigned int intc_irq0_pins[] = {
2260         /* IRQ0 */
2261         RCAR_GP_PIN(4, 4),
2262 };
2263 static const unsigned int intc_irq0_mux[] = {
2264         IRQ0_MARK,
2265 };
2266 static const unsigned int intc_irq1_pins[] = {
2267         /* IRQ1 */
2268         RCAR_GP_PIN(4, 18),
2269 };
2270 static const unsigned int intc_irq1_mux[] = {
2271         IRQ1_MARK,
2272 };
2273 static const unsigned int intc_irq2_pins[] = {
2274         /* IRQ2 */
2275         RCAR_GP_PIN(4, 19),
2276 };
2277 static const unsigned int intc_irq2_mux[] = {
2278         IRQ2_MARK,
2279 };
2280 static const unsigned int intc_irq3_pins[] = {
2281         /* IRQ3 */
2282         RCAR_GP_PIN(0, 7),
2283 };
2284 static const unsigned int intc_irq3_mux[] = {
2285         IRQ3_MARK,
2286 };
2287 static const unsigned int intc_irq4_pins[] = {
2288         /* IRQ4 */
2289         RCAR_GP_PIN(0, 0),
2290 };
2291 static const unsigned int intc_irq4_mux[] = {
2292         IRQ4_MARK,
2293 };
2294 static const unsigned int intc_irq5_pins[] = {
2295         /* IRQ5 */
2296         RCAR_GP_PIN(4, 1),
2297 };
2298 static const unsigned int intc_irq5_mux[] = {
2299         IRQ5_MARK,
2300 };
2301 static const unsigned int intc_irq6_pins[] = {
2302         /* IRQ6 */
2303         RCAR_GP_PIN(0, 10),
2304 };
2305 static const unsigned int intc_irq6_mux[] = {
2306         IRQ6_MARK,
2307 };
2308 static const unsigned int intc_irq7_pins[] = {
2309         /* IRQ7 */
2310         RCAR_GP_PIN(6, 15),
2311 };
2312 static const unsigned int intc_irq7_mux[] = {
2313         IRQ7_MARK,
2314 };
2315 static const unsigned int intc_irq8_pins[] = {
2316         /* IRQ8 */
2317         RCAR_GP_PIN(5, 0),
2318 };
2319 static const unsigned int intc_irq8_mux[] = {
2320         IRQ8_MARK,
2321 };
2322 static const unsigned int intc_irq9_pins[] = {
2323         /* IRQ9 */
2324         RCAR_GP_PIN(5, 10),
2325 };
2326 static const unsigned int intc_irq9_mux[] = {
2327         IRQ9_MARK,
2328 };
2329 /* - MMCIF ------------------------------------------------------------------ */
2330 static const unsigned int mmc_data1_pins[] = {
2331         /* D[0] */
2332         RCAR_GP_PIN(6, 18),
2333 };
2334 static const unsigned int mmc_data1_mux[] = {
2335         MMC_D0_MARK,
2336 };
2337 static const unsigned int mmc_data4_pins[] = {
2338         /* D[0:3] */
2339         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2340         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2341 };
2342 static const unsigned int mmc_data4_mux[] = {
2343         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2344 };
2345 static const unsigned int mmc_data8_pins[] = {
2346         /* D[0:7] */
2347         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2348         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2349         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2350         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2351 };
2352 static const unsigned int mmc_data8_mux[] = {
2353         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2354         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2355 };
2356 static const unsigned int mmc_ctrl_pins[] = {
2357         /* CLK, CMD */
2358         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2359 };
2360 static const unsigned int mmc_ctrl_mux[] = {
2361         MMC_CLK_MARK, MMC_CMD_MARK,
2362 };
2363 /* - MSIOF0 ----------------------------------------------------------------- */
2364 static const unsigned int msiof0_clk_pins[] = {
2365         /* SCK */
2366         RCAR_GP_PIN(4, 4),
2367 };
2368 static const unsigned int msiof0_clk_mux[] = {
2369         MSIOF0_SCK_MARK,
2370 };
2371 static const unsigned int msiof0_sync_pins[] = {
2372         /* SYNC */
2373         RCAR_GP_PIN(4, 5),
2374 };
2375 static const unsigned int msiof0_sync_mux[] = {
2376         MSIOF0_SYNC_MARK,
2377 };
2378 static const unsigned int msiof0_ss1_pins[] = {
2379         /* SS1 */
2380         RCAR_GP_PIN(4, 6),
2381 };
2382 static const unsigned int msiof0_ss1_mux[] = {
2383         MSIOF0_SS1_MARK,
2384 };
2385 static const unsigned int msiof0_ss2_pins[] = {
2386         /* SS2 */
2387         RCAR_GP_PIN(4, 7),
2388 };
2389 static const unsigned int msiof0_ss2_mux[] = {
2390         MSIOF0_SS2_MARK,
2391 };
2392 static const unsigned int msiof0_rx_pins[] = {
2393         /* RXD */
2394         RCAR_GP_PIN(4, 2),
2395 };
2396 static const unsigned int msiof0_rx_mux[] = {
2397         MSIOF0_RXD_MARK,
2398 };
2399 static const unsigned int msiof0_tx_pins[] = {
2400         /* TXD */
2401         RCAR_GP_PIN(4, 3),
2402 };
2403 static const unsigned int msiof0_tx_mux[] = {
2404         MSIOF0_TXD_MARK,
2405 };
2406 /* - MSIOF1 ----------------------------------------------------------------- */
2407 static const unsigned int msiof1_clk_pins[] = {
2408         /* SCK */
2409         RCAR_GP_PIN(0, 26),
2410 };
2411 static const unsigned int msiof1_clk_mux[] = {
2412         MSIOF1_SCK_MARK,
2413 };
2414 static const unsigned int msiof1_sync_pins[] = {
2415         /* SYNC */
2416         RCAR_GP_PIN(0, 27),
2417 };
2418 static const unsigned int msiof1_sync_mux[] = {
2419         MSIOF1_SYNC_MARK,
2420 };
2421 static const unsigned int msiof1_ss1_pins[] = {
2422         /* SS1 */
2423         RCAR_GP_PIN(0, 28),
2424 };
2425 static const unsigned int msiof1_ss1_mux[] = {
2426         MSIOF1_SS1_MARK,
2427 };
2428 static const unsigned int msiof1_ss2_pins[] = {
2429         /* SS2 */
2430         RCAR_GP_PIN(0, 29),
2431 };
2432 static const unsigned int msiof1_ss2_mux[] = {
2433         MSIOF1_SS2_MARK,
2434 };
2435 static const unsigned int msiof1_rx_pins[] = {
2436         /* RXD */
2437         RCAR_GP_PIN(0, 24),
2438 };
2439 static const unsigned int msiof1_rx_mux[] = {
2440         MSIOF1_RXD_MARK,
2441 };
2442 static const unsigned int msiof1_tx_pins[] = {
2443         /* TXD */
2444         RCAR_GP_PIN(0, 25),
2445 };
2446 static const unsigned int msiof1_tx_mux[] = {
2447         MSIOF1_TXD_MARK,
2448 };
2449 static const unsigned int msiof1_clk_b_pins[] = {
2450         /* SCK */
2451         RCAR_GP_PIN(5, 3),
2452 };
2453 static const unsigned int msiof1_clk_b_mux[] = {
2454         MSIOF1_SCK_B_MARK,
2455 };
2456 static const unsigned int msiof1_sync_b_pins[] = {
2457         /* SYNC */
2458         RCAR_GP_PIN(5, 4),
2459 };
2460 static const unsigned int msiof1_sync_b_mux[] = {
2461         MSIOF1_SYNC_B_MARK,
2462 };
2463 static const unsigned int msiof1_ss1_b_pins[] = {
2464         /* SS1 */
2465         RCAR_GP_PIN(5, 5),
2466 };
2467 static const unsigned int msiof1_ss1_b_mux[] = {
2468         MSIOF1_SS1_B_MARK,
2469 };
2470 static const unsigned int msiof1_ss2_b_pins[] = {
2471         /* SS2 */
2472         RCAR_GP_PIN(5, 6),
2473 };
2474 static const unsigned int msiof1_ss2_b_mux[] = {
2475         MSIOF1_SS2_B_MARK,
2476 };
2477 static const unsigned int msiof1_rx_b_pins[] = {
2478         /* RXD */
2479         RCAR_GP_PIN(5, 1),
2480 };
2481 static const unsigned int msiof1_rx_b_mux[] = {
2482         MSIOF1_RXD_B_MARK,
2483 };
2484 static const unsigned int msiof1_tx_b_pins[] = {
2485         /* TXD */
2486         RCAR_GP_PIN(5, 2),
2487 };
2488 static const unsigned int msiof1_tx_b_mux[] = {
2489         MSIOF1_TXD_B_MARK,
2490 };
2491 /* - MSIOF2 ----------------------------------------------------------------- */
2492 static const unsigned int msiof2_clk_pins[] = {
2493         /* SCK */
2494         RCAR_GP_PIN(1, 0),
2495 };
2496 static const unsigned int msiof2_clk_mux[] = {
2497         MSIOF2_SCK_MARK,
2498 };
2499 static const unsigned int msiof2_sync_pins[] = {
2500         /* SYNC */
2501         RCAR_GP_PIN(1, 1),
2502 };
2503 static const unsigned int msiof2_sync_mux[] = {
2504         MSIOF2_SYNC_MARK,
2505 };
2506 static const unsigned int msiof2_ss1_pins[] = {
2507         /* SS1 */
2508         RCAR_GP_PIN(1, 2),
2509 };
2510 static const unsigned int msiof2_ss1_mux[] = {
2511         MSIOF2_SS1_MARK,
2512 };
2513 static const unsigned int msiof2_ss2_pins[] = {
2514         /* SS2 */
2515         RCAR_GP_PIN(1, 3),
2516 };
2517 static const unsigned int msiof2_ss2_mux[] = {
2518         MSIOF2_SS2_MARK,
2519 };
2520 static const unsigned int msiof2_rx_pins[] = {
2521         /* RXD */
2522         RCAR_GP_PIN(0, 30),
2523 };
2524 static const unsigned int msiof2_rx_mux[] = {
2525         MSIOF2_RXD_MARK,
2526 };
2527 static const unsigned int msiof2_tx_pins[] = {
2528         /* TXD */
2529         RCAR_GP_PIN(0, 31),
2530 };
2531 static const unsigned int msiof2_tx_mux[] = {
2532         MSIOF2_TXD_MARK,
2533 };
2534 static const unsigned int msiof2_clk_b_pins[] = {
2535         /* SCK */
2536         RCAR_GP_PIN(3, 15),
2537 };
2538 static const unsigned int msiof2_clk_b_mux[] = {
2539         MSIOF2_SCK_B_MARK,
2540 };
2541 static const unsigned int msiof2_sync_b_pins[] = {
2542         /* SYNC */
2543         RCAR_GP_PIN(3, 16),
2544 };
2545 static const unsigned int msiof2_sync_b_mux[] = {
2546         MSIOF2_SYNC_B_MARK,
2547 };
2548 static const unsigned int msiof2_ss1_b_pins[] = {
2549         /* SS1 */
2550         RCAR_GP_PIN(3, 17),
2551 };
2552 static const unsigned int msiof2_ss1_b_mux[] = {
2553         MSIOF2_SS1_B_MARK,
2554 };
2555 static const unsigned int msiof2_ss2_b_pins[] = {
2556         /* SS2 */
2557         RCAR_GP_PIN(3, 18),
2558 };
2559 static const unsigned int msiof2_ss2_b_mux[] = {
2560         MSIOF2_SS2_B_MARK,
2561 };
2562 static const unsigned int msiof2_rx_b_pins[] = {
2563         /* RXD */
2564         RCAR_GP_PIN(3, 13),
2565 };
2566 static const unsigned int msiof2_rx_b_mux[] = {
2567         MSIOF2_RXD_B_MARK,
2568 };
2569 static const unsigned int msiof2_tx_b_pins[] = {
2570         /* TXD */
2571         RCAR_GP_PIN(3, 14),
2572 };
2573 static const unsigned int msiof2_tx_b_mux[] = {
2574         MSIOF2_TXD_B_MARK,
2575 };
2576 /* - PWM -------------------------------------------------------------------- */
2577 static const unsigned int pwm0_pins[] = {
2578         RCAR_GP_PIN(1, 14),
2579 };
2580 static const unsigned int pwm0_mux[] = {
2581         PWM0_MARK,
2582 };
2583 static const unsigned int pwm0_b_pins[] = {
2584         RCAR_GP_PIN(5, 3),
2585 };
2586 static const unsigned int pwm0_b_mux[] = {
2587         PWM0_B_MARK,
2588 };
2589 static const unsigned int pwm1_pins[] = {
2590         RCAR_GP_PIN(4, 5),
2591 };
2592 static const unsigned int pwm1_mux[] = {
2593         PWM1_MARK,
2594 };
2595 static const unsigned int pwm1_b_pins[] = {
2596         RCAR_GP_PIN(5, 10),
2597 };
2598 static const unsigned int pwm1_b_mux[] = {
2599         PWM1_B_MARK,
2600 };
2601 static const unsigned int pwm1_c_pins[] = {
2602         RCAR_GP_PIN(1, 18),
2603 };
2604 static const unsigned int pwm1_c_mux[] = {
2605         PWM1_C_MARK,
2606 };
2607 static const unsigned int pwm2_pins[] = {
2608         RCAR_GP_PIN(4, 10),
2609 };
2610 static const unsigned int pwm2_mux[] = {
2611         PWM2_MARK,
2612 };
2613 static const unsigned int pwm2_b_pins[] = {
2614         RCAR_GP_PIN(5, 17),
2615 };
2616 static const unsigned int pwm2_b_mux[] = {
2617         PWM2_B_MARK,
2618 };
2619 static const unsigned int pwm2_c_pins[] = {
2620         RCAR_GP_PIN(0, 13),
2621 };
2622 static const unsigned int pwm2_c_mux[] = {
2623         PWM2_C_MARK,
2624 };
2625 static const unsigned int pwm3_pins[] = {
2626         RCAR_GP_PIN(4, 13),
2627 };
2628 static const unsigned int pwm3_mux[] = {
2629         PWM3_MARK,
2630 };
2631 static const unsigned int pwm3_b_pins[] = {
2632         RCAR_GP_PIN(0, 16),
2633 };
2634 static const unsigned int pwm3_b_mux[] = {
2635         PWM3_B_MARK,
2636 };
2637 static const unsigned int pwm4_pins[] = {
2638         RCAR_GP_PIN(1, 3),
2639 };
2640 static const unsigned int pwm4_mux[] = {
2641         PWM4_MARK,
2642 };
2643 static const unsigned int pwm4_b_pins[] = {
2644         RCAR_GP_PIN(0, 21),
2645 };
2646 static const unsigned int pwm4_b_mux[] = {
2647         PWM4_B_MARK,
2648 };
2649 static const unsigned int pwm5_pins[] = {
2650         RCAR_GP_PIN(3, 30),
2651 };
2652 static const unsigned int pwm5_mux[] = {
2653         PWM5_MARK,
2654 };
2655 static const unsigned int pwm5_b_pins[] = {
2656         RCAR_GP_PIN(4, 0),
2657 };
2658 static const unsigned int pwm5_b_mux[] = {
2659         PWM5_B_MARK,
2660 };
2661 static const unsigned int pwm5_c_pins[] = {
2662         RCAR_GP_PIN(0, 10),
2663 };
2664 static const unsigned int pwm5_c_mux[] = {
2665         PWM5_C_MARK,
2666 };
2667 static const unsigned int pwm6_pins[] = {
2668         RCAR_GP_PIN(4, 8),
2669 };
2670 static const unsigned int pwm6_mux[] = {
2671         PWM6_MARK,
2672 };
2673 static const unsigned int pwm6_b_pins[] = {
2674         RCAR_GP_PIN(0, 7),
2675 };
2676 static const unsigned int pwm6_b_mux[] = {
2677         PWM6_B_MARK,
2678 };
2679 /* - QSPI ------------------------------------------------------------------- */
2680 static const unsigned int qspi_ctrl_pins[] = {
2681         /* SPCLK, SSL */
2682         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2683 };
2684 static const unsigned int qspi_ctrl_mux[] = {
2685         SPCLK_MARK, SSL_MARK,
2686 };
2687 static const unsigned int qspi_data2_pins[] = {
2688         /* MOSI_IO0, MISO_IO1 */
2689         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2690 };
2691 static const unsigned int qspi_data2_mux[] = {
2692         MOSI_IO0_MARK, MISO_IO1_MARK,
2693 };
2694 static const unsigned int qspi_data4_pins[] = {
2695         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2696         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2697         RCAR_GP_PIN(1, 8),
2698 };
2699 static const unsigned int qspi_data4_mux[] = {
2700         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2701 };
2702 /* - SCIF0 ------------------------------------------------------------------ */
2703 static const unsigned int scif0_data_pins[] = {
2704         /* RX, TX */
2705         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2706 };
2707 static const unsigned int scif0_data_mux[] = {
2708         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2709 };
2710 static const unsigned int scif0_data_b_pins[] = {
2711         /* RX, TX */
2712         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2713 };
2714 static const unsigned int scif0_data_b_mux[] = {
2715         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2716 };
2717 static const unsigned int scif0_data_c_pins[] = {
2718         /* RX, TX */
2719         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2720 };
2721 static const unsigned int scif0_data_c_mux[] = {
2722         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2723 };
2724 static const unsigned int scif0_data_d_pins[] = {
2725         /* RX, TX */
2726         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2727 };
2728 static const unsigned int scif0_data_d_mux[] = {
2729         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2730 };
2731 /* - SCIF1 ------------------------------------------------------------------ */
2732 static const unsigned int scif1_data_pins[] = {
2733         /* RX, TX */
2734         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2735 };
2736 static const unsigned int scif1_data_mux[] = {
2737         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2738 };
2739 static const unsigned int scif1_clk_pins[] = {
2740         /* SCK */
2741         RCAR_GP_PIN(4, 13),
2742 };
2743 static const unsigned int scif1_clk_mux[] = {
2744         SCIF1_SCK_MARK,
2745 };
2746 static const unsigned int scif1_data_b_pins[] = {
2747         /* RX, TX */
2748         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2749 };
2750 static const unsigned int scif1_data_b_mux[] = {
2751         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2752 };
2753 static const unsigned int scif1_clk_b_pins[] = {
2754         /* SCK */
2755         RCAR_GP_PIN(5, 10),
2756 };
2757 static const unsigned int scif1_clk_b_mux[] = {
2758         SCIF1_SCK_B_MARK,
2759 };
2760 static const unsigned int scif1_data_c_pins[] = {
2761         /* RX, TX */
2762         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2763 };
2764 static const unsigned int scif1_data_c_mux[] = {
2765         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2766 };
2767 static const unsigned int scif1_clk_c_pins[] = {
2768         /* SCK */
2769         RCAR_GP_PIN(0, 10),
2770 };
2771 static const unsigned int scif1_clk_c_mux[] = {
2772         SCIF1_SCK_C_MARK,
2773 };
2774 /* - SCIF2 ------------------------------------------------------------------ */
2775 static const unsigned int scif2_data_pins[] = {
2776         /* RX, TX */
2777         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2778 };
2779 static const unsigned int scif2_data_mux[] = {
2780         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2781 };
2782 static const unsigned int scif2_clk_pins[] = {
2783         /* SCK */
2784         RCAR_GP_PIN(4, 18),
2785 };
2786 static const unsigned int scif2_clk_mux[] = {
2787         SCIF2_SCK_MARK,
2788 };
2789 static const unsigned int scif2_data_b_pins[] = {
2790         /* RX, TX */
2791         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2792 };
2793 static const unsigned int scif2_data_b_mux[] = {
2794         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2795 };
2796 static const unsigned int scif2_clk_b_pins[] = {
2797         /* SCK */
2798         RCAR_GP_PIN(5, 17),
2799 };
2800 static const unsigned int scif2_clk_b_mux[] = {
2801         SCIF2_SCK_B_MARK,
2802 };
2803 static const unsigned int scif2_data_c_pins[] = {
2804         /* RX, TX */
2805         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2806 };
2807 static const unsigned int scif2_data_c_mux[] = {
2808         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2809 };
2810 static const unsigned int scif2_clk_c_pins[] = {
2811         /* SCK */
2812         RCAR_GP_PIN(3, 19),
2813 };
2814 static const unsigned int scif2_clk_c_mux[] = {
2815         SCIF2_SCK_C_MARK,
2816 };
2817 /* - SCIF3 ------------------------------------------------------------------ */
2818 static const unsigned int scif3_data_pins[] = {
2819         /* RX, TX */
2820         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2821 };
2822 static const unsigned int scif3_data_mux[] = {
2823         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2824 };
2825 static const unsigned int scif3_clk_pins[] = {
2826         /* SCK */
2827         RCAR_GP_PIN(4, 19),
2828 };
2829 static const unsigned int scif3_clk_mux[] = {
2830         SCIF3_SCK_MARK,
2831 };
2832 static const unsigned int scif3_data_b_pins[] = {
2833         /* RX, TX */
2834         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2835 };
2836 static const unsigned int scif3_data_b_mux[] = {
2837         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2838 };
2839 static const unsigned int scif3_clk_b_pins[] = {
2840         /* SCK */
2841         RCAR_GP_PIN(3, 22),
2842 };
2843 static const unsigned int scif3_clk_b_mux[] = {
2844         SCIF3_SCK_B_MARK,
2845 };
2846 /* - SCIF4 ------------------------------------------------------------------ */
2847 static const unsigned int scif4_data_pins[] = {
2848         /* RX, TX */
2849         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2850 };
2851 static const unsigned int scif4_data_mux[] = {
2852         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2853 };
2854 static const unsigned int scif4_data_b_pins[] = {
2855         /* RX, TX */
2856         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2857 };
2858 static const unsigned int scif4_data_b_mux[] = {
2859         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2860 };
2861 static const unsigned int scif4_data_c_pins[] = {
2862         /* RX, TX */
2863         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2864 };
2865 static const unsigned int scif4_data_c_mux[] = {
2866         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2867 };
2868 static const unsigned int scif4_data_d_pins[] = {
2869         /* RX, TX */
2870         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2871 };
2872 static const unsigned int scif4_data_d_mux[] = {
2873         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2874 };
2875 static const unsigned int scif4_data_e_pins[] = {
2876         /* RX, TX */
2877         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2878 };
2879 static const unsigned int scif4_data_e_mux[] = {
2880         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2881 };
2882 /* - SCIF5 ------------------------------------------------------------------ */
2883 static const unsigned int scif5_data_pins[] = {
2884         /* RX, TX */
2885         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2886 };
2887 static const unsigned int scif5_data_mux[] = {
2888         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2889 };
2890 static const unsigned int scif5_data_b_pins[] = {
2891         /* RX, TX */
2892         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2893 };
2894 static const unsigned int scif5_data_b_mux[] = {
2895         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2896 };
2897 static const unsigned int scif5_data_c_pins[] = {
2898         /* RX, TX */
2899         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2900 };
2901 static const unsigned int scif5_data_c_mux[] = {
2902         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2903 };
2904 static const unsigned int scif5_data_d_pins[] = {
2905         /* RX, TX */
2906         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2907 };
2908 static const unsigned int scif5_data_d_mux[] = {
2909         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2910 };
2911 /* - SCIFA0 ----------------------------------------------------------------- */
2912 static const unsigned int scifa0_data_pins[] = {
2913         /* RXD, TXD */
2914         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2915 };
2916 static const unsigned int scifa0_data_mux[] = {
2917         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2918 };
2919 static const unsigned int scifa0_data_b_pins[] = {
2920         /* RXD, TXD */
2921         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2922 };
2923 static const unsigned int scifa0_data_b_mux[] = {
2924         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2925 };
2926 static const unsigned int scifa0_data_c_pins[] = {
2927         /* RXD, TXD */
2928         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2929 };
2930 static const unsigned int scifa0_data_c_mux[] = {
2931         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2932 };
2933 static const unsigned int scifa0_data_d_pins[] = {
2934         /* RXD, TXD */
2935         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2936 };
2937 static const unsigned int scifa0_data_d_mux[] = {
2938         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2939 };
2940 /* - SCIFA1 ----------------------------------------------------------------- */
2941 static const unsigned int scifa1_data_pins[] = {
2942         /* RXD, TXD */
2943         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2944 };
2945 static const unsigned int scifa1_data_mux[] = {
2946         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2947 };
2948 static const unsigned int scifa1_clk_pins[] = {
2949         /* SCK */
2950         RCAR_GP_PIN(0, 13),
2951 };
2952 static const unsigned int scifa1_clk_mux[] = {
2953         SCIFA1_SCK_MARK,
2954 };
2955 static const unsigned int scifa1_data_b_pins[] = {
2956         /* RXD, TXD */
2957         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2958 };
2959 static const unsigned int scifa1_data_b_mux[] = {
2960         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2961 };
2962 static const unsigned int scifa1_clk_b_pins[] = {
2963         /* SCK */
2964         RCAR_GP_PIN(4, 27),
2965 };
2966 static const unsigned int scifa1_clk_b_mux[] = {
2967         SCIFA1_SCK_B_MARK,
2968 };
2969 static const unsigned int scifa1_data_c_pins[] = {
2970         /* RXD, TXD */
2971         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2972 };
2973 static const unsigned int scifa1_data_c_mux[] = {
2974         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2975 };
2976 static const unsigned int scifa1_clk_c_pins[] = {
2977         /* SCK */
2978         RCAR_GP_PIN(5, 4),
2979 };
2980 static const unsigned int scifa1_clk_c_mux[] = {
2981         SCIFA1_SCK_C_MARK,
2982 };
2983 /* - SCIFA2 ----------------------------------------------------------------- */
2984 static const unsigned int scifa2_data_pins[] = {
2985         /* RXD, TXD */
2986         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2987 };
2988 static const unsigned int scifa2_data_mux[] = {
2989         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2990 };
2991 static const unsigned int scifa2_clk_pins[] = {
2992         /* SCK */
2993         RCAR_GP_PIN(1, 15),
2994 };
2995 static const unsigned int scifa2_clk_mux[] = {
2996         SCIFA2_SCK_MARK,
2997 };
2998 static const unsigned int scifa2_data_b_pins[] = {
2999         /* RXD, TXD */
3000         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
3001 };
3002 static const unsigned int scifa2_data_b_mux[] = {
3003         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3004 };
3005 static const unsigned int scifa2_clk_b_pins[] = {
3006         /* SCK */
3007         RCAR_GP_PIN(4, 30),
3008 };
3009 static const unsigned int scifa2_clk_b_mux[] = {
3010         SCIFA2_SCK_B_MARK,
3011 };
3012 /* - SCIFA3 ----------------------------------------------------------------- */
3013 static const unsigned int scifa3_data_pins[] = {
3014         /* RXD, TXD */
3015         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3016 };
3017 static const unsigned int scifa3_data_mux[] = {
3018         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3019 };
3020 static const unsigned int scifa3_clk_pins[] = {
3021         /* SCK */
3022         RCAR_GP_PIN(4, 24),
3023 };
3024 static const unsigned int scifa3_clk_mux[] = {
3025         SCIFA3_SCK_MARK,
3026 };
3027 static const unsigned int scifa3_data_b_pins[] = {
3028         /* RXD, TXD */
3029         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
3030 };
3031 static const unsigned int scifa3_data_b_mux[] = {
3032         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3033 };
3034 static const unsigned int scifa3_clk_b_pins[] = {
3035         /* SCK */
3036         RCAR_GP_PIN(0, 0),
3037 };
3038 static const unsigned int scifa3_clk_b_mux[] = {
3039         SCIFA3_SCK_B_MARK,
3040 };
3041 /* - SCIFA4 ----------------------------------------------------------------- */
3042 static const unsigned int scifa4_data_pins[] = {
3043         /* RXD, TXD */
3044         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
3045 };
3046 static const unsigned int scifa4_data_mux[] = {
3047         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3048 };
3049 static const unsigned int scifa4_data_b_pins[] = {
3050         /* RXD, TXD */
3051         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
3052 };
3053 static const unsigned int scifa4_data_b_mux[] = {
3054         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3055 };
3056 static const unsigned int scifa4_data_c_pins[] = {
3057         /* RXD, TXD */
3058         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3059 };
3060 static const unsigned int scifa4_data_c_mux[] = {
3061         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3062 };
3063 static const unsigned int scifa4_data_d_pins[] = {
3064         /* RXD, TXD */
3065         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3066 };
3067 static const unsigned int scifa4_data_d_mux[] = {
3068         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
3069 };
3070 /* - SCIFA5 ----------------------------------------------------------------- */
3071 static const unsigned int scifa5_data_pins[] = {
3072         /* RXD, TXD */
3073         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3074 };
3075 static const unsigned int scifa5_data_mux[] = {
3076         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3077 };
3078 static const unsigned int scifa5_data_b_pins[] = {
3079         /* RXD, TXD */
3080         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
3081 };
3082 static const unsigned int scifa5_data_b_mux[] = {
3083         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3084 };
3085 static const unsigned int scifa5_data_c_pins[] = {
3086         /* RXD, TXD */
3087         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
3088 };
3089 static const unsigned int scifa5_data_c_mux[] = {
3090         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3091 };
3092 static const unsigned int scifa5_data_d_pins[] = {
3093         /* RXD, TXD */
3094         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3095 };
3096 static const unsigned int scifa5_data_d_mux[] = {
3097         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
3098 };
3099 /* - SCIFB0 ----------------------------------------------------------------- */
3100 static const unsigned int scifb0_data_pins[] = {
3101         /* RXD, TXD */
3102         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
3103 };
3104 static const unsigned int scifb0_data_mux[] = {
3105         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3106 };
3107 static const unsigned int scifb0_clk_pins[] = {
3108         /* SCK */
3109         RCAR_GP_PIN(0, 19),
3110 };
3111 static const unsigned int scifb0_clk_mux[] = {
3112         SCIFB0_SCK_MARK,
3113 };
3114 static const unsigned int scifb0_ctrl_pins[] = {
3115         /* RTS, CTS */
3116         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
3117 };
3118 static const unsigned int scifb0_ctrl_mux[] = {
3119         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3120 };
3121 /* - SCIFB1 ----------------------------------------------------------------- */
3122 static const unsigned int scifb1_data_pins[] = {
3123         /* RXD, TXD */
3124         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
3125 };
3126 static const unsigned int scifb1_data_mux[] = {
3127         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3128 };
3129 static const unsigned int scifb1_clk_pins[] = {
3130         /* SCK */
3131         RCAR_GP_PIN(0, 16),
3132 };
3133 static const unsigned int scifb1_clk_mux[] = {
3134         SCIFB1_SCK_MARK,
3135 };
3136 /* - SCIFB2 ----------------------------------------------------------------- */
3137 static const unsigned int scifb2_data_pins[] = {
3138         /* RXD, TXD */
3139         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3140 };
3141 static const unsigned int scifb2_data_mux[] = {
3142         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3143 };
3144 static const unsigned int scifb2_clk_pins[] = {
3145         /* SCK */
3146         RCAR_GP_PIN(1, 15),
3147 };
3148 static const unsigned int scifb2_clk_mux[] = {
3149         SCIFB2_SCK_MARK,
3150 };
3151 static const unsigned int scifb2_ctrl_pins[] = {
3152         /* RTS, CTS */
3153         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
3154 };
3155 static const unsigned int scifb2_ctrl_mux[] = {
3156         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3157 };
3158 /* - SCIF Clock ------------------------------------------------------------- */
3159 static const unsigned int scif_clk_pins[] = {
3160         /* SCIF_CLK */
3161         RCAR_GP_PIN(1, 23),
3162 };
3163 static const unsigned int scif_clk_mux[] = {
3164         SCIF_CLK_MARK,
3165 };
3166 static const unsigned int scif_clk_b_pins[] = {
3167         /* SCIF_CLK */
3168         RCAR_GP_PIN(3, 29),
3169 };
3170 static const unsigned int scif_clk_b_mux[] = {
3171         SCIF_CLK_B_MARK,
3172 };
3173 /* - SDHI0 ------------------------------------------------------------------ */
3174 static const unsigned int sdhi0_data1_pins[] = {
3175         /* D0 */
3176         RCAR_GP_PIN(6, 2),
3177 };
3178 static const unsigned int sdhi0_data1_mux[] = {
3179         SD0_DATA0_MARK,
3180 };
3181 static const unsigned int sdhi0_data4_pins[] = {
3182         /* D[0:3] */
3183         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3184         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3185 };
3186 static const unsigned int sdhi0_data4_mux[] = {
3187         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3188 };
3189 static const unsigned int sdhi0_ctrl_pins[] = {
3190         /* CLK, CMD */
3191         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3192 };
3193 static const unsigned int sdhi0_ctrl_mux[] = {
3194         SD0_CLK_MARK, SD0_CMD_MARK,
3195 };
3196 static const unsigned int sdhi0_cd_pins[] = {
3197         /* CD */
3198         RCAR_GP_PIN(6, 6),
3199 };
3200 static const unsigned int sdhi0_cd_mux[] = {
3201         SD0_CD_MARK,
3202 };
3203 static const unsigned int sdhi0_wp_pins[] = {
3204         /* WP */
3205         RCAR_GP_PIN(6, 7),
3206 };
3207 static const unsigned int sdhi0_wp_mux[] = {
3208         SD0_WP_MARK,
3209 };
3210 /* - SDHI1 ------------------------------------------------------------------ */
3211 static const unsigned int sdhi1_data1_pins[] = {
3212         /* D0 */
3213         RCAR_GP_PIN(6, 10),
3214 };
3215 static const unsigned int sdhi1_data1_mux[] = {
3216         SD1_DATA0_MARK,
3217 };
3218 static const unsigned int sdhi1_data4_pins[] = {
3219         /* D[0:3] */
3220         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3221         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3222 };
3223 static const unsigned int sdhi1_data4_mux[] = {
3224         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3225 };
3226 static const unsigned int sdhi1_ctrl_pins[] = {
3227         /* CLK, CMD */
3228         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3229 };
3230 static const unsigned int sdhi1_ctrl_mux[] = {
3231         SD1_CLK_MARK, SD1_CMD_MARK,
3232 };
3233 static const unsigned int sdhi1_cd_pins[] = {
3234         /* CD */
3235         RCAR_GP_PIN(6, 14),
3236 };
3237 static const unsigned int sdhi1_cd_mux[] = {
3238         SD1_CD_MARK,
3239 };
3240 static const unsigned int sdhi1_wp_pins[] = {
3241         /* WP */
3242         RCAR_GP_PIN(6, 15),
3243 };
3244 static const unsigned int sdhi1_wp_mux[] = {
3245         SD1_WP_MARK,
3246 };
3247 /* - SDHI2 ------------------------------------------------------------------ */
3248 static const unsigned int sdhi2_data1_pins[] = {
3249         /* D0 */
3250         RCAR_GP_PIN(6, 18),
3251 };
3252 static const unsigned int sdhi2_data1_mux[] = {
3253         SD2_DATA0_MARK,
3254 };
3255 static const unsigned int sdhi2_data4_pins[] = {
3256         /* D[0:3] */
3257         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3258         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3259 };
3260 static const unsigned int sdhi2_data4_mux[] = {
3261         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3262 };
3263 static const unsigned int sdhi2_ctrl_pins[] = {
3264         /* CLK, CMD */
3265         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3266 };
3267 static const unsigned int sdhi2_ctrl_mux[] = {
3268         SD2_CLK_MARK, SD2_CMD_MARK,
3269 };
3270 static const unsigned int sdhi2_cd_pins[] = {
3271         /* CD */
3272         RCAR_GP_PIN(6, 22),
3273 };
3274 static const unsigned int sdhi2_cd_mux[] = {
3275         SD2_CD_MARK,
3276 };
3277 static const unsigned int sdhi2_wp_pins[] = {
3278         /* WP */
3279         RCAR_GP_PIN(6, 23),
3280 };
3281 static const unsigned int sdhi2_wp_mux[] = {
3282         SD2_WP_MARK,
3283 };
3284 /* - SSI -------------------------------------------------------------------- */
3285 static const unsigned int ssi0_data_pins[] = {
3286         /* SDATA0 */
3287         RCAR_GP_PIN(5, 3),
3288 };
3289 static const unsigned int ssi0_data_mux[] = {
3290         SSI_SDATA0_MARK,
3291 };
3292 static const unsigned int ssi0129_ctrl_pins[] = {
3293         /* SCK0129, WS0129 */
3294         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3295 };
3296 static const unsigned int ssi0129_ctrl_mux[] = {
3297         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3298 };
3299 static const unsigned int ssi1_data_pins[] = {
3300         /* SDATA1 */
3301         RCAR_GP_PIN(5, 13),
3302 };
3303 static const unsigned int ssi1_data_mux[] = {
3304         SSI_SDATA1_MARK,
3305 };
3306 static const unsigned int ssi1_ctrl_pins[] = {
3307         /* SCK1, WS1 */
3308         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3309 };
3310 static const unsigned int ssi1_ctrl_mux[] = {
3311         SSI_SCK1_MARK, SSI_WS1_MARK,
3312 };
3313 static const unsigned int ssi1_data_b_pins[] = {
3314         /* SDATA1 */
3315         RCAR_GP_PIN(4, 13),
3316 };
3317 static const unsigned int ssi1_data_b_mux[] = {
3318         SSI_SDATA1_B_MARK,
3319 };
3320 static const unsigned int ssi1_ctrl_b_pins[] = {
3321         /* SCK1, WS1 */
3322         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3323 };
3324 static const unsigned int ssi1_ctrl_b_mux[] = {
3325         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3326 };
3327 static const unsigned int ssi2_data_pins[] = {
3328         /* SDATA2 */
3329         RCAR_GP_PIN(5, 16),
3330 };
3331 static const unsigned int ssi2_data_mux[] = {
3332         SSI_SDATA2_MARK,
3333 };
3334 static const unsigned int ssi2_ctrl_pins[] = {
3335         /* SCK2, WS2 */
3336         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3337 };
3338 static const unsigned int ssi2_ctrl_mux[] = {
3339         SSI_SCK2_MARK, SSI_WS2_MARK,
3340 };
3341 static const unsigned int ssi2_data_b_pins[] = {
3342         /* SDATA2 */
3343         RCAR_GP_PIN(4, 16),
3344 };
3345 static const unsigned int ssi2_data_b_mux[] = {
3346         SSI_SDATA2_B_MARK,
3347 };
3348 static const unsigned int ssi2_ctrl_b_pins[] = {
3349         /* SCK2, WS2 */
3350         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3351 };
3352 static const unsigned int ssi2_ctrl_b_mux[] = {
3353         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3354 };
3355 static const unsigned int ssi3_data_pins[] = {
3356         /* SDATA3 */
3357         RCAR_GP_PIN(5, 6),
3358 };
3359 static const unsigned int ssi3_data_mux[] = {
3360         SSI_SDATA3_MARK
3361 };
3362 static const unsigned int ssi34_ctrl_pins[] = {
3363         /* SCK34, WS34 */
3364         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3365 };
3366 static const unsigned int ssi34_ctrl_mux[] = {
3367         SSI_SCK34_MARK, SSI_WS34_MARK,
3368 };
3369 static const unsigned int ssi4_data_pins[] = {
3370         /* SDATA4 */
3371         RCAR_GP_PIN(5, 9),
3372 };
3373 static const unsigned int ssi4_data_mux[] = {
3374         SSI_SDATA4_MARK,
3375 };
3376 static const unsigned int ssi4_ctrl_pins[] = {
3377         /* SCK4, WS4 */
3378         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3379 };
3380 static const unsigned int ssi4_ctrl_mux[] = {
3381         SSI_SCK4_MARK, SSI_WS4_MARK,
3382 };
3383 static const unsigned int ssi4_data_b_pins[] = {
3384         /* SDATA4 */
3385         RCAR_GP_PIN(4, 22),
3386 };
3387 static const unsigned int ssi4_data_b_mux[] = {
3388         SSI_SDATA4_B_MARK,
3389 };
3390 static const unsigned int ssi4_ctrl_b_pins[] = {
3391         /* SCK4, WS4 */
3392         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3393 };
3394 static const unsigned int ssi4_ctrl_b_mux[] = {
3395         SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3396 };
3397 static const unsigned int ssi5_data_pins[] = {
3398         /* SDATA5 */
3399         RCAR_GP_PIN(4, 26),
3400 };
3401 static const unsigned int ssi5_data_mux[] = {
3402         SSI_SDATA5_MARK,
3403 };
3404 static const unsigned int ssi5_ctrl_pins[] = {
3405         /* SCK5, WS5 */
3406         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3407 };
3408 static const unsigned int ssi5_ctrl_mux[] = {
3409         SSI_SCK5_MARK, SSI_WS5_MARK,
3410 };
3411 static const unsigned int ssi5_data_b_pins[] = {
3412         /* SDATA5 */
3413         RCAR_GP_PIN(3, 21),
3414 };
3415 static const unsigned int ssi5_data_b_mux[] = {
3416         SSI_SDATA5_B_MARK,
3417 };
3418 static const unsigned int ssi5_ctrl_b_pins[] = {
3419         /* SCK5, WS5 */
3420         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3421 };
3422 static const unsigned int ssi5_ctrl_b_mux[] = {
3423         SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3424 };
3425 static const unsigned int ssi6_data_pins[] = {
3426         /* SDATA6 */
3427         RCAR_GP_PIN(4, 29),
3428 };
3429 static const unsigned int ssi6_data_mux[] = {
3430         SSI_SDATA6_MARK,
3431 };
3432 static const unsigned int ssi6_ctrl_pins[] = {
3433         /* SCK6, WS6 */
3434         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3435 };
3436 static const unsigned int ssi6_ctrl_mux[] = {
3437         SSI_SCK6_MARK, SSI_WS6_MARK,
3438 };
3439 static const unsigned int ssi6_data_b_pins[] = {
3440         /* SDATA6 */
3441         RCAR_GP_PIN(3, 24),
3442 };
3443 static const unsigned int ssi6_data_b_mux[] = {
3444         SSI_SDATA6_B_MARK,
3445 };
3446 static const unsigned int ssi6_ctrl_b_pins[] = {
3447         /* SCK6, WS6 */
3448         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3449 };
3450 static const unsigned int ssi6_ctrl_b_mux[] = {
3451         SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3452 };
3453 static const unsigned int ssi7_data_pins[] = {
3454         /* SDATA7 */
3455         RCAR_GP_PIN(5, 0),
3456 };
3457 static const unsigned int ssi7_data_mux[] = {
3458         SSI_SDATA7_MARK,
3459 };
3460 static const unsigned int ssi78_ctrl_pins[] = {
3461         /* SCK78, WS78 */
3462         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3463 };
3464 static const unsigned int ssi78_ctrl_mux[] = {
3465         SSI_SCK78_MARK, SSI_WS78_MARK,
3466 };
3467 static const unsigned int ssi7_data_b_pins[] = {
3468         /* SDATA7 */
3469         RCAR_GP_PIN(3, 27),
3470 };
3471 static const unsigned int ssi7_data_b_mux[] = {
3472         SSI_SDATA7_B_MARK,
3473 };
3474 static const unsigned int ssi78_ctrl_b_pins[] = {
3475         /* SCK78, WS78 */
3476         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3477 };
3478 static const unsigned int ssi78_ctrl_b_mux[] = {
3479         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3480 };
3481 static const unsigned int ssi8_data_pins[] = {
3482         /* SDATA8 */
3483         RCAR_GP_PIN(5, 10),
3484 };
3485 static const unsigned int ssi8_data_mux[] = {
3486         SSI_SDATA8_MARK,
3487 };
3488 static const unsigned int ssi8_data_b_pins[] = {
3489         /* SDATA8 */
3490         RCAR_GP_PIN(3, 28),
3491 };
3492 static const unsigned int ssi8_data_b_mux[] = {
3493         SSI_SDATA8_B_MARK,
3494 };
3495 static const unsigned int ssi9_data_pins[] = {
3496         /* SDATA9 */
3497         RCAR_GP_PIN(5, 19),
3498 };
3499 static const unsigned int ssi9_data_mux[] = {
3500         SSI_SDATA9_MARK,
3501 };
3502 static const unsigned int ssi9_ctrl_pins[] = {
3503         /* SCK9, WS9 */
3504         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3505 };
3506 static const unsigned int ssi9_ctrl_mux[] = {
3507         SSI_SCK9_MARK, SSI_WS9_MARK,
3508 };
3509 static const unsigned int ssi9_data_b_pins[] = {
3510         /* SDATA9 */
3511         RCAR_GP_PIN(4, 19),
3512 };
3513 static const unsigned int ssi9_data_b_mux[] = {
3514         SSI_SDATA9_B_MARK,
3515 };
3516 static const unsigned int ssi9_ctrl_b_pins[] = {
3517         /* SCK9, WS9 */
3518         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3519 };
3520 static const unsigned int ssi9_ctrl_b_mux[] = {
3521         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3522 };
3523 /* - TPU -------------------------------------------------------------------- */
3524 static const unsigned int tpu_to0_pins[] = {
3525         RCAR_GP_PIN(3, 31),
3526 };
3527 static const unsigned int tpu_to0_mux[] = {
3528         TPUTO0_MARK,
3529 };
3530 static const unsigned int tpu_to0_b_pins[] = {
3531         RCAR_GP_PIN(3, 30),
3532 };
3533 static const unsigned int tpu_to0_b_mux[] = {
3534         TPUTO0_B_MARK,
3535 };
3536 static const unsigned int tpu_to0_c_pins[] = {
3537         RCAR_GP_PIN(1, 18),
3538 };
3539 static const unsigned int tpu_to0_c_mux[] = {
3540         TPUTO0_C_MARK,
3541 };
3542 static const unsigned int tpu_to1_pins[] = {
3543         RCAR_GP_PIN(4, 9),
3544 };
3545 static const unsigned int tpu_to1_mux[] = {
3546         TPUTO1_MARK,
3547 };
3548 static const unsigned int tpu_to1_b_pins[] = {
3549         RCAR_GP_PIN(4, 0),
3550 };
3551 static const unsigned int tpu_to1_b_mux[] = {
3552         TPUTO1_B_MARK,
3553 };
3554 static const unsigned int tpu_to1_c_pins[] = {
3555         RCAR_GP_PIN(4, 4),
3556 };
3557 static const unsigned int tpu_to1_c_mux[] = {
3558         TPUTO1_C_MARK,
3559 };
3560 static const unsigned int tpu_to2_pins[] = {
3561         RCAR_GP_PIN(1, 3),
3562 };
3563 static const unsigned int tpu_to2_mux[] = {
3564         TPUTO2_MARK,
3565 };
3566 static const unsigned int tpu_to2_b_pins[] = {
3567         RCAR_GP_PIN(1, 0),
3568 };
3569 static const unsigned int tpu_to2_b_mux[] = {
3570         TPUTO2_B_MARK,
3571 };
3572 static const unsigned int tpu_to2_c_pins[] = {
3573         RCAR_GP_PIN(0, 22),
3574 };
3575 static const unsigned int tpu_to2_c_mux[] = {
3576         TPUTO2_C_MARK,
3577 };
3578 static const unsigned int tpu_to3_pins[] = {
3579         RCAR_GP_PIN(1, 14),
3580 };
3581 static const unsigned int tpu_to3_mux[] = {
3582         TPUTO3_MARK,
3583 };
3584 static const unsigned int tpu_to3_b_pins[] = {
3585         RCAR_GP_PIN(1, 13),
3586 };
3587 static const unsigned int tpu_to3_b_mux[] = {
3588         TPUTO3_B_MARK,
3589 };
3590 static const unsigned int tpu_to3_c_pins[] = {
3591         RCAR_GP_PIN(0, 21),
3592 };
3593 static const unsigned int tpu_to3_c_mux[] = {
3594         TPUTO3_C_MARK,
3595 };
3596 /* - USB0 ------------------------------------------------------------------- */
3597 static const unsigned int usb0_pins[] = {
3598         RCAR_GP_PIN(5, 24), /* PWEN */
3599         RCAR_GP_PIN(5, 25), /* OVC */
3600 };
3601 static const unsigned int usb0_mux[] = {
3602         USB0_PWEN_MARK,
3603         USB0_OVC_MARK,
3604 };
3605 /* - USB1 ------------------------------------------------------------------- */
3606 static const unsigned int usb1_pins[] = {
3607         RCAR_GP_PIN(5, 26), /* PWEN */
3608         RCAR_GP_PIN(5, 27), /* OVC */
3609 };
3610 static const unsigned int usb1_mux[] = {
3611         USB1_PWEN_MARK,
3612         USB1_OVC_MARK,
3613 };
3614 /* - VIN0 ------------------------------------------------------------------- */
3615 static const union vin_data vin0_data_pins = {
3616         .data24 = {
3617                 /* B */
3618                 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3619                 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3620                 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3621                 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3622                 /* G */
3623                 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3624                 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3625                 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3626                 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3627                 /* R */
3628                 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3629                 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3630                 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3631                 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3632         },
3633 };
3634 static const union vin_data vin0_data_mux = {
3635         .data24 = {
3636                 /* B */
3637                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3638                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3639                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3640                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3641                 /* G */
3642                 VI0_G0_MARK, VI0_G1_MARK,
3643                 VI0_G2_MARK, VI0_G3_MARK,
3644                 VI0_G4_MARK, VI0_G5_MARK,
3645                 VI0_G6_MARK, VI0_G7_MARK,
3646                 /* R */
3647                 VI0_R0_MARK, VI0_R1_MARK,
3648                 VI0_R2_MARK, VI0_R3_MARK,
3649                 VI0_R4_MARK, VI0_R5_MARK,
3650                 VI0_R6_MARK, VI0_R7_MARK,
3651         },
3652 };
3653 static const unsigned int vin0_data18_pins[] = {
3654         /* B */
3655         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3656         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3657         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3658         /* G */
3659         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3660         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3661         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3662         /* R */
3663         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3664         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3665         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3666 };
3667 static const unsigned int vin0_data18_mux[] = {
3668         /* B */
3669         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3670         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3671         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3672         /* G */
3673         VI0_G2_MARK, VI0_G3_MARK,
3674         VI0_G4_MARK, VI0_G5_MARK,
3675         VI0_G6_MARK, VI0_G7_MARK,
3676         /* R */
3677         VI0_R2_MARK, VI0_R3_MARK,
3678         VI0_R4_MARK, VI0_R5_MARK,
3679         VI0_R6_MARK, VI0_R7_MARK,
3680 };
3681 static const unsigned int vin0_sync_pins[] = {
3682         RCAR_GP_PIN(3, 11), /* HSYNC */
3683         RCAR_GP_PIN(3, 12), /* VSYNC */
3684 };
3685 static const unsigned int vin0_sync_mux[] = {
3686         VI0_HSYNC_N_MARK,
3687         VI0_VSYNC_N_MARK,
3688 };
3689 static const unsigned int vin0_field_pins[] = {
3690         RCAR_GP_PIN(3, 10),
3691 };
3692 static const unsigned int vin0_field_mux[] = {
3693         VI0_FIELD_MARK,
3694 };
3695 static const unsigned int vin0_clkenb_pins[] = {
3696         RCAR_GP_PIN(3, 9),
3697 };
3698 static const unsigned int vin0_clkenb_mux[] = {
3699         VI0_CLKENB_MARK,
3700 };
3701 static const unsigned int vin0_clk_pins[] = {
3702         RCAR_GP_PIN(3, 0),
3703 };
3704 static const unsigned int vin0_clk_mux[] = {
3705         VI0_CLK_MARK,
3706 };
3707 /* - VIN1 ------------------------------------------------------------------- */
3708 static const union vin_data12 vin1_data_pins = {
3709         .data12 = {
3710                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3711                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3712                 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3713                 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3714                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3715                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3716         },
3717 };
3718 static const union vin_data12 vin1_data_mux = {
3719         .data12 = {
3720                 VI1_DATA0_MARK, VI1_DATA1_MARK,
3721                 VI1_DATA2_MARK, VI1_DATA3_MARK,
3722                 VI1_DATA4_MARK, VI1_DATA5_MARK,
3723                 VI1_DATA6_MARK, VI1_DATA7_MARK,
3724                 VI1_DATA8_MARK, VI1_DATA9_MARK,
3725                 VI1_DATA10_MARK, VI1_DATA11_MARK,
3726         },
3727 };
3728 static const unsigned int vin1_sync_pins[] = {
3729         RCAR_GP_PIN(5, 22), /* HSYNC */
3730         RCAR_GP_PIN(5, 23), /* VSYNC */
3731 };
3732 static const unsigned int vin1_sync_mux[] = {
3733         VI1_HSYNC_N_MARK,
3734         VI1_VSYNC_N_MARK,
3735 };
3736 static const unsigned int vin1_field_pins[] = {
3737         RCAR_GP_PIN(5, 21),
3738 };
3739 static const unsigned int vin1_field_mux[] = {
3740         VI1_FIELD_MARK,
3741 };
3742 static const unsigned int vin1_clkenb_pins[] = {
3743         RCAR_GP_PIN(5, 20),
3744 };
3745 static const unsigned int vin1_clkenb_mux[] = {
3746         VI1_CLKENB_MARK,
3747 };
3748 static const unsigned int vin1_clk_pins[] = {
3749         RCAR_GP_PIN(5, 11),
3750 };
3751 static const unsigned int vin1_clk_mux[] = {
3752         VI1_CLK_MARK,
3753 };
3754
3755 static const struct sh_pfc_pin_group pinmux_groups[] = {
3756         SH_PFC_PIN_GROUP(audio_clka),
3757         SH_PFC_PIN_GROUP(audio_clka_b),
3758         SH_PFC_PIN_GROUP(audio_clka_c),
3759         SH_PFC_PIN_GROUP(audio_clka_d),
3760         SH_PFC_PIN_GROUP(audio_clkb),
3761         SH_PFC_PIN_GROUP(audio_clkb_b),
3762         SH_PFC_PIN_GROUP(audio_clkb_c),
3763         SH_PFC_PIN_GROUP(audio_clkc),
3764         SH_PFC_PIN_GROUP(audio_clkc_b),
3765         SH_PFC_PIN_GROUP(audio_clkc_c),
3766         SH_PFC_PIN_GROUP(audio_clkout),
3767         SH_PFC_PIN_GROUP(audio_clkout_b),
3768         SH_PFC_PIN_GROUP(audio_clkout_c),
3769         SH_PFC_PIN_GROUP(avb_link),
3770         SH_PFC_PIN_GROUP(avb_magic),
3771         SH_PFC_PIN_GROUP(avb_phy_int),
3772         SH_PFC_PIN_GROUP(avb_mdio),
3773         SH_PFC_PIN_GROUP(avb_mii),
3774         SH_PFC_PIN_GROUP(avb_gmii),
3775         SH_PFC_PIN_GROUP(can0_data),
3776         SH_PFC_PIN_GROUP(can0_data_b),
3777         SH_PFC_PIN_GROUP(can0_data_c),
3778         SH_PFC_PIN_GROUP(can0_data_d),
3779         SH_PFC_PIN_GROUP(can1_data),
3780         SH_PFC_PIN_GROUP(can1_data_b),
3781         SH_PFC_PIN_GROUP(can1_data_c),
3782         SH_PFC_PIN_GROUP(can1_data_d),
3783         SH_PFC_PIN_GROUP(can_clk),
3784         SH_PFC_PIN_GROUP(can_clk_b),
3785         SH_PFC_PIN_GROUP(can_clk_c),
3786         SH_PFC_PIN_GROUP(can_clk_d),
3787         SH_PFC_PIN_GROUP(du0_rgb666),
3788         SH_PFC_PIN_GROUP(du0_rgb888),
3789         SH_PFC_PIN_GROUP(du0_clk0_out),
3790         SH_PFC_PIN_GROUP(du0_clk1_out),
3791         SH_PFC_PIN_GROUP(du0_clk_in),
3792         SH_PFC_PIN_GROUP(du0_sync),
3793         SH_PFC_PIN_GROUP(du0_oddf),
3794         SH_PFC_PIN_GROUP(du0_cde),
3795         SH_PFC_PIN_GROUP(du0_disp),
3796         SH_PFC_PIN_GROUP(du1_rgb666),
3797         SH_PFC_PIN_GROUP(du1_rgb888),
3798         SH_PFC_PIN_GROUP(du1_clk0_out),
3799         SH_PFC_PIN_GROUP(du1_clk1_out),
3800         SH_PFC_PIN_GROUP(du1_clk_in),
3801         SH_PFC_PIN_GROUP(du1_sync),
3802         SH_PFC_PIN_GROUP(du1_oddf),
3803         SH_PFC_PIN_GROUP(du1_cde),
3804         SH_PFC_PIN_GROUP(du1_disp),
3805         SH_PFC_PIN_GROUP(eth_link),
3806         SH_PFC_PIN_GROUP(eth_magic),
3807         SH_PFC_PIN_GROUP(eth_mdio),
3808         SH_PFC_PIN_GROUP(eth_rmii),
3809         SH_PFC_PIN_GROUP(eth_link_b),
3810         SH_PFC_PIN_GROUP(eth_magic_b),
3811         SH_PFC_PIN_GROUP(eth_mdio_b),
3812         SH_PFC_PIN_GROUP(eth_rmii_b),
3813         SH_PFC_PIN_GROUP(hscif0_data),
3814         SH_PFC_PIN_GROUP(hscif0_clk),
3815         SH_PFC_PIN_GROUP(hscif0_ctrl),
3816         SH_PFC_PIN_GROUP(hscif0_data_b),
3817         SH_PFC_PIN_GROUP(hscif0_clk_b),
3818         SH_PFC_PIN_GROUP(hscif1_data),
3819         SH_PFC_PIN_GROUP(hscif1_clk),
3820         SH_PFC_PIN_GROUP(hscif1_ctrl),
3821         SH_PFC_PIN_GROUP(hscif1_data_b),
3822         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3823         SH_PFC_PIN_GROUP(hscif2_data),
3824         SH_PFC_PIN_GROUP(hscif2_clk),
3825         SH_PFC_PIN_GROUP(hscif2_ctrl),
3826         SH_PFC_PIN_GROUP(i2c0),
3827         SH_PFC_PIN_GROUP(i2c0_b),
3828         SH_PFC_PIN_GROUP(i2c0_c),
3829         SH_PFC_PIN_GROUP(i2c0_d),
3830         SH_PFC_PIN_GROUP(i2c0_e),
3831         SH_PFC_PIN_GROUP(i2c1),
3832         SH_PFC_PIN_GROUP(i2c1_b),
3833         SH_PFC_PIN_GROUP(i2c1_c),
3834         SH_PFC_PIN_GROUP(i2c1_d),
3835         SH_PFC_PIN_GROUP(i2c1_e),
3836         SH_PFC_PIN_GROUP(i2c2),
3837         SH_PFC_PIN_GROUP(i2c2_b),
3838         SH_PFC_PIN_GROUP(i2c2_c),
3839         SH_PFC_PIN_GROUP(i2c2_d),
3840         SH_PFC_PIN_GROUP(i2c2_e),
3841         SH_PFC_PIN_GROUP(i2c3),
3842         SH_PFC_PIN_GROUP(i2c3_b),
3843         SH_PFC_PIN_GROUP(i2c3_c),
3844         SH_PFC_PIN_GROUP(i2c3_d),
3845         SH_PFC_PIN_GROUP(i2c3_e),
3846         SH_PFC_PIN_GROUP(i2c4),
3847         SH_PFC_PIN_GROUP(i2c4_b),
3848         SH_PFC_PIN_GROUP(i2c4_c),
3849         SH_PFC_PIN_GROUP(i2c4_d),
3850         SH_PFC_PIN_GROUP(i2c4_e),
3851         SH_PFC_PIN_GROUP(i2c5),
3852         SH_PFC_PIN_GROUP(i2c5_b),
3853         SH_PFC_PIN_GROUP(i2c5_c),
3854         SH_PFC_PIN_GROUP(i2c5_d),
3855         SH_PFC_PIN_GROUP(intc_irq0),
3856         SH_PFC_PIN_GROUP(intc_irq1),
3857         SH_PFC_PIN_GROUP(intc_irq2),
3858         SH_PFC_PIN_GROUP(intc_irq3),
3859         SH_PFC_PIN_GROUP(intc_irq4),
3860         SH_PFC_PIN_GROUP(intc_irq5),
3861         SH_PFC_PIN_GROUP(intc_irq6),
3862         SH_PFC_PIN_GROUP(intc_irq7),
3863         SH_PFC_PIN_GROUP(intc_irq8),
3864         SH_PFC_PIN_GROUP(intc_irq9),
3865         SH_PFC_PIN_GROUP(mmc_data1),
3866         SH_PFC_PIN_GROUP(mmc_data4),
3867         SH_PFC_PIN_GROUP(mmc_data8),
3868         SH_PFC_PIN_GROUP(mmc_ctrl),
3869         SH_PFC_PIN_GROUP(msiof0_clk),
3870         SH_PFC_PIN_GROUP(msiof0_sync),
3871         SH_PFC_PIN_GROUP(msiof0_ss1),
3872         SH_PFC_PIN_GROUP(msiof0_ss2),
3873         SH_PFC_PIN_GROUP(msiof0_rx),
3874         SH_PFC_PIN_GROUP(msiof0_tx),
3875         SH_PFC_PIN_GROUP(msiof1_clk),
3876         SH_PFC_PIN_GROUP(msiof1_sync),
3877         SH_PFC_PIN_GROUP(msiof1_ss1),
3878         SH_PFC_PIN_GROUP(msiof1_ss2),
3879         SH_PFC_PIN_GROUP(msiof1_rx),
3880         SH_PFC_PIN_GROUP(msiof1_tx),
3881         SH_PFC_PIN_GROUP(msiof1_clk_b),
3882         SH_PFC_PIN_GROUP(msiof1_sync_b),
3883         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3884         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3885         SH_PFC_PIN_GROUP(msiof1_rx_b),
3886         SH_PFC_PIN_GROUP(msiof1_tx_b),
3887         SH_PFC_PIN_GROUP(msiof2_clk),
3888         SH_PFC_PIN_GROUP(msiof2_sync),
3889         SH_PFC_PIN_GROUP(msiof2_ss1),
3890         SH_PFC_PIN_GROUP(msiof2_ss2),
3891         SH_PFC_PIN_GROUP(msiof2_rx),
3892         SH_PFC_PIN_GROUP(msiof2_tx),
3893         SH_PFC_PIN_GROUP(msiof2_clk_b),
3894         SH_PFC_PIN_GROUP(msiof2_sync_b),
3895         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3896         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3897         SH_PFC_PIN_GROUP(msiof2_rx_b),
3898         SH_PFC_PIN_GROUP(msiof2_tx_b),
3899         SH_PFC_PIN_GROUP(pwm0),
3900         SH_PFC_PIN_GROUP(pwm0_b),
3901         SH_PFC_PIN_GROUP(pwm1),
3902         SH_PFC_PIN_GROUP(pwm1_b),
3903         SH_PFC_PIN_GROUP(pwm1_c),
3904         SH_PFC_PIN_GROUP(pwm2),
3905         SH_PFC_PIN_GROUP(pwm2_b),
3906         SH_PFC_PIN_GROUP(pwm2_c),
3907         SH_PFC_PIN_GROUP(pwm3),
3908         SH_PFC_PIN_GROUP(pwm3_b),
3909         SH_PFC_PIN_GROUP(pwm4),
3910         SH_PFC_PIN_GROUP(pwm4_b),
3911         SH_PFC_PIN_GROUP(pwm5),
3912         SH_PFC_PIN_GROUP(pwm5_b),
3913         SH_PFC_PIN_GROUP(pwm5_c),
3914         SH_PFC_PIN_GROUP(pwm6),
3915         SH_PFC_PIN_GROUP(pwm6_b),
3916         SH_PFC_PIN_GROUP(qspi_ctrl),
3917         SH_PFC_PIN_GROUP(qspi_data2),
3918         SH_PFC_PIN_GROUP(qspi_data4),
3919         SH_PFC_PIN_GROUP(scif0_data),
3920         SH_PFC_PIN_GROUP(scif0_data_b),
3921         SH_PFC_PIN_GROUP(scif0_data_c),
3922         SH_PFC_PIN_GROUP(scif0_data_d),
3923         SH_PFC_PIN_GROUP(scif1_data),
3924         SH_PFC_PIN_GROUP(scif1_clk),
3925         SH_PFC_PIN_GROUP(scif1_data_b),
3926         SH_PFC_PIN_GROUP(scif1_clk_b),
3927         SH_PFC_PIN_GROUP(scif1_data_c),
3928         SH_PFC_PIN_GROUP(scif1_clk_c),
3929         SH_PFC_PIN_GROUP(scif2_data),
3930         SH_PFC_PIN_GROUP(scif2_clk),
3931         SH_PFC_PIN_GROUP(scif2_data_b),
3932         SH_PFC_PIN_GROUP(scif2_clk_b),
3933         SH_PFC_PIN_GROUP(scif2_data_c),
3934         SH_PFC_PIN_GROUP(scif2_clk_c),
3935         SH_PFC_PIN_GROUP(scif3_data),
3936         SH_PFC_PIN_GROUP(scif3_clk),
3937         SH_PFC_PIN_GROUP(scif3_data_b),
3938         SH_PFC_PIN_GROUP(scif3_clk_b),
3939         SH_PFC_PIN_GROUP(scif4_data),
3940         SH_PFC_PIN_GROUP(scif4_data_b),
3941         SH_PFC_PIN_GROUP(scif4_data_c),
3942         SH_PFC_PIN_GROUP(scif4_data_d),
3943         SH_PFC_PIN_GROUP(scif4_data_e),
3944         SH_PFC_PIN_GROUP(scif5_data),
3945         SH_PFC_PIN_GROUP(scif5_data_b),
3946         SH_PFC_PIN_GROUP(scif5_data_c),
3947         SH_PFC_PIN_GROUP(scif5_data_d),
3948         SH_PFC_PIN_GROUP(scifa0_data),
3949         SH_PFC_PIN_GROUP(scifa0_data_b),
3950         SH_PFC_PIN_GROUP(scifa0_data_c),
3951         SH_PFC_PIN_GROUP(scifa0_data_d),
3952         SH_PFC_PIN_GROUP(scifa1_data),
3953         SH_PFC_PIN_GROUP(scifa1_clk),
3954         SH_PFC_PIN_GROUP(scifa1_data_b),
3955         SH_PFC_PIN_GROUP(scifa1_clk_b),
3956         SH_PFC_PIN_GROUP(scifa1_data_c),
3957         SH_PFC_PIN_GROUP(scifa1_clk_c),
3958         SH_PFC_PIN_GROUP(scifa2_data),
3959         SH_PFC_PIN_GROUP(scifa2_clk),
3960         SH_PFC_PIN_GROUP(scifa2_data_b),
3961         SH_PFC_PIN_GROUP(scifa2_clk_b),
3962         SH_PFC_PIN_GROUP(scifa3_data),
3963         SH_PFC_PIN_GROUP(scifa3_clk),
3964         SH_PFC_PIN_GROUP(scifa3_data_b),
3965         SH_PFC_PIN_GROUP(scifa3_clk_b),
3966         SH_PFC_PIN_GROUP(scifa4_data),
3967         SH_PFC_PIN_GROUP(scifa4_data_b),
3968         SH_PFC_PIN_GROUP(scifa4_data_c),
3969         SH_PFC_PIN_GROUP(scifa4_data_d),
3970         SH_PFC_PIN_GROUP(scifa5_data),
3971         SH_PFC_PIN_GROUP(scifa5_data_b),
3972         SH_PFC_PIN_GROUP(scifa5_data_c),
3973         SH_PFC_PIN_GROUP(scifa5_data_d),
3974         SH_PFC_PIN_GROUP(scifb0_data),
3975         SH_PFC_PIN_GROUP(scifb0_clk),
3976         SH_PFC_PIN_GROUP(scifb0_ctrl),
3977         SH_PFC_PIN_GROUP(scifb1_data),
3978         SH_PFC_PIN_GROUP(scifb1_clk),
3979         SH_PFC_PIN_GROUP(scifb2_data),
3980         SH_PFC_PIN_GROUP(scifb2_clk),
3981         SH_PFC_PIN_GROUP(scifb2_ctrl),
3982         SH_PFC_PIN_GROUP(scif_clk),
3983         SH_PFC_PIN_GROUP(scif_clk_b),
3984         SH_PFC_PIN_GROUP(sdhi0_data1),
3985         SH_PFC_PIN_GROUP(sdhi0_data4),
3986         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3987         SH_PFC_PIN_GROUP(sdhi0_cd),
3988         SH_PFC_PIN_GROUP(sdhi0_wp),
3989         SH_PFC_PIN_GROUP(sdhi1_data1),
3990         SH_PFC_PIN_GROUP(sdhi1_data4),
3991         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3992         SH_PFC_PIN_GROUP(sdhi1_cd),
3993         SH_PFC_PIN_GROUP(sdhi1_wp),
3994         SH_PFC_PIN_GROUP(sdhi2_data1),
3995         SH_PFC_PIN_GROUP(sdhi2_data4),
3996         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3997         SH_PFC_PIN_GROUP(sdhi2_cd),
3998         SH_PFC_PIN_GROUP(sdhi2_wp),
3999         SH_PFC_PIN_GROUP(ssi0_data),
4000         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4001         SH_PFC_PIN_GROUP(ssi1_data),
4002         SH_PFC_PIN_GROUP(ssi1_ctrl),
4003         SH_PFC_PIN_GROUP(ssi1_data_b),
4004         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4005         SH_PFC_PIN_GROUP(ssi2_data),
4006         SH_PFC_PIN_GROUP(ssi2_ctrl),
4007         SH_PFC_PIN_GROUP(ssi2_data_b),
4008         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4009         SH_PFC_PIN_GROUP(ssi3_data),
4010         SH_PFC_PIN_GROUP(ssi34_ctrl),
4011         SH_PFC_PIN_GROUP(ssi4_data),
4012         SH_PFC_PIN_GROUP(ssi4_ctrl),
4013         SH_PFC_PIN_GROUP(ssi4_data_b),
4014         SH_PFC_PIN_GROUP(ssi4_ctrl_b),
4015         SH_PFC_PIN_GROUP(ssi5_data),
4016         SH_PFC_PIN_GROUP(ssi5_ctrl),
4017         SH_PFC_PIN_GROUP(ssi5_data_b),
4018         SH_PFC_PIN_GROUP(ssi5_ctrl_b),
4019         SH_PFC_PIN_GROUP(ssi6_data),
4020         SH_PFC_PIN_GROUP(ssi6_ctrl),
4021         SH_PFC_PIN_GROUP(ssi6_data_b),
4022         SH_PFC_PIN_GROUP(ssi6_ctrl_b),
4023         SH_PFC_PIN_GROUP(ssi7_data),
4024         SH_PFC_PIN_GROUP(ssi78_ctrl),
4025         SH_PFC_PIN_GROUP(ssi7_data_b),
4026         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4027         SH_PFC_PIN_GROUP(ssi8_data),
4028         SH_PFC_PIN_GROUP(ssi8_data_b),
4029         SH_PFC_PIN_GROUP(ssi9_data),
4030         SH_PFC_PIN_GROUP(ssi9_ctrl),
4031         SH_PFC_PIN_GROUP(ssi9_data_b),
4032         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4033         SH_PFC_PIN_GROUP(tpu_to0),
4034         SH_PFC_PIN_GROUP(tpu_to0_b),
4035         SH_PFC_PIN_GROUP(tpu_to0_c),
4036         SH_PFC_PIN_GROUP(tpu_to1),
4037         SH_PFC_PIN_GROUP(tpu_to1_b),
4038         SH_PFC_PIN_GROUP(tpu_to1_c),
4039         SH_PFC_PIN_GROUP(tpu_to2),
4040         SH_PFC_PIN_GROUP(tpu_to2_b),
4041         SH_PFC_PIN_GROUP(tpu_to2_c),
4042         SH_PFC_PIN_GROUP(tpu_to3),
4043         SH_PFC_PIN_GROUP(tpu_to3_b),
4044         SH_PFC_PIN_GROUP(tpu_to3_c),
4045         SH_PFC_PIN_GROUP(usb0),
4046         SH_PFC_PIN_GROUP(usb1),
4047         VIN_DATA_PIN_GROUP(vin0_data, 24),
4048         VIN_DATA_PIN_GROUP(vin0_data, 20),
4049         SH_PFC_PIN_GROUP(vin0_data18),
4050         VIN_DATA_PIN_GROUP(vin0_data, 16),
4051         VIN_DATA_PIN_GROUP(vin0_data, 12),
4052         VIN_DATA_PIN_GROUP(vin0_data, 10),
4053         VIN_DATA_PIN_GROUP(vin0_data, 8),
4054         SH_PFC_PIN_GROUP(vin0_sync),
4055         SH_PFC_PIN_GROUP(vin0_field),
4056         SH_PFC_PIN_GROUP(vin0_clkenb),
4057         SH_PFC_PIN_GROUP(vin0_clk),
4058         VIN_DATA_PIN_GROUP(vin1_data, 12),
4059         VIN_DATA_PIN_GROUP(vin1_data, 10),
4060         VIN_DATA_PIN_GROUP(vin1_data, 8),
4061         SH_PFC_PIN_GROUP(vin1_sync),
4062         SH_PFC_PIN_GROUP(vin1_field),
4063         SH_PFC_PIN_GROUP(vin1_clkenb),
4064         SH_PFC_PIN_GROUP(vin1_clk),
4065 };
4066
4067 static const char * const audio_clk_groups[] = {
4068         "audio_clka",
4069         "audio_clka_b",
4070         "audio_clka_c",
4071         "audio_clka_d",
4072         "audio_clkb",
4073         "audio_clkb_b",
4074         "audio_clkb_c",
4075         "audio_clkc",
4076         "audio_clkc_b",
4077         "audio_clkc_c",
4078         "audio_clkout",
4079         "audio_clkout_b",
4080         "audio_clkout_c",
4081 };
4082
4083 static const char * const avb_groups[] = {
4084         "avb_link",
4085         "avb_magic",
4086         "avb_phy_int",
4087         "avb_mdio",
4088         "avb_mii",
4089         "avb_gmii",
4090 };
4091
4092 static const char * const can0_groups[] = {
4093         "can0_data",
4094         "can0_data_b",
4095         "can0_data_c",
4096         "can0_data_d",
4097         /*
4098          * Retained for backwards compatibility, use can_clk_groups in new
4099          * designs.
4100          */
4101         "can_clk",
4102         "can_clk_b",
4103         "can_clk_c",
4104         "can_clk_d",
4105 };
4106
4107 static const char * const can1_groups[] = {
4108         "can1_data",
4109         "can1_data_b",
4110         "can1_data_c",
4111         "can1_data_d",
4112         /*
4113          * Retained for backwards compatibility, use can_clk_groups in new
4114          * designs.
4115          */
4116         "can_clk",
4117         "can_clk_b",
4118         "can_clk_c",
4119         "can_clk_d",
4120 };
4121
4122 /*
4123  * can_clk_groups allows for independent configuration, use can_clk function
4124  * in new designs.
4125  */
4126 static const char * const can_clk_groups[] = {
4127         "can_clk",
4128         "can_clk_b",
4129         "can_clk_c",
4130         "can_clk_d",
4131 };
4132
4133 static const char * const du0_groups[] = {
4134         "du0_rgb666",
4135         "du0_rgb888",
4136         "du0_clk0_out",
4137         "du0_clk1_out",
4138         "du0_clk_in",
4139         "du0_sync",
4140         "du0_oddf",
4141         "du0_cde",
4142         "du0_disp",
4143 };
4144
4145 static const char * const du1_groups[] = {
4146         "du1_rgb666",
4147         "du1_rgb888",
4148         "du1_clk0_out",
4149         "du1_clk1_out",
4150         "du1_clk_in",
4151         "du1_sync",
4152         "du1_oddf",
4153         "du1_cde",
4154         "du1_disp",
4155 };
4156
4157 static const char * const eth_groups[] = {
4158         "eth_link",
4159         "eth_magic",
4160         "eth_mdio",
4161         "eth_rmii",
4162         "eth_link_b",
4163         "eth_magic_b",
4164         "eth_mdio_b",
4165         "eth_rmii_b",
4166 };
4167
4168 static const char * const hscif0_groups[] = {
4169         "hscif0_data",
4170         "hscif0_clk",
4171         "hscif0_ctrl",
4172         "hscif0_data_b",
4173         "hscif0_clk_b",
4174 };
4175
4176 static const char * const hscif1_groups[] = {
4177         "hscif1_data",
4178         "hscif1_clk",
4179         "hscif1_ctrl",
4180         "hscif1_data_b",
4181         "hscif1_ctrl_b",
4182 };
4183
4184 static const char * const hscif2_groups[] = {
4185         "hscif2_data",
4186         "hscif2_clk",
4187         "hscif2_ctrl",
4188 };
4189
4190 static const char * const i2c0_groups[] = {
4191         "i2c0",
4192         "i2c0_b",
4193         "i2c0_c",
4194         "i2c0_d",
4195         "i2c0_e",
4196 };
4197
4198 static const char * const i2c1_groups[] = {
4199         "i2c1",
4200         "i2c1_b",
4201         "i2c1_c",
4202         "i2c1_d",
4203         "i2c1_e",
4204 };
4205
4206 static const char * const i2c2_groups[] = {
4207         "i2c2",
4208         "i2c2_b",
4209         "i2c2_c",
4210         "i2c2_d",
4211         "i2c2_e",
4212 };
4213
4214 static const char * const i2c3_groups[] = {
4215         "i2c3",
4216         "i2c3_b",
4217         "i2c3_c",
4218         "i2c3_d",
4219         "i2c3_e",
4220 };
4221
4222 static const char * const i2c4_groups[] = {
4223         "i2c4",
4224         "i2c4_b",
4225         "i2c4_c",
4226         "i2c4_d",
4227         "i2c4_e",
4228 };
4229
4230 static const char * const i2c5_groups[] = {
4231         "i2c5",
4232         "i2c5_b",
4233         "i2c5_c",
4234         "i2c5_d",
4235 };
4236
4237 static const char * const intc_groups[] = {
4238         "intc_irq0",
4239         "intc_irq1",
4240         "intc_irq2",
4241         "intc_irq3",
4242         "intc_irq4",
4243         "intc_irq5",
4244         "intc_irq6",
4245         "intc_irq7",
4246         "intc_irq8",
4247         "intc_irq9",
4248 };
4249
4250 static const char * const mmc_groups[] = {
4251         "mmc_data1",
4252         "mmc_data4",
4253         "mmc_data8",
4254         "mmc_ctrl",
4255 };
4256
4257 static const char * const msiof0_groups[] = {
4258         "msiof0_clk",
4259         "msiof0_sync",
4260         "msiof0_ss1",
4261         "msiof0_ss2",
4262         "msiof0_rx",
4263         "msiof0_tx",
4264 };
4265
4266 static const char * const msiof1_groups[] = {
4267         "msiof1_clk",
4268         "msiof1_sync",
4269         "msiof1_ss1",
4270         "msiof1_ss2",
4271         "msiof1_rx",
4272         "msiof1_tx",
4273         "msiof1_clk_b",
4274         "msiof1_sync_b",
4275         "msiof1_ss1_b",
4276         "msiof1_ss2_b",
4277         "msiof1_rx_b",
4278         "msiof1_tx_b",
4279 };
4280
4281 static const char * const msiof2_groups[] = {
4282         "msiof2_clk",
4283         "msiof2_sync",
4284         "msiof2_ss1",
4285         "msiof2_ss2",
4286         "msiof2_rx",
4287         "msiof2_tx",
4288         "msiof2_clk_b",
4289         "msiof2_sync_b",
4290         "msiof2_ss1_b",
4291         "msiof2_ss2_b",
4292         "msiof2_rx_b",
4293         "msiof2_tx_b",
4294 };
4295
4296 static const char * const pwm0_groups[] = {
4297         "pwm0",
4298         "pwm0_b",
4299 };
4300
4301 static const char * const pwm1_groups[] = {
4302         "pwm1",
4303         "pwm1_b",
4304         "pwm1_c",
4305 };
4306
4307 static const char * const pwm2_groups[] = {
4308         "pwm2",
4309         "pwm2_b",
4310         "pwm2_c",
4311 };
4312
4313 static const char * const pwm3_groups[] = {
4314         "pwm3",
4315         "pwm3_b",
4316 };
4317
4318 static const char * const pwm4_groups[] = {
4319         "pwm4",
4320         "pwm4_b",
4321 };
4322
4323 static const char * const pwm5_groups[] = {
4324         "pwm5",
4325         "pwm5_b",
4326         "pwm5_c",
4327 };
4328
4329 static const char * const pwm6_groups[] = {
4330         "pwm6",
4331         "pwm6_b",
4332 };
4333
4334 static const char * const qspi_groups[] = {
4335         "qspi_ctrl",
4336         "qspi_data2",
4337         "qspi_data4",
4338 };
4339
4340 static const char * const scif0_groups[] = {
4341         "scif0_data",
4342         "scif0_data_b",
4343         "scif0_data_c",
4344         "scif0_data_d",
4345 };
4346
4347 static const char * const scif1_groups[] = {
4348         "scif1_data",
4349         "scif1_clk",
4350         "scif1_data_b",
4351         "scif1_clk_b",
4352         "scif1_data_c",
4353         "scif1_clk_c",
4354 };
4355
4356 static const char * const scif2_groups[] = {
4357         "scif2_data",
4358         "scif2_clk",
4359         "scif2_data_b",
4360         "scif2_clk_b",
4361         "scif2_data_c",
4362         "scif2_clk_c",
4363 };
4364
4365 static const char * const scif3_groups[] = {
4366         "scif3_data",
4367         "scif3_clk",
4368         "scif3_data_b",
4369         "scif3_clk_b",
4370 };
4371
4372 static const char * const scif4_groups[] = {
4373         "scif4_data",
4374         "scif4_data_b",
4375         "scif4_data_c",
4376         "scif4_data_d",
4377         "scif4_data_e",
4378 };
4379
4380 static const char * const scif5_groups[] = {
4381         "scif5_data",
4382         "scif5_data_b",
4383         "scif5_data_c",
4384         "scif5_data_d",
4385 };
4386
4387 static const char * const scifa0_groups[] = {
4388         "scifa0_data",
4389         "scifa0_data_b",
4390         "scifa0_data_c",
4391         "scifa0_data_d",
4392 };
4393
4394 static const char * const scifa1_groups[] = {
4395         "scifa1_data",
4396         "scifa1_clk",
4397         "scifa1_data_b",
4398         "scifa1_clk_b",
4399         "scifa1_data_c",
4400         "scifa1_clk_c",
4401 };
4402
4403 static const char * const scifa2_groups[] = {
4404         "scifa2_data",
4405         "scifa2_clk",
4406         "scifa2_data_b",
4407         "scifa2_clk_b",
4408 };
4409
4410 static const char * const scifa3_groups[] = {
4411         "scifa3_data",
4412         "scifa3_clk",
4413         "scifa3_data_b",
4414         "scifa3_clk_b",
4415 };
4416
4417 static const char * const scifa4_groups[] = {
4418         "scifa4_data",
4419         "scifa4_data_b",
4420         "scifa4_data_c",
4421         "scifa4_data_d",
4422 };
4423
4424 static const char * const scifa5_groups[] = {
4425         "scifa5_data",
4426         "scifa5_data_b",
4427         "scifa5_data_c",
4428         "scifa5_data_d",
4429 };
4430
4431 static const char * const scifb0_groups[] = {
4432         "scifb0_data",
4433         "scifb0_clk",
4434         "scifb0_ctrl",
4435 };
4436
4437 static const char * const scifb1_groups[] = {
4438         "scifb1_data",
4439         "scifb1_clk",
4440 };
4441
4442 static const char * const scifb2_groups[] = {
4443         "scifb2_data",
4444         "scifb2_clk",
4445         "scifb2_ctrl",
4446 };
4447
4448 static const char * const scif_clk_groups[] = {
4449         "scif_clk",
4450         "scif_clk_b",
4451 };
4452
4453 static const char * const sdhi0_groups[] = {
4454         "sdhi0_data1",
4455         "sdhi0_data4",
4456         "sdhi0_ctrl",
4457         "sdhi0_cd",
4458         "sdhi0_wp",
4459 };
4460
4461 static const char * const sdhi1_groups[] = {
4462         "sdhi1_data1",
4463         "sdhi1_data4",
4464         "sdhi1_ctrl",
4465         "sdhi1_cd",
4466         "sdhi1_wp",
4467 };
4468
4469 static const char * const sdhi2_groups[] = {
4470         "sdhi2_data1",
4471         "sdhi2_data4",
4472         "sdhi2_ctrl",
4473         "sdhi2_cd",
4474         "sdhi2_wp",
4475 };
4476
4477 static const char * const ssi_groups[] = {
4478         "ssi0_data",
4479         "ssi0129_ctrl",
4480         "ssi1_data",
4481         "ssi1_ctrl",
4482         "ssi1_data_b",
4483         "ssi1_ctrl_b",
4484         "ssi2_data",
4485         "ssi2_ctrl",
4486         "ssi2_data_b",
4487         "ssi2_ctrl_b",
4488         "ssi3_data",
4489         "ssi34_ctrl",
4490         "ssi4_data",
4491         "ssi4_ctrl",
4492         "ssi4_data_b",
4493         "ssi4_ctrl_b",
4494         "ssi5_data",
4495         "ssi5_ctrl",
4496         "ssi5_data_b",
4497         "ssi5_ctrl_b",
4498         "ssi6_data",
4499         "ssi6_ctrl",
4500         "ssi6_data_b",
4501         "ssi6_ctrl_b",
4502         "ssi7_data",
4503         "ssi78_ctrl",
4504         "ssi7_data_b",
4505         "ssi78_ctrl_b",
4506         "ssi8_data",
4507         "ssi8_data_b",
4508         "ssi9_data",
4509         "ssi9_ctrl",
4510         "ssi9_data_b",
4511         "ssi9_ctrl_b",
4512 };
4513
4514 static const char * const tpu_groups[] = {
4515         "tpu_to0",
4516         "tpu_to0_b",
4517         "tpu_to0_c",
4518         "tpu_to1",
4519         "tpu_to1_b",
4520         "tpu_to1_c",
4521         "tpu_to2",
4522         "tpu_to2_b",
4523         "tpu_to2_c",
4524         "tpu_to3",
4525         "tpu_to3_b",
4526         "tpu_to3_c",
4527 };
4528
4529 static const char * const usb0_groups[] = {
4530         "usb0",
4531 };
4532
4533 static const char * const usb1_groups[] = {
4534         "usb1",
4535 };
4536
4537 static const char * const vin0_groups[] = {
4538         "vin0_data24",
4539         "vin0_data20",
4540         "vin0_data18",
4541         "vin0_data16",
4542         "vin0_data12",
4543         "vin0_data10",
4544         "vin0_data8",
4545         "vin0_sync",
4546         "vin0_field",
4547         "vin0_clkenb",
4548         "vin0_clk",
4549 };
4550
4551 static const char * const vin1_groups[] = {
4552         "vin1_data12",
4553         "vin1_data10",
4554         "vin1_data8",
4555         "vin1_sync",
4556         "vin1_field",
4557         "vin1_clkenb",
4558         "vin1_clk",
4559 };
4560
4561 static const struct sh_pfc_function pinmux_functions[] = {
4562         SH_PFC_FUNCTION(audio_clk),
4563         SH_PFC_FUNCTION(avb),
4564         SH_PFC_FUNCTION(can0),
4565         SH_PFC_FUNCTION(can1),
4566         SH_PFC_FUNCTION(can_clk),
4567         SH_PFC_FUNCTION(du0),
4568         SH_PFC_FUNCTION(du1),
4569         SH_PFC_FUNCTION(eth),
4570         SH_PFC_FUNCTION(hscif0),
4571         SH_PFC_FUNCTION(hscif1),
4572         SH_PFC_FUNCTION(hscif2),
4573         SH_PFC_FUNCTION(i2c0),
4574         SH_PFC_FUNCTION(i2c1),
4575         SH_PFC_FUNCTION(i2c2),
4576         SH_PFC_FUNCTION(i2c3),
4577         SH_PFC_FUNCTION(i2c4),
4578         SH_PFC_FUNCTION(i2c5),
4579         SH_PFC_FUNCTION(intc),
4580         SH_PFC_FUNCTION(mmc),
4581         SH_PFC_FUNCTION(msiof0),
4582         SH_PFC_FUNCTION(msiof1),
4583         SH_PFC_FUNCTION(msiof2),
4584         SH_PFC_FUNCTION(pwm0),
4585         SH_PFC_FUNCTION(pwm1),
4586         SH_PFC_FUNCTION(pwm2),
4587         SH_PFC_FUNCTION(pwm3),
4588         SH_PFC_FUNCTION(pwm4),
4589         SH_PFC_FUNCTION(pwm5),
4590         SH_PFC_FUNCTION(pwm6),
4591         SH_PFC_FUNCTION(qspi),
4592         SH_PFC_FUNCTION(scif0),
4593         SH_PFC_FUNCTION(scif1),
4594         SH_PFC_FUNCTION(scif2),
4595         SH_PFC_FUNCTION(scif3),
4596         SH_PFC_FUNCTION(scif4),
4597         SH_PFC_FUNCTION(scif5),
4598         SH_PFC_FUNCTION(scifa0),
4599         SH_PFC_FUNCTION(scifa1),
4600         SH_PFC_FUNCTION(scifa2),
4601         SH_PFC_FUNCTION(scifa3),
4602         SH_PFC_FUNCTION(scifa4),
4603         SH_PFC_FUNCTION(scifa5),
4604         SH_PFC_FUNCTION(scifb0),
4605         SH_PFC_FUNCTION(scifb1),
4606         SH_PFC_FUNCTION(scifb2),
4607         SH_PFC_FUNCTION(scif_clk),
4608         SH_PFC_FUNCTION(sdhi0),
4609         SH_PFC_FUNCTION(sdhi1),
4610         SH_PFC_FUNCTION(sdhi2),
4611         SH_PFC_FUNCTION(ssi),
4612         SH_PFC_FUNCTION(tpu),
4613         SH_PFC_FUNCTION(usb0),
4614         SH_PFC_FUNCTION(usb1),
4615         SH_PFC_FUNCTION(vin0),
4616         SH_PFC_FUNCTION(vin1),
4617 };
4618
4619 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4620         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4621                 GP_0_31_FN, FN_IP2_17_16,
4622                 GP_0_30_FN, FN_IP2_15_14,
4623                 GP_0_29_FN, FN_IP2_13_12,
4624                 GP_0_28_FN, FN_IP2_11_10,
4625                 GP_0_27_FN, FN_IP2_9_8,
4626                 GP_0_26_FN, FN_IP2_7_6,
4627                 GP_0_25_FN, FN_IP2_5_4,
4628                 GP_0_24_FN, FN_IP2_3_2,
4629                 GP_0_23_FN, FN_IP2_1_0,
4630                 GP_0_22_FN, FN_IP1_31_30,
4631                 GP_0_21_FN, FN_IP1_29_28,
4632                 GP_0_20_FN, FN_IP1_27,
4633                 GP_0_19_FN, FN_IP1_26,
4634                 GP_0_18_FN, FN_A2,
4635                 GP_0_17_FN, FN_IP1_24,
4636                 GP_0_16_FN, FN_IP1_23_22,
4637                 GP_0_15_FN, FN_IP1_21_20,
4638                 GP_0_14_FN, FN_IP1_19_18,
4639                 GP_0_13_FN, FN_IP1_17_15,
4640                 GP_0_12_FN, FN_IP1_14_13,
4641                 GP_0_11_FN, FN_IP1_12_11,
4642                 GP_0_10_FN, FN_IP1_10_8,
4643                 GP_0_9_FN, FN_IP1_7_6,
4644                 GP_0_8_FN, FN_IP1_5_4,
4645                 GP_0_7_FN, FN_IP1_3_2,
4646                 GP_0_6_FN, FN_IP1_1_0,
4647                 GP_0_5_FN, FN_IP0_31_30,
4648                 GP_0_4_FN, FN_IP0_29_28,
4649                 GP_0_3_FN, FN_IP0_27_26,
4650                 GP_0_2_FN, FN_IP0_25,
4651                 GP_0_1_FN, FN_IP0_24,
4652                 GP_0_0_FN, FN_IP0_23_22, }
4653         },
4654         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4655                 0, 0,
4656                 0, 0,
4657                 0, 0,
4658                 0, 0,
4659                 0, 0,
4660                 0, 0,
4661                 GP_1_25_FN, FN_DACK0,
4662                 GP_1_24_FN, FN_IP7_31,
4663                 GP_1_23_FN, FN_IP4_1_0,
4664                 GP_1_22_FN, FN_WE1_N,
4665                 GP_1_21_FN, FN_WE0_N,
4666                 GP_1_20_FN, FN_IP3_31,
4667                 GP_1_19_FN, FN_IP3_30,
4668                 GP_1_18_FN, FN_IP3_29_27,
4669                 GP_1_17_FN, FN_IP3_26_24,
4670                 GP_1_16_FN, FN_IP3_23_21,
4671                 GP_1_15_FN, FN_IP3_20_18,
4672                 GP_1_14_FN, FN_IP3_17_15,
4673                 GP_1_13_FN, FN_IP3_14_13,
4674                 GP_1_12_FN, FN_IP3_12,
4675                 GP_1_11_FN, FN_IP3_11,
4676                 GP_1_10_FN, FN_IP3_10,
4677                 GP_1_9_FN, FN_IP3_9_8,
4678                 GP_1_8_FN, FN_IP3_7_6,
4679                 GP_1_7_FN, FN_IP3_5_4,
4680                 GP_1_6_FN, FN_IP3_3_2,
4681                 GP_1_5_FN, FN_IP3_1_0,
4682                 GP_1_4_FN, FN_IP2_31_30,
4683                 GP_1_3_FN, FN_IP2_29_27,
4684                 GP_1_2_FN, FN_IP2_26_24,
4685                 GP_1_1_FN, FN_IP2_23_21,
4686                 GP_1_0_FN, FN_IP2_20_18, }
4687         },
4688         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4689                 GP_2_31_FN, FN_IP6_7_6,
4690                 GP_2_30_FN, FN_IP6_5_4,
4691                 GP_2_29_FN, FN_IP6_3_2,
4692                 GP_2_28_FN, FN_IP6_1_0,
4693                 GP_2_27_FN, FN_IP5_31_30,
4694                 GP_2_26_FN, FN_IP5_29_28,
4695                 GP_2_25_FN, FN_IP5_27_26,
4696                 GP_2_24_FN, FN_IP5_25_24,
4697                 GP_2_23_FN, FN_IP5_23_22,
4698                 GP_2_22_FN, FN_IP5_21_20,
4699                 GP_2_21_FN, FN_IP5_19_18,
4700                 GP_2_20_FN, FN_IP5_17_16,
4701                 GP_2_19_FN, FN_IP5_15_14,
4702                 GP_2_18_FN, FN_IP5_13_12,
4703                 GP_2_17_FN, FN_IP5_11_9,
4704                 GP_2_16_FN, FN_IP5_8_6,
4705                 GP_2_15_FN, FN_IP5_5_4,
4706                 GP_2_14_FN, FN_IP5_3_2,
4707                 GP_2_13_FN, FN_IP5_1_0,
4708                 GP_2_12_FN, FN_IP4_31_30,
4709                 GP_2_11_FN, FN_IP4_29_28,
4710                 GP_2_10_FN, FN_IP4_27_26,
4711                 GP_2_9_FN, FN_IP4_25_23,
4712                 GP_2_8_FN, FN_IP4_22_20,
4713                 GP_2_7_FN, FN_IP4_19_18,
4714                 GP_2_6_FN, FN_IP4_17_16,
4715                 GP_2_5_FN, FN_IP4_15_14,
4716                 GP_2_4_FN, FN_IP4_13_12,
4717                 GP_2_3_FN, FN_IP4_11_10,
4718                 GP_2_2_FN, FN_IP4_9_8,
4719                 GP_2_1_FN, FN_IP4_7_5,
4720                 GP_2_0_FN, FN_IP4_4_2 }
4721         },
4722         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4723                 GP_3_31_FN, FN_IP8_22_20,
4724                 GP_3_30_FN, FN_IP8_19_17,
4725                 GP_3_29_FN, FN_IP8_16_15,
4726                 GP_3_28_FN, FN_IP8_14_12,
4727                 GP_3_27_FN, FN_IP8_11_9,
4728                 GP_3_26_FN, FN_IP8_8_6,
4729                 GP_3_25_FN, FN_IP8_5_3,
4730                 GP_3_24_FN, FN_IP8_2_0,
4731                 GP_3_23_FN, FN_IP7_29_27,
4732                 GP_3_22_FN, FN_IP7_26_24,
4733                 GP_3_21_FN, FN_IP7_23_21,
4734                 GP_3_20_FN, FN_IP7_20_18,
4735                 GP_3_19_FN, FN_IP7_17_15,
4736                 GP_3_18_FN, FN_IP7_14_12,
4737                 GP_3_17_FN, FN_IP7_11_9,
4738                 GP_3_16_FN, FN_IP7_8_6,
4739                 GP_3_15_FN, FN_IP7_5_3,
4740                 GP_3_14_FN, FN_IP7_2_0,
4741                 GP_3_13_FN, FN_IP6_31_29,
4742                 GP_3_12_FN, FN_IP6_28_26,
4743                 GP_3_11_FN, FN_IP6_25_23,
4744                 GP_3_10_FN, FN_IP6_22_20,
4745                 GP_3_9_FN, FN_IP6_19_17,
4746                 GP_3_8_FN, FN_IP6_16,
4747                 GP_3_7_FN, FN_IP6_15,
4748                 GP_3_6_FN, FN_IP6_14,
4749                 GP_3_5_FN, FN_IP6_13,
4750                 GP_3_4_FN, FN_IP6_12,
4751                 GP_3_3_FN, FN_IP6_11,
4752                 GP_3_2_FN, FN_IP6_10,
4753                 GP_3_1_FN, FN_IP6_9,
4754                 GP_3_0_FN, FN_IP6_8 }
4755         },
4756         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4757                 GP_4_31_FN, FN_IP11_17_16,
4758                 GP_4_30_FN, FN_IP11_15_14,
4759                 GP_4_29_FN, FN_IP11_13_11,
4760                 GP_4_28_FN, FN_IP11_10_8,
4761                 GP_4_27_FN, FN_IP11_7_6,
4762                 GP_4_26_FN, FN_IP11_5_3,
4763                 GP_4_25_FN, FN_IP11_2_0,
4764                 GP_4_24_FN, FN_IP10_31_30,
4765                 GP_4_23_FN, FN_IP10_29_27,
4766                 GP_4_22_FN, FN_IP10_26_24,
4767                 GP_4_21_FN, FN_IP10_23_21,
4768                 GP_4_20_FN, FN_IP10_20_18,
4769                 GP_4_19_FN, FN_IP10_17_15,
4770                 GP_4_18_FN, FN_IP10_14_12,
4771                 GP_4_17_FN, FN_IP10_11_9,
4772                 GP_4_16_FN, FN_IP10_8_6,
4773                 GP_4_15_FN, FN_IP10_5_3,
4774                 GP_4_14_FN, FN_IP10_2_0,
4775                 GP_4_13_FN, FN_IP9_30_28,
4776                 GP_4_12_FN, FN_IP9_27_25,
4777                 GP_4_11_FN, FN_IP9_24_22,
4778                 GP_4_10_FN, FN_IP9_21_19,
4779                 GP_4_9_FN, FN_IP9_18_17,
4780                 GP_4_8_FN, FN_IP9_16_15,
4781                 GP_4_7_FN, FN_IP9_14_12,
4782                 GP_4_6_FN, FN_IP9_11_9,
4783                 GP_4_5_FN, FN_IP9_8_6,
4784                 GP_4_4_FN, FN_IP9_5_3,
4785                 GP_4_3_FN, FN_IP9_2_0,
4786                 GP_4_2_FN, FN_IP8_31_29,
4787                 GP_4_1_FN, FN_IP8_28_26,
4788                 GP_4_0_FN, FN_IP8_25_23 }
4789         },
4790         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4791                 0, 0,
4792                 0, 0,
4793                 0, 0,
4794                 0, 0,
4795                 GP_5_27_FN, FN_USB1_OVC,
4796                 GP_5_26_FN, FN_USB1_PWEN,
4797                 GP_5_25_FN, FN_USB0_OVC,
4798                 GP_5_24_FN, FN_USB0_PWEN,
4799                 GP_5_23_FN, FN_IP13_26_24,
4800                 GP_5_22_FN, FN_IP13_23_21,
4801                 GP_5_21_FN, FN_IP13_20_18,
4802                 GP_5_20_FN, FN_IP13_17_15,
4803                 GP_5_19_FN, FN_IP13_14_12,
4804                 GP_5_18_FN, FN_IP13_11_9,
4805                 GP_5_17_FN, FN_IP13_8_6,
4806                 GP_5_16_FN, FN_IP13_5_3,
4807                 GP_5_15_FN, FN_IP13_2_0,
4808                 GP_5_14_FN, FN_IP12_29_27,
4809                 GP_5_13_FN, FN_IP12_26_24,
4810                 GP_5_12_FN, FN_IP12_23_21,
4811                 GP_5_11_FN, FN_IP12_20_18,
4812                 GP_5_10_FN, FN_IP12_17_15,
4813                 GP_5_9_FN, FN_IP12_14_13,
4814                 GP_5_8_FN, FN_IP12_12_11,
4815                 GP_5_7_FN, FN_IP12_10_9,
4816                 GP_5_6_FN, FN_IP12_8_6,
4817                 GP_5_5_FN, FN_IP12_5_3,
4818                 GP_5_4_FN, FN_IP12_2_0,
4819                 GP_5_3_FN, FN_IP11_29_27,
4820                 GP_5_2_FN, FN_IP11_26_24,
4821                 GP_5_1_FN, FN_IP11_23_21,
4822                 GP_5_0_FN, FN_IP11_20_18 }
4823         },
4824         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4825                 0, 0,
4826                 0, 0,
4827                 0, 0,
4828                 0, 0,
4829                 0, 0,
4830                 0, 0,
4831                 GP_6_25_FN, FN_IP0_21_20,
4832                 GP_6_24_FN, FN_IP0_19_18,
4833                 GP_6_23_FN, FN_IP0_17,
4834                 GP_6_22_FN, FN_IP0_16,
4835                 GP_6_21_FN, FN_IP0_15,
4836                 GP_6_20_FN, FN_IP0_14,
4837                 GP_6_19_FN, FN_IP0_13,
4838                 GP_6_18_FN, FN_IP0_12,
4839                 GP_6_17_FN, FN_IP0_11,
4840                 GP_6_16_FN, FN_IP0_10,
4841                 GP_6_15_FN, FN_IP0_9_8,
4842                 GP_6_14_FN, FN_IP0_0,
4843                 GP_6_13_FN, FN_SD1_DATA3,
4844                 GP_6_12_FN, FN_SD1_DATA2,
4845                 GP_6_11_FN, FN_SD1_DATA1,
4846                 GP_6_10_FN, FN_SD1_DATA0,
4847                 GP_6_9_FN, FN_SD1_CMD,
4848                 GP_6_8_FN, FN_SD1_CLK,
4849                 GP_6_7_FN, FN_SD0_WP,
4850                 GP_6_6_FN, FN_SD0_CD,
4851                 GP_6_5_FN, FN_SD0_DATA3,
4852                 GP_6_4_FN, FN_SD0_DATA2,
4853                 GP_6_3_FN, FN_SD0_DATA1,
4854                 GP_6_2_FN, FN_SD0_DATA0,
4855                 GP_6_1_FN, FN_SD0_CMD,
4856                 GP_6_0_FN, FN_SD0_CLK }
4857         },
4858         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4859                              2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4860                              2, 1, 1, 1, 1, 1, 1, 1, 1) {
4861                 /* IP0_31_30 [2] */
4862                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4863                 /* IP0_29_28 [2] */
4864                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4865                 /* IP0_27_26 [2] */
4866                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4867                 /* IP0_25 [1] */
4868                 FN_D2, FN_SCIFA3_TXD_B,
4869                 /* IP0_24 [1] */
4870                 FN_D1, FN_SCIFA3_RXD_B,
4871                 /* IP0_23_22 [2] */
4872                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4873                 /* IP0_21_20 [2] */
4874                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4875                 /* IP0_19_18 [2] */
4876                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4877                 /* IP0_17 [1] */
4878                 FN_MMC_D5, FN_SD2_WP,
4879                 /* IP0_16 [1] */
4880                 FN_MMC_D4, FN_SD2_CD,
4881                 /* IP0_15 [1] */
4882                 FN_MMC_D3, FN_SD2_DATA3,
4883                 /* IP0_14 [1] */
4884                 FN_MMC_D2, FN_SD2_DATA2,
4885                 /* IP0_13 [1] */
4886                 FN_MMC_D1, FN_SD2_DATA1,
4887                 /* IP0_12 [1] */
4888                 FN_MMC_D0, FN_SD2_DATA0,
4889                 /* IP0_11 [1] */
4890                 FN_MMC_CMD, FN_SD2_CMD,
4891                 /* IP0_10 [1] */
4892                 FN_MMC_CLK, FN_SD2_CLK,
4893                 /* IP0_9_8 [2] */
4894                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4895                 /* IP0_7 [1] */
4896                 0, 0,
4897                 /* IP0_6 [1] */
4898                 0, 0,
4899                 /* IP0_5 [1] */
4900                 0, 0,
4901                 /* IP0_4 [1] */
4902                 0, 0,
4903                 /* IP0_3 [1] */
4904                 0, 0,
4905                 /* IP0_2 [1] */
4906                 0, 0,
4907                 /* IP0_1 [1] */
4908                 0, 0,
4909                 /* IP0_0 [1] */
4910                 FN_SD1_CD, FN_CAN0_RX, }
4911         },
4912         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4913                              2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
4914                              2, 2) {
4915                 /* IP1_31_30 [2] */
4916                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4917                 /* IP1_29_28 [2] */
4918                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4919                 /* IP1_27 [1] */
4920                 FN_A4, FN_SCIFB0_TXD,
4921                 /* IP1_26 [1] */
4922                 FN_A3, FN_SCIFB0_SCK,
4923                 /* IP1_25 [1] */
4924                 0, 0,
4925                 /* IP1_24 [1] */
4926                 FN_A1, FN_SCIFB1_TXD,
4927                 /* IP1_23_22 [2] */
4928                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4929                 /* IP1_21_20 [2] */
4930                 FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
4931                 /* IP1_19_18 [2] */
4932                 FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
4933                 /* IP1_17_15 [3] */
4934                 FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
4935                 0, 0, 0,
4936                 /* IP1_14_13 [2] */
4937                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4938                 /* IP1_12_11 [2] */
4939                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4940                 /* IP1_10_8 [3] */
4941                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4942                 0, 0, 0,
4943                 /* IP1_7_6 [2] */
4944                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4945                 /* IP1_5_4 [2] */
4946                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4947                 /* IP1_3_2 [2] */
4948                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4949                 /* IP1_1_0 [2] */
4950                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
4951         },
4952         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4953                              2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4954                 /* IP2_31_30 [2] */
4955                 FN_A20, FN_SPCLK, 0, 0,
4956                 /* IP2_29_27 [3] */
4957                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4958                 0, 0, 0, 0,
4959                 /* IP2_26_24 [3] */
4960                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4961                 0, 0, 0, 0,
4962                 /* IP2_23_21 [3] */
4963                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4964                 0, 0, 0, 0,
4965                 /* IP2_20_18 [3] */
4966                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4967                 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4968                 /* IP2_17_16 [2] */
4969                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4970                 /* IP2_15_14 [2] */
4971                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4972                 /* IP2_13_12 [2] */
4973                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4974                 /* IP2_11_10 [2] */
4975                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4976                 /* IP2_9_8 [2] */
4977                 FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
4978                 /* IP2_7_6 [2] */
4979                 FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
4980                 /* IP2_5_4 [2] */
4981                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4982                 /* IP2_3_2 [2] */
4983                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4984                 /* IP2_1_0 [2] */
4985                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
4986         },
4987         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4988                              1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
4989                 /* IP3_31 [1] */
4990                 FN_RD_WR_N, FN_ATAG1_N,
4991                 /* IP3_30 [1] */
4992                 FN_RD_N, FN_ATACS11_N,
4993                 /* IP3_29_27 [3] */
4994                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4995                 0, 0, 0,
4996                 /* IP3_26_24 [3] */
4997                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4998                 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
4999                 /* IP3_23_21 [3] */
5000                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
5001                 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
5002                 /* IP3_20_18 [3] */
5003                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
5004                 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
5005                 /* IP3_17_15 [3] */
5006                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
5007                 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
5008                 /* IP3_14_13 [2] */
5009                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
5010                 /* IP3_12 [1] */
5011                 FN_EX_CS0_N, FN_VI1_DATA10,
5012                 /* IP3_11 [1] */
5013                 FN_CS1_N_A26, FN_VI1_DATA9,
5014                 /* IP3_10 [1] */
5015                 FN_CS0_N, FN_VI1_DATA8,
5016                 /* IP3_9_8 [2] */
5017                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
5018                 /* IP3_7_6 [2] */
5019                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
5020                 /* IP3_5_4 [2] */
5021                 FN_A23, FN_IO2, 0, FN_ATAWR1_N,
5022                 /* IP3_3_2 [2] */
5023                 FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
5024                 /* IP3_1_0 [2] */
5025                 FN_A21, FN_MOSI_IO0, 0, 0, }
5026         },
5027         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5028                              2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
5029                 /* IP4_31_30 [2] */
5030                 FN_DU0_DG4, FN_LCDOUT12, 0, 0,
5031                 /* IP4_29_28 [2] */
5032                 FN_DU0_DG3, FN_LCDOUT11, 0, 0,
5033                 /* IP4_27_26 [2] */
5034                 FN_DU0_DG2, FN_LCDOUT10, 0, 0,
5035                 /* IP4_25_23 [3] */
5036                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
5037                 0, 0, 0, 0,
5038                 /* IP4_22_20 [3] */
5039                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
5040                 0, 0, 0, 0,
5041                 /* IP4_19_18 [2] */
5042                 FN_DU0_DR7, FN_LCDOUT23, 0, 0,
5043                 /* IP4_17_16 [2] */
5044                 FN_DU0_DR6, FN_LCDOUT22, 0, 0,
5045                 /* IP4_15_14 [2] */
5046                 FN_DU0_DR5, FN_LCDOUT21, 0, 0,
5047                 /* IP4_13_12 [2] */
5048                 FN_DU0_DR4, FN_LCDOUT20, 0, 0,
5049                 /* IP4_11_10 [2] */
5050                 FN_DU0_DR3, FN_LCDOUT19, 0, 0,
5051                 /* IP4_9_8 [2] */
5052                 FN_DU0_DR2, FN_LCDOUT18, 0, 0,
5053                 /* IP4_7_5 [3] */
5054                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
5055                 0, 0, 0, 0,
5056                 /* IP4_4_2 [3] */
5057                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
5058                 0, 0, 0, 0,
5059                 /* IP4_1_0 [2] */
5060                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, }
5061         },
5062         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5063                              2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
5064                 /* IP5_31_30 [2] */
5065                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
5066                 /* IP5_29_28 [2] */
5067                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
5068                 /* IP5_27_26 [2] */
5069                 FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
5070                 /* IP5_25_24 [2] */
5071                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
5072                 /* IP5_23_22 [2] */
5073                 FN_DU0_DB7, FN_LCDOUT7, 0, 0,
5074                 /* IP5_21_20 [2] */
5075                 FN_DU0_DB6, FN_LCDOUT6, 0, 0,
5076                 /* IP5_19_18 [2] */
5077                 FN_DU0_DB5, FN_LCDOUT5, 0, 0,
5078                 /* IP5_17_16 [2] */
5079                 FN_DU0_DB4, FN_LCDOUT4, 0, 0,
5080                 /* IP5_15_14 [2] */
5081                 FN_DU0_DB3, FN_LCDOUT3, 0, 0,
5082                 /* IP5_13_12 [2] */
5083                 FN_DU0_DB2, FN_LCDOUT2, 0, 0,
5084                 /* IP5_11_9 [3] */
5085                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
5086                 FN_CAN0_TX_C, 0, 0, 0,
5087                 /* IP5_8_6 [3] */
5088                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
5089                 FN_CAN0_RX_C, 0, 0, 0,
5090                 /* IP5_5_4 [2] */
5091                 FN_DU0_DG7, FN_LCDOUT15, 0, 0,
5092                 /* IP5_3_2 [2] */
5093                 FN_DU0_DG6, FN_LCDOUT14, 0, 0,
5094                 /* IP5_1_0 [2] */
5095                 FN_DU0_DG5, FN_LCDOUT13, 0, 0, }
5096         },
5097         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5098                              3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5099                              2, 2) {
5100                 /* IP6_31_29 [3] */
5101                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
5102                 FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
5103                 /* IP6_28_26 [3] */
5104                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
5105                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
5106                 /* IP6_25_23 [3] */
5107                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
5108                 FN_AVB_COL, 0, 0, 0,
5109                 /* IP6_22_20 [3] */
5110                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
5111                 FN_AVB_RX_ER, 0, 0, 0,
5112                 /* IP6_19_17 [3] */
5113                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
5114                 FN_AVB_RXD7, 0, 0, 0,
5115                 /* IP6_16 [1] */
5116                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
5117                 /* IP6_15 [1] */
5118                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
5119                 /* IP6_14 [1] */
5120                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
5121                 /* IP6_13 [1] */
5122                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
5123                 /* IP6_12 [1] */
5124                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
5125                 /* IP6_11 [1] */
5126                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
5127                 /* IP6_10 [1] */
5128                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
5129                 /* IP6_9 [1] */
5130                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
5131                 /* IP6_8 [1] */
5132                 FN_VI0_CLK, FN_AVB_RX_CLK,
5133                 /* IP6_7_6 [2] */
5134                 FN_DU0_CDE, FN_QPOLB, 0, 0,
5135                 /* IP6_5_4 [2] */
5136                 FN_DU0_DISP, FN_QPOLA, 0, 0,
5137                 /* IP6_3_2 [2] */
5138                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
5139                 0,
5140                 /* IP6_1_0 [2] */
5141                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, }
5142         },
5143         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5144                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5145                 /* IP7_31 [1] */
5146                 FN_DREQ0_N, FN_SCIFB1_RXD,
5147                 /* IP7_30 [1] */
5148                 0, 0,
5149                 /* IP7_29_27 [3] */
5150                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
5151                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
5152                 /* IP7_26_24 [3] */
5153                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
5154                 FN_SSI_SCK6_B, 0, 0, 0,
5155                 /* IP7_23_21 [3] */
5156                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
5157                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
5158                 /* IP7_20_18 [3] */
5159                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
5160                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
5161                 /* IP7_17_15 [3] */
5162                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
5163                 FN_SSI_SCK5_B, 0, 0, 0,
5164                 /* IP7_14_12 [3] */
5165                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
5166                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
5167                 /* IP7_11_9 [3] */
5168                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
5169                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
5170                 /* IP7_8_6 [3] */
5171                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
5172                 FN_AVB_TXD2, FN_ADICHS0, 0, 0,
5173                 /* IP7_5_3 [3] */
5174                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
5175                 FN_AVB_TXD1, FN_ADICLK, 0, 0,
5176                 /* IP7_2_0 [3] */
5177                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
5178                 FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, }
5179         },
5180         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5181                              3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
5182                 /* IP8_31_29 [3] */
5183                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
5184                 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
5185                 /* IP8_28_26 [3] */
5186                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
5187                 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
5188                 /* IP8_25_23 [3] */
5189                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
5190                 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
5191                 /* IP8_22_20 [3] */
5192                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
5193                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
5194                 /* IP8_19_17 [3] */
5195                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
5196                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
5197                 /* IP8_16_15 [2] */
5198                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
5199                 /* IP8_14_12 [3] */
5200                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
5201                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
5202                 /* IP8_11_9 [3] */
5203                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
5204                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
5205                 /* IP8_8_6 [3] */
5206                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
5207                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
5208                 /* IP8_5_3 [3] */
5209                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
5210                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
5211                 /* IP8_2_0 [3] */
5212                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
5213                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
5214         },
5215         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5216                              1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
5217                 /* IP9_31 [1] */
5218                 0, 0,
5219                 /* IP9_30_28 [3] */
5220                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
5221                 FN_SSI_SDATA1_B, 0, 0, 0,
5222                 /* IP9_27_25 [3] */
5223                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
5224                 FN_SSI_WS1_B, 0, 0, 0,
5225                 /* IP9_24_22 [3] */
5226                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
5227                 FN_SSI_SCK1_B, 0, 0, 0,
5228                 /* IP9_21_19 [3] */
5229                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
5230                 FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
5231                 /* IP9_18_17 [2] */
5232                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
5233                 /* IP9_16_15 [2] */
5234                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
5235                 /* IP9_14_12 [3] */
5236                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
5237                 0, FN_FMIN_B, 0, 0,
5238                 /* IP9_11_9 [3] */
5239                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
5240                 0, FN_FMCLK_B, 0, 0,
5241                 /* IP9_8_6 [3] */
5242                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
5243                 0, FN_BPFCLK_B, 0, 0,
5244                 /* IP9_5_3 [3] */
5245                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
5246                 0, FN_TPUTO1_C, 0, 0,
5247                 /* IP9_2_0 [3] */
5248                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
5249                 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, }
5250         },
5251         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5252                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5253                 /* IP10_31_30 [2] */
5254                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
5255                 /* IP10_29_27 [3] */
5256                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
5257                 0, 0, 0, 0,
5258                 /* IP10_26_24 [3] */
5259                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
5260                 FN_SSI_SDATA4_B, 0, 0, 0,
5261                 /* IP10_23_21 [3] */
5262                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
5263                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
5264                 /* IP10_20_18 [3] */
5265                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
5266                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
5267                 /* IP10_17_15 [3] */
5268                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
5269                 FN_SSI_SDATA9_B, 0, 0, 0,
5270                 /* IP10_14_12 [3] */
5271                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
5272                 0, 0, 0, 0,
5273                 /* IP10_11_9 [3] */
5274                 FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
5275                 0, 0, 0, 0,
5276                 /* IP10_8_6 [3] */
5277                 FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
5278                 0, 0, 0, 0,
5279                 /* IP10_5_3 [3] */
5280                 FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
5281                 0, 0, 0, 0,
5282                 /* IP10_2_0 [3] */
5283                 FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
5284                 0, 0, 0, 0, }
5285         },
5286         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5287                              2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
5288                 /* IP11_31_30 [2] */
5289                 0, 0, 0, 0,
5290                 /* IP11_29_27 [3] */
5291                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
5292                 0, 0, 0, 0,
5293                 /* IP11_26_24 [3] */
5294                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
5295                 0, 0, 0, 0,
5296                 /* IP11_23_21 [3] */
5297                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
5298                 0, 0, 0, 0,
5299                 /* IP11_20_18 [3] */
5300                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
5301                 FN_CAN_CLK_D, 0, 0, 0,
5302                 /* IP11_17_16 [2] */
5303                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
5304                 /* IP11_15_14 [2] */
5305                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
5306                 /* IP11_13_11 [3] */
5307                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
5308                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
5309                 /* IP11_10_8 [3] */
5310                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
5311                 FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
5312                 /* IP11_7_6 [2] */
5313                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
5314                 /* IP11_5_3 [3] */
5315                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
5316                 0, 0, 0, 0,
5317                 /* IP11_2_0 [3] */
5318                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
5319                 0, 0, 0, 0, }
5320         },
5321         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5322                              2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
5323                 /* IP12_31_30 [2] */
5324                 0, 0, 0, 0,
5325                 /* IP12_29_27 [3] */
5326                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
5327                 FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
5328                 /* IP12_26_24 [3] */
5329                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
5330                 FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
5331                 /* IP12_23_21 [3] */
5332                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
5333                 FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
5334                 /* IP12_20_18 [3] */
5335                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
5336                 FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
5337                 /* IP12_17_15 [3] */
5338                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
5339                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
5340                 /* IP12_14_13 [2] */
5341                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
5342                 /* IP12_12_11 [2] */
5343                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
5344                 /* IP12_10_9 [2] */
5345                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
5346                 /* IP12_8_6 [3] */
5347                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
5348                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
5349                 /* IP12_5_3 [3] */
5350                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
5351                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
5352                 /* IP12_2_0 [3] */
5353                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
5354                 0, FN_DREQ1_N_B, 0, 0, }
5355         },
5356         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5357                              1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5358                 /* IP13_31 [1] */
5359                 0, 0,
5360                 /* IP13_30 [1] */
5361                 0, 0,
5362                 /* IP13_29 [1] */
5363                 0, 0,
5364                 /* IP13_28 [1] */
5365                 0, 0,
5366                 /* IP13_27 [1] */
5367                 0, 0,
5368                 /* IP13_26_24 [3] */
5369                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
5370                 FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
5371                 /* IP13_23_21 [3] */
5372                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
5373                 FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
5374                 /* IP13_20_18 [3] */
5375                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
5376                 FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
5377                 /* IP13_17_15 [3] */
5378                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
5379                 FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
5380                 /* IP13_14_12 [3] */
5381                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
5382                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
5383                 /* IP13_11_9 [3] */
5384                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
5385                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5386                 /* IP13_8_6 [3] */
5387                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
5388                 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5389                 /* IP13_5_3 [2] */
5390                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
5391                 FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5392                 /* IP13_2_0 [3] */
5393                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5394                 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
5395         },
5396         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5397                              2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3,
5398                              2, 1) {
5399                 /* SEL_ADG [2] */
5400                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5401                 /* RESERVED [1] */
5402                 0, 0,
5403                 /* SEL_CAN [2] */
5404                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
5405                 /* SEL_DARC [3] */
5406                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
5407                 FN_SEL_DARC_4, 0, 0, 0,
5408                 /* RESERVED [4] */
5409                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5410                 /* SEL_ETH [1] */
5411                 FN_SEL_ETH_0, FN_SEL_ETH_1,
5412                 /* RESERVED [1] */
5413                 0, 0,
5414                 /* SEL_IC200 [3] */
5415                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5416                 FN_SEL_I2C00_4, 0, 0, 0,
5417                 /* SEL_I2C01 [3] */
5418                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
5419                 FN_SEL_I2C01_4, 0, 0, 0,
5420                 /* SEL_I2C02 [3] */
5421                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
5422                 FN_SEL_I2C02_4, 0, 0, 0,
5423                 /* SEL_I2C03 [3] */
5424                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
5425                 FN_SEL_I2C03_4, 0, 0, 0,
5426                 /* SEL_I2C04 [3] */
5427                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
5428                 FN_SEL_I2C04_4, 0, 0, 0,
5429                 /* SEL_I2C05 [2] */
5430                 FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
5431                 /* RESERVED [1] */
5432                 0, 0, }
5433         },
5434         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5435                              2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
5436                              2, 2, 2, 1, 1, 2) {
5437                 /* SEL_IEB [2] */
5438                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5439                 /* SEL_IIC0 [2] */
5440                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
5441                 /* SEL_LBS [1] */
5442                 FN_SEL_LBS_0, FN_SEL_LBS_1,
5443                 /* SEL_MSI1 [1] */
5444                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
5445                 /* SEL_MSI2 [1] */
5446                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
5447                 /* SEL_RAD [1] */
5448                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5449                 /* SEL_RCN [1] */
5450                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5451                 /* SEL_RSP [1] */
5452                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5453                 /* SEL_SCIFA0 [2] */
5454                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
5455                 FN_SEL_SCIFA0_3,
5456                 /* SEL_SCIFA1 [2] */
5457                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5458                 /* SEL_SCIFA2 [1] */
5459                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5460                 /* SEL_SCIFA3 [1] */
5461                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
5462                 /* SEL_SCIFA4 [2] */
5463                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
5464                 FN_SEL_SCIFA4_3,
5465                 /* SEL_SCIFA5 [2] */
5466                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5467                 FN_SEL_SCIFA5_3,
5468                 /* RESERVED [1] */
5469                 0, 0,
5470                 /* SEL_TMU [1] */
5471                 FN_SEL_TMU_0, FN_SEL_TMU_1,
5472                 /* SEL_TSIF0 [2] */
5473                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5474                 /* SEL_CAN0 [2] */
5475                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5476                 /* SEL_CAN1 [2] */
5477                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5478                 /* SEL_HSCIF0 [1] */
5479                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5480                 /* SEL_HSCIF1 [1] */
5481                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5482                 /* RESERVED [2] */
5483                 0, 0, 0, 0, }
5484         },
5485         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5486                              2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
5487                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
5488                 /* SEL_SCIF0 [2] */
5489                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5490                 /* SEL_SCIF1 [2] */
5491                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5492                 /* SEL_SCIF2 [2] */
5493                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5494                 /* SEL_SCIF3 [1] */
5495                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5496                 /* SEL_SCIF4 [3] */
5497                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5498                 FN_SEL_SCIF4_4, 0, 0, 0,
5499                 /* SEL_SCIF5 [2] */
5500                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5501                 /* SEL_SSI1 [1] */
5502                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5503                 /* SEL_SSI2 [1] */
5504                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5505                 /* SEL_SSI4 [1] */
5506                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5507                 /* SEL_SSI5 [1] */
5508                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5509                 /* SEL_SSI6 [1] */
5510                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5511                 /* SEL_SSI7 [1] */
5512                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5513                 /* SEL_SSI8 [1] */
5514                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5515                 /* SEL_SSI9 [1] */
5516                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5517                 /* RESERVED [1] */
5518                 0, 0,
5519                 /* RESERVED [1] */
5520                 0, 0,
5521                 /* RESERVED [1] */
5522                 0, 0,
5523                 /* RESERVED [1] */
5524                 0, 0,
5525                 /* RESERVED [1] */
5526                 0, 0,
5527                 /* RESERVED [1] */
5528                 0, 0,
5529                 /* RESERVED [1] */
5530                 0, 0,
5531                 /* RESERVED [1] */
5532                 0, 0,
5533                 /* RESERVED [1] */
5534                 0, 0,
5535                 /* RESERVED [1] */
5536                 0, 0,
5537                 /* RESERVED [1] */
5538                 0, 0,
5539                 /* RESERVED [1] */
5540                 0, 0, }
5541         },
5542         { },
5543 };
5544
5545 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5546 {
5547         *pocctrl = 0xe606006c;
5548
5549         switch (pin & 0x1f) {
5550         case 6: return 23;
5551         case 7: return 16;
5552         case 14: return 15;
5553         case 15: return 8;
5554         case 0 ... 5:
5555         case 8 ... 13:
5556                 return 22 - (pin & 0x1f);
5557         case 16 ... 23:
5558                 return 47 - (pin & 0x1f);
5559         }
5560
5561         return -EINVAL;
5562 }
5563
5564 static const struct soc_device_attribute r8a7794_tdsel[] = {
5565         { .soc_id = "r8a7794", .revision = "ES1.0" },
5566         { /* sentinel */ }
5567 };
5568
5569 static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
5570 {
5571         /* Initialize TDSEL on old revisions */
5572         if (soc_device_match(r8a7794_tdsel))
5573                 sh_pfc_write(pfc, 0xe6060068, 0x55555500);
5574
5575         return 0;
5576 }
5577
5578 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5579         .init = r8a7794_pinmux_soc_init,
5580         .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5581 };
5582
5583 #ifdef CONFIG_PINCTRL_PFC_R8A7745
5584 const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5585         .name = "r8a77450_pfc",
5586         .ops = &r8a7794_pinmux_ops,
5587         .unlock_reg = 0xe6060000, /* PMMR */
5588
5589         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5590
5591         .pins = pinmux_pins,
5592         .nr_pins = ARRAY_SIZE(pinmux_pins),
5593         .groups = pinmux_groups,
5594         .nr_groups = ARRAY_SIZE(pinmux_groups),
5595         .functions = pinmux_functions,
5596         .nr_functions = ARRAY_SIZE(pinmux_functions),
5597
5598         .cfg_regs = pinmux_config_regs,
5599
5600         .pinmux_data = pinmux_data,
5601         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5602 };
5603 #endif
5604
5605 #ifdef CONFIG_PINCTRL_PFC_R8A7794
5606 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5607         .name = "r8a77940_pfc",
5608         .ops = &r8a7794_pinmux_ops,
5609         .unlock_reg = 0xe6060000, /* PMMR */
5610
5611         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5612
5613         .pins = pinmux_pins,
5614         .nr_pins = ARRAY_SIZE(pinmux_pins),
5615         .groups = pinmux_groups,
5616         .nr_groups = ARRAY_SIZE(pinmux_groups),
5617         .functions = pinmux_functions,
5618         .nr_functions = ARRAY_SIZE(pinmux_functions),
5619
5620         .cfg_regs = pinmux_config_regs,
5621
5622         .pinmux_data = pinmux_data,
5623         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5624 };
5625 #endif