2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio.h>
15 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
29 #include "../pinctrl-utils.h"
31 #define PMIC_GPIO_ADDRESS_RANGE 0x100
33 /* type and subtype registers base address offsets */
34 #define PMIC_GPIO_REG_TYPE 0x4
35 #define PMIC_GPIO_REG_SUBTYPE 0x5
37 /* GPIO peripheral type and subtype out_values */
38 #define PMIC_GPIO_TYPE 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
44 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
46 #define PMIC_MPP_REG_RT_STS 0x10
47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
49 /* control register base address offsets */
50 #define PMIC_GPIO_REG_MODE_CTL 0x40
51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
56 #define PMIC_GPIO_REG_EN_CTL 0x46
57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
59 /* PMIC_GPIO_REG_MODE_CTL */
60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
72 /* PMIC_GPIO_REG_DIG_VIN_CTL */
73 #define PMIC_GPIO_REG_VIN_SHIFT 0
74 #define PMIC_GPIO_REG_VIN_MASK 0x7
76 /* PMIC_GPIO_REG_DIG_PULL_CTL */
77 #define PMIC_GPIO_REG_PULL_SHIFT 0
78 #define PMIC_GPIO_REG_PULL_MASK 0x7
80 #define PMIC_GPIO_PULL_DOWN 4
81 #define PMIC_GPIO_PULL_DISABLE 5
83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
88 /* PMIC_GPIO_REG_DIG_IN_CTL */
89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
93 /* PMIC_GPIO_REG_DIG_OUT_CTL */
94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
100 * Output type - indicates pin should be configured as push-pull,
101 * open drain or open source.
103 #define PMIC_GPIO_OUT_BUF_CMOS 0
104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
107 /* PMIC_GPIO_REG_EN_CTL */
108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
110 #define PMIC_GPIO_PHYSICAL_OFFSET 1
112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
115 /* Qualcomm specific pin configurations */
116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
122 /* The index of each function in pmic_gpio_functions[] array */
123 enum pmic_gpio_func_index {
124 PMIC_GPIO_FUNC_INDEX_NORMAL,
125 PMIC_GPIO_FUNC_INDEX_PAIRED,
126 PMIC_GPIO_FUNC_INDEX_FUNC1,
127 PMIC_GPIO_FUNC_INDEX_FUNC2,
128 PMIC_GPIO_FUNC_INDEX_FUNC3,
129 PMIC_GPIO_FUNC_INDEX_FUNC4,
130 PMIC_GPIO_FUNC_INDEX_DTEST1,
131 PMIC_GPIO_FUNC_INDEX_DTEST2,
132 PMIC_GPIO_FUNC_INDEX_DTEST3,
133 PMIC_GPIO_FUNC_INDEX_DTEST4,
137 * struct pmic_gpio_pad - keep current GPIO settings
138 * @base: Address base in SPMI device.
139 * @irq: IRQ number which this GPIO generate.
140 * @is_enabled: Set to false when GPIO should be put in high Z state.
141 * @out_value: Cached pin output value
142 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
143 * open-drain or open-source mode.
144 * @output_enabled: Set to true if GPIO output logic is enabled.
145 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
148 * @num_sources: Number of power-sources supported by this GPIO.
149 * @power_source: Current power-source used.
150 * @buffer_type: Push-pull, open-drain or open-source.
151 * @pullup: Constant current which flow trough GPIO output buffer.
152 * @strength: No, Low, Medium, High
153 * @function: See pmic_gpio_functions[]
154 * @atest: the ATEST selection for GPIO analog-pass-through mode
155 * @dtest_buffer: the DTEST buffer selection for digital input mode.
157 struct pmic_gpio_pad {
167 unsigned int num_sources;
168 unsigned int power_source;
169 unsigned int buffer_type;
171 unsigned int strength;
172 unsigned int function;
174 unsigned int dtest_buffer;
177 struct pmic_gpio_state {
180 struct pinctrl_dev *ctrl;
181 struct gpio_chip chip;
184 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
192 #ifdef CONFIG_DEBUG_FS
193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
202 static const char *const pmic_gpio_groups[] = {
203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
210 static const char *const pmic_gpio_functions[] = {
211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
223 static int pmic_gpio_read(struct pmic_gpio_state *state,
224 struct pmic_gpio_pad *pad, unsigned int addr)
229 ret = regmap_read(state->map, pad->base + addr, &val);
231 dev_err(state->dev, "read 0x%x failed\n", addr);
238 static int pmic_gpio_write(struct pmic_gpio_state *state,
239 struct pmic_gpio_pad *pad, unsigned int addr,
244 ret = regmap_write(state->map, pad->base + addr, val);
246 dev_err(state->dev, "write 0x%x failed\n", addr);
251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
253 /* Every PIN is a group */
254 return pctldev->desc->npins;
257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
260 return pctldev->desc->pins[pin].name;
263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 const unsigned **pins, unsigned *num_pins)
266 *pins = &pctldev->desc->pins[pin].number;
271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 .get_groups_count = pmic_gpio_get_groups_count,
273 .get_group_name = pmic_gpio_get_group_name,
274 .get_group_pins = pmic_gpio_get_group_pins,
275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
276 .dt_free_map = pinctrl_utils_free_map,
279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
281 return ARRAY_SIZE(pmic_gpio_functions);
284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
287 return pmic_gpio_functions[function];
290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
292 const char *const **groups,
293 unsigned *const num_qgroups)
295 *groups = pmic_gpio_groups;
296 *num_qgroups = pctldev->desc->npins;
300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 struct pmic_gpio_pad *pad;
308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 pr_err("function: %d is not defined\n", function);
313 pad = pctldev->desc->pins[pin].drv_data;
315 * Non-LV/MV subtypes only support 2 special functions,
316 * offsetting the dtestx function values by 2
318 if (!pad->lv_mv_type) {
319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 pr_err("LV/MV subtype doesn't have func3/func4\n");
324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 PMIC_GPIO_FUNC_INDEX_FUNC3);
329 pad->function = function;
331 if (pad->analog_pass)
332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 else if (pad->output_enabled && pad->input_enabled)
334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 else if (pad->output_enabled)
336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
338 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
340 if (pad->lv_mv_type) {
341 ret = pmic_gpio_write(state, pad,
342 PMIC_GPIO_REG_MODE_CTL, val);
346 val = pad->atest - 1;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 ret = pmic_gpio_write(state, pad,
357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
375 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 .get_functions_count = pmic_gpio_get_functions_count,
377 .get_function_name = pmic_gpio_get_function_name,
378 .get_function_groups = pmic_gpio_get_function_groups,
379 .set_mux = pmic_gpio_set_mux,
382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 unsigned int pin, unsigned long *config)
385 unsigned param = pinconf_to_config_param(*config);
386 struct pmic_gpio_pad *pad;
389 pad = pctldev->desc->pins[pin].drv_data;
392 case PIN_CONFIG_DRIVE_PUSH_PULL:
393 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
395 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
396 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
398 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
399 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
401 case PIN_CONFIG_BIAS_PULL_DOWN:
402 arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
404 case PIN_CONFIG_BIAS_DISABLE:
405 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
407 case PIN_CONFIG_BIAS_PULL_UP:
408 arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
410 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
411 arg = !pad->is_enabled;
413 case PIN_CONFIG_POWER_SOURCE:
414 arg = pad->power_source;
416 case PIN_CONFIG_INPUT_ENABLE:
417 arg = pad->input_enabled;
419 case PIN_CONFIG_OUTPUT:
420 arg = pad->out_value;
422 case PMIC_GPIO_CONF_PULL_UP:
425 case PMIC_GPIO_CONF_STRENGTH:
428 case PMIC_GPIO_CONF_ATEST:
431 case PMIC_GPIO_CONF_ANALOG_PASS:
432 arg = pad->analog_pass;
434 case PMIC_GPIO_CONF_DTEST_BUFFER:
435 arg = pad->dtest_buffer;
441 *config = pinconf_to_config_packed(param, arg);
445 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
446 unsigned long *configs, unsigned nconfs)
448 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
449 struct pmic_gpio_pad *pad;
454 pad = pctldev->desc->pins[pin].drv_data;
456 for (i = 0; i < nconfs; i++) {
457 param = pinconf_to_config_param(configs[i]);
458 arg = pinconf_to_config_argument(configs[i]);
461 case PIN_CONFIG_DRIVE_PUSH_PULL:
462 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
464 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
465 if (!pad->have_buffer)
467 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
469 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
470 if (!pad->have_buffer)
472 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
474 case PIN_CONFIG_BIAS_DISABLE:
475 pad->pullup = PMIC_GPIO_PULL_DISABLE;
477 case PIN_CONFIG_BIAS_PULL_UP:
478 pad->pullup = PMIC_GPIO_PULL_UP_30;
480 case PIN_CONFIG_BIAS_PULL_DOWN:
482 pad->pullup = PMIC_GPIO_PULL_DOWN;
484 pad->pullup = PMIC_GPIO_PULL_DISABLE;
486 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
487 pad->is_enabled = false;
489 case PIN_CONFIG_POWER_SOURCE:
490 if (arg >= pad->num_sources)
492 pad->power_source = arg;
494 case PIN_CONFIG_INPUT_ENABLE:
495 pad->input_enabled = arg ? true : false;
497 case PIN_CONFIG_OUTPUT:
498 pad->output_enabled = true;
499 pad->out_value = arg;
501 case PMIC_GPIO_CONF_PULL_UP:
502 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
506 case PMIC_GPIO_CONF_STRENGTH:
507 if (arg > PMIC_GPIO_STRENGTH_LOW)
511 case PMIC_GPIO_CONF_ATEST:
512 if (!pad->lv_mv_type || arg > 4)
516 case PMIC_GPIO_CONF_ANALOG_PASS:
517 if (!pad->lv_mv_type)
519 pad->analog_pass = true;
521 case PMIC_GPIO_CONF_DTEST_BUFFER:
524 pad->dtest_buffer = arg;
531 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
533 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
537 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
539 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
543 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
544 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
546 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
550 if (pad->dtest_buffer == 0) {
553 if (pad->lv_mv_type) {
554 val = pad->dtest_buffer - 1;
555 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
557 val = BIT(pad->dtest_buffer - 1);
560 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
564 if (pad->analog_pass)
565 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
566 else if (pad->output_enabled && pad->input_enabled)
567 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
568 else if (pad->output_enabled)
569 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
571 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
573 if (pad->lv_mv_type) {
574 ret = pmic_gpio_write(state, pad,
575 PMIC_GPIO_REG_MODE_CTL, val);
579 val = pad->atest - 1;
580 ret = pmic_gpio_write(state, pad,
581 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
586 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
588 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
589 ret = pmic_gpio_write(state, pad,
590 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
594 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
595 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
596 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
598 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
606 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
607 struct seq_file *s, unsigned pin)
609 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
610 struct pmic_gpio_pad *pad;
611 int ret, val, function;
613 static const char *const biases[] = {
614 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
615 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
617 static const char *const buffer_types[] = {
618 "push-pull", "open-drain", "open-source"
620 static const char *const strengths[] = {
621 "no", "high", "medium", "low"
624 pad = pctldev->desc->pins[pin].drv_data;
626 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
628 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
630 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
633 if (pad->input_enabled) {
634 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
638 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
639 pad->out_value = ret;
642 * For the non-LV/MV subtypes only 2 special functions are
643 * available, offsetting the dtest function values by 2.
645 function = pad->function;
646 if (!pad->lv_mv_type &&
647 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
648 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
649 PMIC_GPIO_FUNC_INDEX_FUNC3;
651 if (pad->analog_pass)
652 seq_puts(s, " analog-pass");
654 seq_printf(s, " %-4s",
655 pad->output_enabled ? "out" : "in");
656 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
657 seq_printf(s, " vin-%d", pad->power_source);
658 seq_printf(s, " %-27s", biases[pad->pullup]);
659 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
660 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
661 seq_printf(s, " %-7s", strengths[pad->strength]);
662 seq_printf(s, " atest-%d", pad->atest);
663 seq_printf(s, " dtest-%d", pad->dtest_buffer);
667 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
669 .pin_config_group_get = pmic_gpio_config_get,
670 .pin_config_group_set = pmic_gpio_config_set,
671 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
674 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
676 struct pmic_gpio_state *state = gpiochip_get_data(chip);
677 unsigned long config;
679 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
681 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
684 static int pmic_gpio_direction_output(struct gpio_chip *chip,
685 unsigned pin, int val)
687 struct pmic_gpio_state *state = gpiochip_get_data(chip);
688 unsigned long config;
690 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
692 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
695 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
697 struct pmic_gpio_state *state = gpiochip_get_data(chip);
698 struct pmic_gpio_pad *pad;
701 pad = state->ctrl->desc->pins[pin].drv_data;
703 if (!pad->is_enabled)
706 if (pad->input_enabled) {
707 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
711 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
714 return !!pad->out_value;
717 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
719 struct pmic_gpio_state *state = gpiochip_get_data(chip);
720 unsigned long config;
722 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
724 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
727 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
728 const struct of_phandle_args *gpio_desc,
731 if (chip->of_gpio_n_cells < 2)
735 *flags = gpio_desc->args[1];
737 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
740 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
742 struct pmic_gpio_state *state = gpiochip_get_data(chip);
743 struct pmic_gpio_pad *pad;
745 pad = state->ctrl->desc->pins[pin].drv_data;
750 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
752 struct pmic_gpio_state *state = gpiochip_get_data(chip);
755 for (i = 0; i < chip->ngpio; i++) {
756 pmic_gpio_config_dbg_show(state->ctrl, s, i);
761 static const struct gpio_chip pmic_gpio_gpio_template = {
762 .direction_input = pmic_gpio_direction_input,
763 .direction_output = pmic_gpio_direction_output,
764 .get = pmic_gpio_get,
765 .set = pmic_gpio_set,
766 .request = gpiochip_generic_request,
767 .free = gpiochip_generic_free,
768 .of_xlate = pmic_gpio_of_xlate,
769 .to_irq = pmic_gpio_to_irq,
770 .dbg_show = pmic_gpio_dbg_show,
773 static int pmic_gpio_populate(struct pmic_gpio_state *state,
774 struct pmic_gpio_pad *pad)
776 int type, subtype, val, dir;
778 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
782 if (type != PMIC_GPIO_TYPE) {
783 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
788 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
793 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
794 pad->have_buffer = true;
795 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
796 pad->num_sources = 4;
798 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
799 pad->have_buffer = true;
800 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
801 pad->num_sources = 8;
803 case PMIC_GPIO_SUBTYPE_GPIO_LV:
804 pad->num_sources = 1;
805 pad->have_buffer = true;
806 pad->lv_mv_type = true;
808 case PMIC_GPIO_SUBTYPE_GPIO_MV:
809 pad->num_sources = 2;
810 pad->have_buffer = true;
811 pad->lv_mv_type = true;
814 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
818 if (pad->lv_mv_type) {
819 val = pmic_gpio_read(state, pad,
820 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
824 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
825 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
827 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
831 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
833 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
837 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
839 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
840 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
841 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
842 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
846 case PMIC_GPIO_MODE_DIGITAL_INPUT:
847 pad->input_enabled = true;
848 pad->output_enabled = false;
850 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
851 pad->input_enabled = false;
852 pad->output_enabled = true;
854 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
855 pad->input_enabled = true;
856 pad->output_enabled = true;
858 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
859 if (!pad->lv_mv_type)
861 pad->analog_pass = true;
864 dev_err(state->dev, "unknown GPIO direction\n");
868 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
872 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
873 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
875 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
879 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
880 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
882 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
886 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
888 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
889 else if (!pad->lv_mv_type)
890 pad->dtest_buffer = ffs(val);
892 pad->dtest_buffer = 0;
894 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
898 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
899 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
901 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
902 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
904 if (pad->lv_mv_type) {
905 val = pmic_gpio_read(state, pad,
906 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
909 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
912 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
913 pad->is_enabled = true;
917 static int pmic_gpio_probe(struct platform_device *pdev)
919 struct device *dev = &pdev->dev;
920 struct pinctrl_pin_desc *pindesc;
921 struct pinctrl_desc *pctrldesc;
922 struct pmic_gpio_pad *pad, *pads;
923 struct pmic_gpio_state *state;
927 ret = of_property_read_u32(dev->of_node, "reg", ®);
929 dev_err(dev, "missing base address");
933 npins = platform_irq_count(pdev);
939 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
941 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
945 platform_set_drvdata(pdev, state);
947 state->dev = &pdev->dev;
948 state->map = dev_get_regmap(dev->parent, NULL);
950 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
954 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
958 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
962 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
963 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
964 pctrldesc->confops = &pmic_gpio_pinconf_ops;
965 pctrldesc->owner = THIS_MODULE;
966 pctrldesc->name = dev_name(dev);
967 pctrldesc->pins = pindesc;
968 pctrldesc->npins = npins;
969 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
970 pctrldesc->custom_params = pmic_gpio_bindings;
971 #ifdef CONFIG_DEBUG_FS
972 pctrldesc->custom_conf_items = pmic_conf_items;
975 for (i = 0; i < npins; i++, pindesc++) {
977 pindesc->drv_data = pad;
979 pindesc->name = pmic_gpio_groups[i];
981 pad->irq = platform_get_irq(pdev, i);
985 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
987 ret = pmic_gpio_populate(state, pad);
992 state->chip = pmic_gpio_gpio_template;
993 state->chip.parent = dev;
994 state->chip.base = -1;
995 state->chip.ngpio = npins;
996 state->chip.label = dev_name(dev);
997 state->chip.of_gpio_n_cells = 2;
998 state->chip.can_sleep = false;
1000 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1001 if (IS_ERR(state->ctrl))
1002 return PTR_ERR(state->ctrl);
1004 ret = gpiochip_add_data(&state->chip, state);
1006 dev_err(state->dev, "can't add gpio chip\n");
1010 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
1012 dev_err(dev, "failed to add pin range\n");
1019 gpiochip_remove(&state->chip);
1023 static int pmic_gpio_remove(struct platform_device *pdev)
1025 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1027 gpiochip_remove(&state->chip);
1031 static const struct of_device_id pmic_gpio_of_match[] = {
1032 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
1033 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
1034 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
1035 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
1036 { .compatible = "qcom,spmi-gpio" }, /* Generic */
1040 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1042 static struct platform_driver pmic_gpio_driver = {
1044 .name = "qcom-spmi-gpio",
1045 .of_match_table = pmic_gpio_of_match,
1047 .probe = pmic_gpio_probe,
1048 .remove = pmic_gpio_remove,
1051 module_platform_driver(pmic_gpio_driver);
1053 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1054 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1055 MODULE_ALIAS("platform:qcom-spmi-gpio");
1056 MODULE_LICENSE("GPL v2");