drivers/pinctrl/pinctrl-u300.c

   1 /*
   2  * Driver for the U300 pin controller
   3  *
   4  * Based on the original U300 padmux functions
   5  * Copyright (C) 2009-2011 ST-Ericsson AB
   6  * Author: Martin Persson <martin.persson@stericsson.com>
   7  * Author: Linus Walleij <linus.walleij@linaro.org>
   8  *
   9  * The DB3350 design and control registers are oriented around pads rather than
  10  * pins, so we enumerate the pads we can mux rather than actual pins. The pads
  11  * are connected to different pins in different packaging types, so it would
  12  * be confusing.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/mod_devicetable.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/slab.h>
  20 #include <linux/err.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include "pinctrl-coh901.h"
  26
  27 /*
  28  * Register definitions for the U300 Padmux control registers in the
  29  * system controller
  30  */
  31
  32 /* PAD MUX Control register 1 (LOW) 16bit (R/W) */
  33 #define U300_SYSCON_PMC1LR                                      0x007C
  34 #define U300_SYSCON_PMC1LR_MASK                                 0xFFFF
  35 #define U300_SYSCON_PMC1LR_CDI_MASK                             0xC000
  36 #define U300_SYSCON_PMC1LR_CDI_CDI                              0x0000
  37 #define U300_SYSCON_PMC1LR_CDI_EMIF                             0x4000
  38 /* For BS335 */
  39 #define U300_SYSCON_PMC1LR_CDI_CDI2                             0x8000
  40 #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO                   0xC000
  41 /* For BS365 */
  42 #define U300_SYSCON_PMC1LR_CDI_GPIO                             0x8000
  43 #define U300_SYSCON_PMC1LR_CDI_WCDMA                            0xC000
  44 /* Common defs */
  45 #define U300_SYSCON_PMC1LR_PDI_MASK                             0x3000
  46 #define U300_SYSCON_PMC1LR_PDI_PDI                              0x0000
  47 #define U300_SYSCON_PMC1LR_PDI_EGG                              0x1000
  48 #define U300_SYSCON_PMC1LR_PDI_WCDMA                            0x3000
  49 #define U300_SYSCON_PMC1LR_MMCSD_MASK                           0x0C00
  50 #define U300_SYSCON_PMC1LR_MMCSD_MMCSD                          0x0000
  51 #define U300_SYSCON_PMC1LR_MMCSD_MSPRO                          0x0400
  52 #define U300_SYSCON_PMC1LR_MMCSD_DSP                            0x0800
  53 #define U300_SYSCON_PMC1LR_MMCSD_WCDMA                          0x0C00
  54 #define U300_SYSCON_PMC1LR_ETM_MASK                             0x0300
  55 #define U300_SYSCON_PMC1LR_ETM_ACC                              0x0000
  56 #define U300_SYSCON_PMC1LR_ETM_APP                              0x0100
  57 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK                      0x00C0
  58 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC                    0x0000
  59 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF                      0x0040
  60 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM                     0x0080
  61 #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB                0x00C0
  62 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK                      0x0030
  63 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC                    0x0000
  64 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF                      0x0010
  65 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM                     0x0020
  66 #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI                      0x0030
  67 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK                      0x000C
  68 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC                    0x0000
  69 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF                      0x0004
  70 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM                     0x0008
  71 #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI                      0x000C
  72 #define U300_SYSCON_PMC1LR_EMIF_1_MASK                          0x0003
  73 #define U300_SYSCON_PMC1LR_EMIF_1_STATIC                        0x0000
  74 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0                        0x0001
  75 #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1                        0x0002
  76 #define U300_SYSCON_PMC1LR_EMIF_1                               0x0003
  77 /* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
  78 #define U300_SYSCON_PMC1HR                                      0x007E
  79 #define U300_SYSCON_PMC1HR_MASK                                 0xFFFF
  80 #define U300_SYSCON_PMC1HR_MISC_2_MASK                          0xC000
  81 #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO                      0x0000
  82 #define U300_SYSCON_PMC1HR_MISC_2_MSPRO                         0x4000
  83 #define U300_SYSCON_PMC1HR_MISC_2_DSP                           0x8000
  84 #define U300_SYSCON_PMC1HR_MISC_2_AAIF                          0xC000
  85 #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK                      0x3000
  86 #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO                  0x0000
  87 #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF                      0x1000
  88 #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP                       0x2000
  89 #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF                      0x3000
  90 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK                      0x0C00
  91 #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO                  0x0000
  92 #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC                       0x0400
  93 #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP                       0x0800
  94 #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF                      0x0C00
  95 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK                    0x0300
  96 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO                0x0000
  97 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI                     0x0100
  98 #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF                    0x0300
  99 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK                    0x00C0
 100 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO                0x0000
 101 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI                     0x0040
 102 #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF                    0x00C0
 103 #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK                       0x0030
 104 #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO                   0x0000
 105 #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI                        0x0010
 106 #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP                        0x0020
 107 #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF                       0x0030
 108 #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK                     0x000C
 109 #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO                 0x0000
 110 #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0                    0x0004
 111 #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS                  0x0008
 112 #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF                     0x000C
 113 #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK                     0x0003
 114 #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO                 0x0000
 115 #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0                    0x0001
 116 #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF                     0x0003
 117 /* Padmux 2 control */
 118 #define U300_SYSCON_PMC2R                                       0x100
 119 #define U300_SYSCON_PMC2R_APP_MISC_0_MASK                       0x00C0
 120 #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO                   0x0000
 121 #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM                 0x0040
 122 #define U300_SYSCON_PMC2R_APP_MISC_0_MMC                        0x0080
 123 #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2                       0x00C0
 124 #define U300_SYSCON_PMC2R_APP_MISC_1_MASK                       0x0300
 125 #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO                   0x0000
 126 #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM                 0x0100
 127 #define U300_SYSCON_PMC2R_APP_MISC_1_MMC                        0x0200
 128 #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2                       0x0300
 129 #define U300_SYSCON_PMC2R_APP_MISC_2_MASK                       0x0C00
 130 #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO                   0x0000
 131 #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM                 0x0400
 132 #define U300_SYSCON_PMC2R_APP_MISC_2_MMC                        0x0800
 133 #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2                       0x0C00
 134 #define U300_SYSCON_PMC2R_APP_MISC_3_MASK                       0x3000
 135 #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO                   0x0000
 136 #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM                 0x1000
 137 #define U300_SYSCON_PMC2R_APP_MISC_3_MMC                        0x2000
 138 #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2                       0x3000
 139 #define U300_SYSCON_PMC2R_APP_MISC_4_MASK                       0xC000
 140 #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO                   0x0000
 141 #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM                 0x4000
 142 #define U300_SYSCON_PMC2R_APP_MISC_4_MMC                        0x8000
 143 #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO                   0xC000
 144 /* TODO: More SYSCON registers missing */
 145 #define U300_SYSCON_PMC3R                                       0x10C
 146 #define U300_SYSCON_PMC3R_APP_MISC_11_MASK                      0xC000
 147 #define U300_SYSCON_PMC3R_APP_MISC_11_SPI                       0x4000
 148 #define U300_SYSCON_PMC3R_APP_MISC_10_MASK                      0x3000
 149 #define U300_SYSCON_PMC3R_APP_MISC_10_SPI                       0x1000
 150 /* TODO: Missing other configs */
 151 #define U300_SYSCON_PMC4R                                       0x168
 152 #define U300_SYSCON_PMC4R_APP_MISC_12_MASK                      0x0003
 153 #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO                  0x0000
 154 #define U300_SYSCON_PMC4R_APP_MISC_13_MASK                      0x000C
 155 #define U300_SYSCON_PMC4R_APP_MISC_13_CDI                       0x0000
 156 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA                      0x0004
 157 #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2                     0x0008
 158 #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO                  0x000C
 159 #define U300_SYSCON_PMC4R_APP_MISC_14_MASK                      0x0030
 160 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI                       0x0000
 161 #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA                      0x0010
 162 #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2                      0x0020
 163 #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO                  0x0030
 164 #define U300_SYSCON_PMC4R_APP_MISC_16_MASK                      0x0300
 165 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13               0x0000
 166 #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS             0x0100
 167 #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N       0x0200
 168
 169 #define DRIVER_NAME "pinctrl-u300"
 170
 171 /*
 172  * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
 173  * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
 174  * Data taken from the PadRing chart, arranged like this:
 175  *
 176  *   0 ..... 104
 177  * 466        105
 178  *   .        .
 179  *   .        .
 180  * 358        224
 181  *  357 .... 225
 182  */
 183 #define U300_NUM_PADS 467
 184
 185 /* Pad names for the pinmux subsystem */
 186 static const struct pinctrl_pin_desc u300_pads[] = {
 187         /* Pads along the top edge of the chip */
 188         PINCTRL_PIN(0, "P PAD VDD 28"),
 189         PINCTRL_PIN(1, "P PAD GND 28"),
 190         PINCTRL_PIN(2, "PO SIM RST N"),
 191         PINCTRL_PIN(3, "VSSIO 25"),
 192         PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
 193         PINCTRL_PIN(5, "PWR VSSCOMMON"),
 194         PINCTRL_PIN(6, "PI ADC I1 POS"),
 195         PINCTRL_PIN(7, "PI ADC I1 NEG"),
 196         PINCTRL_PIN(8, "PWR VSSAD0"),
 197         PINCTRL_PIN(9, "PWR VCCAD0"),
 198         PINCTRL_PIN(10, "PI ADC Q1 NEG"),
 199         PINCTRL_PIN(11, "PI ADC Q1 POS"),
 200         PINCTRL_PIN(12, "PWR VDDAD"),
 201         PINCTRL_PIN(13, "PWR GNDAD"),
 202         PINCTRL_PIN(14, "PI ADC I2 POS"),
 203         PINCTRL_PIN(15, "PI ADC I2 NEG"),
 204         PINCTRL_PIN(16, "PWR VSSAD1"),
 205         PINCTRL_PIN(17, "PWR VCCAD1"),
 206         PINCTRL_PIN(18, "PI ADC Q2 NEG"),
 207         PINCTRL_PIN(19, "PI ADC Q2 POS"),
 208         PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
 209         PINCTRL_PIN(21, "PWR VCCGPAD"),
 210         PINCTRL_PIN(22, "PI TX POW"),
 211         PINCTRL_PIN(23, "PWR VSSGPAD"),
 212         PINCTRL_PIN(24, "PO DAC I POS"),
 213         PINCTRL_PIN(25, "PO DAC I NEG"),
 214         PINCTRL_PIN(26, "PO DAC Q POS"),
 215         PINCTRL_PIN(27, "PO DAC Q NEG"),
 216         PINCTRL_PIN(28, "PWR VSSDA"),
 217         PINCTRL_PIN(29, "PWR VCCDA"),
 218         PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
 219         PINCTRL_PIN(31, "P PAD VDDIO 11"),
 220         PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
 221         PINCTRL_PIN(33, "PI PLL 26 VCONT"),
 222         PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
 223         PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
 224         PINCTRL_PIN(36, "VDDA PLL ESD"),
 225         PINCTRL_PIN(37, "VSSA PLL ESD"),
 226         PINCTRL_PIN(38, "VSS PLL"),
 227         PINCTRL_PIN(39, "VDDC PLL"),
 228         PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
 229         PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
 230         PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
 231         PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
 232         PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
 233         PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
 234         PINCTRL_PIN(46, "P PAD VSSIO 11"),
 235         PINCTRL_PIN(47, "P PAD VSSIO 12"),
 236         PINCTRL_PIN(48, "PI POW RST N"),
 237         PINCTRL_PIN(49, "VDDC IO"),
 238         PINCTRL_PIN(50, "P PAD VDDIO 16"),
 239         PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
 240         PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
 241         PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
 242         PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
 243         PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
 244         PINCTRL_PIN(56, "PO GSM PA ENABLE"),
 245         PINCTRL_PIN(57, "PO RF DATA STRB"),
 246         PINCTRL_PIN(58, "PO RF DATA2"),
 247         PINCTRL_PIN(59, "PIO RF DATA1"),
 248         PINCTRL_PIN(60, "PIO RF DATA0"),
 249         PINCTRL_PIN(61, "P PAD VDD 11"),
 250         PINCTRL_PIN(62, "P PAD GND 11"),
 251         PINCTRL_PIN(63, "P PAD VSSIO 16"),
 252         PINCTRL_PIN(64, "P PAD VDDIO 18"),
 253         PINCTRL_PIN(65, "PO RF CTRL STRB2"),
 254         PINCTRL_PIN(66, "PO RF CTRL STRB1"),
 255         PINCTRL_PIN(67, "PO RF CTRL STRB0"),
 256         PINCTRL_PIN(68, "PIO RF CTRL DATA"),
 257         PINCTRL_PIN(69, "PO RF CTRL CLK"),
 258         PINCTRL_PIN(70, "PO TX ADC STRB"),
 259         PINCTRL_PIN(71, "PO ANT SW 2"),
 260         PINCTRL_PIN(72, "PO ANT SW 3"),
 261         PINCTRL_PIN(73, "PO ANT SW 0"),
 262         PINCTRL_PIN(74, "PO ANT SW 1"),
 263         PINCTRL_PIN(75, "PO M CLKRQ"),
 264         PINCTRL_PIN(76, "PI M CLK"),
 265         PINCTRL_PIN(77, "PI RTC CLK"),
 266         PINCTRL_PIN(78, "P PAD VDD 8"),
 267         PINCTRL_PIN(79, "P PAD GND 8"),
 268         PINCTRL_PIN(80, "P PAD VSSIO 13"),
 269         PINCTRL_PIN(81, "P PAD VDDIO 13"),
 270         PINCTRL_PIN(82, "PO SYS 1 CLK"),
 271         PINCTRL_PIN(83, "PO SYS 2 CLK"),
 272         PINCTRL_PIN(84, "PO SYS 0 CLK"),
 273         PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
 274         PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
 275         PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
 276         PINCTRL_PIN(88, "PO RESOUT2 RST N"),
 277         PINCTRL_PIN(89, "PO RESOUT1 RST N"),
 278         PINCTRL_PIN(90, "PO RESOUT0 RST N"),
 279         PINCTRL_PIN(91, "PI SERVICE N"),
 280         PINCTRL_PIN(92, "P PAD VDD 29"),
 281         PINCTRL_PIN(93, "P PAD GND 29"),
 282         PINCTRL_PIN(94, "P PAD VSSIO 8"),
 283         PINCTRL_PIN(95, "P PAD VDDIO 8"),
 284         PINCTRL_PIN(96, "PI EXT IRQ1 N"),
 285         PINCTRL_PIN(97, "PI EXT IRQ0 N"),
 286         PINCTRL_PIN(98, "PIO DC ON"),
 287         PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
 288         PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
 289         PINCTRL_PIN(101, "P PAD VDD 12"),
 290         PINCTRL_PIN(102, "P PAD GND 12"),
 291         PINCTRL_PIN(103, "P PAD VSSIO 14"),
 292         PINCTRL_PIN(104, "P PAD VDDIO 14"),
 293         /* Pads along the right edge of the chip */
 294         PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
 295         PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
 296         PINCTRL_PIN(107, "PO KEY OUT0"),
 297         PINCTRL_PIN(108, "PO KEY OUT1"),
 298         PINCTRL_PIN(109, "PO KEY OUT2"),
 299         PINCTRL_PIN(110, "PO KEY OUT3"),
 300         PINCTRL_PIN(111, "PO KEY OUT4"),
 301         PINCTRL_PIN(112, "PI KEY IN0"),
 302         PINCTRL_PIN(113, "PI KEY IN1"),
 303         PINCTRL_PIN(114, "PI KEY IN2"),
 304         PINCTRL_PIN(115, "P PAD VDDIO 15"),
 305         PINCTRL_PIN(116, "P PAD VSSIO 15"),
 306         PINCTRL_PIN(117, "P PAD GND 13"),
 307         PINCTRL_PIN(118, "P PAD VDD 13"),
 308         PINCTRL_PIN(119, "PI KEY IN3"),
 309         PINCTRL_PIN(120, "PI KEY IN4"),
 310         PINCTRL_PIN(121, "PI KEY IN5"),
 311         PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
 312         PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
 313         PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
 314         PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
 315         PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
 316         PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
 317         PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
 318         PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
 319         PINCTRL_PIN(130, "P PAD VDD 17"),
 320         PINCTRL_PIN(131, "P PAD GND 17"),
 321         PINCTRL_PIN(132, "P PAD VSSIO 19"),
 322         PINCTRL_PIN(133, "P PAD VDDIO 19"),
 323         PINCTRL_PIN(134, "UART0 RTS"),
 324         PINCTRL_PIN(135, "UART0 CTS"),
 325         PINCTRL_PIN(136, "UART0 TX"),
 326         PINCTRL_PIN(137, "UART0 RX"),
 327         PINCTRL_PIN(138, "PIO ACC SPI DO"),
 328         PINCTRL_PIN(139, "PIO ACC SPI DI"),
 329         PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
 330         PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
 331         PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
 332         PINCTRL_PIN(143, "PIO ACC SPI CLK"),
 333         PINCTRL_PIN(144, "PO PDI EXT RST N"),
 334         PINCTRL_PIN(145, "P PAD VDDIO 22"),
 335         PINCTRL_PIN(146, "P PAD VSSIO 22"),
 336         PINCTRL_PIN(147, "P PAD GND 18"),
 337         PINCTRL_PIN(148, "P PAD VDD 18"),
 338         PINCTRL_PIN(149, "PIO PDI C0"),
 339         PINCTRL_PIN(150, "PIO PDI C1"),
 340         PINCTRL_PIN(151, "PIO PDI C2"),
 341         PINCTRL_PIN(152, "PIO PDI C3"),
 342         PINCTRL_PIN(153, "PIO PDI C4"),
 343         PINCTRL_PIN(154, "PIO PDI C5"),
 344         PINCTRL_PIN(155, "PIO PDI D0"),
 345         PINCTRL_PIN(156, "PIO PDI D1"),
 346         PINCTRL_PIN(157, "PIO PDI D2"),
 347         PINCTRL_PIN(158, "PIO PDI D3"),
 348         PINCTRL_PIN(159, "P PAD VDDIO 21"),
 349         PINCTRL_PIN(160, "P PAD VSSIO 21"),
 350         PINCTRL_PIN(161, "PIO PDI D4"),
 351         PINCTRL_PIN(162, "PIO PDI D5"),
 352         PINCTRL_PIN(163, "PIO PDI D6"),
 353         PINCTRL_PIN(164, "PIO PDI D7"),
 354         PINCTRL_PIN(165, "PIO MS INS"),
 355         PINCTRL_PIN(166, "MMC DATA DIR LS"),
 356         PINCTRL_PIN(167, "MMC DATA 3"),
 357         PINCTRL_PIN(168, "MMC DATA 2"),
 358         PINCTRL_PIN(169, "MMC DATA 1"),
 359         PINCTRL_PIN(170, "MMC DATA 0"),
 360         PINCTRL_PIN(171, "MMC CMD DIR LS"),
 361         PINCTRL_PIN(172, "P PAD VDD 27"),
 362         PINCTRL_PIN(173, "P PAD GND 27"),
 363         PINCTRL_PIN(174, "P PAD VSSIO 20"),
 364         PINCTRL_PIN(175, "P PAD VDDIO 20"),
 365         PINCTRL_PIN(176, "MMC CMD"),
 366         PINCTRL_PIN(177, "MMC CLK"),
 367         PINCTRL_PIN(178, "PIO APP GPIO 14"),
 368         PINCTRL_PIN(179, "PIO APP GPIO 13"),
 369         PINCTRL_PIN(180, "PIO APP GPIO 11"),
 370         PINCTRL_PIN(181, "PIO APP GPIO 25"),
 371         PINCTRL_PIN(182, "PIO APP GPIO 24"),
 372         PINCTRL_PIN(183, "PIO APP GPIO 23"),
 373         PINCTRL_PIN(184, "PIO APP GPIO 22"),
 374         PINCTRL_PIN(185, "PIO APP GPIO 21"),
 375         PINCTRL_PIN(186, "PIO APP GPIO 20"),
 376         PINCTRL_PIN(187, "P PAD VDD 19"),
 377         PINCTRL_PIN(188, "P PAD GND 19"),
 378         PINCTRL_PIN(189, "P PAD VSSIO 23"),
 379         PINCTRL_PIN(190, "P PAD VDDIO 23"),
 380         PINCTRL_PIN(191, "PIO APP GPIO 19"),
 381         PINCTRL_PIN(192, "PIO APP GPIO 18"),
 382         PINCTRL_PIN(193, "PIO APP GPIO 17"),
 383         PINCTRL_PIN(194, "PIO APP GPIO 16"),
 384         PINCTRL_PIN(195, "PI CI D1"),
 385         PINCTRL_PIN(196, "PI CI D0"),
 386         PINCTRL_PIN(197, "PI CI HSYNC"),
 387         PINCTRL_PIN(198, "PI CI VSYNC"),
 388         PINCTRL_PIN(199, "PI CI EXT CLK"),
 389         PINCTRL_PIN(200, "PO CI EXT RST N"),
 390         PINCTRL_PIN(201, "P PAD VSSIO 43"),
 391         PINCTRL_PIN(202, "P PAD VDDIO 43"),
 392         PINCTRL_PIN(203, "PI CI D6"),
 393         PINCTRL_PIN(204, "PI CI D7"),
 394         PINCTRL_PIN(205, "PI CI D2"),
 395         PINCTRL_PIN(206, "PI CI D3"),
 396         PINCTRL_PIN(207, "PI CI D4"),
 397         PINCTRL_PIN(208, "PI CI D5"),
 398         PINCTRL_PIN(209, "PI CI D8"),
 399         PINCTRL_PIN(210, "PI CI D9"),
 400         PINCTRL_PIN(211, "P PAD VDD 20"),
 401         PINCTRL_PIN(212, "P PAD GND 20"),
 402         PINCTRL_PIN(213, "P PAD VSSIO 24"),
 403         PINCTRL_PIN(214, "P PAD VDDIO 24"),
 404         PINCTRL_PIN(215, "P PAD VDDIO 26"),
 405         PINCTRL_PIN(216, "PO EMIF 1 A26"),
 406         PINCTRL_PIN(217, "PO EMIF 1 A25"),
 407         PINCTRL_PIN(218, "P PAD VSSIO 26"),
 408         PINCTRL_PIN(219, "PO EMIF 1 A24"),
 409         PINCTRL_PIN(220, "PO EMIF 1 A23"),
 410         /* Pads along the bottom edge of the chip */
 411         PINCTRL_PIN(221, "PO EMIF 1 A22"),
 412         PINCTRL_PIN(222, "PO EMIF 1 A21"),
 413         PINCTRL_PIN(223, "P PAD VDD 21"),
 414         PINCTRL_PIN(224, "P PAD GND 21"),
 415         PINCTRL_PIN(225, "P PAD VSSIO 27"),
 416         PINCTRL_PIN(226, "P PAD VDDIO 27"),
 417         PINCTRL_PIN(227, "PO EMIF 1 A20"),
 418         PINCTRL_PIN(228, "PO EMIF 1 A19"),
 419         PINCTRL_PIN(229, "PO EMIF 1 A18"),
 420         PINCTRL_PIN(230, "PO EMIF 1 A17"),
 421         PINCTRL_PIN(231, "P PAD VDDIO 28"),
 422         PINCTRL_PIN(232, "P PAD VSSIO 28"),
 423         PINCTRL_PIN(233, "PO EMIF 1 A16"),
 424         PINCTRL_PIN(234, "PIO EMIF 1 D15"),
 425         PINCTRL_PIN(235, "PO EMIF 1 A15"),
 426         PINCTRL_PIN(236, "PIO EMIF 1 D14"),
 427         PINCTRL_PIN(237, "P PAD VDD 22"),
 428         PINCTRL_PIN(238, "P PAD GND 22"),
 429         PINCTRL_PIN(239, "P PAD VSSIO 29"),
 430         PINCTRL_PIN(240, "P PAD VDDIO 29"),
 431         PINCTRL_PIN(241, "PO EMIF 1 A14"),
 432         PINCTRL_PIN(242, "PIO EMIF 1 D13"),
 433         PINCTRL_PIN(243, "PO EMIF 1 A13"),
 434         PINCTRL_PIN(244, "PIO EMIF 1 D12"),
 435         PINCTRL_PIN(245, "P PAD VSSIO 30"),
 436         PINCTRL_PIN(246, "P PAD VDDIO 30"),
 437         PINCTRL_PIN(247, "PO EMIF 1 A12"),
 438         PINCTRL_PIN(248, "PIO EMIF 1 D11"),
 439         PINCTRL_PIN(249, "PO EMIF 1 A11"),
 440         PINCTRL_PIN(250, "PIO EMIF 1 D10"),
 441         PINCTRL_PIN(251, "P PAD VSSIO 31"),
 442         PINCTRL_PIN(252, "P PAD VDDIO 31"),
 443         PINCTRL_PIN(253, "PO EMIF 1 A10"),
 444         PINCTRL_PIN(254, "PIO EMIF 1 D09"),
 445         PINCTRL_PIN(255, "PO EMIF 1 A09"),
 446         PINCTRL_PIN(256, "P PAD VDDIO 32"),
 447         PINCTRL_PIN(257, "P PAD VSSIO 32"),
 448         PINCTRL_PIN(258, "P PAD GND 24"),
 449         PINCTRL_PIN(259, "P PAD VDD 24"),
 450         PINCTRL_PIN(260, "PIO EMIF 1 D08"),
 451         PINCTRL_PIN(261, "PO EMIF 1 A08"),
 452         PINCTRL_PIN(262, "PIO EMIF 1 D07"),
 453         PINCTRL_PIN(263, "PO EMIF 1 A07"),
 454         PINCTRL_PIN(264, "P PAD VDDIO 33"),
 455         PINCTRL_PIN(265, "P PAD VSSIO 33"),
 456         PINCTRL_PIN(266, "PIO EMIF 1 D06"),
 457         PINCTRL_PIN(267, "PO EMIF 1 A06"),
 458         PINCTRL_PIN(268, "PIO EMIF 1 D05"),
 459         PINCTRL_PIN(269, "PO EMIF 1 A05"),
 460         PINCTRL_PIN(270, "P PAD VDDIO 34"),
 461         PINCTRL_PIN(271, "P PAD VSSIO 34"),
 462         PINCTRL_PIN(272, "PIO EMIF 1 D04"),
 463         PINCTRL_PIN(273, "PO EMIF 1 A04"),
 464         PINCTRL_PIN(274, "PIO EMIF 1 D03"),
 465         PINCTRL_PIN(275, "PO EMIF 1 A03"),
 466         PINCTRL_PIN(276, "P PAD VDDIO 35"),
 467         PINCTRL_PIN(277, "P PAD VSSIO 35"),
 468         PINCTRL_PIN(278, "P PAD GND 23"),
 469         PINCTRL_PIN(279, "P PAD VDD 23"),
 470         PINCTRL_PIN(280, "PIO EMIF 1 D02"),
 471         PINCTRL_PIN(281, "PO EMIF 1 A02"),
 472         PINCTRL_PIN(282, "PIO EMIF 1 D01"),
 473         PINCTRL_PIN(283, "PO EMIF 1 A01"),
 474         PINCTRL_PIN(284, "P PAD VDDIO 36"),
 475         PINCTRL_PIN(285, "P PAD VSSIO 36"),
 476         PINCTRL_PIN(286, "PIO EMIF 1 D00"),
 477         PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
 478         PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
 479         PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
 480         PINCTRL_PIN(290, "P PAD VDDIO 37"),
 481         PINCTRL_PIN(291, "P PAD VSSIO 37"),
 482         PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
 483         PINCTRL_PIN(293, "PO EMIF 1 OE N"),
 484         PINCTRL_PIN(294, "PO EMIF 1 WE N"),
 485         PINCTRL_PIN(295, "P PAD VDDIO 38"),
 486         PINCTRL_PIN(296, "P PAD VSSIO 38"),
 487         PINCTRL_PIN(297, "PO EMIF 1 CLK"),
 488         PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
 489         PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
 490         PINCTRL_PIN(300, "P PAD VDDIO 42"),
 491         PINCTRL_PIN(301, "P PAD VSSIO 42"),
 492         PINCTRL_PIN(302, "P PAD GND 31"),
 493         PINCTRL_PIN(303, "P PAD VDD 31"),
 494         PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
 495         PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
 496         PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
 497         PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
 498         PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
 499         PINCTRL_PIN(309, "P PAD VDD 25"),
 500         PINCTRL_PIN(310, "P PAD GND 25"),
 501         PINCTRL_PIN(311, "P PAD VSSIO 39"),
 502         PINCTRL_PIN(312, "P PAD VDDIO 39"),
 503         PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
 504         PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
 505         PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
 506         PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
 507         PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
 508         PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
 509         PINCTRL_PIN(319, "P PAD VDD 30"),
 510         PINCTRL_PIN(320, "P PAD GND 30"),
 511         PINCTRL_PIN(321, "P PAD VSSIO 44"),
 512         PINCTRL_PIN(322, "P PAD VDDIO 44"),
 513         PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
 514         PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
 515         PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
 516         PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
 517         PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
 518         PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
 519         PINCTRL_PIN(329, "P PAD VDD 26"),
 520         PINCTRL_PIN(330, "P PAD GND 26"),
 521         PINCTRL_PIN(331, "P PAD VSSIO 40"),
 522         PINCTRL_PIN(332, "P PAD VDDIO 40"),
 523         PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
 524         PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
 525         PINCTRL_PIN(335, "PO ETM TRACE CLK"),
 526         PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
 527         PINCTRL_PIN(337, "PIO ACC GPIO 33"),
 528         PINCTRL_PIN(338, "PIO ACC GPIO 32"),
 529         PINCTRL_PIN(339, "PIO ACC GPIO 30"),
 530         PINCTRL_PIN(340, "PIO ACC GPIO 29"),
 531         PINCTRL_PIN(341, "P PAD VDDIO 17"),
 532         PINCTRL_PIN(342, "P PAD VSSIO 17"),
 533         PINCTRL_PIN(343, "P PAD GND 15"),
 534         PINCTRL_PIN(344, "P PAD VDD 15"),
 535         PINCTRL_PIN(345, "PIO ACC GPIO 28"),
 536         PINCTRL_PIN(346, "PIO ACC GPIO 27"),
 537         PINCTRL_PIN(347, "PIO ACC GPIO 16"),
 538         PINCTRL_PIN(348, "PI TAP TMS"),
 539         PINCTRL_PIN(349, "PI TAP TDI"),
 540         PINCTRL_PIN(350, "PO TAP TDO"),
 541         PINCTRL_PIN(351, "PI TAP RST N"),
 542         /* Pads along the left edge of the chip */
 543         PINCTRL_PIN(352, "PI EMU MODE 0"),
 544         PINCTRL_PIN(353, "PO TAP RET CLK"),
 545         PINCTRL_PIN(354, "PI TAP CLK"),
 546         PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
 547         PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
 548         PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
 549         PINCTRL_PIN(358, "P PAD VDDIO 1"),
 550         PINCTRL_PIN(359, "P PAD VSSIO 1"),
 551         PINCTRL_PIN(360, "P PAD GND 1"),
 552         PINCTRL_PIN(361, "P PAD VDD 1"),
 553         PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
 554         PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
 555         PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
 556         PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
 557         PINCTRL_PIN(366, "PIO EMIF 0 D15"),
 558         PINCTRL_PIN(367, "PO EMIF 0 A15"),
 559         PINCTRL_PIN(368, "PIO EMIF 0 D14"),
 560         PINCTRL_PIN(369, "PO EMIF 0 A14"),
 561         PINCTRL_PIN(370, "PIO EMIF 0 D13"),
 562         PINCTRL_PIN(371, "PO EMIF 0 A13"),
 563         PINCTRL_PIN(372, "P PAD VDDIO 2"),
 564         PINCTRL_PIN(373, "P PAD VSSIO 2"),
 565         PINCTRL_PIN(374, "P PAD GND 2"),
 566         PINCTRL_PIN(375, "P PAD VDD 2"),
 567         PINCTRL_PIN(376, "PIO EMIF 0 D12"),
 568         PINCTRL_PIN(377, "PO EMIF 0 A12"),
 569         PINCTRL_PIN(378, "PIO EMIF 0 D11"),
 570         PINCTRL_PIN(379, "PO EMIF 0 A11"),
 571         PINCTRL_PIN(380, "PIO EMIF 0 D10"),
 572         PINCTRL_PIN(381, "PO EMIF 0 A10"),
 573         PINCTRL_PIN(382, "PIO EMIF 0 D09"),
 574         PINCTRL_PIN(383, "PO EMIF 0 A09"),
 575         PINCTRL_PIN(384, "PIO EMIF 0 D08"),
 576         PINCTRL_PIN(385, "PO EMIF 0 A08"),
 577         PINCTRL_PIN(386, "PIO EMIF 0 D07"),
 578         PINCTRL_PIN(387, "PO EMIF 0 A07"),
 579         PINCTRL_PIN(388, "P PAD VDDIO 3"),
 580         PINCTRL_PIN(389, "P PAD VSSIO 3"),
 581         PINCTRL_PIN(390, "P PAD GND 3"),
 582         PINCTRL_PIN(391, "P PAD VDD 3"),
 583         PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
 584         PINCTRL_PIN(393, "PIO EMIF 0 D06"),
 585         PINCTRL_PIN(394, "PO EMIF 0 A06"),
 586         PINCTRL_PIN(395, "PIO EMIF 0 D05"),
 587         PINCTRL_PIN(396, "PO EMIF 0 A05"),
 588         PINCTRL_PIN(397, "PIO EMIF 0 D04"),
 589         PINCTRL_PIN(398, "PO EMIF 0 A04"),
 590         PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
 591         PINCTRL_PIN(400, "PWR VDDCO AF"),
 592         PINCTRL_PIN(401, "PWR EFUSE HV1"),
 593         PINCTRL_PIN(402, "P PAD VSSIO 4"),
 594         PINCTRL_PIN(403, "P PAD VDDIO 4"),
 595         PINCTRL_PIN(404, "P PAD GND 4"),
 596         PINCTRL_PIN(405, "P PAD VDD 4"),
 597         PINCTRL_PIN(406, "PIO EMIF 0 D03"),
 598         PINCTRL_PIN(407, "PO EMIF 0 A03"),
 599         PINCTRL_PIN(408, "PWR EFUSE HV2"),
 600         PINCTRL_PIN(409, "PWR EFUSE HV3"),
 601         PINCTRL_PIN(410, "PIO EMIF 0 D02"),
 602         PINCTRL_PIN(411, "PO EMIF 0 A02"),
 603         PINCTRL_PIN(412, "PIO EMIF 0 D01"),
 604         PINCTRL_PIN(413, "P PAD VDDIO 5"),
 605         PINCTRL_PIN(414, "P PAD VSSIO 5"),
 606         PINCTRL_PIN(415, "P PAD GND 5"),
 607         PINCTRL_PIN(416, "P PAD VDD 5"),
 608         PINCTRL_PIN(417, "PO EMIF 0 A01"),
 609         PINCTRL_PIN(418, "PIO EMIF 0 D00"),
 610         PINCTRL_PIN(419, "IF 0 SD CLK"),
 611         PINCTRL_PIN(420, "APP SPI CLK"),
 612         PINCTRL_PIN(421, "APP SPI DO"),
 613         PINCTRL_PIN(422, "APP SPI DI"),
 614         PINCTRL_PIN(423, "APP SPI CS0"),
 615         PINCTRL_PIN(424, "APP SPI CS1"),
 616         PINCTRL_PIN(425, "APP SPI CS2"),
 617         PINCTRL_PIN(426, "PIO APP GPIO 10"),
 618         PINCTRL_PIN(427, "P PAD VDDIO 41"),
 619         PINCTRL_PIN(428, "P PAD VSSIO 41"),
 620         PINCTRL_PIN(429, "P PAD GND 6"),
 621         PINCTRL_PIN(430, "P PAD VDD 6"),
 622         PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
 623         PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
 624         PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
 625         PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
 626         PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
 627         PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
 628         PINCTRL_PIN(437, "PIO USB PU"),
 629         PINCTRL_PIN(438, "PIO USB SP"),
 630         PINCTRL_PIN(439, "PIO USB DAT VP"),
 631         PINCTRL_PIN(440, "PIO USB SE0 VM"),
 632         PINCTRL_PIN(441, "PIO USB OE"),
 633         PINCTRL_PIN(442, "PIO USB SUSP"),
 634         PINCTRL_PIN(443, "P PAD VSSIO 6"),
 635         PINCTRL_PIN(444, "P PAD VDDIO 6"),
 636         PINCTRL_PIN(445, "PIO USB PUEN"),
 637         PINCTRL_PIN(446, "PIO ACC UART0 RX"),
 638         PINCTRL_PIN(447, "PIO ACC UART0 TX"),
 639         PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
 640         PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
 641         PINCTRL_PIN(450, "PIO ACC UART3 RX"),
 642         PINCTRL_PIN(451, "PIO ACC UART3 TX"),
 643         PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
 644         PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
 645         PINCTRL_PIN(454, "PIO ACC IRDA TX"),
 646         PINCTRL_PIN(455, "P PAD VDDIO 7"),
 647         PINCTRL_PIN(456, "P PAD VSSIO 7"),
 648         PINCTRL_PIN(457, "P PAD GND 7"),
 649         PINCTRL_PIN(458, "P PAD VDD 7"),
 650         PINCTRL_PIN(459, "PIO ACC IRDA RX"),
 651         PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
 652         PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
 653         PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
 654         PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
 655         PINCTRL_PIN(464, "PO SIM CLK"),
 656         PINCTRL_PIN(465, "PIO ACC IRDA SD"),
 657         PINCTRL_PIN(466, "PIO SIM DATA"),
 658 };
 659
 660 /**
 661  * @dev: a pointer back to containing device
 662  * @virtbase: the offset to the controller in virtual memory
 663  */
 664 struct u300_pmx {
 665         struct device *dev;
 666         struct pinctrl_dev *pctl;
 667         void __iomem *virtbase;
 668 };
 669
 670 /**
 671  * u300_pmx_registers - the array of registers read/written for each pinmux
 672  * shunt setting
 673  */
 674 static const u32 u300_pmx_registers[] = {
 675         U300_SYSCON_PMC1LR,
 676         U300_SYSCON_PMC1HR,
 677         U300_SYSCON_PMC2R,
 678         U300_SYSCON_PMC3R,
 679         U300_SYSCON_PMC4R,
 680 };
 681
 682 /**
 683  * struct u300_pin_group - describes a U300 pin group
 684  * @name: the name of this specific pin group
 685  * @pins: an array of discrete physical pins used in this group, taken
 686  *      from the driver-local pin enumeration space
 687  * @num_pins: the number of pins in this group array, i.e. the number of
 688  *      elements in .pins so we can iterate over that array
 689  */
 690 struct u300_pin_group {
 691         const char *name;
 692         const unsigned int *pins;
 693         const unsigned num_pins;
 694 };
 695
 696 /**
 697  * struct pmx_onmask - mask bits to enable/disable padmux
 698  * @mask: mask bits to disable
 699  * @val: mask bits to enable
 700  *
 701  * onmask lazy dog:
 702  * onmask = {
 703  *   {"PMC1LR" mask, "PMC1LR" value},
 704  *   {"PMC1HR" mask, "PMC1HR" value},
 705  *   {"PMC2R"  mask, "PMC2R"  value},
 706  *   {"PMC3R"  mask, "PMC3R"  value},
 707  *   {"PMC4R"  mask, "PMC4R"  value}
 708  * }
 709  */
 710 struct u300_pmx_mask {
 711         u16 mask;
 712         u16 bits;
 713 };
 714
 715 /* The chip power pins are VDD, GND, VDDIO and VSSIO */
 716 static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
 717         64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
 718         118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
 719         175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
 720         224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
 721         257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
 722         291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
 723         321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
 724         372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
 725         415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
 726 static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
 727         367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
 728         385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
 729         417, 418 };
 730 static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
 731         229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
 732         253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
 733         275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
 734         304, 305, 306, 307, 308, 313, 314, 315 };
 735 static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
 736 static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
 737 static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
 738
 739 static const struct u300_pmx_mask emif0_mask[] = {
 740         {0, 0},
 741         {0, 0},
 742         {0, 0},
 743         {0, 0},
 744         {0, 0},
 745 };
 746
 747 static const struct u300_pmx_mask emif1_mask[] = {
 748         /*
 749          * This connects the SDRAM to CS2 and a NAND flash to
 750          * CS0 on the EMIF.
 751          */
 752         {
 753                 U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
 754                 U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
 755                 U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
 756                 U300_SYSCON_PMC1LR_EMIF_1_MASK,
 757                 U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
 758                 U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
 759                 U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
 760                 U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
 761         },
 762         {0, 0},
 763         {0, 0},
 764         {0, 0},
 765         {0, 0},
 766 };
 767
 768 static const struct u300_pmx_mask uart0_mask[] = {
 769         {0, 0},
 770         {
 771                 U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
 772                 U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
 773                 U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
 774                 U300_SYSCON_PMC1HR_APP_UART0_2_UART0
 775         },
 776         {0, 0},
 777         {0, 0},
 778         {0, 0},
 779 };
 780
 781 static const struct u300_pmx_mask mmc0_mask[] = {
 782         { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
 783         {0, 0},
 784         {0, 0},
 785         {0, 0},
 786         { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
 787           U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
 788 };
 789
 790 static const struct u300_pmx_mask spi0_mask[] = {
 791         {0, 0},
 792         {
 793                 U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
 794                 U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
 795                 U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
 796                 U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
 797                 U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
 798                 U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
 799         },
 800         {0, 0},
 801         {0, 0},
 802         {0, 0}
 803 };
 804
 805 static const struct u300_pin_group u300_pin_groups[] = {
 806         {
 807                 .name = "powergrp",
 808                 .pins = power_pins,
 809                 .num_pins = ARRAY_SIZE(power_pins),
 810         },
 811         {
 812                 .name = "emif0grp",
 813                 .pins = emif0_pins,
 814                 .num_pins = ARRAY_SIZE(emif0_pins),
 815         },
 816         {
 817                 .name = "emif1grp",
 818                 .pins = emif1_pins,
 819                 .num_pins = ARRAY_SIZE(emif1_pins),
 820         },
 821         {
 822                 .name = "uart0grp",
 823                 .pins = uart0_pins,
 824                 .num_pins = ARRAY_SIZE(uart0_pins),
 825         },
 826         {
 827                 .name = "mmc0grp",
 828                 .pins = mmc0_pins,
 829                 .num_pins = ARRAY_SIZE(mmc0_pins),
 830         },
 831         {
 832                 .name = "spi0grp",
 833                 .pins = spi0_pins,
 834                 .num_pins = ARRAY_SIZE(spi0_pins),
 835         },
 836 };
 837
 838 static int u300_get_groups_count(struct pinctrl_dev *pctldev)
 839 {
 840         return ARRAY_SIZE(u300_pin_groups);
 841 }
 842
 843 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
 844                                        unsigned selector)
 845 {
 846         return u300_pin_groups[selector].name;
 847 }
 848
 849 static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 850                                const unsigned **pins,
 851                                unsigned *num_pins)
 852 {
 853         *pins = u300_pin_groups[selector].pins;
 854         *num_pins = u300_pin_groups[selector].num_pins;
 855         return 0;
 856 }
 857
 858 static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 859                    unsigned offset)
 860 {
 861         seq_printf(s, " " DRIVER_NAME);
 862 }
 863
 864 static const struct pinctrl_ops u300_pctrl_ops = {
 865         .get_groups_count = u300_get_groups_count,
 866         .get_group_name = u300_get_group_name,
 867         .get_group_pins = u300_get_group_pins,
 868         .pin_dbg_show = u300_pin_dbg_show,
 869 };
 870
 871 /*
 872  * Here we define the available functions and their corresponding pin groups
 873  */
 874
 875 /**
 876  * struct u300_pmx_func - describes U300 pinmux functions
 877  * @name: the name of this specific function
 878  * @groups: corresponding pin groups
 879  * @onmask: bits to set to enable this when doing pin muxing
 880  */
 881 struct u300_pmx_func {
 882         const char *name;
 883         const char * const *groups;
 884         const unsigned num_groups;
 885         const struct u300_pmx_mask *mask;
 886 };
 887
 888 static const char * const powergrps[] = { "powergrp" };
 889 static const char * const emif0grps[] = { "emif0grp" };
 890 static const char * const emif1grps[] = { "emif1grp" };
 891 static const char * const uart0grps[] = { "uart0grp" };
 892 static const char * const mmc0grps[] = { "mmc0grp" };
 893 static const char * const spi0grps[] = { "spi0grp" };
 894
 895 static const struct u300_pmx_func u300_pmx_functions[] = {
 896         {
 897                 .name = "power",
 898                 .groups = powergrps,
 899                 .num_groups = ARRAY_SIZE(powergrps),
 900                 /* Mask is N/A */
 901         },
 902         {
 903                 .name = "emif0",
 904                 .groups = emif0grps,
 905                 .num_groups = ARRAY_SIZE(emif0grps),
 906                 .mask = emif0_mask,
 907         },
 908         {
 909                 .name = "emif1",
 910                 .groups = emif1grps,
 911                 .num_groups = ARRAY_SIZE(emif1grps),
 912                 .mask = emif1_mask,
 913         },
 914         {
 915                 .name = "uart0",
 916                 .groups = uart0grps,
 917                 .num_groups = ARRAY_SIZE(uart0grps),
 918                 .mask = uart0_mask,
 919         },
 920         {
 921                 .name = "mmc0",
 922                 .groups = mmc0grps,
 923                 .num_groups = ARRAY_SIZE(mmc0grps),
 924                 .mask = mmc0_mask,
 925         },
 926         {
 927                 .name = "spi0",
 928                 .groups = spi0grps,
 929                 .num_groups = ARRAY_SIZE(spi0grps),
 930                 .mask = spi0_mask,
 931         },
 932 };
 933
 934 static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
 935                                bool enable)
 936 {
 937         u16 regval, val, mask;
 938         int i;
 939         const struct u300_pmx_mask *upmx_mask;
 940
 941         upmx_mask = u300_pmx_functions[selector].mask;
 942         for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
 943                 if (enable)
 944                         val = upmx_mask->bits;
 945                 else
 946                         val = 0;
 947
 948                 mask = upmx_mask->mask;
 949                 if (mask != 0) {
 950                         regval = readw(upmx->virtbase + u300_pmx_registers[i]);
 951                         regval &= ~mask;
 952                         regval |= val;
 953                         writew(regval, upmx->virtbase + u300_pmx_registers[i]);
 954                 }
 955                 upmx_mask++;
 956         }
 957 }
 958
 959 static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
 960                             unsigned group)
 961 {
 962         struct u300_pmx *upmx;
 963
 964         /* There is nothing to do with the power pins */
 965         if (selector == 0)
 966                 return 0;
 967
 968         upmx = pinctrl_dev_get_drvdata(pctldev);
 969         u300_pmx_endisable(upmx, selector, true);
 970
 971         return 0;
 972 }
 973
 974 static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 975 {
 976         return ARRAY_SIZE(u300_pmx_functions);
 977 }
 978
 979 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
 980                                           unsigned selector)
 981 {
 982         return u300_pmx_functions[selector].name;
 983 }
 984
 985 static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 986                                const char * const **groups,
 987                                unsigned * const num_groups)
 988 {
 989         *groups = u300_pmx_functions[selector].groups;
 990         *num_groups = u300_pmx_functions[selector].num_groups;
 991         return 0;
 992 }
 993
 994 static const struct pinmux_ops u300_pmx_ops = {
 995         .get_functions_count = u300_pmx_get_funcs_count,
 996         .get_function_name = u300_pmx_get_func_name,
 997         .get_function_groups = u300_pmx_get_groups,
 998         .set_mux = u300_pmx_set_mux,
 999 };
1000
1001 static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1002                                unsigned long *config)
1003 {
1004         struct pinctrl_gpio_range *range =
1005                 pinctrl_find_gpio_range_from_pin(pctldev, pin);
1006
1007         /* We get config for those pins we CAN get it for and that's it */
1008         if (!range)
1009                 return -ENOTSUPP;
1010
1011         return u300_gpio_config_get(range->gc,
1012                                     (pin - range->pin_base + range->base),
1013                                     config);
1014 }
1015
1016 static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1017                                unsigned long *configs, unsigned num_configs)
1018 {
1019         struct pinctrl_gpio_range *range =
1020                 pinctrl_find_gpio_range_from_pin(pctldev, pin);
1021         int ret, i;
1022
1023         if (!range)
1024                 return -EINVAL;
1025
1026         for (i = 0; i < num_configs; i++) {
1027                 /* Note: none of these configurations take any argument */
1028                 ret = u300_gpio_config_set(range->gc,
1029                         (pin - range->pin_base + range->base),
1030                         pinconf_to_config_param(configs[i]));
1031                 if (ret)
1032                         return ret;
1033         } /* for each config */
1034
1035         return 0;
1036 }
1037
1038 static const struct pinconf_ops u300_pconf_ops = {
1039         .is_generic = true,
1040         .pin_config_get = u300_pin_config_get,
1041         .pin_config_set = u300_pin_config_set,
1042 };
1043
1044 static struct pinctrl_desc u300_pmx_desc = {
1045         .name = DRIVER_NAME,
1046         .pins = u300_pads,
1047         .npins = ARRAY_SIZE(u300_pads),
1048         .pctlops = &u300_pctrl_ops,
1049         .pmxops = &u300_pmx_ops,
1050         .confops = &u300_pconf_ops,
1051         .owner = THIS_MODULE,
1052 };
1053
1054 static int u300_pmx_probe(struct platform_device *pdev)
1055 {
1056         struct u300_pmx *upmx;
1057         struct resource *res;
1058
1059         /* Create state holders etc for this driver */
1060         upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
1061         if (!upmx)
1062                 return -ENOMEM;
1063
1064         upmx->dev = &pdev->dev;
1065
1066         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1067         upmx->virtbase = devm_ioremap_resource(&pdev->dev, res);
1068         if (IS_ERR(upmx->virtbase))
1069                 return PTR_ERR(upmx->virtbase);
1070
1071         upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
1072         if (IS_ERR(upmx->pctl)) {
1073                 dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
1074                 return PTR_ERR(upmx->pctl);
1075         }
1076
1077         platform_set_drvdata(pdev, upmx);
1078
1079         dev_info(&pdev->dev, "initialized U300 pin control driver\n");
1080
1081         return 0;
1082 }
1083
1084 static const struct of_device_id u300_pinctrl_match[] = {
1085         { .compatible = "stericsson,pinctrl-u300" },
1086         {},
1087 };
1088
1089
1090 static struct platform_driver u300_pmx_driver = {
1091         .driver = {
1092                 .name = DRIVER_NAME,
1093                 .of_match_table = u300_pinctrl_match,
1094         },
1095         .probe = u300_pmx_probe,
1096 };
1097
1098 static int __init u300_pmx_init(void)
1099 {
1100         return platform_driver_register(&u300_pmx_driver);
1101 }
1102 arch_initcall(u300_pmx_init);
1103
1104 static void __exit u300_pmx_exit(void)
1105 {
1106         platform_driver_unregister(&u300_pmx_driver);
1107 }
1108 module_exit(u300_pmx_exit);
1109
1110 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1111 MODULE_DESCRIPTION("U300 pin control driver");
1112 MODULE_LICENSE("GPL v2");