drivers/pinctrl/freescale/pinctrl-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Core driver for the imx pin controller
   4 //
   5 // Copyright (C) 2012 Freescale Semiconductor, Inc.
   6 // Copyright (C) 2012 Linaro Ltd.
   7 //
   8 // Author: Dong Aisheng <dong.aisheng@linaro.org>
   9
  10 #include <linux/err.h>
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/pinctrl/machine.h>
  18 #include <linux/pinctrl/pinconf.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/slab.h>
  22 #include <linux/regmap.h>
  23
  24 #include "../core.h"
  25 #include "../pinconf.h"
  26 #include "../pinmux.h"
  27 #include "pinctrl-imx.h"
  28
  29 /* The bits in CONFIG cell defined in binding doc*/
  30 #define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
  31 #define IMX_PAD_SION 0x40000000         /* set SION */
  32
  33 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
  34                                 struct pinctrl_dev *pctldev,
  35                                 const char *name)
  36 {
  37         const struct group_desc *grp = NULL;
  38         int i;
  39
  40         for (i = 0; i < pctldev->num_groups; i++) {
  41                 grp = pinctrl_generic_get_group(pctldev, i);
  42                 if (grp && !strcmp(grp->name, name))
  43                         break;
  44         }
  45
  46         return grp;
  47 }
  48
  49 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  50                    unsigned offset)
  51 {
  52         seq_printf(s, "%s", dev_name(pctldev->dev));
  53 }
  54
  55 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
  56                         struct device_node *np,
  57                         struct pinctrl_map **map, unsigned *num_maps)
  58 {
  59         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  60         const struct group_desc *grp;
  61         struct pinctrl_map *new_map;
  62         struct device_node *parent;
  63         int map_num = 1;
  64         int i, j;
  65
  66         /*
  67          * first find the group of this node and check if we need create
  68          * config maps for pins
  69          */
  70         grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
  71         if (!grp) {
  72                 dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
  73                 return -EINVAL;
  74         }
  75
  76         for (i = 0; i < grp->num_pins; i++) {
  77                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
  78
  79                 if (!(pin->config & IMX_NO_PAD_CTL))
  80                         map_num++;
  81         }
  82
  83         new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
  84                                 GFP_KERNEL);
  85         if (!new_map)
  86                 return -ENOMEM;
  87
  88         *map = new_map;
  89         *num_maps = map_num;
  90
  91         /* create mux map */
  92         parent = of_get_parent(np);
  93         if (!parent) {
  94                 kfree(new_map);
  95                 return -EINVAL;
  96         }
  97         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  98         new_map[0].data.mux.function = parent->name;
  99         new_map[0].data.mux.group = np->name;
 100         of_node_put(parent);
 101
 102         /* create config map */
 103         new_map++;
 104         for (i = j = 0; i < grp->num_pins; i++) {
 105                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 106
 107                 if (!(pin->config & IMX_NO_PAD_CTL)) {
 108                         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 109                         new_map[j].data.configs.group_or_pin =
 110                                         pin_get_name(pctldev, pin->pin);
 111                         new_map[j].data.configs.configs = &pin->config;
 112                         new_map[j].data.configs.num_configs = 1;
 113                         j++;
 114                 }
 115         }
 116
 117         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 118                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 119
 120         return 0;
 121 }
 122
 123 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
 124                                 struct pinctrl_map *map, unsigned num_maps)
 125 {
 126         kfree(map);
 127 }
 128
 129 static const struct pinctrl_ops imx_pctrl_ops = {
 130         .get_groups_count = pinctrl_generic_get_group_count,
 131         .get_group_name = pinctrl_generic_get_group_name,
 132         .get_group_pins = pinctrl_generic_get_group_pins,
 133         .pin_dbg_show = imx_pin_dbg_show,
 134         .dt_node_to_map = imx_dt_node_to_map,
 135         .dt_free_map = imx_dt_free_map,
 136
 137 };
 138
 139 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 140                        unsigned group)
 141 {
 142         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 143         const struct imx_pinctrl_soc_info *info = ipctl->info;
 144         const struct imx_pin_reg *pin_reg;
 145         unsigned int npins, pin_id;
 146         int i;
 147         struct group_desc *grp = NULL;
 148         struct function_desc *func = NULL;
 149
 150         /*
 151          * Configure the mux mode for each pin in the group for a specific
 152          * function.
 153          */
 154         grp = pinctrl_generic_get_group(pctldev, group);
 155         if (!grp)
 156                 return -EINVAL;
 157
 158         func = pinmux_generic_get_function(pctldev, selector);
 159         if (!func)
 160                 return -EINVAL;
 161
 162         npins = grp->num_pins;
 163
 164         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 165                 func->name, grp->name);
 166
 167         for (i = 0; i < npins; i++) {
 168                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 169
 170                 pin_id = pin->pin;
 171                 pin_reg = &ipctl->pin_regs[pin_id];
 172
 173                 if (pin_reg->mux_reg == -1) {
 174                         dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
 175                                 info->pins[pin_id].name);
 176                         continue;
 177                 }
 178
 179                 if (info->flags & SHARE_MUX_CONF_REG) {
 180                         u32 reg;
 181                         reg = readl(ipctl->base + pin_reg->mux_reg);
 182                         reg &= ~info->mux_mask;
 183                         reg |= (pin->mux_mode << info->mux_shift);
 184                         writel(reg, ipctl->base + pin_reg->mux_reg);
 185                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 186                                 pin_reg->mux_reg, reg);
 187                 } else {
 188                         writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
 189                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 190                                 pin_reg->mux_reg, pin->mux_mode);
 191                 }
 192
 193                 /*
 194                  * If the select input value begins with 0xff, it's a quirky
 195                  * select input and the value should be interpreted as below.
 196                  *     31     23      15      7        0
 197                  *     | 0xff | shift | width | select |
 198                  * It's used to work around the problem that the select
 199                  * input for some pin is not implemented in the select
 200                  * input register but in some general purpose register.
 201                  * We encode the select input value, width and shift of
 202                  * the bit field into input_val cell of pin function ID
 203                  * in device tree, and then decode them here for setting
 204                  * up the select input bits in general purpose register.
 205                  */
 206                 if (pin->input_val >> 24 == 0xff) {
 207                         u32 val = pin->input_val;
 208                         u8 select = val & 0xff;
 209                         u8 width = (val >> 8) & 0xff;
 210                         u8 shift = (val >> 16) & 0xff;
 211                         u32 mask = ((1 << width) - 1) << shift;
 212                         /*
 213                          * The input_reg[i] here is actually some IOMUXC general
 214                          * purpose register, not regular select input register.
 215                          */
 216                         val = readl(ipctl->base + pin->input_reg);
 217                         val &= ~mask;
 218                         val |= select << shift;
 219                         writel(val, ipctl->base + pin->input_reg);
 220                 } else if (pin->input_reg) {
 221                         /*
 222                          * Regular select input register can never be at offset
 223                          * 0, and we only print register value for regular case.
 224                          */
 225                         if (ipctl->input_sel_base)
 226                                 writel(pin->input_val, ipctl->input_sel_base +
 227                                                 pin->input_reg);
 228                         else
 229                                 writel(pin->input_val, ipctl->base +
 230                                                 pin->input_reg);
 231                         dev_dbg(ipctl->dev,
 232                                 "==>select_input: offset 0x%x val 0x%x\n",
 233                                 pin->input_reg, pin->input_val);
 234                 }
 235         }
 236
 237         return 0;
 238 }
 239
 240 struct pinmux_ops imx_pmx_ops = {
 241         .get_functions_count = pinmux_generic_get_function_count,
 242         .get_function_name = pinmux_generic_get_function_name,
 243         .get_function_groups = pinmux_generic_get_function_groups,
 244         .set_mux = imx_pmx_set,
 245 };
 246
 247 /* decode generic config into raw register values */
 248 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
 249                                               unsigned long *configs,
 250                                               unsigned int num_configs)
 251 {
 252         const struct imx_pinctrl_soc_info *info = ipctl->info;
 253         const struct imx_cfg_params_decode *decode;
 254         enum pin_config_param param;
 255         u32 raw_config = 0;
 256         u32 param_val;
 257         int i, j;
 258
 259         WARN_ON(num_configs > info->num_decodes);
 260
 261         for (i = 0; i < num_configs; i++) {
 262                 param = pinconf_to_config_param(configs[i]);
 263                 param_val = pinconf_to_config_argument(configs[i]);
 264                 decode = info->decodes;
 265                 for (j = 0; j < info->num_decodes; j++) {
 266                         if (param == decode->param) {
 267                                 if (decode->invert)
 268                                         param_val = !param_val;
 269                                 raw_config |= (param_val << decode->shift)
 270                                               & decode->mask;
 271                                 break;
 272                         }
 273                         decode++;
 274                 }
 275         }
 276
 277         if (info->fixup)
 278                 info->fixup(configs, num_configs, &raw_config);
 279
 280         return raw_config;
 281 }
 282
 283 static u32 imx_pinconf_parse_generic_config(struct device_node *np,
 284                                             struct imx_pinctrl *ipctl)
 285 {
 286         const struct imx_pinctrl_soc_info *info = ipctl->info;
 287         struct pinctrl_dev *pctl = ipctl->pctl;
 288         unsigned int num_configs;
 289         unsigned long *configs;
 290         int ret;
 291
 292         if (!info->generic_pinconf)
 293                 return 0;
 294
 295         ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
 296                                               &num_configs);
 297         if (ret)
 298                 return 0;
 299
 300         return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
 301 }
 302
 303 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 304                              unsigned pin_id, unsigned long *config)
 305 {
 306         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 307         const struct imx_pinctrl_soc_info *info = ipctl->info;
 308         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 309
 310         if (pin_reg->conf_reg == -1) {
 311                 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
 312                         info->pins[pin_id].name);
 313                 return -EINVAL;
 314         }
 315
 316         *config = readl(ipctl->base + pin_reg->conf_reg);
 317
 318         if (info->flags & SHARE_MUX_CONF_REG)
 319                 *config &= ~info->mux_mask;
 320
 321         return 0;
 322 }
 323
 324 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 325                              unsigned pin_id, unsigned long *configs,
 326                              unsigned num_configs)
 327 {
 328         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 329         const struct imx_pinctrl_soc_info *info = ipctl->info;
 330         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 331         int i;
 332
 333         if (pin_reg->conf_reg == -1) {
 334                 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
 335                         info->pins[pin_id].name);
 336                 return -EINVAL;
 337         }
 338
 339         dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 340                 info->pins[pin_id].name);
 341
 342         for (i = 0; i < num_configs; i++) {
 343                 if (info->flags & SHARE_MUX_CONF_REG) {
 344                         u32 reg;
 345                         reg = readl(ipctl->base + pin_reg->conf_reg);
 346                         reg &= info->mux_mask;
 347                         reg |= configs[i];
 348                         writel(reg, ipctl->base + pin_reg->conf_reg);
 349                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 350                                 pin_reg->conf_reg, reg);
 351                 } else {
 352                         writel(configs[i], ipctl->base + pin_reg->conf_reg);
 353                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 354                                 pin_reg->conf_reg, configs[i]);
 355                 }
 356         } /* for each config */
 357
 358         return 0;
 359 }
 360
 361 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 362                                    struct seq_file *s, unsigned pin_id)
 363 {
 364         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 365         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 366         unsigned long config;
 367
 368         if (!pin_reg || pin_reg->conf_reg == -1) {
 369                 seq_puts(s, "N/A");
 370                 return;
 371         }
 372
 373         config = readl(ipctl->base + pin_reg->conf_reg);
 374         seq_printf(s, "0x%lx", config);
 375 }
 376
 377 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 378                                          struct seq_file *s, unsigned group)
 379 {
 380         struct group_desc *grp;
 381         unsigned long config;
 382         const char *name;
 383         int i, ret;
 384
 385         if (group >= pctldev->num_groups)
 386                 return;
 387
 388         seq_puts(s, "\n");
 389         grp = pinctrl_generic_get_group(pctldev, group);
 390         if (!grp)
 391                 return;
 392
 393         for (i = 0; i < grp->num_pins; i++) {
 394                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 395
 396                 name = pin_get_name(pctldev, pin->pin);
 397                 ret = imx_pinconf_get(pctldev, pin->pin, &config);
 398                 if (ret)
 399                         return;
 400                 seq_printf(s, "  %s: 0x%lx\n", name, config);
 401         }
 402 }
 403
 404 static const struct pinconf_ops imx_pinconf_ops = {
 405         .pin_config_get = imx_pinconf_get,
 406         .pin_config_set = imx_pinconf_set,
 407         .pin_config_dbg_show = imx_pinconf_dbg_show,
 408         .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
 409 };
 410
 411 /*
 412  * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
 413  * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
 414  * For generic_pinconf case, there's no extra u32 CONFIG.
 415  *
 416  * PIN_FUNC_ID format:
 417  * Default:
 418  *     <mux_reg conf_reg input_reg mux_mode input_val>
 419  * SHARE_MUX_CONF_REG:
 420  *     <mux_conf_reg input_reg mux_mode input_val>
 421  */
 422 #define FSL_PIN_SIZE 24
 423 #define FSL_PIN_SHARE_SIZE 20
 424
 425 static int imx_pinctrl_parse_groups(struct device_node *np,
 426                                     struct group_desc *grp,
 427                                     struct imx_pinctrl *ipctl,
 428                                     u32 index)
 429 {
 430         const struct imx_pinctrl_soc_info *info = ipctl->info;
 431         int size, pin_size;
 432         const __be32 *list;
 433         int i;
 434         u32 config;
 435
 436         dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
 437
 438         if (info->flags & SHARE_MUX_CONF_REG)
 439                 pin_size = FSL_PIN_SHARE_SIZE;
 440         else
 441                 pin_size = FSL_PIN_SIZE;
 442
 443         if (info->generic_pinconf)
 444                 pin_size -= 4;
 445
 446         /* Initialise group */
 447         grp->name = np->name;
 448
 449         /*
 450          * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
 451          * do sanity check and calculate pins number
 452          *
 453          * First try legacy 'fsl,pins' property, then fall back to the
 454          * generic 'pinmux'.
 455          *
 456          * Note: for generic 'pinmux' case, there's no CONFIG part in
 457          * the binding format.
 458          */
 459         list = of_get_property(np, "fsl,pins", &size);
 460         if (!list) {
 461                 list = of_get_property(np, "pinmux", &size);
 462                 if (!list) {
 463                         dev_err(ipctl->dev,
 464                                 "no fsl,pins and pins property in node %pOF\n", np);
 465                         return -EINVAL;
 466                 }
 467         }
 468
 469         /* we do not check return since it's safe node passed down */
 470         if (!size || size % pin_size) {
 471                 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
 472                 return -EINVAL;
 473         }
 474
 475         /* first try to parse the generic pin config */
 476         config = imx_pinconf_parse_generic_config(np, ipctl);
 477
 478         grp->num_pins = size / pin_size;
 479         grp->data = devm_kcalloc(ipctl->dev,
 480                                  grp->num_pins, sizeof(struct imx_pin),
 481                                  GFP_KERNEL);
 482         grp->pins = devm_kcalloc(ipctl->dev,
 483                                  grp->num_pins, sizeof(unsigned int),
 484                                  GFP_KERNEL);
 485         if (!grp->pins || !grp->data)
 486                 return -ENOMEM;
 487
 488         for (i = 0; i < grp->num_pins; i++) {
 489                 u32 mux_reg = be32_to_cpu(*list++);
 490                 u32 conf_reg;
 491                 unsigned int pin_id;
 492                 struct imx_pin_reg *pin_reg;
 493                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 494
 495                 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
 496                         mux_reg = -1;
 497
 498                 if (info->flags & SHARE_MUX_CONF_REG) {
 499                         conf_reg = mux_reg;
 500                 } else {
 501                         conf_reg = be32_to_cpu(*list++);
 502                         if (!conf_reg)
 503                                 conf_reg = -1;
 504                 }
 505
 506                 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
 507                 pin_reg = &ipctl->pin_regs[pin_id];
 508                 pin->pin = pin_id;
 509                 grp->pins[i] = pin_id;
 510                 pin_reg->mux_reg = mux_reg;
 511                 pin_reg->conf_reg = conf_reg;
 512                 pin->input_reg = be32_to_cpu(*list++);
 513                 pin->mux_mode = be32_to_cpu(*list++);
 514                 pin->input_val = be32_to_cpu(*list++);
 515
 516                 if (info->generic_pinconf) {
 517                         /* generic pin config decoded */
 518                         pin->config = config;
 519                 } else {
 520                         /* legacy pin config read from devicetree */
 521                         config = be32_to_cpu(*list++);
 522
 523                         /* SION bit is in mux register */
 524                         if (config & IMX_PAD_SION)
 525                                 pin->mux_mode |= IOMUXC_CONFIG_SION;
 526                         pin->config = config & ~IMX_PAD_SION;
 527                 }
 528
 529                 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 530                                 pin->mux_mode, pin->config);
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int imx_pinctrl_parse_functions(struct device_node *np,
 537                                        struct imx_pinctrl *ipctl,
 538                                        u32 index)
 539 {
 540         struct pinctrl_dev *pctl = ipctl->pctl;
 541         struct device_node *child;
 542         struct function_desc *func;
 543         struct group_desc *grp;
 544         u32 i = 0;
 545
 546         dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
 547
 548         func = pinmux_generic_get_function(pctl, index);
 549         if (!func)
 550                 return -EINVAL;
 551
 552         /* Initialise function */
 553         func->name = np->name;
 554         func->num_group_names = of_get_child_count(np);
 555         if (func->num_group_names == 0) {
 556                 dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
 557                 return -EINVAL;
 558         }
 559         func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
 560                                          sizeof(char *), GFP_KERNEL);
 561         if (!func->group_names)
 562                 return -ENOMEM;
 563
 564         for_each_child_of_node(np, child) {
 565                 func->group_names[i] = child->name;
 566
 567                 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
 568                                    GFP_KERNEL);
 569                 if (!grp)
 570                         return -ENOMEM;
 571
 572                 mutex_lock(&ipctl->mutex);
 573                 radix_tree_insert(&pctl->pin_group_tree,
 574                                   ipctl->group_index++, grp);
 575                 mutex_unlock(&ipctl->mutex);
 576
 577                 imx_pinctrl_parse_groups(child, grp, ipctl, i++);
 578         }
 579
 580         return 0;
 581 }
 582
 583 /*
 584  * Check if the DT contains pins in the direct child nodes. This indicates the
 585  * newer DT format to store pins. This function returns true if the first found
 586  * fsl,pins property is in a child of np. Otherwise false is returned.
 587  */
 588 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
 589 {
 590         struct device_node *function_np;
 591         struct device_node *pinctrl_np;
 592
 593         for_each_child_of_node(np, function_np) {
 594                 if (of_property_read_bool(function_np, "fsl,pins"))
 595                         return true;
 596
 597                 for_each_child_of_node(function_np, pinctrl_np) {
 598                         if (of_property_read_bool(pinctrl_np, "fsl,pins"))
 599                                 return false;
 600                 }
 601         }
 602
 603         return true;
 604 }
 605
 606 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 607                                 struct imx_pinctrl *ipctl)
 608 {
 609         struct device_node *np = pdev->dev.of_node;
 610         struct device_node *child;
 611         struct pinctrl_dev *pctl = ipctl->pctl;
 612         u32 nfuncs = 0;
 613         u32 i = 0;
 614         bool flat_funcs;
 615
 616         if (!np)
 617                 return -ENODEV;
 618
 619         flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
 620         if (flat_funcs) {
 621                 nfuncs = 1;
 622         } else {
 623                 nfuncs = of_get_child_count(np);
 624                 if (nfuncs == 0) {
 625                         dev_err(&pdev->dev, "no functions defined\n");
 626                         return -EINVAL;
 627                 }
 628         }
 629
 630         for (i = 0; i < nfuncs; i++) {
 631                 struct function_desc *function;
 632
 633                 function = devm_kzalloc(&pdev->dev, sizeof(*function),
 634                                         GFP_KERNEL);
 635                 if (!function)
 636                         return -ENOMEM;
 637
 638                 mutex_lock(&ipctl->mutex);
 639                 radix_tree_insert(&pctl->pin_function_tree, i, function);
 640                 mutex_unlock(&ipctl->mutex);
 641         }
 642         pctl->num_functions = nfuncs;
 643
 644         ipctl->group_index = 0;
 645         if (flat_funcs) {
 646                 pctl->num_groups = of_get_child_count(np);
 647         } else {
 648                 pctl->num_groups = 0;
 649                 for_each_child_of_node(np, child)
 650                         pctl->num_groups += of_get_child_count(child);
 651         }
 652
 653         if (flat_funcs) {
 654                 imx_pinctrl_parse_functions(np, ipctl, 0);
 655         } else {
 656                 i = 0;
 657                 for_each_child_of_node(np, child)
 658                         imx_pinctrl_parse_functions(child, ipctl, i++);
 659         }
 660
 661         return 0;
 662 }
 663
 664 /*
 665  * imx_free_resources() - free memory used by this driver
 666  * @info: info driver instance
 667  */
 668 static void imx_free_resources(struct imx_pinctrl *ipctl)
 669 {
 670         if (ipctl->pctl)
 671                 pinctrl_unregister(ipctl->pctl);
 672 }
 673
 674 int imx_pinctrl_probe(struct platform_device *pdev,
 675                       const struct imx_pinctrl_soc_info *info)
 676 {
 677         struct regmap_config config = { .name = "gpr" };
 678         struct device_node *dev_np = pdev->dev.of_node;
 679         struct pinctrl_desc *imx_pinctrl_desc;
 680         struct device_node *np;
 681         struct imx_pinctrl *ipctl;
 682         struct resource *res;
 683         struct regmap *gpr;
 684         int ret, i;
 685
 686         if (!info || !info->pins || !info->npins) {
 687                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 688                 return -EINVAL;
 689         }
 690
 691         if (info->gpr_compatible) {
 692                 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
 693                 if (!IS_ERR(gpr))
 694                         regmap_attach_dev(&pdev->dev, gpr, &config);
 695         }
 696
 697         /* Create state holders etc for this driver */
 698         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 699         if (!ipctl)
 700                 return -ENOMEM;
 701
 702         ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
 703                                        info->npins, sizeof(*ipctl->pin_regs),
 704                                        GFP_KERNEL);
 705         if (!ipctl->pin_regs)
 706                 return -ENOMEM;
 707
 708         for (i = 0; i < info->npins; i++) {
 709                 ipctl->pin_regs[i].mux_reg = -1;
 710                 ipctl->pin_regs[i].conf_reg = -1;
 711         }
 712
 713         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 714         ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 715         if (IS_ERR(ipctl->base))
 716                 return PTR_ERR(ipctl->base);
 717
 718         if (of_property_read_bool(dev_np, "fsl,input-sel")) {
 719                 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
 720                 if (!np) {
 721                         dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
 722                         return -EINVAL;
 723                 }
 724
 725                 ipctl->input_sel_base = of_iomap(np, 0);
 726                 of_node_put(np);
 727                 if (!ipctl->input_sel_base) {
 728                         dev_err(&pdev->dev,
 729                                 "iomuxc input select base address not found\n");
 730                         return -ENOMEM;
 731                 }
 732         }
 733
 734         imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
 735                                         GFP_KERNEL);
 736         if (!imx_pinctrl_desc)
 737                 return -ENOMEM;
 738
 739         imx_pinctrl_desc->name = dev_name(&pdev->dev);
 740         imx_pinctrl_desc->pins = info->pins;
 741         imx_pinctrl_desc->npins = info->npins;
 742         imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
 743         imx_pinctrl_desc->pmxops = &imx_pmx_ops;
 744         imx_pinctrl_desc->confops = &imx_pinconf_ops;
 745         imx_pinctrl_desc->owner = THIS_MODULE;
 746
 747         /* for generic pinconf */
 748         imx_pinctrl_desc->custom_params = info->custom_params;
 749         imx_pinctrl_desc->num_custom_params = info->num_custom_params;
 750
 751         /* platform specific callback */
 752         imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
 753
 754         mutex_init(&ipctl->mutex);
 755
 756         ipctl->info = info;
 757         ipctl->dev = &pdev->dev;
 758         platform_set_drvdata(pdev, ipctl);
 759         ret = devm_pinctrl_register_and_init(&pdev->dev,
 760                                              imx_pinctrl_desc, ipctl,
 761                                              &ipctl->pctl);
 762         if (ret) {
 763                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 764                 goto free;
 765         }
 766
 767         ret = imx_pinctrl_probe_dt(pdev, ipctl);
 768         if (ret) {
 769                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 770                 goto free;
 771         }
 772
 773         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 774
 775         return pinctrl_enable(ipctl->pctl);
 776
 777 free:
 778         imx_free_resources(ipctl);
 779
 780         return ret;
 781 }