drivers/pinctrl/actions/pinctrl-owl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * OWL SoC's Pinctrl driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Author: David Liu <liuwei@actions-semi.com>
   7  *
   8  * Copyright (c) 2018 Linaro Ltd.
   9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/machine.h>
  20 #include <linux/pinctrl/pinctrl.h>
  21 #include <linux/pinctrl/pinmux.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/pinconf-generic.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26
  27 #include "../core.h"
  28 #include "../pinctrl-utils.h"
  29 #include "pinctrl-owl.h"
  30
  31 /**
  32  * struct owl_pinctrl - pinctrl state of the device
  33  * @dev: device handle
  34  * @pctrldev: pinctrl handle
  35  * @chip: gpio chip
  36  * @lock: spinlock to protect registers
  37  * @soc: reference to soc_data
  38  * @base: pinctrl register base address
  39  */
  40 struct owl_pinctrl {
  41         struct device *dev;
  42         struct pinctrl_dev *pctrldev;
  43         struct gpio_chip chip;
  44         raw_spinlock_t lock;
  45         struct clk *clk;
  46         const struct owl_pinctrl_soc_data *soc;
  47         void __iomem *base;
  48 };
  49
  50 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
  51 {
  52         u32 reg_val;
  53
  54         reg_val = readl_relaxed(base);
  55
  56         reg_val = (reg_val & ~mask) | (val & mask);
  57
  58         writel_relaxed(reg_val, base);
  59 }
  60
  61 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
  62                                 u32 bit, u32 width)
  63 {
  64         u32 tmp, mask;
  65
  66         tmp = readl_relaxed(pctrl->base + reg);
  67         mask = (1 << width) - 1;
  68
  69         return (tmp >> bit) & mask;
  70 }
  71
  72 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
  73                                 u32 bit, u32 width)
  74 {
  75         u32 mask;
  76
  77         mask = (1 << width) - 1;
  78         mask = mask << bit;
  79
  80         owl_update_bits(pctrl->base + reg, mask, (arg << bit));
  81 }
  82
  83 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
  84 {
  85         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
  86
  87         return pctrl->soc->ngroups;
  88 }
  89
  90 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
  91                                 unsigned int group)
  92 {
  93         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
  94
  95         return pctrl->soc->groups[group].name;
  96 }
  97
  98 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
  99                                 unsigned int group,
 100                                 const unsigned int **pins,
 101                                 unsigned int *num_pins)
 102 {
 103         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 104
 105         *pins = pctrl->soc->groups[group].pads;
 106         *num_pins = pctrl->soc->groups[group].npads;
 107
 108         return 0;
 109 }
 110
 111 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
 112                                 struct seq_file *s,
 113                                 unsigned int offset)
 114 {
 115         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 116
 117         seq_printf(s, "%s", dev_name(pctrl->dev));
 118 }
 119
 120 static struct pinctrl_ops owl_pinctrl_ops = {
 121         .get_groups_count = owl_get_groups_count,
 122         .get_group_name = owl_get_group_name,
 123         .get_group_pins = owl_get_group_pins,
 124         .pin_dbg_show = owl_pin_dbg_show,
 125         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 126         .dt_free_map = pinctrl_utils_free_map,
 127 };
 128
 129 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
 130 {
 131         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 132
 133         return pctrl->soc->nfunctions;
 134 }
 135
 136 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
 137                                 unsigned int function)
 138 {
 139         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 140
 141         return pctrl->soc->functions[function].name;
 142 }
 143
 144 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
 145                                 unsigned int function,
 146                                 const char * const **groups,
 147                                 unsigned int * const num_groups)
 148 {
 149         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 150
 151         *groups = pctrl->soc->functions[function].groups;
 152         *num_groups = pctrl->soc->functions[function].ngroups;
 153
 154         return 0;
 155 }
 156
 157 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
 158                                 int function,
 159                                 u32 *mask,
 160                                 u32 *val)
 161 {
 162         int id;
 163         u32 option_num;
 164         u32 option_mask;
 165
 166         for (id = 0; id < g->nfuncs; id++) {
 167                 if (g->funcs[id] == function)
 168                         break;
 169         }
 170         if (WARN_ON(id == g->nfuncs))
 171                 return -EINVAL;
 172
 173         option_num = (1 << g->mfpctl_width);
 174         if (id > option_num)
 175                 id -= option_num;
 176
 177         option_mask = option_num - 1;
 178         *mask = (option_mask  << g->mfpctl_shift);
 179         *val = (id << g->mfpctl_shift);
 180
 181         return 0;
 182 }
 183
 184 static int owl_set_mux(struct pinctrl_dev *pctrldev,
 185                                 unsigned int function,
 186                                 unsigned int group)
 187 {
 188         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 189         const struct owl_pingroup *g;
 190         unsigned long flags;
 191         u32 val, mask;
 192
 193         g = &pctrl->soc->groups[group];
 194
 195         if (get_group_mfp_mask_val(g, function, &mask, &val))
 196                 return -EINVAL;
 197
 198         raw_spin_lock_irqsave(&pctrl->lock, flags);
 199
 200         owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
 201
 202         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 203
 204         return 0;
 205 }
 206
 207 static struct pinmux_ops owl_pinmux_ops = {
 208         .get_functions_count = owl_get_funcs_count,
 209         .get_function_name = owl_get_func_name,
 210         .get_function_groups = owl_get_func_groups,
 211         .set_mux = owl_set_mux,
 212 };
 213
 214 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
 215                                 unsigned int param,
 216                                 u32 *reg,
 217                                 u32 *bit,
 218                                 u32 *width)
 219 {
 220         switch (param) {
 221         case PIN_CONFIG_BIAS_BUS_HOLD:
 222         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 223         case PIN_CONFIG_BIAS_PULL_DOWN:
 224         case PIN_CONFIG_BIAS_PULL_UP:
 225                 if (!info->pullctl)
 226                         return -EINVAL;
 227                 *reg = info->pullctl->reg;
 228                 *bit = info->pullctl->shift;
 229                 *width = info->pullctl->width;
 230                 break;
 231         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 232                 if (!info->st)
 233                         return -EINVAL;
 234                 *reg = info->st->reg;
 235                 *bit = info->st->shift;
 236                 *width = info->st->width;
 237                 break;
 238         default:
 239                 return -ENOTSUPP;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
 246                                 unsigned int param,
 247                                 u32 *arg)
 248 {
 249         switch (param) {
 250         case PIN_CONFIG_BIAS_BUS_HOLD:
 251                 *arg = OWL_PINCONF_PULL_HOLD;
 252                 break;
 253         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 254                 *arg = OWL_PINCONF_PULL_HIZ;
 255                 break;
 256         case PIN_CONFIG_BIAS_PULL_DOWN:
 257                 *arg = OWL_PINCONF_PULL_DOWN;
 258                 break;
 259         case PIN_CONFIG_BIAS_PULL_UP:
 260                 *arg = OWL_PINCONF_PULL_UP;
 261                 break;
 262         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 263                 *arg = (*arg >= 1 ? 1 : 0);
 264                 break;
 265         default:
 266                 return -ENOTSUPP;
 267         }
 268
 269         return 0;
 270 }
 271
 272 static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
 273                                 unsigned int param,
 274                                 u32 *arg)
 275 {
 276         switch (param) {
 277         case PIN_CONFIG_BIAS_BUS_HOLD:
 278                 *arg = *arg == OWL_PINCONF_PULL_HOLD;
 279                 break;
 280         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 281                 *arg = *arg == OWL_PINCONF_PULL_HIZ;
 282                 break;
 283         case PIN_CONFIG_BIAS_PULL_DOWN:
 284                 *arg = *arg == OWL_PINCONF_PULL_DOWN;
 285                 break;
 286         case PIN_CONFIG_BIAS_PULL_UP:
 287                 *arg = *arg == OWL_PINCONF_PULL_UP;
 288                 break;
 289         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 290                 *arg = *arg == 1;
 291                 break;
 292         default:
 293                 return -ENOTSUPP;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
 300                                 unsigned int pin,
 301                                 unsigned long *config)
 302 {
 303         int ret = 0;
 304         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 305         const struct owl_padinfo *info;
 306         unsigned int param = pinconf_to_config_param(*config);
 307         u32 reg, bit, width, arg;
 308
 309         info = &pctrl->soc->padinfo[pin];
 310
 311         ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
 312         if (ret)
 313                 return ret;
 314
 315         arg = owl_read_field(pctrl, reg, bit, width);
 316
 317         ret = owl_pad_pinconf_val2arg(info, param, &arg);
 318         if (ret)
 319                 return ret;
 320
 321         *config = pinconf_to_config_packed(param, arg);
 322
 323         return ret;
 324 }
 325
 326 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
 327                                 unsigned int pin,
 328                                 unsigned long *configs,
 329                                 unsigned int num_configs)
 330 {
 331         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 332         const struct owl_padinfo *info;
 333         unsigned long flags;
 334         unsigned int param;
 335         u32 reg, bit, width, arg;
 336         int ret, i;
 337
 338         info = &pctrl->soc->padinfo[pin];
 339
 340         for (i = 0; i < num_configs; i++) {
 341                 param = pinconf_to_config_param(configs[i]);
 342                 arg = pinconf_to_config_argument(configs[i]);
 343
 344                 ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
 345                 if (ret)
 346                         return ret;
 347
 348                 ret = owl_pad_pinconf_arg2val(info, param, &arg);
 349                 if (ret)
 350                         return ret;
 351
 352                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 353
 354                 owl_write_field(pctrl, reg, arg, bit, width);
 355
 356                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 357         }
 358
 359         return ret;
 360 }
 361
 362 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
 363                                 unsigned int param,
 364                                 u32 *reg,
 365                                 u32 *bit,
 366                                 u32 *width)
 367 {
 368         switch (param) {
 369         case PIN_CONFIG_DRIVE_STRENGTH:
 370                 if (g->drv_reg < 0)
 371                         return -EINVAL;
 372                 *reg = g->drv_reg;
 373                 *bit = g->drv_shift;
 374                 *width = g->drv_width;
 375                 break;
 376         case PIN_CONFIG_SLEW_RATE:
 377                 if (g->sr_reg < 0)
 378                         return -EINVAL;
 379                 *reg = g->sr_reg;
 380                 *bit = g->sr_shift;
 381                 *width = g->sr_width;
 382                 break;
 383         default:
 384                 return -ENOTSUPP;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
 391                                 unsigned int param,
 392                                 u32 *arg)
 393 {
 394         switch (param) {
 395         case PIN_CONFIG_DRIVE_STRENGTH:
 396                 switch (*arg) {
 397                 case 2:
 398                         *arg = OWL_PINCONF_DRV_2MA;
 399                         break;
 400                 case 4:
 401                         *arg = OWL_PINCONF_DRV_4MA;
 402                         break;
 403                 case 8:
 404                         *arg = OWL_PINCONF_DRV_8MA;
 405                         break;
 406                 case 12:
 407                         *arg = OWL_PINCONF_DRV_12MA;
 408                         break;
 409                 default:
 410                         return -EINVAL;
 411                 }
 412                 break;
 413         case PIN_CONFIG_SLEW_RATE:
 414                 if (*arg)
 415                         *arg = OWL_PINCONF_SLEW_FAST;
 416                 else
 417                         *arg = OWL_PINCONF_SLEW_SLOW;
 418                 break;
 419         default:
 420                 return -ENOTSUPP;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
 427                                 unsigned int param,
 428                                 u32 *arg)
 429 {
 430         switch (param) {
 431         case PIN_CONFIG_DRIVE_STRENGTH:
 432                 switch (*arg) {
 433                 case OWL_PINCONF_DRV_2MA:
 434                         *arg = 2;
 435                         break;
 436                 case OWL_PINCONF_DRV_4MA:
 437                         *arg = 4;
 438                         break;
 439                 case OWL_PINCONF_DRV_8MA:
 440                         *arg = 8;
 441                         break;
 442                 case OWL_PINCONF_DRV_12MA:
 443                         *arg = 12;
 444                         break;
 445                 default:
 446                         return -EINVAL;
 447                 }
 448                 break;
 449         case PIN_CONFIG_SLEW_RATE:
 450                 if (*arg)
 451                         *arg = 1;
 452                 else
 453                         *arg = 0;
 454                 break;
 455         default:
 456                 return -ENOTSUPP;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
 463                                 unsigned int group,
 464                                 unsigned long *config)
 465 {
 466         const struct owl_pingroup *g;
 467         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 468         unsigned int param = pinconf_to_config_param(*config);
 469         u32 reg, bit, width, arg;
 470         int ret;
 471
 472         g = &pctrl->soc->groups[group];
 473
 474         ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
 475         if (ret)
 476                 return ret;
 477
 478         arg = owl_read_field(pctrl, reg, bit, width);
 479
 480         ret = owl_group_pinconf_val2arg(g, param, &arg);
 481         if (ret)
 482                 return ret;
 483
 484         *config = pinconf_to_config_packed(param, arg);
 485
 486         return ret;
 487
 488 }
 489
 490 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
 491                                 unsigned int group,
 492                                 unsigned long *configs,
 493                                 unsigned int num_configs)
 494 {
 495         const struct owl_pingroup *g;
 496         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 497         unsigned long flags;
 498         unsigned int param;
 499         u32 reg, bit, width, arg;
 500         int ret, i;
 501
 502         g = &pctrl->soc->groups[group];
 503
 504         for (i = 0; i < num_configs; i++) {
 505                 param = pinconf_to_config_param(configs[i]);
 506                 arg = pinconf_to_config_argument(configs[i]);
 507
 508                 ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
 509                 if (ret)
 510                         return ret;
 511
 512                 ret = owl_group_pinconf_arg2val(g, param, &arg);
 513                 if (ret)
 514                         return ret;
 515
 516                 /* Update register */
 517                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 518
 519                 owl_write_field(pctrl, reg, arg, bit, width);
 520
 521                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 522         }
 523
 524         return 0;
 525 }
 526
 527 static const struct pinconf_ops owl_pinconf_ops = {
 528         .is_generic = true,
 529         .pin_config_get = owl_pin_config_get,
 530         .pin_config_set = owl_pin_config_set,
 531         .pin_config_group_get = owl_group_config_get,
 532         .pin_config_group_set = owl_group_config_set,
 533 };
 534
 535 static struct pinctrl_desc owl_pinctrl_desc = {
 536         .pctlops = &owl_pinctrl_ops,
 537         .pmxops = &owl_pinmux_ops,
 538         .confops = &owl_pinconf_ops,
 539         .owner = THIS_MODULE,
 540 };
 541
 542 static const struct owl_gpio_port *
 543 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
 544 {
 545         unsigned int start = 0, i;
 546
 547         for (i = 0; i < pctrl->soc->nports; i++) {
 548                 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
 549
 550                 if (*pin >= start && *pin < start + port->pins) {
 551                         *pin -= start;
 552                         return port;
 553                 }
 554
 555                 start += port->pins;
 556         }
 557
 558         return NULL;
 559 }
 560
 561 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
 562 {
 563         u32 val;
 564
 565         val = readl_relaxed(base);
 566
 567         if (flag)
 568                 val |= BIT(pin);
 569         else
 570                 val &= ~BIT(pin);
 571
 572         writel_relaxed(val, base);
 573 }
 574
 575 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
 576 {
 577         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 578         const struct owl_gpio_port *port;
 579         void __iomem *gpio_base;
 580         unsigned long flags;
 581
 582         port = owl_gpio_get_port(pctrl, &offset);
 583         if (WARN_ON(port == NULL))
 584                 return -ENODEV;
 585
 586         gpio_base = pctrl->base + port->offset;
 587
 588         /*
 589          * GPIOs have higher priority over other modules, so either setting
 590          * them as OUT or IN is sufficient
 591          */
 592         raw_spin_lock_irqsave(&pctrl->lock, flags);
 593         owl_gpio_update_reg(gpio_base + port->outen, offset, true);
 594         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 595
 596         return 0;
 597 }
 598
 599 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
 600 {
 601         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 602         const struct owl_gpio_port *port;
 603         void __iomem *gpio_base;
 604         unsigned long flags;
 605
 606         port = owl_gpio_get_port(pctrl, &offset);
 607         if (WARN_ON(port == NULL))
 608                 return;
 609
 610         gpio_base = pctrl->base + port->offset;
 611
 612         raw_spin_lock_irqsave(&pctrl->lock, flags);
 613         /* disable gpio output */
 614         owl_gpio_update_reg(gpio_base + port->outen, offset, false);
 615
 616         /* disable gpio input */
 617         owl_gpio_update_reg(gpio_base + port->inen, offset, false);
 618         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 619 }
 620
 621 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
 622 {
 623         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 624         const struct owl_gpio_port *port;
 625         void __iomem *gpio_base;
 626         unsigned long flags;
 627         u32 val;
 628
 629         port = owl_gpio_get_port(pctrl, &offset);
 630         if (WARN_ON(port == NULL))
 631                 return -ENODEV;
 632
 633         gpio_base = pctrl->base + port->offset;
 634
 635         raw_spin_lock_irqsave(&pctrl->lock, flags);
 636         val = readl_relaxed(gpio_base + port->dat);
 637         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 638
 639         return !!(val & BIT(offset));
 640 }
 641
 642 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 643 {
 644         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 645         const struct owl_gpio_port *port;
 646         void __iomem *gpio_base;
 647         unsigned long flags;
 648
 649         port = owl_gpio_get_port(pctrl, &offset);
 650         if (WARN_ON(port == NULL))
 651                 return;
 652
 653         gpio_base = pctrl->base + port->offset;
 654
 655         raw_spin_lock_irqsave(&pctrl->lock, flags);
 656         owl_gpio_update_reg(gpio_base + port->dat, offset, value);
 657         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 658 }
 659
 660 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 661 {
 662         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 663         const struct owl_gpio_port *port;
 664         void __iomem *gpio_base;
 665         unsigned long flags;
 666
 667         port = owl_gpio_get_port(pctrl, &offset);
 668         if (WARN_ON(port == NULL))
 669                 return -ENODEV;
 670
 671         gpio_base = pctrl->base + port->offset;
 672
 673         raw_spin_lock_irqsave(&pctrl->lock, flags);
 674         owl_gpio_update_reg(gpio_base + port->outen, offset, false);
 675         owl_gpio_update_reg(gpio_base + port->inen, offset, true);
 676         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 677
 678         return 0;
 679 }
 680
 681 static int owl_gpio_direction_output(struct gpio_chip *chip,
 682                                 unsigned int offset, int value)
 683 {
 684         struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
 685         const struct owl_gpio_port *port;
 686         void __iomem *gpio_base;
 687         unsigned long flags;
 688
 689         port = owl_gpio_get_port(pctrl, &offset);
 690         if (WARN_ON(port == NULL))
 691                 return -ENODEV;
 692
 693         gpio_base = pctrl->base + port->offset;
 694
 695         raw_spin_lock_irqsave(&pctrl->lock, flags);
 696         owl_gpio_update_reg(gpio_base + port->inen, offset, false);
 697         owl_gpio_update_reg(gpio_base + port->outen, offset, true);
 698         owl_gpio_update_reg(gpio_base + port->dat, offset, value);
 699         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 700
 701         return 0;
 702 }
 703
 704 static int owl_gpio_init(struct owl_pinctrl *pctrl)
 705 {
 706         struct gpio_chip *chip;
 707         int ret;
 708
 709         chip = &pctrl->chip;
 710         chip->base = -1;
 711         chip->ngpio = pctrl->soc->ngpios;
 712         chip->label = dev_name(pctrl->dev);
 713         chip->parent = pctrl->dev;
 714         chip->owner = THIS_MODULE;
 715         chip->of_node = pctrl->dev->of_node;
 716
 717         ret = gpiochip_add_data(&pctrl->chip, pctrl);
 718         if (ret) {
 719                 dev_err(pctrl->dev, "failed to register gpiochip\n");
 720                 return ret;
 721         }
 722
 723         return 0;
 724 }
 725
 726 int owl_pinctrl_probe(struct platform_device *pdev,
 727                                 struct owl_pinctrl_soc_data *soc_data)
 728 {
 729         struct resource *res;
 730         struct owl_pinctrl *pctrl;
 731         int ret;
 732
 733         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 734         if (!pctrl)
 735                 return -ENOMEM;
 736
 737         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 738         pctrl->base = devm_ioremap_resource(&pdev->dev, res);
 739         if (IS_ERR(pctrl->base))
 740                 return PTR_ERR(pctrl->base);
 741
 742         /* enable GPIO/MFP clock */
 743         pctrl->clk = devm_clk_get(&pdev->dev, NULL);
 744         if (IS_ERR(pctrl->clk)) {
 745                 dev_err(&pdev->dev, "no clock defined\n");
 746                 return PTR_ERR(pctrl->clk);
 747         }
 748
 749         ret = clk_prepare_enable(pctrl->clk);
 750         if (ret) {
 751                 dev_err(&pdev->dev, "clk enable failed\n");
 752                 return ret;
 753         }
 754
 755         raw_spin_lock_init(&pctrl->lock);
 756
 757         owl_pinctrl_desc.name = dev_name(&pdev->dev);
 758         owl_pinctrl_desc.pins = soc_data->pins;
 759         owl_pinctrl_desc.npins = soc_data->npins;
 760
 761         pctrl->chip.direction_input  = owl_gpio_direction_input;
 762         pctrl->chip.direction_output = owl_gpio_direction_output;
 763         pctrl->chip.get = owl_gpio_get;
 764         pctrl->chip.set = owl_gpio_set;
 765         pctrl->chip.request = owl_gpio_request;
 766         pctrl->chip.free = owl_gpio_free;
 767
 768         pctrl->soc = soc_data;
 769         pctrl->dev = &pdev->dev;
 770
 771         pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
 772                                         &owl_pinctrl_desc, pctrl);
 773         if (IS_ERR(pctrl->pctrldev)) {
 774                 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
 775                 return PTR_ERR(pctrl->pctrldev);
 776         }
 777
 778         ret = owl_gpio_init(pctrl);
 779         if (ret)
 780                 return ret;
 781
 782         platform_set_drvdata(pdev, pctrl);
 783
 784         return 0;
 785 }