drivers/phy/qualcomm/phy-qcom-qusb2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/nvmem-consumer.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  24
  25 #define QUSB2PHY_PLL_TEST               0x04
  26 #define CLK_REF_SEL                     BIT(7)
  27
  28 #define QUSB2PHY_PLL_TUNE               0x08
  29 #define QUSB2PHY_PLL_USER_CTL1          0x0c
  30 #define QUSB2PHY_PLL_USER_CTL2          0x10
  31 #define QUSB2PHY_PLL_AUTOPGM_CTL1       0x1c
  32 #define QUSB2PHY_PLL_PWR_CTRL           0x18
  33
  34 /* QUSB2PHY_PLL_STATUS register bits */
  35 #define PLL_LOCKED                      BIT(5)
  36
  37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
  38 #define CORE_READY_STATUS               BIT(0)
  39
  40 /* QUSB2PHY_PORT_POWERDOWN register bits */
  41 #define CLAMP_N_EN                      BIT(5)
  42 #define FREEZIO_N                       BIT(1)
  43 #define POWER_DOWN                      BIT(0)
  44
  45 /* QUSB2PHY_PWR_CTRL1 register bits */
  46 #define PWR_CTRL1_VREF_SUPPLY_TRIM      BIT(5)
  47 #define PWR_CTRL1_CLAMP_N_EN            BIT(1)
  48
  49 #define QUSB2PHY_REFCLK_ENABLE          BIT(0)
  50
  51 #define PHY_CLK_SCHEME_SEL              BIT(0)
  52
  53 /* QUSB2PHY_INTR_CTRL register bits */
  54 #define DMSE_INTR_HIGH_SEL                      BIT(4)
  55 #define DPSE_INTR_HIGH_SEL                      BIT(3)
  56 #define CHG_DET_INTR_EN                         BIT(2)
  57 #define DMSE_INTR_EN                            BIT(1)
  58 #define DPSE_INTR_EN                            BIT(0)
  59
  60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
  61 #define CORE_PLL_EN_FROM_RESET                  BIT(4)
  62 #define CORE_RESET                              BIT(5)
  63 #define CORE_RESET_MUX                          BIT(6)
  64
  65 /* QUSB2PHY_IMP_CTRL1 register bits */
  66 #define IMP_RES_OFFSET_MASK                     GENMASK(5, 0)
  67 #define IMP_RES_OFFSET_SHIFT                    0x0
  68
  69 /* QUSB2PHY_PORT_TUNE1 register bits */
  70 #define HSTX_TRIM_MASK                          GENMASK(7, 4)
  71 #define HSTX_TRIM_SHIFT                         0x4
  72 #define PREEMPH_WIDTH_HALF_BIT                  BIT(2)
  73 #define PREEMPHASIS_EN_MASK                     GENMASK(1, 0)
  74 #define PREEMPHASIS_EN_SHIFT                    0x0
  75
  76 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO        0x04
  77 #define QUSB2PHY_PLL_CLOCK_INVERTERS            0x18c
  78 #define QUSB2PHY_PLL_CMODE                      0x2c
  79 #define QUSB2PHY_PLL_LOCK_DELAY                 0x184
  80 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO         0xb4
  81 #define QUSB2PHY_PLL_BIAS_CONTROL_1             0x194
  82 #define QUSB2PHY_PLL_BIAS_CONTROL_2             0x198
  83 #define QUSB2PHY_PWR_CTRL2                      0x214
  84 #define QUSB2PHY_IMP_CTRL1                      0x220
  85 #define QUSB2PHY_IMP_CTRL2                      0x224
  86 #define QUSB2PHY_CHG_CTRL2                      0x23c
  87
  88 struct qusb2_phy_init_tbl {
  89         unsigned int offset;
  90         unsigned int val;
  91         /*
  92          * register part of layout ?
  93          * if yes, then offset gives index in the reg-layout
  94          */
  95         int in_layout;
  96 };
  97
  98 #define QUSB2_PHY_INIT_CFG(o, v) \
  99         {                       \
 100                 .offset = o,    \
 101                 .val = v,       \
 102         }
 103
 104 #define QUSB2_PHY_INIT_CFG_L(o, v) \
 105         {                       \
 106                 .offset = o,    \
 107                 .val = v,       \
 108                 .in_layout = 1, \
 109         }
 110
 111 /* set of registers with offsets different per-PHY */
 112 enum qusb2phy_reg_layout {
 113         QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
 114         QUSB2PHY_PLL_STATUS,
 115         QUSB2PHY_PORT_TUNE1,
 116         QUSB2PHY_PORT_TUNE2,
 117         QUSB2PHY_PORT_TUNE3,
 118         QUSB2PHY_PORT_TUNE4,
 119         QUSB2PHY_PORT_TUNE5,
 120         QUSB2PHY_PORT_TEST1,
 121         QUSB2PHY_PORT_TEST2,
 122         QUSB2PHY_PORT_POWERDOWN,
 123         QUSB2PHY_INTR_CTRL,
 124 };
 125
 126 static const unsigned int msm8996_regs_layout[] = {
 127         [QUSB2PHY_PLL_STATUS]           = 0x38,
 128         [QUSB2PHY_PORT_TUNE1]           = 0x80,
 129         [QUSB2PHY_PORT_TUNE2]           = 0x84,
 130         [QUSB2PHY_PORT_TUNE3]           = 0x88,
 131         [QUSB2PHY_PORT_TUNE4]           = 0x8c,
 132         [QUSB2PHY_PORT_TUNE5]           = 0x90,
 133         [QUSB2PHY_PORT_TEST1]           = 0xb8,
 134         [QUSB2PHY_PORT_TEST2]           = 0x9c,
 135         [QUSB2PHY_PORT_POWERDOWN]       = 0xb4,
 136         [QUSB2PHY_INTR_CTRL]            = 0xbc,
 137 };
 138
 139 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
 140         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
 141         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
 142         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
 143         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
 144
 145         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
 146         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
 147         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
 148
 149         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
 150
 151         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
 152         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 153 };
 154
 155 static const unsigned int sdm845_regs_layout[] = {
 156         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 157         [QUSB2PHY_PLL_STATUS]           = 0x1a0,
 158         [QUSB2PHY_PORT_TUNE1]           = 0x240,
 159         [QUSB2PHY_PORT_TUNE2]           = 0x244,
 160         [QUSB2PHY_PORT_TUNE3]           = 0x248,
 161         [QUSB2PHY_PORT_TUNE4]           = 0x24c,
 162         [QUSB2PHY_PORT_TUNE5]           = 0x250,
 163         [QUSB2PHY_PORT_TEST1]           = 0x254,
 164         [QUSB2PHY_PORT_TEST2]           = 0x258,
 165         [QUSB2PHY_PORT_POWERDOWN]       = 0x210,
 166         [QUSB2PHY_INTR_CTRL]            = 0x230,
 167 };
 168
 169 static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = {
 170         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
 171         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 172         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 173         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 174         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 175         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
 176         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
 177         QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
 178         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
 179         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
 180
 181         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
 182         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
 183         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
 184         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
 185         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
 186
 187         QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
 188 };
 189
 190 struct qusb2_phy_cfg {
 191         const struct qusb2_phy_init_tbl *tbl;
 192         /* number of entries in the table */
 193         unsigned int tbl_num;
 194         /* offset to PHY_CLK_SCHEME register in TCSR map */
 195         unsigned int clk_scheme_offset;
 196
 197         /* array of registers with different offsets */
 198         const unsigned int *regs;
 199         unsigned int mask_core_ready;
 200         unsigned int disable_ctrl;
 201         unsigned int autoresume_en;
 202
 203         /* true if PHY has PLL_TEST register to select clk_scheme */
 204         bool has_pll_test;
 205
 206         /* true if TUNE1 register must be updated by fused value, else TUNE2 */
 207         bool update_tune1_with_efuse;
 208
 209         /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
 210         bool has_pll_override;
 211 };
 212
 213 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
 214         .tbl            = msm8996_init_tbl,
 215         .tbl_num        = ARRAY_SIZE(msm8996_init_tbl),
 216         .regs           = msm8996_regs_layout,
 217
 218         .has_pll_test   = true,
 219         .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 220         .mask_core_ready = PLL_LOCKED,
 221         .autoresume_en   = BIT(3),
 222 };
 223
 224 static const struct qusb2_phy_cfg sdm845_phy_cfg = {
 225         .tbl            = sdm845_init_tbl,
 226         .tbl_num        = ARRAY_SIZE(sdm845_init_tbl),
 227         .regs           = sdm845_regs_layout,
 228
 229         .disable_ctrl   = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
 230                            POWER_DOWN),
 231         .mask_core_ready = CORE_READY_STATUS,
 232         .has_pll_override = true,
 233         .autoresume_en    = BIT(0),
 234 };
 235
 236 static const char * const qusb2_phy_vreg_names[] = {
 237         "vdda-pll", "vdda-phy-dpdm",
 238 };
 239
 240 #define QUSB2_NUM_VREGS         ARRAY_SIZE(qusb2_phy_vreg_names)
 241
 242 /**
 243  * struct qusb2_phy - structure holding qusb2 phy attributes
 244  *
 245  * @phy: generic phy
 246  * @base: iomapped memory space for qubs2 phy
 247  *
 248  * @cfg_ahb_clk: AHB2PHY interface clock
 249  * @ref_clk: phy reference clock
 250  * @iface_clk: phy interface clock
 251  * @phy_reset: phy reset control
 252  * @vregs: regulator supplies bulk data
 253  *
 254  * @tcsr: TCSR syscon register map
 255  * @cell: nvmem cell containing phy tuning value
 256  *
 257  * @override_imp_res_offset: PHY should use different rescode offset
 258  * @imp_res_offset_value: rescode offset to be updated in IMP_CTRL1 register
 259  * @override_hstx_trim: PHY should use different HSTX o/p current value
 260  * @hstx_trim_value: HSTX_TRIM value to be updated in TUNE1 register
 261  * @override_preemphasis: PHY should use different pre-amphasis amplitude
 262  * @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register
 263  * @override_preemphasis_width: PHY should use different pre-emphasis duration
 264  * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
 265  *
 266  * @cfg: phy config data
 267  * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
 268  * @phy_initialized: indicate if PHY has been initialized
 269  * @mode: current PHY mode
 270  */
 271 struct qusb2_phy {
 272         struct phy *phy;
 273         void __iomem *base;
 274
 275         struct clk *cfg_ahb_clk;
 276         struct clk *ref_clk;
 277         struct clk *iface_clk;
 278         struct reset_control *phy_reset;
 279         struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
 280
 281         struct regmap *tcsr;
 282         struct nvmem_cell *cell;
 283
 284         bool override_imp_res_offset;
 285         u8 imp_res_offset_value;
 286         bool override_hstx_trim;
 287         u8 hstx_trim_value;
 288         bool override_preemphasis;
 289         u8 preemphasis_level;
 290         bool override_preemphasis_width;
 291         u8 preemphasis_width;
 292
 293         const struct qusb2_phy_cfg *cfg;
 294         bool has_se_clk_scheme;
 295         bool phy_initialized;
 296         enum phy_mode mode;
 297 };
 298
 299 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
 300                                     u32 val, u32 mask)
 301 {
 302         u32 reg;
 303
 304         reg = readl(base + offset);
 305         reg &= ~mask;
 306         reg |= val & mask;
 307         writel(reg, base + offset);
 308
 309         /* Ensure above write is completed */
 310         readl(base + offset);
 311 }
 312
 313 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
 314 {
 315         u32 reg;
 316
 317         reg = readl(base + offset);
 318         reg |= val;
 319         writel(reg, base + offset);
 320
 321         /* Ensure above write is completed */
 322         readl(base + offset);
 323 }
 324
 325 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
 326 {
 327         u32 reg;
 328
 329         reg = readl(base + offset);
 330         reg &= ~val;
 331         writel(reg, base + offset);
 332
 333         /* Ensure above write is completed */
 334         readl(base + offset);
 335 }
 336
 337 static inline
 338 void qcom_qusb2_phy_configure(void __iomem *base,
 339                               const unsigned int *regs,
 340                               const struct qusb2_phy_init_tbl tbl[], int num)
 341 {
 342         int i;
 343
 344         for (i = 0; i < num; i++) {
 345                 if (tbl[i].in_layout)
 346                         writel(tbl[i].val, base + regs[tbl[i].offset]);
 347                 else
 348                         writel(tbl[i].val, base + tbl[i].offset);
 349         }
 350 }
 351
 352 /*
 353  * Update board specific PHY tuning override values if specified from
 354  * device tree.
 355  */
 356 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
 357 {
 358         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 359
 360         if (qphy->override_imp_res_offset)
 361                 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
 362                              qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT,
 363                              IMP_RES_OFFSET_MASK);
 364
 365         if (qphy->override_hstx_trim)
 366                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 367                                  qphy->hstx_trim_value << HSTX_TRIM_SHIFT,
 368                                  HSTX_TRIM_MASK);
 369
 370         if (qphy->override_preemphasis)
 371                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 372                                 qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT,
 373                                 PREEMPHASIS_EN_MASK);
 374
 375         if (qphy->override_preemphasis_width) {
 376                 if (qphy->preemphasis_width ==
 377                     QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
 378                         qusb2_setbits(qphy->base,
 379                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 380                                       PREEMPH_WIDTH_HALF_BIT);
 381                 else
 382                         qusb2_clrbits(qphy->base,
 383                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 384                                       PREEMPH_WIDTH_HALF_BIT);
 385         }
 386 }
 387
 388 /*
 389  * Fetches HS Tx tuning value from nvmem and sets the
 390  * QUSB2PHY_PORT_TUNE1/2 register.
 391  * For error case, skip setting the value and use the default value.
 392  */
 393 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
 394 {
 395         struct device *dev = &qphy->phy->dev;
 396         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 397         u8 *val;
 398
 399         /* efuse register is optional */
 400         if (!qphy->cell)
 401                 return;
 402
 403         /*
 404          * Read efuse register having TUNE2/1 parameter's high nibble.
 405          * If efuse register shows value as 0x0, or if we fail to find
 406          * a valid efuse register settings, then use default value
 407          * as 0xB for high nibble that we have already set while
 408          * configuring phy.
 409          */
 410         val = nvmem_cell_read(qphy->cell, NULL);
 411         if (IS_ERR(val) || !val[0]) {
 412                 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
 413                 return;
 414         }
 415
 416         /* Fused TUNE1/2 value is the higher nibble only */
 417         if (cfg->update_tune1_with_efuse)
 418                 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 419                               val[0] << 0x4);
 420         else
 421                 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
 422                               val[0] << 0x4);
 423
 424 }
 425
 426 static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
 427 {
 428         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 429
 430         qphy->mode = mode;
 431
 432         return 0;
 433 }
 434
 435 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
 436 {
 437         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 438         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 439         u32 intr_mask;
 440
 441         dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
 442
 443         if (!qphy->phy_initialized) {
 444                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 445                 return 0;
 446         }
 447
 448         /*
 449          * Enable DP/DM interrupts to detect line state changes based on current
 450          * speed. In other words, enable the triggers _opposite_ of what the
 451          * current D+/D- levels are e.g. if currently D+ high, D- low
 452          * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
 453          */
 454         intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
 455         switch (qphy->mode) {
 456         case PHY_MODE_USB_HOST_HS:
 457         case PHY_MODE_USB_HOST_FS:
 458         case PHY_MODE_USB_DEVICE_HS:
 459         case PHY_MODE_USB_DEVICE_FS:
 460                 intr_mask |= DMSE_INTR_HIGH_SEL;
 461                 break;
 462         case PHY_MODE_USB_HOST_LS:
 463         case PHY_MODE_USB_DEVICE_LS:
 464                 intr_mask |= DPSE_INTR_HIGH_SEL;
 465                 break;
 466         default:
 467                 /* No device connected, enable both DP/DM high interrupt */
 468                 intr_mask |= DMSE_INTR_HIGH_SEL;
 469                 intr_mask |= DPSE_INTR_HIGH_SEL;
 470                 break;
 471         }
 472
 473         writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 474
 475         /* hold core PLL into reset */
 476         if (cfg->has_pll_override) {
 477                 qusb2_setbits(qphy->base,
 478                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 479                               CORE_PLL_EN_FROM_RESET | CORE_RESET |
 480                               CORE_RESET_MUX);
 481         }
 482
 483         /* enable phy auto-resume only if device is connected on bus */
 484         if (qphy->mode != PHY_MODE_INVALID) {
 485                 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 486                               cfg->autoresume_en);
 487                 /* Autoresume bit has to be toggled in order to enable it */
 488                 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 489                               cfg->autoresume_en);
 490         }
 491
 492         if (!qphy->has_se_clk_scheme)
 493                 clk_disable_unprepare(qphy->ref_clk);
 494
 495         clk_disable_unprepare(qphy->cfg_ahb_clk);
 496         clk_disable_unprepare(qphy->iface_clk);
 497
 498         return 0;
 499 }
 500
 501 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
 502 {
 503         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 504         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 505         int ret;
 506
 507         dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
 508
 509         if (!qphy->phy_initialized) {
 510                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 511                 return 0;
 512         }
 513
 514         ret = clk_prepare_enable(qphy->iface_clk);
 515         if (ret) {
 516                 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
 517                 return ret;
 518         }
 519
 520         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 521         if (ret) {
 522                 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
 523                 goto disable_iface_clk;
 524         }
 525
 526         if (!qphy->has_se_clk_scheme) {
 527                 clk_prepare_enable(qphy->ref_clk);
 528                 if (ret) {
 529                         dev_err(dev, "failed to enable ref clk, %d\n", ret);
 530                         goto disable_ahb_clk;
 531                 }
 532         }
 533
 534         writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 535
 536         /* bring core PLL out of reset */
 537         if (cfg->has_pll_override) {
 538                 qusb2_clrbits(qphy->base,
 539                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 540                               CORE_RESET | CORE_RESET_MUX);
 541         }
 542
 543         return 0;
 544
 545 disable_ahb_clk:
 546         clk_disable_unprepare(qphy->cfg_ahb_clk);
 547 disable_iface_clk:
 548         clk_disable_unprepare(qphy->iface_clk);
 549
 550         return ret;
 551 }
 552
 553 static int qusb2_phy_init(struct phy *phy)
 554 {
 555         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 556         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 557         unsigned int val = 0;
 558         unsigned int clk_scheme;
 559         int ret;
 560
 561         dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
 562
 563         /* turn on regulator supplies */
 564         ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 565         if (ret)
 566                 return ret;
 567
 568         ret = clk_prepare_enable(qphy->iface_clk);
 569         if (ret) {
 570                 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
 571                 goto poweroff_phy;
 572         }
 573
 574         /* enable ahb interface clock to program phy */
 575         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 576         if (ret) {
 577                 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
 578                 goto disable_iface_clk;
 579         }
 580
 581         /* Perform phy reset */
 582         ret = reset_control_assert(qphy->phy_reset);
 583         if (ret) {
 584                 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
 585                 goto disable_ahb_clk;
 586         }
 587
 588         /* 100 us delay to keep PHY in reset mode */
 589         usleep_range(100, 150);
 590
 591         ret = reset_control_deassert(qphy->phy_reset);
 592         if (ret) {
 593                 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
 594                 goto disable_ahb_clk;
 595         }
 596
 597         /* Disable the PHY */
 598         qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 599                       qphy->cfg->disable_ctrl);
 600
 601         if (cfg->has_pll_test) {
 602                 /* save reset value to override reference clock scheme later */
 603                 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
 604         }
 605
 606         qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
 607                                  cfg->tbl_num);
 608
 609         /* Override board specific PHY tuning values */
 610         qusb2_phy_override_phy_params(qphy);
 611
 612         /* Set efuse value for tuning the PHY */
 613         qusb2_phy_set_tune2_param(qphy);
 614
 615         /* Enable the PHY */
 616         qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 617                       POWER_DOWN);
 618
 619         /* Required to get phy pll lock successfully */
 620         usleep_range(150, 160);
 621
 622         /* Default is single-ended clock on msm8996 */
 623         qphy->has_se_clk_scheme = true;
 624         /*
 625          * read TCSR_PHY_CLK_SCHEME register to check if single-ended
 626          * clock scheme is selected. If yes, then disable differential
 627          * ref_clk and use single-ended clock, otherwise use differential
 628          * ref_clk only.
 629          */
 630         if (qphy->tcsr) {
 631                 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
 632                                   &clk_scheme);
 633                 if (ret) {
 634                         dev_err(&phy->dev, "failed to read clk scheme reg\n");
 635                         goto assert_phy_reset;
 636                 }
 637
 638                 /* is it a differential clock scheme ? */
 639                 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
 640                         dev_vdbg(&phy->dev, "%s(): select differential clk\n",
 641                                  __func__);
 642                         qphy->has_se_clk_scheme = false;
 643                 } else {
 644                         dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
 645                                  __func__);
 646                 }
 647         }
 648
 649         if (!qphy->has_se_clk_scheme) {
 650                 ret = clk_prepare_enable(qphy->ref_clk);
 651                 if (ret) {
 652                         dev_err(&phy->dev, "failed to enable ref clk, %d\n",
 653                                 ret);
 654                         goto assert_phy_reset;
 655                 }
 656         }
 657
 658         if (cfg->has_pll_test) {
 659                 if (!qphy->has_se_clk_scheme)
 660                         val &= ~CLK_REF_SEL;
 661                 else
 662                         val |= CLK_REF_SEL;
 663
 664                 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
 665
 666                 /* ensure above write is through */
 667                 readl(qphy->base + QUSB2PHY_PLL_TEST);
 668         }
 669
 670         /* Required to get phy pll lock successfully */
 671         usleep_range(100, 110);
 672
 673         val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
 674         if (!(val & cfg->mask_core_ready)) {
 675                 dev_err(&phy->dev,
 676                         "QUSB2PHY pll lock failed: status reg = %x\n", val);
 677                 ret = -EBUSY;
 678                 goto disable_ref_clk;
 679         }
 680         qphy->phy_initialized = true;
 681
 682         return 0;
 683
 684 disable_ref_clk:
 685         if (!qphy->has_se_clk_scheme)
 686                 clk_disable_unprepare(qphy->ref_clk);
 687 assert_phy_reset:
 688         reset_control_assert(qphy->phy_reset);
 689 disable_ahb_clk:
 690         clk_disable_unprepare(qphy->cfg_ahb_clk);
 691 disable_iface_clk:
 692         clk_disable_unprepare(qphy->iface_clk);
 693 poweroff_phy:
 694         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 695
 696         return ret;
 697 }
 698
 699 static int qusb2_phy_exit(struct phy *phy)
 700 {
 701         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 702
 703         /* Disable the PHY */
 704         qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 705                       qphy->cfg->disable_ctrl);
 706
 707         if (!qphy->has_se_clk_scheme)
 708                 clk_disable_unprepare(qphy->ref_clk);
 709
 710         reset_control_assert(qphy->phy_reset);
 711
 712         clk_disable_unprepare(qphy->cfg_ahb_clk);
 713         clk_disable_unprepare(qphy->iface_clk);
 714
 715         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 716
 717         qphy->phy_initialized = false;
 718
 719         return 0;
 720 }
 721
 722 static const struct phy_ops qusb2_phy_gen_ops = {
 723         .init           = qusb2_phy_init,
 724         .exit           = qusb2_phy_exit,
 725         .set_mode       = qusb2_phy_set_mode,
 726         .owner          = THIS_MODULE,
 727 };
 728
 729 static const struct of_device_id qusb2_phy_of_match_table[] = {
 730         {
 731                 .compatible     = "qcom,msm8996-qusb2-phy",
 732                 .data           = &msm8996_phy_cfg,
 733         }, {
 734                 .compatible     = "qcom,sdm845-qusb2-phy",
 735                 .data           = &sdm845_phy_cfg,
 736         },
 737         { },
 738 };
 739 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
 740
 741 static const struct dev_pm_ops qusb2_phy_pm_ops = {
 742         SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
 743                            qusb2_phy_runtime_resume, NULL)
 744 };
 745
 746 static int qusb2_phy_probe(struct platform_device *pdev)
 747 {
 748         struct device *dev = &pdev->dev;
 749         struct qusb2_phy *qphy;
 750         struct phy_provider *phy_provider;
 751         struct phy *generic_phy;
 752         struct resource *res;
 753         int ret, i;
 754         int num;
 755         u32 value;
 756
 757         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
 758         if (!qphy)
 759                 return -ENOMEM;
 760
 761         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 762         qphy->base = devm_ioremap_resource(dev, res);
 763         if (IS_ERR(qphy->base))
 764                 return PTR_ERR(qphy->base);
 765
 766         qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
 767         if (IS_ERR(qphy->cfg_ahb_clk)) {
 768                 ret = PTR_ERR(qphy->cfg_ahb_clk);
 769                 if (ret != -EPROBE_DEFER)
 770                         dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
 771                 return ret;
 772         }
 773
 774         qphy->ref_clk = devm_clk_get(dev, "ref");
 775         if (IS_ERR(qphy->ref_clk)) {
 776                 ret = PTR_ERR(qphy->ref_clk);
 777                 if (ret != -EPROBE_DEFER)
 778                         dev_err(dev, "failed to get ref clk, %d\n", ret);
 779                 return ret;
 780         }
 781
 782         qphy->iface_clk = devm_clk_get(dev, "iface");
 783         if (IS_ERR(qphy->iface_clk)) {
 784                 ret = PTR_ERR(qphy->iface_clk);
 785                 if (ret == -EPROBE_DEFER)
 786                         return ret;
 787                 qphy->iface_clk = NULL;
 788                 dev_dbg(dev, "failed to get iface clk, %d\n", ret);
 789         }
 790
 791         qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
 792         if (IS_ERR(qphy->phy_reset)) {
 793                 dev_err(dev, "failed to get phy core reset\n");
 794                 return PTR_ERR(qphy->phy_reset);
 795         }
 796
 797         num = ARRAY_SIZE(qphy->vregs);
 798         for (i = 0; i < num; i++)
 799                 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
 800
 801         ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
 802         if (ret) {
 803                 if (ret != -EPROBE_DEFER)
 804                         dev_err(dev, "failed to get regulator supplies: %d\n",
 805                                 ret);
 806                 return ret;
 807         }
 808
 809         /* Get the specific init parameters of QMP phy */
 810         qphy->cfg = of_device_get_match_data(dev);
 811
 812         qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
 813                                                         "qcom,tcsr-syscon");
 814         if (IS_ERR(qphy->tcsr)) {
 815                 dev_dbg(dev, "failed to lookup TCSR regmap\n");
 816                 qphy->tcsr = NULL;
 817         }
 818
 819         qphy->cell = devm_nvmem_cell_get(dev, NULL);
 820         if (IS_ERR(qphy->cell)) {
 821                 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
 822                         return -EPROBE_DEFER;
 823                 qphy->cell = NULL;
 824                 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
 825         }
 826
 827         if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
 828                                   &value)) {
 829                 qphy->imp_res_offset_value = (u8)value;
 830                 qphy->override_imp_res_offset = true;
 831         }
 832
 833         if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
 834                                   &value)) {
 835                 qphy->hstx_trim_value = (u8)value;
 836                 qphy->override_hstx_trim = true;
 837         }
 838
 839         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
 840                                      &value)) {
 841                 qphy->preemphasis_level = (u8)value;
 842                 qphy->override_preemphasis = true;
 843         }
 844
 845         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
 846                                      &value)) {
 847                 qphy->preemphasis_width = (u8)value;
 848                 qphy->override_preemphasis_width = true;
 849         }
 850
 851         pm_runtime_set_active(dev);
 852         pm_runtime_enable(dev);
 853         /*
 854          * Prevent runtime pm from being ON by default. Users can enable
 855          * it using power/control in sysfs.
 856          */
 857         pm_runtime_forbid(dev);
 858
 859         generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
 860         if (IS_ERR(generic_phy)) {
 861                 ret = PTR_ERR(generic_phy);
 862                 dev_err(dev, "failed to create phy, %d\n", ret);
 863                 pm_runtime_disable(dev);
 864                 return ret;
 865         }
 866         qphy->phy = generic_phy;
 867
 868         dev_set_drvdata(dev, qphy);
 869         phy_set_drvdata(generic_phy, qphy);
 870
 871         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 872         if (!IS_ERR(phy_provider))
 873                 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
 874         else
 875                 pm_runtime_disable(dev);
 876
 877         return PTR_ERR_OR_ZERO(phy_provider);
 878 }
 879
 880 static struct platform_driver qusb2_phy_driver = {
 881         .probe          = qusb2_phy_probe,
 882         .driver = {
 883                 .name   = "qcom-qusb2-phy",
 884                 .pm     = &qusb2_phy_pm_ops,
 885                 .of_match_table = qusb2_phy_of_match_table,
 886         },
 887 };
 888
 889 module_platform_driver(qusb2_phy_driver);
 890
 891 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
 892 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
 893 MODULE_LICENSE("GPL v2");