drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 /* QPHY_COM_PCS_READY_STATUS bit */
  39 #define PCS_READY                               BIT(0)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64 #define RCVR_DETECT                             BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 #define PHY_INIT_COMPLETE_TIMEOUT               1000
  70 #define POWER_DOWN_DELAY_US_MIN                 10
  71 #define POWER_DOWN_DELAY_US_MAX                 11
  72
  73 #define MAX_PROP_NAME                           32
  74
  75 /* Define the assumed distance between lanes for underspecified device trees. */
  76 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  77
  78 struct qmp_phy_init_tbl {
  79         unsigned int offset;
  80         unsigned int val;
  81         /*
  82          * register part of layout ?
  83          * if yes, then offset gives index in the reg-layout
  84          */
  85         int in_layout;
  86 };
  87
  88 #define QMP_PHY_INIT_CFG(o, v)          \
  89         {                               \
  90                 .offset = o,            \
  91                 .val = v,               \
  92         }
  93
  94 #define QMP_PHY_INIT_CFG_L(o, v)        \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .in_layout = 1,         \
  99         }
 100
 101 /* set of registers with offsets different per-PHY */
 102 enum qphy_reg_layout {
 103         /* Common block control registers */
 104         QPHY_COM_SW_RESET,
 105         QPHY_COM_POWER_DOWN_CONTROL,
 106         QPHY_COM_START_CONTROL,
 107         QPHY_COM_PCS_READY_STATUS,
 108         /* PCS registers */
 109         QPHY_PLL_LOCK_CHK_DLY_TIME,
 110         QPHY_FLL_CNTRL1,
 111         QPHY_FLL_CNTRL2,
 112         QPHY_FLL_CNT_VAL_L,
 113         QPHY_FLL_CNT_VAL_H_TOL,
 114         QPHY_FLL_MAN_CODE,
 115         QPHY_SW_RESET,
 116         QPHY_START_CTRL,
 117         QPHY_PCS_READY_STATUS,
 118         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 119         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 120         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 121 };
 122
 123 static const unsigned int pciephy_regs_layout[] = {
 124         [QPHY_COM_SW_RESET]             = 0x400,
 125         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 126         [QPHY_COM_START_CONTROL]        = 0x408,
 127         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 128         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 129         [QPHY_FLL_CNTRL1]               = 0xc4,
 130         [QPHY_FLL_CNTRL2]               = 0xc8,
 131         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 132         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 133         [QPHY_FLL_MAN_CODE]             = 0xd4,
 134         [QPHY_SW_RESET]                 = 0x00,
 135         [QPHY_START_CTRL]               = 0x08,
 136         [QPHY_PCS_READY_STATUS]         = 0x174,
 137 };
 138
 139 static const unsigned int usb3phy_regs_layout[] = {
 140         [QPHY_FLL_CNTRL1]               = 0xc0,
 141         [QPHY_FLL_CNTRL2]               = 0xc4,
 142         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 143         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 144         [QPHY_FLL_MAN_CODE]             = 0xd0,
 145         [QPHY_SW_RESET]                 = 0x00,
 146         [QPHY_START_CTRL]               = 0x08,
 147         [QPHY_PCS_READY_STATUS]         = 0x17c,
 148         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 149         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 150         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 151 };
 152
 153 static const unsigned int qmp_v3_usb3phy_regs_layout[] = {
 154         [QPHY_SW_RESET]                 = 0x00,
 155         [QPHY_START_CTRL]               = 0x08,
 156         [QPHY_PCS_READY_STATUS]         = 0x174,
 157         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 158         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 159         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 160 };
 161
 162 static const unsigned int sdm845_ufsphy_regs_layout[] = {
 163         [QPHY_START_CTRL]               = 0x00,
 164         [QPHY_PCS_READY_STATUS]         = 0x160,
 165 };
 166
 167 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 168         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 169         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 170         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 171         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 172         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 173         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 174         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 175         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 176         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 177         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 178         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 179         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 180         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 181         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 182         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 183         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 184         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 185         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 186         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 187         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 188         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 189         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 190         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 191         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 192         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 193         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 194         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 195         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 199         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 203         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 204         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 205         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 206         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 207         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 208         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 209         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 210         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 211 };
 212
 213 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 214         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 215         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 216 };
 217
 218 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 219         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 220         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 221         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 222         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 223         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 224         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 225         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 226         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 227         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 228         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 229 };
 230
 231 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 232         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 233         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 234         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 235
 236         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 237
 238         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 239         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 240         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 241         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 242         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 243 };
 244
 245 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 246         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 247         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 248         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 250         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 251         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 253         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 255         /* PLL and Loop filter settings */
 256         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 262         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 263         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 264         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 265         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 266         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 267         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 268         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 272         /* SSC settings */
 273         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 278         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 279         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 280 };
 281
 282 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 283         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 284         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 285         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 286 };
 287
 288 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 289         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 290         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 291         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 292         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 293         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 294         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 295         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 296         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 297         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 298         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 299 };
 300
 301 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 302         /* FLL settings */
 303         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 304         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 305         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 306         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 307         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 308
 309         /* Lock Det settings */
 310         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 311         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 312         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 313         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 314 };
 315
 316 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 317         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 338         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 339         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 349         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
 350         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 354         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 355         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 356         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 357         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 358         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
 359 };
 360
 361 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 362         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 363         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 364         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 365         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 366 };
 367
 368 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 369         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 370         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 371         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 372         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 373         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 374         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 375         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 376         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
 377 };
 378
 379 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 380         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 381         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 382         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 383         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 384         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 385         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 386         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 387         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 388         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 389         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 390         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 391         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 392         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 393 };
 394
 395 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 414         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 415         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 416         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 417         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 418         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 419         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 420         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 421         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 424         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 425         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 426         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 427         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 429         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 430         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 432 };
 433
 434 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 435         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 440 };
 441
 442 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 443         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 444         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 445         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 446         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 447         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 448         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 449         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 450         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 451         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 452 };
 453
 454 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 455         /* FLL settings */
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 458         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 459         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 460         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 461
 462         /* Lock Det settings */
 463         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 464         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 465         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 466         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 467
 468         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 469         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 470         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 471         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 472         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 473         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 474         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 475         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 476         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 477         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 478         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 479         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 480         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 481         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 482         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 483         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 484         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 485         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 486         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 487
 488         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 489         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 490         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 491         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 492         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 493         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 494         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 495         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 496         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 497         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 498         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 499 };
 500
 501 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 502         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 503         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 504         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 505         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 506         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 507         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 508         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 509         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 510         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 511         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 512         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 513         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 514         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 515         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 516         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 517         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 518         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 519         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 520         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 521         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 522         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 523         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 524         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 525         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 526         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 527         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 528         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 529         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 530         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 531         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 532         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 533         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 534         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 535         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 536         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 537         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 538 };
 539
 540 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 541         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 542         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 543         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 544         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 545         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 546 };
 547
 548 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 549         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 550         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 551         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 552         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 553         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 554         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 555         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 556         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 557         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 558         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 559         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 560 };
 561
 562 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 563         /* FLL settings */
 564         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 565         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 566         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 567         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 568         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 569
 570         /* Lock Det settings */
 571         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 572         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 573         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 574         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 575
 576         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 577         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 578         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 579         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 580         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 581         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 582         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 583         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 584         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 585         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 586         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 587         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 588         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 589         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 590         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 591         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 592         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 593         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 594         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 595
 596         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 597         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 598         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 599         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 600         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 601         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 602         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 603         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 604         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 605         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 606         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 607
 608         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 609         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 610 };
 611
 612 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
 613         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 614         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 615         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 616         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 617         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 618         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
 619         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 620         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 621         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 622         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 623         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 624         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 625         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
 626         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
 627         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
 628         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
 629         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 630         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 631         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 632         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 633         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 634         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 635         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
 636         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 637         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
 638         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
 639         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
 640         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
 641         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
 642         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
 643         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 644         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 645         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
 646         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
 647         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
 648         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
 649
 650         /* Rate B */
 651         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 652 };
 653
 654 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
 655         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 656         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
 657         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 658 };
 659
 660 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
 661         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 662         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 663         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 664         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 665         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 666         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 667         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 668         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 669         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 670         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 671         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 672         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 673         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 674         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 675         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 676         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 677 };
 678
 679 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
 680         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
 681         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 682         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
 683         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
 684         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
 685         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
 686         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
 687         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
 688 };
 689
 690 /* struct qmp_phy_cfg - per-PHY initialization config */
 691 struct qmp_phy_cfg {
 692         /* phy-type - PCIE/UFS/USB */
 693         unsigned int type;
 694         /* number of lanes provided by phy */
 695         int nlanes;
 696
 697         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 698         const struct qmp_phy_init_tbl *serdes_tbl;
 699         int serdes_tbl_num;
 700         const struct qmp_phy_init_tbl *tx_tbl;
 701         int tx_tbl_num;
 702         const struct qmp_phy_init_tbl *rx_tbl;
 703         int rx_tbl_num;
 704         const struct qmp_phy_init_tbl *pcs_tbl;
 705         int pcs_tbl_num;
 706
 707         /* clock ids to be requested */
 708         const char * const *clk_list;
 709         int num_clks;
 710         /* resets to be requested */
 711         const char * const *reset_list;
 712         int num_resets;
 713         /* regulators to be requested */
 714         const char * const *vreg_list;
 715         int num_vregs;
 716
 717         /* array of registers with different offsets */
 718         const unsigned int *regs;
 719
 720         unsigned int start_ctrl;
 721         unsigned int pwrdn_ctrl;
 722         unsigned int mask_pcs_ready;
 723         unsigned int mask_com_pcs_ready;
 724
 725         /* true, if PHY has a separate PHY_COM control block */
 726         bool has_phy_com_ctrl;
 727         /* true, if PHY has a reset for individual lanes */
 728         bool has_lane_rst;
 729         /* true, if PHY needs delay after POWER_DOWN */
 730         bool has_pwrdn_delay;
 731         /* power_down delay in usec */
 732         int pwrdn_delay_min;
 733         int pwrdn_delay_max;
 734
 735         /* true, if PHY has a separate DP_COM control block */
 736         bool has_phy_dp_com_ctrl;
 737         /* true, if PHY has secondary tx/rx lanes to be configured */
 738         bool is_dual_lane_phy;
 739
 740         /* true, if PCS block has no separate SW_RESET register */
 741         bool no_pcs_sw_reset;
 742 };
 743
 744 /**
 745  * struct qmp_phy - per-lane phy descriptor
 746  *
 747  * @phy: generic phy
 748  * @tx: iomapped memory space for lane's tx
 749  * @rx: iomapped memory space for lane's rx
 750  * @pcs: iomapped memory space for lane's pcs
 751  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
 752  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
 753  * @pcs_misc: iomapped memory space for lane's pcs_misc
 754  * @pipe_clk: pipe lock
 755  * @index: lane index
 756  * @qmp: QMP phy to which this lane belongs
 757  * @lane_rst: lane's reset controller
 758  */
 759 struct qmp_phy {
 760         struct phy *phy;
 761         void __iomem *tx;
 762         void __iomem *rx;
 763         void __iomem *pcs;
 764         void __iomem *tx2;
 765         void __iomem *rx2;
 766         void __iomem *pcs_misc;
 767         struct clk *pipe_clk;
 768         unsigned int index;
 769         struct qcom_qmp *qmp;
 770         struct reset_control *lane_rst;
 771 };
 772
 773 /**
 774  * struct qcom_qmp - structure holding QMP phy block attributes
 775  *
 776  * @dev: device
 777  * @serdes: iomapped memory space for phy's serdes
 778  * @dp_com: iomapped memory space for phy's dp_com control block
 779  *
 780  * @clks: array of clocks required by phy
 781  * @resets: array of resets required by phy
 782  * @vregs: regulator supplies bulk data
 783  *
 784  * @cfg: phy specific configuration
 785  * @phys: array of per-lane phy descriptors
 786  * @phy_mutex: mutex lock for PHY common block initialization
 787  * @init_count: phy common block initialization count
 788  * @phy_initialized: indicate if PHY has been initialized
 789  * @mode: current PHY mode
 790  */
 791 struct qcom_qmp {
 792         struct device *dev;
 793         void __iomem *serdes;
 794         void __iomem *dp_com;
 795
 796         struct clk_bulk_data *clks;
 797         struct reset_control **resets;
 798         struct regulator_bulk_data *vregs;
 799
 800         const struct qmp_phy_cfg *cfg;
 801         struct qmp_phy **phys;
 802
 803         struct mutex phy_mutex;
 804         int init_count;
 805         bool phy_initialized;
 806         enum phy_mode mode;
 807 };
 808
 809 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 810 {
 811         u32 reg;
 812
 813         reg = readl(base + offset);
 814         reg |= val;
 815         writel(reg, base + offset);
 816
 817         /* ensure that above write is through */
 818         readl(base + offset);
 819 }
 820
 821 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 822 {
 823         u32 reg;
 824
 825         reg = readl(base + offset);
 826         reg &= ~val;
 827         writel(reg, base + offset);
 828
 829         /* ensure that above write is through */
 830         readl(base + offset);
 831 }
 832
 833 /* list of clocks required by phy */
 834 static const char * const msm8996_phy_clk_l[] = {
 835         "aux", "cfg_ahb", "ref",
 836 };
 837
 838 static const char * const qmp_v3_phy_clk_l[] = {
 839         "aux", "cfg_ahb", "ref", "com_aux",
 840 };
 841
 842 static const char * const sdm845_ufs_phy_clk_l[] = {
 843         "ref", "ref_aux",
 844 };
 845
 846 /* list of resets */
 847 static const char * const msm8996_pciephy_reset_l[] = {
 848         "phy", "common", "cfg",
 849 };
 850
 851 static const char * const msm8996_usb3phy_reset_l[] = {
 852         "phy", "common",
 853 };
 854
 855 /* list of regulators */
 856 static const char * const qmp_phy_vreg_l[] = {
 857         "vdda-phy", "vdda-pll",
 858 };
 859
 860 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
 861         .type                   = PHY_TYPE_PCIE,
 862         .nlanes                 = 3,
 863
 864         .serdes_tbl             = msm8996_pcie_serdes_tbl,
 865         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
 866         .tx_tbl                 = msm8996_pcie_tx_tbl,
 867         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
 868         .rx_tbl                 = msm8996_pcie_rx_tbl,
 869         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
 870         .pcs_tbl                = msm8996_pcie_pcs_tbl,
 871         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
 872         .clk_list               = msm8996_phy_clk_l,
 873         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
 874         .reset_list             = msm8996_pciephy_reset_l,
 875         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
 876         .vreg_list              = qmp_phy_vreg_l,
 877         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 878         .regs                   = pciephy_regs_layout,
 879
 880         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
 881         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
 882         .mask_com_pcs_ready     = PCS_READY,
 883
 884         .has_phy_com_ctrl       = true,
 885         .has_lane_rst           = true,
 886         .has_pwrdn_delay        = true,
 887         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
 888         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
 889 };
 890
 891 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
 892         .type                   = PHY_TYPE_USB3,
 893         .nlanes                 = 1,
 894
 895         .serdes_tbl             = msm8996_usb3_serdes_tbl,
 896         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
 897         .tx_tbl                 = msm8996_usb3_tx_tbl,
 898         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
 899         .rx_tbl                 = msm8996_usb3_rx_tbl,
 900         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
 901         .pcs_tbl                = msm8996_usb3_pcs_tbl,
 902         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
 903         .clk_list               = msm8996_phy_clk_l,
 904         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
 905         .reset_list             = msm8996_usb3phy_reset_l,
 906         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
 907         .vreg_list              = qmp_phy_vreg_l,
 908         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 909         .regs                   = usb3phy_regs_layout,
 910
 911         .start_ctrl             = SERDES_START | PCS_START,
 912         .pwrdn_ctrl             = SW_PWRDN,
 913         .mask_pcs_ready         = PHYSTATUS,
 914 };
 915
 916 /* list of resets */
 917 static const char * const ipq8074_pciephy_reset_l[] = {
 918         "phy", "common",
 919 };
 920
 921 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
 922         .type                   = PHY_TYPE_PCIE,
 923         .nlanes                 = 1,
 924
 925         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
 926         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
 927         .tx_tbl                 = ipq8074_pcie_tx_tbl,
 928         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
 929         .rx_tbl                 = ipq8074_pcie_rx_tbl,
 930         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
 931         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
 932         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
 933         .clk_list               = NULL,
 934         .num_clks               = 0,
 935         .reset_list             = ipq8074_pciephy_reset_l,
 936         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
 937         .vreg_list              = NULL,
 938         .num_vregs              = 0,
 939         .regs                   = pciephy_regs_layout,
 940
 941         .start_ctrl             = SERDES_START | PCS_START,
 942         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
 943         .mask_pcs_ready         = PHYSTATUS,
 944
 945         .has_phy_com_ctrl       = false,
 946         .has_lane_rst           = false,
 947         .has_pwrdn_delay        = true,
 948         .pwrdn_delay_min        = 995,          /* us */
 949         .pwrdn_delay_max        = 1005,         /* us */
 950 };
 951
 952 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
 953         .type                   = PHY_TYPE_USB3,
 954         .nlanes                 = 1,
 955
 956         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
 957         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
 958         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
 959         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
 960         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
 961         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
 962         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
 963         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
 964         .clk_list               = qmp_v3_phy_clk_l,
 965         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
 966         .reset_list             = msm8996_usb3phy_reset_l,
 967         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
 968         .vreg_list              = qmp_phy_vreg_l,
 969         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 970         .regs                   = qmp_v3_usb3phy_regs_layout,
 971
 972         .start_ctrl             = SERDES_START | PCS_START,
 973         .pwrdn_ctrl             = SW_PWRDN,
 974         .mask_pcs_ready         = PHYSTATUS,
 975
 976         .has_pwrdn_delay        = true,
 977         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
 978         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
 979
 980         .has_phy_dp_com_ctrl    = true,
 981         .is_dual_lane_phy       = true,
 982 };
 983
 984 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
 985         .type                   = PHY_TYPE_USB3,
 986         .nlanes                 = 1,
 987
 988         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
 989         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
 990         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
 991         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
 992         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
 993         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
 994         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
 995         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
 996         .clk_list               = qmp_v3_phy_clk_l,
 997         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
 998         .reset_list             = msm8996_usb3phy_reset_l,
 999         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1000         .vreg_list              = qmp_phy_vreg_l,
1001         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1002         .regs                   = qmp_v3_usb3phy_regs_layout,
1003
1004         .start_ctrl             = SERDES_START | PCS_START,
1005         .pwrdn_ctrl             = SW_PWRDN,
1006         .mask_pcs_ready         = PHYSTATUS,
1007
1008         .has_pwrdn_delay        = true,
1009         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1010         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1011 };
1012
1013 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1014         .type                   = PHY_TYPE_UFS,
1015         .nlanes                 = 2,
1016
1017         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
1018         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
1019         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
1020         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
1021         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
1022         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
1023         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
1024         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
1025         .clk_list               = sdm845_ufs_phy_clk_l,
1026         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1027         .vreg_list              = qmp_phy_vreg_l,
1028         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1029         .regs                   = sdm845_ufsphy_regs_layout,
1030
1031         .start_ctrl             = SERDES_START,
1032         .pwrdn_ctrl             = SW_PWRDN,
1033         .mask_pcs_ready         = PCS_READY,
1034
1035         .is_dual_lane_phy       = true,
1036         .no_pcs_sw_reset        = true,
1037 };
1038
1039 static void qcom_qmp_phy_configure(void __iomem *base,
1040                                    const unsigned int *regs,
1041                                    const struct qmp_phy_init_tbl tbl[],
1042                                    int num)
1043 {
1044         int i;
1045         const struct qmp_phy_init_tbl *t = tbl;
1046
1047         if (!t)
1048                 return;
1049
1050         for (i = 0; i < num; i++, t++) {
1051                 if (t->in_layout)
1052                         writel(t->val, base + regs[t->offset]);
1053                 else
1054                         writel(t->val, base + t->offset);
1055         }
1056 }
1057
1058 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
1059 {
1060         struct qcom_qmp *qmp = qphy->qmp;
1061         const struct qmp_phy_cfg *cfg = qmp->cfg;
1062         void __iomem *serdes = qmp->serdes;
1063         void __iomem *pcs = qphy->pcs;
1064         void __iomem *dp_com = qmp->dp_com;
1065         int ret, i;
1066
1067         mutex_lock(&qmp->phy_mutex);
1068         if (qmp->init_count++) {
1069                 mutex_unlock(&qmp->phy_mutex);
1070                 return 0;
1071         }
1072
1073         /* turn on regulator supplies */
1074         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1075         if (ret) {
1076                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1077                 goto err_reg_enable;
1078         }
1079
1080         for (i = 0; i < cfg->num_resets; i++) {
1081                 ret = reset_control_assert(qmp->resets[i]);
1082                 if (ret) {
1083                         dev_err(qmp->dev, "%s reset assert failed\n",
1084                                 cfg->reset_list[i]);
1085                         goto err_rst_assert;
1086                 }
1087         }
1088
1089         for (i = cfg->num_resets - 1; i >= 0; i--) {
1090                 ret = reset_control_deassert(qmp->resets[i]);
1091                 if (ret) {
1092                         dev_err(qmp->dev, "%s reset deassert failed\n",
1093                                 qmp->cfg->reset_list[i]);
1094                         goto err_rst;
1095                 }
1096         }
1097
1098         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1099         if (ret) {
1100                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1101                 goto err_rst;
1102         }
1103
1104         if (cfg->has_phy_dp_com_ctrl) {
1105                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
1106                              SW_PWRDN);
1107                 /* override hardware control for reset of qmp phy */
1108                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1109                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1110                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1111
1112                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
1113                              USB3_MODE | DP_MODE);
1114
1115                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
1116                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
1117                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
1118                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
1119         }
1120
1121         if (cfg->has_phy_com_ctrl)
1122                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1123                              SW_PWRDN);
1124         else
1125                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1126
1127         /* Serdes configuration */
1128         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
1129                                cfg->serdes_tbl_num);
1130
1131         if (cfg->has_phy_com_ctrl) {
1132                 void __iomem *status;
1133                 unsigned int mask, val;
1134
1135                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
1136                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1137                              SERDES_START | PCS_START);
1138
1139                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
1140                 mask = cfg->mask_com_pcs_ready;
1141
1142                 ret = readl_poll_timeout(status, val, (val & mask), 10,
1143                                          PHY_INIT_COMPLETE_TIMEOUT);
1144                 if (ret) {
1145                         dev_err(qmp->dev,
1146                                 "phy common block init timed-out\n");
1147                         goto err_com_init;
1148                 }
1149         }
1150
1151         mutex_unlock(&qmp->phy_mutex);
1152
1153         return 0;
1154
1155 err_com_init:
1156         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1157 err_rst:
1158         while (++i < cfg->num_resets)
1159                 reset_control_assert(qmp->resets[i]);
1160 err_rst_assert:
1161         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1162 err_reg_enable:
1163         mutex_unlock(&qmp->phy_mutex);
1164
1165         return ret;
1166 }
1167
1168 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
1169 {
1170         const struct qmp_phy_cfg *cfg = qmp->cfg;
1171         void __iomem *serdes = qmp->serdes;
1172         int i = cfg->num_resets;
1173
1174         mutex_lock(&qmp->phy_mutex);
1175         if (--qmp->init_count) {
1176                 mutex_unlock(&qmp->phy_mutex);
1177                 return 0;
1178         }
1179
1180         if (cfg->has_phy_com_ctrl) {
1181                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
1182                              SERDES_START | PCS_START);
1183                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
1184                              SW_RESET);
1185                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
1186                              SW_PWRDN);
1187         }
1188
1189         while (--i >= 0)
1190                 reset_control_assert(qmp->resets[i]);
1191
1192         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1193
1194         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1195
1196         mutex_unlock(&qmp->phy_mutex);
1197
1198         return 0;
1199 }
1200
1201 /* PHY Initialization */
1202 static int qcom_qmp_phy_init(struct phy *phy)
1203 {
1204         struct qmp_phy *qphy = phy_get_drvdata(phy);
1205         struct qcom_qmp *qmp = qphy->qmp;
1206         const struct qmp_phy_cfg *cfg = qmp->cfg;
1207         void __iomem *tx = qphy->tx;
1208         void __iomem *rx = qphy->rx;
1209         void __iomem *pcs = qphy->pcs;
1210         void __iomem *dp_com = qmp->dp_com;
1211         void __iomem *status;
1212         unsigned int mask, val;
1213         int ret;
1214
1215         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1216
1217         ret = qcom_qmp_phy_com_init(qphy);
1218         if (ret)
1219                 return ret;
1220
1221         if (cfg->has_lane_rst) {
1222                 ret = reset_control_deassert(qphy->lane_rst);
1223                 if (ret) {
1224                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
1225                                 qphy->index);
1226                         goto err_lane_rst;
1227                 }
1228         }
1229
1230         ret = clk_prepare_enable(qphy->pipe_clk);
1231         if (ret) {
1232                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1233                 goto err_clk_enable;
1234         }
1235
1236         /* Tx, Rx, and PCS configurations */
1237         qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);
1238         /* Configuration for other LANE for USB-DP combo PHY */
1239         if (cfg->is_dual_lane_phy)
1240                 qcom_qmp_phy_configure(qphy->tx2, cfg->regs,
1241                                        cfg->tx_tbl, cfg->tx_tbl_num);
1242
1243         qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);
1244         if (cfg->is_dual_lane_phy)
1245                 qcom_qmp_phy_configure(qphy->rx2, cfg->regs,
1246                                        cfg->rx_tbl, cfg->rx_tbl_num);
1247
1248         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1249
1250         /*
1251          * UFS PHY requires the deassert of software reset before serdes start.
1252          * For UFS PHYs that do not have software reset control bits, defer
1253          * starting serdes until the power on callback.
1254          */
1255         if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset)
1256                 goto out;
1257
1258         /*
1259          * Pull out PHY from POWER DOWN state.
1260          * This is active low enable signal to power-down PHY.
1261          */
1262         if(cfg->type == PHY_TYPE_PCIE)
1263                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1264
1265         if (cfg->has_pwrdn_delay)
1266                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
1267
1268         /* Pull PHY out of reset state */
1269         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1270         if (cfg->has_phy_dp_com_ctrl)
1271                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
1272
1273         /* start SerDes and Phy-Coding-Sublayer */
1274         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1275
1276         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1277         mask = cfg->mask_pcs_ready;
1278
1279         ret = readl_poll_timeout(status, val, !(val & mask), 1,
1280                                  PHY_INIT_COMPLETE_TIMEOUT);
1281         if (ret) {
1282                 dev_err(qmp->dev, "phy initialization timed-out\n");
1283                 goto err_pcs_ready;
1284         }
1285         qmp->phy_initialized = true;
1286
1287 out:
1288         return ret;
1289
1290 err_pcs_ready:
1291         clk_disable_unprepare(qphy->pipe_clk);
1292 err_clk_enable:
1293         if (cfg->has_lane_rst)
1294                 reset_control_assert(qphy->lane_rst);
1295 err_lane_rst:
1296         qcom_qmp_phy_com_exit(qmp);
1297
1298         return ret;
1299 }
1300
1301 static int qcom_qmp_phy_exit(struct phy *phy)
1302 {
1303         struct qmp_phy *qphy = phy_get_drvdata(phy);
1304         struct qcom_qmp *qmp = qphy->qmp;
1305         const struct qmp_phy_cfg *cfg = qmp->cfg;
1306
1307         clk_disable_unprepare(qphy->pipe_clk);
1308
1309         /* PHY reset */
1310         if (!cfg->no_pcs_sw_reset)
1311                 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1312
1313         /* stop SerDes and Phy-Coding-Sublayer */
1314         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1315
1316         /* Put PHY into POWER DOWN state: active low */
1317         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
1318
1319         if (cfg->has_lane_rst)
1320                 reset_control_assert(qphy->lane_rst);
1321
1322         qcom_qmp_phy_com_exit(qmp);
1323
1324         qmp->phy_initialized = false;
1325
1326         return 0;
1327 }
1328
1329 static int qcom_qmp_phy_poweron(struct phy *phy)
1330 {
1331         struct qmp_phy *qphy = phy_get_drvdata(phy);
1332         struct qcom_qmp *qmp = qphy->qmp;
1333         const struct qmp_phy_cfg *cfg = qmp->cfg;
1334         void __iomem *pcs = qphy->pcs;
1335         void __iomem *status;
1336         unsigned int mask, val;
1337         int ret = 0;
1338
1339         if (cfg->type != PHY_TYPE_UFS)
1340                 return 0;
1341
1342         /*
1343          * For UFS PHY that has not software reset control, serdes start
1344          * should only happen when UFS driver explicitly calls phy_power_on
1345          * after it deasserts software reset.
1346          */
1347         if (cfg->no_pcs_sw_reset && !qmp->phy_initialized &&
1348             (qmp->init_count != 0)) {
1349                 /* start SerDes and Phy-Coding-Sublayer */
1350                 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
1351
1352                 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1353                 mask = cfg->mask_pcs_ready;
1354
1355                 ret = readl_poll_timeout(status, val, !(val & mask), 1,
1356                                          PHY_INIT_COMPLETE_TIMEOUT);
1357                 if (ret) {
1358                         dev_err(qmp->dev, "phy initialization timed-out\n");
1359                         return ret;
1360                 }
1361                 qmp->phy_initialized = true;
1362         }
1363
1364         return ret;
1365 }
1366
1367 static int qcom_qmp_phy_set_mode(struct phy *phy,
1368                                  enum phy_mode mode, int submode)
1369 {
1370         struct qmp_phy *qphy = phy_get_drvdata(phy);
1371         struct qcom_qmp *qmp = qphy->qmp;
1372
1373         qmp->mode = mode;
1374
1375         return 0;
1376 }
1377
1378 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
1379 {
1380         struct qcom_qmp *qmp = qphy->qmp;
1381         const struct qmp_phy_cfg *cfg = qmp->cfg;
1382         void __iomem *pcs = qphy->pcs;
1383         void __iomem *pcs_misc = qphy->pcs_misc;
1384         u32 intr_mask;
1385
1386         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1387             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1388                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1389         else
1390                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1391
1392         /* Clear any pending interrupts status */
1393         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1394         /* Writing 1 followed by 0 clears the interrupt */
1395         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1396
1397         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1398                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1399
1400         /* Enable required PHY autonomous mode interrupts */
1401         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1402
1403         /* Enable i/o clamp_n for autonomous mode */
1404         if (pcs_misc)
1405                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1406 }
1407
1408 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
1409 {
1410         struct qcom_qmp *qmp = qphy->qmp;
1411         const struct qmp_phy_cfg *cfg = qmp->cfg;
1412         void __iomem *pcs = qphy->pcs;
1413         void __iomem *pcs_misc = qphy->pcs_misc;
1414
1415         /* Disable i/o clamp_n on resume for normal mode */
1416         if (pcs_misc)
1417                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1418
1419         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1420                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1421
1422         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1423         /* Writing 1 followed by 0 clears the interrupt */
1424         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1425 }
1426
1427 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
1428 {
1429         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1430         struct qmp_phy *qphy = qmp->phys[0];
1431         const struct qmp_phy_cfg *cfg = qmp->cfg;
1432
1433         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1434
1435         /* Supported only for USB3 PHY */
1436         if (cfg->type != PHY_TYPE_USB3)
1437                 return 0;
1438
1439         if (!qmp->phy_initialized) {
1440                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1441                 return 0;
1442         }
1443
1444         qcom_qmp_phy_enable_autonomous_mode(qphy);
1445
1446         clk_disable_unprepare(qphy->pipe_clk);
1447         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1448
1449         return 0;
1450 }
1451
1452 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
1453 {
1454         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1455         struct qmp_phy *qphy = qmp->phys[0];
1456         const struct qmp_phy_cfg *cfg = qmp->cfg;
1457         int ret = 0;
1458
1459         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1460
1461         /* Supported only for USB3 PHY */
1462         if (cfg->type != PHY_TYPE_USB3)
1463                 return 0;
1464
1465         if (!qmp->phy_initialized) {
1466                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1467                 return 0;
1468         }
1469
1470         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1471         if (ret) {
1472                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
1473                 return ret;
1474         }
1475
1476         ret = clk_prepare_enable(qphy->pipe_clk);
1477         if (ret) {
1478                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1479                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1480                 return ret;
1481         }
1482
1483         qcom_qmp_phy_disable_autonomous_mode(qphy);
1484
1485         return 0;
1486 }
1487
1488 static int qcom_qmp_phy_vreg_init(struct device *dev)
1489 {
1490         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1491         int num = qmp->cfg->num_vregs;
1492         int i;
1493
1494         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1495         if (!qmp->vregs)
1496                 return -ENOMEM;
1497
1498         for (i = 0; i < num; i++)
1499                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
1500
1501         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1502 }
1503
1504 static int qcom_qmp_phy_reset_init(struct device *dev)
1505 {
1506         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1507         int i;
1508
1509         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
1510                                    sizeof(*qmp->resets), GFP_KERNEL);
1511         if (!qmp->resets)
1512                 return -ENOMEM;
1513
1514         for (i = 0; i < qmp->cfg->num_resets; i++) {
1515                 struct reset_control *rst;
1516                 const char *name = qmp->cfg->reset_list[i];
1517
1518                 rst = devm_reset_control_get(dev, name);
1519                 if (IS_ERR(rst)) {
1520                         dev_err(dev, "failed to get %s reset\n", name);
1521                         return PTR_ERR(rst);
1522                 }
1523                 qmp->resets[i] = rst;
1524         }
1525
1526         return 0;
1527 }
1528
1529 static int qcom_qmp_phy_clk_init(struct device *dev)
1530 {
1531         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1532         int num = qmp->cfg->num_clks;
1533         int i;
1534
1535         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1536         if (!qmp->clks)
1537                 return -ENOMEM;
1538
1539         for (i = 0; i < num; i++)
1540                 qmp->clks[i].id = qmp->cfg->clk_list[i];
1541
1542         return devm_clk_bulk_get(dev, num, qmp->clks);
1543 }
1544
1545 /*
1546  * Register a fixed rate pipe clock.
1547  *
1548  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1549  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1550  * by the PHY driver for its operations.
1551  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1552  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1553  * Below picture shows this relationship.
1554  *
1555  *         +---------------+
1556  *         |   PHY block   |<<---------------------------------------+
1557  *         |               |                                         |
1558  *         |   +-------+   |                   +-----+               |
1559  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1560  *    clk  |   +-------+   |                   +-----+
1561  *         +---------------+
1562  */
1563 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
1564 {
1565         struct clk_fixed_rate *fixed;
1566         struct clk_init_data init = { };
1567         int ret;
1568
1569         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
1570             (qmp->cfg->type != PHY_TYPE_PCIE)) {
1571                 /* not all phys register pipe clocks, so return success */
1572                 return 0;
1573         }
1574
1575         ret = of_property_read_string(np, "clock-output-names", &init.name);
1576         if (ret) {
1577                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1578                 return ret;
1579         }
1580
1581         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
1582         if (!fixed)
1583                 return -ENOMEM;
1584
1585         init.ops = &clk_fixed_rate_ops;
1586
1587         /* controllers using QMP phys use 125MHz pipe clock interface */
1588         fixed->fixed_rate = 125000000;
1589         fixed->hw.init = &init;
1590
1591         return devm_clk_hw_register(qmp->dev, &fixed->hw);
1592 }
1593
1594 static const struct phy_ops qcom_qmp_phy_gen_ops = {
1595         .init           = qcom_qmp_phy_init,
1596         .exit           = qcom_qmp_phy_exit,
1597         .power_on       = qcom_qmp_phy_poweron,
1598         .set_mode       = qcom_qmp_phy_set_mode,
1599         .owner          = THIS_MODULE,
1600 };
1601
1602 static
1603 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
1604 {
1605         struct qcom_qmp *qmp = dev_get_drvdata(dev);
1606         struct phy *generic_phy;
1607         struct qmp_phy *qphy;
1608         char prop_name[MAX_PROP_NAME];
1609         int ret;
1610
1611         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
1612         if (!qphy)
1613                 return -ENOMEM;
1614
1615         /*
1616          * Get memory resources for each phy lane:
1617          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1618          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1619          * For single lane PHYs: pcs_misc (optional) -> 3.
1620          */
1621         qphy->tx = of_iomap(np, 0);
1622         if (!qphy->tx)
1623                 return -ENOMEM;
1624
1625         qphy->rx = of_iomap(np, 1);
1626         if (!qphy->rx)
1627                 return -ENOMEM;
1628
1629         qphy->pcs = of_iomap(np, 2);
1630         if (!qphy->pcs)
1631                 return -ENOMEM;
1632
1633         /*
1634          * If this is a dual-lane PHY, then there should be registers for the
1635          * second lane. Some old device trees did not specify this, so fall
1636          * back to old legacy behavior of assuming they can be reached at an
1637          * offset from the first lane.
1638          */
1639         if (qmp->cfg->is_dual_lane_phy) {
1640                 qphy->tx2 = of_iomap(np, 3);
1641                 qphy->rx2 = of_iomap(np, 4);
1642                 if (!qphy->tx2 || !qphy->rx2) {
1643                         dev_warn(dev,
1644                                  "Underspecified device tree, falling back to legacy register regions\n");
1645
1646                         /* In the old version, pcs_misc is at index 3. */
1647                         qphy->pcs_misc = qphy->tx2;
1648                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
1649                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
1650
1651                 } else {
1652                         qphy->pcs_misc = of_iomap(np, 5);
1653                 }
1654
1655         } else {
1656                 qphy->pcs_misc = of_iomap(np, 3);
1657         }
1658
1659         if (!qphy->pcs_misc)
1660                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1661
1662         /*
1663          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
1664          * based phys, so they essentially have pipe clock. So,
1665          * we return error in case phy is USB3 or PIPE type.
1666          * Otherwise, we initialize pipe clock to NULL for
1667          * all phys that don't need this.
1668          */
1669         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
1670         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
1671         if (IS_ERR(qphy->pipe_clk)) {
1672                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
1673                     qmp->cfg->type == PHY_TYPE_USB3) {
1674                         ret = PTR_ERR(qphy->pipe_clk);
1675                         if (ret != -EPROBE_DEFER)
1676                                 dev_err(dev,
1677                                         "failed to get lane%d pipe_clk, %d\n",
1678                                         id, ret);
1679                         return ret;
1680                 }
1681                 qphy->pipe_clk = NULL;
1682         }
1683
1684         /* Get lane reset, if any */
1685         if (qmp->cfg->has_lane_rst) {
1686                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
1687                 qphy->lane_rst = of_reset_control_get(np, prop_name);
1688                 if (IS_ERR(qphy->lane_rst)) {
1689                         dev_err(dev, "failed to get lane%d reset\n", id);
1690                         return PTR_ERR(qphy->lane_rst);
1691                 }
1692         }
1693
1694         generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
1695         if (IS_ERR(generic_phy)) {
1696                 ret = PTR_ERR(generic_phy);
1697                 dev_err(dev, "failed to create qphy %d\n", ret);
1698                 return ret;
1699         }
1700
1701         qphy->phy = generic_phy;
1702         qphy->index = id;
1703         qphy->qmp = qmp;
1704         qmp->phys[id] = qphy;
1705         phy_set_drvdata(generic_phy, qphy);
1706
1707         return 0;
1708 }
1709
1710 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
1711         {
1712                 .compatible = "qcom,msm8996-qmp-pcie-phy",
1713                 .data = &msm8996_pciephy_cfg,
1714         }, {
1715                 .compatible = "qcom,msm8996-qmp-usb3-phy",
1716                 .data = &msm8996_usb3phy_cfg,
1717         }, {
1718                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
1719                 .data = &ipq8074_pciephy_cfg,
1720         }, {
1721                 .compatible = "qcom,sdm845-qmp-usb3-phy",
1722                 .data = &qmp_v3_usb3phy_cfg,
1723         }, {
1724                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
1725                 .data = &qmp_v3_usb3_uniphy_cfg,
1726         }, {
1727                 .compatible = "qcom,sdm845-qmp-ufs-phy",
1728                 .data = &sdm845_ufsphy_cfg,
1729         },
1730         { },
1731 };
1732 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
1733
1734 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
1735         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
1736                            qcom_qmp_phy_runtime_resume, NULL)
1737 };
1738
1739 static int qcom_qmp_phy_probe(struct platform_device *pdev)
1740 {
1741         struct qcom_qmp *qmp;
1742         struct device *dev = &pdev->dev;
1743         struct resource *res;
1744         struct device_node *child;
1745         struct phy_provider *phy_provider;
1746         void __iomem *base;
1747         int num, id;
1748         int ret;
1749
1750         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1751         if (!qmp)
1752                 return -ENOMEM;
1753
1754         qmp->dev = dev;
1755         dev_set_drvdata(dev, qmp);
1756
1757         /* Get the specific init parameters of QMP phy */
1758         qmp->cfg = of_device_get_match_data(dev);
1759         if (!qmp->cfg)
1760                 return -EINVAL;
1761
1762         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1763         base = devm_ioremap_resource(dev, res);
1764         if (IS_ERR(base))
1765                 return PTR_ERR(base);
1766
1767         /* per PHY serdes; usually located at base address */
1768         qmp->serdes = base;
1769
1770         /* per PHY dp_com; if PHY has dp_com control block */
1771         if (qmp->cfg->has_phy_dp_com_ctrl) {
1772                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1773                                                    "dp_com");
1774                 base = devm_ioremap_resource(dev, res);
1775                 if (IS_ERR(base))
1776                         return PTR_ERR(base);
1777
1778                 qmp->dp_com = base;
1779         }
1780
1781         mutex_init(&qmp->phy_mutex);
1782
1783         ret = qcom_qmp_phy_clk_init(dev);
1784         if (ret)
1785                 return ret;
1786
1787         ret = qcom_qmp_phy_reset_init(dev);
1788         if (ret)
1789                 return ret;
1790
1791         ret = qcom_qmp_phy_vreg_init(dev);
1792         if (ret) {
1793                 if (ret != -EPROBE_DEFER)
1794                         dev_err(dev, "failed to get regulator supplies: %d\n",
1795                                 ret);
1796                 return ret;
1797         }
1798
1799         num = of_get_available_child_count(dev->of_node);
1800         /* do we have a rogue child node ? */
1801         if (num > qmp->cfg->nlanes)
1802                 return -EINVAL;
1803
1804         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
1805         if (!qmp->phys)
1806                 return -ENOMEM;
1807
1808         id = 0;
1809         pm_runtime_set_active(dev);
1810         pm_runtime_enable(dev);
1811         /*
1812          * Prevent runtime pm from being ON by default. Users can enable
1813          * it using power/control in sysfs.
1814          */
1815         pm_runtime_forbid(dev);
1816
1817         for_each_available_child_of_node(dev->of_node, child) {
1818                 /* Create per-lane phy */
1819                 ret = qcom_qmp_phy_create(dev, child, id);
1820                 if (ret) {
1821                         dev_err(dev, "failed to create lane%d phy, %d\n",
1822                                 id, ret);
1823                         pm_runtime_disable(dev);
1824                         return ret;
1825                 }
1826
1827                 /*
1828                  * Register the pipe clock provided by phy.
1829                  * See function description to see details of this pipe clock.
1830                  */
1831                 ret = phy_pipe_clk_register(qmp, child);
1832                 if (ret) {
1833                         dev_err(qmp->dev,
1834                                 "failed to register pipe clock source\n");
1835                         pm_runtime_disable(dev);
1836                         return ret;
1837                 }
1838                 id++;
1839         }
1840
1841         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1842         if (!IS_ERR(phy_provider))
1843                 dev_info(dev, "Registered Qcom-QMP phy\n");
1844         else
1845                 pm_runtime_disable(dev);
1846
1847         return PTR_ERR_OR_ZERO(phy_provider);
1848 }
1849
1850 static struct platform_driver qcom_qmp_phy_driver = {
1851         .probe          = qcom_qmp_phy_probe,
1852         .driver = {
1853                 .name   = "qcom-qmp-phy",
1854                 .pm     = &qcom_qmp_phy_pm_ops,
1855                 .of_match_table = qcom_qmp_phy_of_match_table,
1856         },
1857 };
1858
1859 module_platform_driver(qcom_qmp_phy_driver);
1860
1861 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1862 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
1863 MODULE_LICENSE("GPL v2");