2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21 #include <linux/log2.h>
22 #include <linux/pci-aspm.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pci_hotplug.h>
28 #include <asm-generic/pci-bridge.h>
29 #include <asm/setup.h>
32 const char *pci_power_names[] = {
33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
35 EXPORT_SYMBOL_GPL(pci_power_names);
37 int isa_dma_bridge_buggy;
38 EXPORT_SYMBOL(isa_dma_bridge_buggy);
41 EXPORT_SYMBOL(pci_pci_problems);
43 unsigned int pci_pm_d3_delay;
45 static void pci_pme_list_scan(struct work_struct *work);
47 static LIST_HEAD(pci_pme_list);
48 static DEFINE_MUTEX(pci_pme_list_mutex);
49 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
51 struct pci_pme_device {
52 struct list_head list;
56 #define PME_TIMEOUT 1000 /* How long between PME checks */
58 static void pci_dev_d3_sleep(struct pci_dev *dev)
60 unsigned int delay = dev->d3_delay;
62 if (delay < pci_pm_d3_delay)
63 delay = pci_pm_d3_delay;
68 #ifdef CONFIG_PCI_DOMAINS
69 int pci_domains_supported = 1;
72 #define DEFAULT_CARDBUS_IO_SIZE (256)
73 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
74 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
75 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
76 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
78 #define DEFAULT_HOTPLUG_IO_SIZE (256)
79 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
80 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
81 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
82 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
84 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
87 * The default CLS is used if arch didn't set CLS explicitly and not
88 * all pci devices agree on the same value. Arch can override either
89 * the dfl or actual value as it sees fit. Don't forget this is
90 * measured in 32-bit words, not bytes.
92 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
93 u8 pci_cache_line_size;
96 * If we set up a device for bus mastering, we need to check the latency
97 * timer as certain BIOSes forget to set it properly.
99 unsigned int pcibios_max_latency = 255;
101 /* If set, the PCIe ARI capability will not be used. */
102 static bool pcie_ari_disabled;
105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
106 * @bus: pointer to PCI bus structure to search
108 * Given a PCI bus, returns the highest PCI bus number present in the set
109 * including the given PCI bus and its list of child PCI buses.
111 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
114 unsigned char max, n;
116 max = bus->busn_res.end;
117 list_for_each_entry(tmp, &bus->children, node) {
118 n = pci_bus_max_busnr(tmp);
124 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
126 #ifdef CONFIG_HAS_IOMEM
127 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
129 struct resource *res = &pdev->resource[bar];
132 * Make sure the BAR is actually a memory resource, not an IO resource
134 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
135 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
138 return ioremap_nocache(res->start, resource_size(res));
140 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
142 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
145 * Make sure the BAR is actually a memory resource, not an IO resource
147 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
151 return ioremap_wc(pci_resource_start(pdev, bar),
152 pci_resource_len(pdev, bar));
154 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
158 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
159 u8 pos, int cap, int *ttl)
164 pci_bus_read_config_byte(bus, devfn, pos, &pos);
170 pci_bus_read_config_word(bus, devfn, pos, &ent);
182 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
185 int ttl = PCI_FIND_CAP_TTL;
187 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
190 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
192 return __pci_find_next_cap(dev->bus, dev->devfn,
193 pos + PCI_CAP_LIST_NEXT, cap);
195 EXPORT_SYMBOL_GPL(pci_find_next_capability);
197 static int __pci_bus_find_cap_start(struct pci_bus *bus,
198 unsigned int devfn, u8 hdr_type)
202 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
203 if (!(status & PCI_STATUS_CAP_LIST))
207 case PCI_HEADER_TYPE_NORMAL:
208 case PCI_HEADER_TYPE_BRIDGE:
209 return PCI_CAPABILITY_LIST;
210 case PCI_HEADER_TYPE_CARDBUS:
211 return PCI_CB_CAPABILITY_LIST;
218 * pci_find_capability - query for devices' capabilities
219 * @dev: PCI device to query
220 * @cap: capability code
222 * Tell if a device supports a given PCI capability.
223 * Returns the address of the requested capability structure within the
224 * device's PCI configuration space or 0 in case the device does not
225 * support it. Possible values for @cap:
227 * %PCI_CAP_ID_PM Power Management
228 * %PCI_CAP_ID_AGP Accelerated Graphics Port
229 * %PCI_CAP_ID_VPD Vital Product Data
230 * %PCI_CAP_ID_SLOTID Slot Identification
231 * %PCI_CAP_ID_MSI Message Signalled Interrupts
232 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
233 * %PCI_CAP_ID_PCIX PCI-X
234 * %PCI_CAP_ID_EXP PCI Express
236 int pci_find_capability(struct pci_dev *dev, int cap)
240 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
242 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
246 EXPORT_SYMBOL(pci_find_capability);
249 * pci_bus_find_capability - query for devices' capabilities
250 * @bus: the PCI bus to query
251 * @devfn: PCI device to query
252 * @cap: capability code
254 * Like pci_find_capability() but works for pci devices that do not have a
255 * pci_dev structure set up yet.
257 * Returns the address of the requested capability structure within the
258 * device's PCI configuration space or 0 in case the device does not
261 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
266 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
268 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
270 pos = __pci_find_next_cap(bus, devfn, pos, cap);
274 EXPORT_SYMBOL(pci_bus_find_capability);
277 * pci_find_next_ext_capability - Find an extended capability
278 * @dev: PCI device to query
279 * @start: address at which to start looking (0 to start at beginning of list)
280 * @cap: capability code
282 * Returns the address of the next matching extended capability structure
283 * within the device's PCI configuration space or 0 if the device does
284 * not support it. Some capabilities can occur several times, e.g., the
285 * vendor-specific capability, and this provides a way to find them all.
287 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
291 int pos = PCI_CFG_SPACE_SIZE;
293 /* minimum 8 bytes per capability */
294 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
296 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
302 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
306 * If we have no capabilities, this is indicated by cap ID,
307 * cap version and next pointer all being 0.
313 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
316 pos = PCI_EXT_CAP_NEXT(header);
317 if (pos < PCI_CFG_SPACE_SIZE)
320 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
326 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
329 * pci_find_ext_capability - Find an extended capability
330 * @dev: PCI device to query
331 * @cap: capability code
333 * Returns the address of the requested extended capability structure
334 * within the device's PCI configuration space or 0 if the device does
335 * not support it. Possible values for @cap:
337 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
338 * %PCI_EXT_CAP_ID_VC Virtual Channel
339 * %PCI_EXT_CAP_ID_DSN Device Serial Number
340 * %PCI_EXT_CAP_ID_PWR Power Budgeting
342 int pci_find_ext_capability(struct pci_dev *dev, int cap)
344 return pci_find_next_ext_capability(dev, 0, cap);
346 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
348 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
350 int rc, ttl = PCI_FIND_CAP_TTL;
353 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
354 mask = HT_3BIT_CAP_MASK;
356 mask = HT_5BIT_CAP_MASK;
358 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
359 PCI_CAP_ID_HT, &ttl);
361 rc = pci_read_config_byte(dev, pos + 3, &cap);
362 if (rc != PCIBIOS_SUCCESSFUL)
365 if ((cap & mask) == ht_cap)
368 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
369 pos + PCI_CAP_LIST_NEXT,
370 PCI_CAP_ID_HT, &ttl);
376 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @pos: Position from which to continue searching
379 * @ht_cap: Hypertransport capability code
381 * To be used in conjunction with pci_find_ht_capability() to search for
382 * all capabilities matching @ht_cap. @pos should always be a value returned
383 * from pci_find_ht_capability().
385 * NB. To be 100% safe against broken PCI devices, the caller should take
386 * steps to avoid an infinite loop.
388 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
390 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
392 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
395 * pci_find_ht_capability - query a device's Hypertransport capabilities
396 * @dev: PCI device to query
397 * @ht_cap: Hypertransport capability code
399 * Tell if a device supports a given Hypertransport capability.
400 * Returns an address within the device's PCI configuration space
401 * or 0 in case the device does not support the request capability.
402 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
403 * which has a Hypertransport capability matching @ht_cap.
405 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
409 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
411 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
415 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
418 * pci_find_parent_resource - return resource region of parent bus of given region
419 * @dev: PCI device structure contains resources to be searched
420 * @res: child resource record for which parent is sought
422 * For given resource region of given device, return the resource
423 * region of parent bus the given region is contained in.
425 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
426 struct resource *res)
428 const struct pci_bus *bus = dev->bus;
432 pci_bus_for_each_resource(bus, r, i) {
435 if (res->start && resource_contains(r, res)) {
438 * If the window is prefetchable but the BAR is
439 * not, the allocator made a mistake.
441 if (r->flags & IORESOURCE_PREFETCH &&
442 !(res->flags & IORESOURCE_PREFETCH))
446 * If we're below a transparent bridge, there may
447 * be both a positively-decoded aperture and a
448 * subtractively-decoded region that contain the BAR.
449 * We want the positively-decoded one, so this depends
450 * on pci_bus_for_each_resource() giving us those
458 EXPORT_SYMBOL(pci_find_parent_resource);
461 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
462 * @dev: the PCI device to operate on
463 * @pos: config space offset of status word
464 * @mask: mask of bit(s) to care about in status word
466 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
468 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
472 /* Wait for Transaction Pending bit clean */
473 for (i = 0; i < 4; i++) {
476 msleep((1 << (i - 1)) * 100);
478 pci_read_config_word(dev, pos, &status);
479 if (!(status & mask))
487 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
488 * @dev: PCI device to have its BARs restored
490 * Restore the BAR values for a given device, so as to make it
491 * accessible by its driver.
493 static void pci_restore_bars(struct pci_dev *dev)
497 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
501 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
502 pci_update_resource(dev, i);
505 static struct pci_platform_pm_ops *pci_platform_pm;
507 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
509 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
512 pci_platform_pm = ops;
516 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
518 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
521 static inline int platform_pci_set_power_state(struct pci_dev *dev,
524 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
527 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
529 return pci_platform_pm ?
530 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
533 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
535 return pci_platform_pm ?
536 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
539 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
541 return pci_platform_pm ?
542 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
545 static inline bool platform_pci_need_resume(struct pci_dev *dev)
547 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
551 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
553 * @dev: PCI device to handle.
554 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
557 * -EINVAL if the requested state is invalid.
558 * -EIO if device does not support PCI PM or its PM capabilities register has a
559 * wrong version, or device doesn't support the requested state.
560 * 0 if device already is in the requested state.
561 * 0 if device's power state has been successfully changed.
563 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
566 bool need_restore = false;
568 /* Check if we're already there */
569 if (dev->current_state == state)
575 if (state < PCI_D0 || state > PCI_D3hot)
578 /* Validate current state:
579 * Can enter D0 from any state, but if we can only go deeper
580 * to sleep if we're already in a low power state
582 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
583 && dev->current_state > state) {
584 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
585 dev->current_state, state);
589 /* check if this device supports the desired state */
590 if ((state == PCI_D1 && !dev->d1_support)
591 || (state == PCI_D2 && !dev->d2_support))
594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
596 /* If we're (effectively) in D3, force entire word to 0.
597 * This doesn't affect PME_Status, disables PME_En, and
598 * sets PowerState to 0.
600 switch (dev->current_state) {
604 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
609 case PCI_UNKNOWN: /* Boot-up */
610 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
611 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
613 /* Fall-through: force to D0 */
619 /* enter specified state */
620 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
622 /* Mandatory power management transition delays */
623 /* see PCI PM 1.1 5.6.1 table 18 */
624 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
625 pci_dev_d3_sleep(dev);
626 else if (state == PCI_D2 || dev->current_state == PCI_D2)
627 udelay(PCI_PM_D2_DELAY);
629 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
630 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
631 if (dev->current_state != state && printk_ratelimit())
632 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
636 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
637 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
638 * from D3hot to D0 _may_ perform an internal reset, thereby
639 * going to "D0 Uninitialized" rather than "D0 Initialized".
640 * For example, at least some versions of the 3c905B and the
641 * 3c556B exhibit this behaviour.
643 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
644 * devices in a D3hot state at boot. Consequently, we need to
645 * restore at least the BARs so that the device will be
646 * accessible to its driver.
649 pci_restore_bars(dev);
652 pcie_aspm_pm_state_change(dev->bus->self);
658 * pci_update_current_state - Read PCI power state of given device from its
659 * PCI PM registers and cache it
660 * @dev: PCI device to handle.
661 * @state: State to cache in case the device doesn't have the PM capability
663 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
669 * Configuration space is not accessible for device in
670 * D3cold, so just keep or set D3cold for safety
672 if (dev->current_state == PCI_D3cold)
674 if (state == PCI_D3cold) {
675 dev->current_state = PCI_D3cold;
678 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
679 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
681 dev->current_state = state;
686 * pci_power_up - Put the given device into D0 forcibly
687 * @dev: PCI device to power up
689 void pci_power_up(struct pci_dev *dev)
691 if (platform_pci_power_manageable(dev))
692 platform_pci_set_power_state(dev, PCI_D0);
694 pci_raw_set_power_state(dev, PCI_D0);
695 pci_update_current_state(dev, PCI_D0);
699 * pci_platform_power_transition - Use platform to change device power state
700 * @dev: PCI device to handle.
701 * @state: State to put the device into.
703 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
707 if (platform_pci_power_manageable(dev)) {
708 error = platform_pci_set_power_state(dev, state);
710 pci_update_current_state(dev, state);
714 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
715 dev->current_state = PCI_D0;
721 * pci_wakeup - Wake up a PCI device
722 * @pci_dev: Device to handle.
723 * @ign: ignored parameter
725 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
727 pci_wakeup_event(pci_dev);
728 pm_request_resume(&pci_dev->dev);
733 * pci_wakeup_bus - Walk given bus and wake up devices on it
734 * @bus: Top bus of the subtree to walk.
736 static void pci_wakeup_bus(struct pci_bus *bus)
739 pci_walk_bus(bus, pci_wakeup, NULL);
743 * __pci_start_power_transition - Start power transition of a PCI device
744 * @dev: PCI device to handle.
745 * @state: State to put the device into.
747 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
749 if (state == PCI_D0) {
750 pci_platform_power_transition(dev, PCI_D0);
752 * Mandatory power management transition delays, see
753 * PCI Express Base Specification Revision 2.0 Section
754 * 6.6.1: Conventional Reset. Do not delay for
755 * devices powered on/off by corresponding bridge,
756 * because have already delayed for the bridge.
758 if (dev->runtime_d3cold) {
759 msleep(dev->d3cold_delay);
761 * When powering on a bridge from D3cold, the
762 * whole hierarchy may be powered on into
763 * D0uninitialized state, resume them to give
764 * them a chance to suspend again
766 pci_wakeup_bus(dev->subordinate);
772 * __pci_dev_set_current_state - Set current state of a PCI device
773 * @dev: Device to handle
774 * @data: pointer to state to be set
776 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
778 pci_power_t state = *(pci_power_t *)data;
780 dev->current_state = state;
785 * __pci_bus_set_current_state - Walk given bus and set current state of devices
786 * @bus: Top bus of the subtree to walk.
787 * @state: state to be set
789 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
792 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
796 * __pci_complete_power_transition - Complete power transition of a PCI device
797 * @dev: PCI device to handle.
798 * @state: State to put the device into.
800 * This function should not be called directly by device drivers.
802 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
808 ret = pci_platform_power_transition(dev, state);
809 /* Power off the bridge may power off the whole hierarchy */
810 if (!ret && state == PCI_D3cold)
811 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
814 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
817 * pci_set_power_state - Set the power state of a PCI device
818 * @dev: PCI device to handle.
819 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
821 * Transition a device to a new power state, using the platform firmware and/or
822 * the device's PCI PM registers.
825 * -EINVAL if the requested state is invalid.
826 * -EIO if device does not support PCI PM or its PM capabilities register has a
827 * wrong version, or device doesn't support the requested state.
828 * 0 if device already is in the requested state.
829 * 0 if device's power state has been successfully changed.
831 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
835 /* bound the state we're entering */
836 if (state > PCI_D3cold)
838 else if (state < PCI_D0)
840 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
842 * If the device or the parent bridge do not support PCI PM,
843 * ignore the request if we're doing anything other than putting
844 * it into D0 (which would only happen on boot).
848 /* Check if we're already there */
849 if (dev->current_state == state)
852 __pci_start_power_transition(dev, state);
854 /* This device is quirked not to be put into D3, so
855 don't put it in D3 */
856 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
860 * To put device in D3cold, we put device into D3hot in native
861 * way, then put device into D3cold with platform ops
863 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
866 if (!__pci_complete_power_transition(dev, state))
871 EXPORT_SYMBOL(pci_set_power_state);
874 * pci_choose_state - Choose the power state of a PCI device
875 * @dev: PCI device to be suspended
876 * @state: target sleep state for the whole system. This is the value
877 * that is passed to suspend() function.
879 * Returns PCI power state suitable for given device and given system
883 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
890 ret = platform_pci_choose_state(dev);
891 if (ret != PCI_POWER_ERROR)
894 switch (state.event) {
897 case PM_EVENT_FREEZE:
898 case PM_EVENT_PRETHAW:
899 /* REVISIT both freeze and pre-thaw "should" use D0 */
900 case PM_EVENT_SUSPEND:
901 case PM_EVENT_HIBERNATE:
904 dev_info(&dev->dev, "unrecognized suspend event %d\n",
910 EXPORT_SYMBOL(pci_choose_state);
912 #define PCI_EXP_SAVE_REGS 7
914 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
915 u16 cap, bool extended)
917 struct pci_cap_saved_state *tmp;
919 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
920 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
926 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
928 return _pci_find_saved_cap(dev, cap, false);
931 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
933 return _pci_find_saved_cap(dev, cap, true);
936 static int pci_save_pcie_state(struct pci_dev *dev)
939 struct pci_cap_saved_state *save_state;
942 if (!pci_is_pcie(dev))
945 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
947 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
951 cap = (u16 *)&save_state->cap.data[0];
952 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
953 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
954 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
955 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
956 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
957 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
958 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
963 static void pci_restore_pcie_state(struct pci_dev *dev)
966 struct pci_cap_saved_state *save_state;
969 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
973 cap = (u16 *)&save_state->cap.data[0];
974 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
975 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
976 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
977 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
978 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
979 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
980 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
984 static int pci_save_pcix_state(struct pci_dev *dev)
987 struct pci_cap_saved_state *save_state;
989 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
993 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
995 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
999 pci_read_config_word(dev, pos + PCI_X_CMD,
1000 (u16 *)save_state->cap.data);
1005 static void pci_restore_pcix_state(struct pci_dev *dev)
1008 struct pci_cap_saved_state *save_state;
1011 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1012 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1013 if (!save_state || !pos)
1015 cap = (u16 *)&save_state->cap.data[0];
1017 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1022 * pci_save_state - save the PCI configuration space of a device before suspending
1023 * @dev: - PCI device that we're dealing with
1025 int pci_save_state(struct pci_dev *dev)
1028 /* XXX: 100% dword access ok here? */
1029 for (i = 0; i < 16; i++)
1030 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1031 dev->state_saved = true;
1033 i = pci_save_pcie_state(dev);
1037 i = pci_save_pcix_state(dev);
1041 return pci_save_vc_state(dev);
1043 EXPORT_SYMBOL(pci_save_state);
1045 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1046 u32 saved_val, int retry)
1050 pci_read_config_dword(pdev, offset, &val);
1051 if (val == saved_val)
1055 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1056 offset, val, saved_val);
1057 pci_write_config_dword(pdev, offset, saved_val);
1061 pci_read_config_dword(pdev, offset, &val);
1062 if (val == saved_val)
1069 static void pci_restore_config_space_range(struct pci_dev *pdev,
1070 int start, int end, int retry)
1074 for (index = end; index >= start; index--)
1075 pci_restore_config_dword(pdev, 4 * index,
1076 pdev->saved_config_space[index],
1080 static void pci_restore_config_space(struct pci_dev *pdev)
1082 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1083 pci_restore_config_space_range(pdev, 10, 15, 0);
1084 /* Restore BARs before the command register. */
1085 pci_restore_config_space_range(pdev, 4, 9, 10);
1086 pci_restore_config_space_range(pdev, 0, 3, 0);
1088 pci_restore_config_space_range(pdev, 0, 15, 0);
1093 * pci_restore_state - Restore the saved state of a PCI device
1094 * @dev: - PCI device that we're dealing with
1096 void pci_restore_state(struct pci_dev *dev)
1098 if (!dev->state_saved)
1101 /* PCI Express register must be restored first */
1102 pci_restore_pcie_state(dev);
1103 pci_restore_ats_state(dev);
1104 pci_restore_vc_state(dev);
1106 pci_restore_config_space(dev);
1108 pci_restore_pcix_state(dev);
1109 pci_restore_msi_state(dev);
1111 /* Restore ACS and IOV configuration state */
1112 pci_enable_acs(dev);
1113 pci_restore_iov_state(dev);
1115 dev->state_saved = false;
1117 EXPORT_SYMBOL(pci_restore_state);
1119 struct pci_saved_state {
1120 u32 config_space[16];
1121 struct pci_cap_saved_data cap[0];
1125 * pci_store_saved_state - Allocate and return an opaque struct containing
1126 * the device saved state.
1127 * @dev: PCI device that we're dealing with
1129 * Return NULL if no state or error.
1131 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1133 struct pci_saved_state *state;
1134 struct pci_cap_saved_state *tmp;
1135 struct pci_cap_saved_data *cap;
1138 if (!dev->state_saved)
1141 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1143 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1144 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1146 state = kzalloc(size, GFP_KERNEL);
1150 memcpy(state->config_space, dev->saved_config_space,
1151 sizeof(state->config_space));
1154 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1155 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1156 memcpy(cap, &tmp->cap, len);
1157 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1159 /* Empty cap_save terminates list */
1163 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1166 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1167 * @dev: PCI device that we're dealing with
1168 * @state: Saved state returned from pci_store_saved_state()
1170 int pci_load_saved_state(struct pci_dev *dev,
1171 struct pci_saved_state *state)
1173 struct pci_cap_saved_data *cap;
1175 dev->state_saved = false;
1180 memcpy(dev->saved_config_space, state->config_space,
1181 sizeof(state->config_space));
1185 struct pci_cap_saved_state *tmp;
1187 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1188 if (!tmp || tmp->cap.size != cap->size)
1191 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1192 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1193 sizeof(struct pci_cap_saved_data) + cap->size);
1196 dev->state_saved = true;
1199 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1202 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1203 * and free the memory allocated for it.
1204 * @dev: PCI device that we're dealing with
1205 * @state: Pointer to saved state returned from pci_store_saved_state()
1207 int pci_load_and_free_saved_state(struct pci_dev *dev,
1208 struct pci_saved_state **state)
1210 int ret = pci_load_saved_state(dev, *state);
1215 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1217 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1219 return pci_enable_resources(dev, bars);
1222 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1225 struct pci_dev *bridge;
1229 err = pci_set_power_state(dev, PCI_D0);
1230 if (err < 0 && err != -EIO)
1233 bridge = pci_upstream_bridge(dev);
1235 pcie_aspm_powersave_config_link(bridge);
1237 err = pcibios_enable_device(dev, bars);
1240 pci_fixup_device(pci_fixup_enable, dev);
1242 if (dev->msi_enabled || dev->msix_enabled)
1245 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1247 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1248 if (cmd & PCI_COMMAND_INTX_DISABLE)
1249 pci_write_config_word(dev, PCI_COMMAND,
1250 cmd & ~PCI_COMMAND_INTX_DISABLE);
1257 * pci_reenable_device - Resume abandoned device
1258 * @dev: PCI device to be resumed
1260 * Note this function is a backend of pci_default_resume and is not supposed
1261 * to be called by normal code, write proper resume handler and use it instead.
1263 int pci_reenable_device(struct pci_dev *dev)
1265 if (pci_is_enabled(dev))
1266 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1269 EXPORT_SYMBOL(pci_reenable_device);
1271 static void pci_enable_bridge(struct pci_dev *dev)
1273 struct pci_dev *bridge;
1276 bridge = pci_upstream_bridge(dev);
1278 pci_enable_bridge(bridge);
1280 if (pci_is_enabled(dev)) {
1281 if (!dev->is_busmaster)
1282 pci_set_master(dev);
1286 retval = pci_enable_device(dev);
1288 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1290 pci_set_master(dev);
1293 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1295 struct pci_dev *bridge;
1300 * Power state could be unknown at this point, either due to a fresh
1301 * boot or a device removal call. So get the current power state
1302 * so that things like MSI message writing will behave as expected
1303 * (e.g. if the device really is in D0 at enable time).
1307 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1308 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1311 if (atomic_inc_return(&dev->enable_cnt) > 1)
1312 return 0; /* already enabled */
1314 bridge = pci_upstream_bridge(dev);
1316 pci_enable_bridge(bridge);
1318 /* only skip sriov related */
1319 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1320 if (dev->resource[i].flags & flags)
1322 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1323 if (dev->resource[i].flags & flags)
1326 err = do_pci_enable_device(dev, bars);
1328 atomic_dec(&dev->enable_cnt);
1333 * pci_enable_device_io - Initialize a device for use with IO space
1334 * @dev: PCI device to be initialized
1336 * Initialize device before it's used by a driver. Ask low-level code
1337 * to enable I/O resources. Wake up the device if it was suspended.
1338 * Beware, this function can fail.
1340 int pci_enable_device_io(struct pci_dev *dev)
1342 return pci_enable_device_flags(dev, IORESOURCE_IO);
1344 EXPORT_SYMBOL(pci_enable_device_io);
1347 * pci_enable_device_mem - Initialize a device for use with Memory space
1348 * @dev: PCI device to be initialized
1350 * Initialize device before it's used by a driver. Ask low-level code
1351 * to enable Memory resources. Wake up the device if it was suspended.
1352 * Beware, this function can fail.
1354 int pci_enable_device_mem(struct pci_dev *dev)
1356 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1358 EXPORT_SYMBOL(pci_enable_device_mem);
1361 * pci_enable_device - Initialize device before it's used by a driver.
1362 * @dev: PCI device to be initialized
1364 * Initialize device before it's used by a driver. Ask low-level code
1365 * to enable I/O and memory. Wake up the device if it was suspended.
1366 * Beware, this function can fail.
1368 * Note we don't actually enable the device many times if we call
1369 * this function repeatedly (we just increment the count).
1371 int pci_enable_device(struct pci_dev *dev)
1373 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1375 EXPORT_SYMBOL(pci_enable_device);
1378 * Managed PCI resources. This manages device on/off, intx/msi/msix
1379 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1380 * there's no need to track it separately. pci_devres is initialized
1381 * when a device is enabled using managed PCI device enable interface.
1384 unsigned int enabled:1;
1385 unsigned int pinned:1;
1386 unsigned int orig_intx:1;
1387 unsigned int restore_intx:1;
1391 static void pcim_release(struct device *gendev, void *res)
1393 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1394 struct pci_devres *this = res;
1397 if (dev->msi_enabled)
1398 pci_disable_msi(dev);
1399 if (dev->msix_enabled)
1400 pci_disable_msix(dev);
1402 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1403 if (this->region_mask & (1 << i))
1404 pci_release_region(dev, i);
1406 if (this->restore_intx)
1407 pci_intx(dev, this->orig_intx);
1409 if (this->enabled && !this->pinned)
1410 pci_disable_device(dev);
1413 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1415 struct pci_devres *dr, *new_dr;
1417 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1421 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1424 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1427 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1429 if (pci_is_managed(pdev))
1430 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1435 * pcim_enable_device - Managed pci_enable_device()
1436 * @pdev: PCI device to be initialized
1438 * Managed pci_enable_device().
1440 int pcim_enable_device(struct pci_dev *pdev)
1442 struct pci_devres *dr;
1445 dr = get_pci_dr(pdev);
1451 rc = pci_enable_device(pdev);
1453 pdev->is_managed = 1;
1458 EXPORT_SYMBOL(pcim_enable_device);
1461 * pcim_pin_device - Pin managed PCI device
1462 * @pdev: PCI device to pin
1464 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1465 * driver detach. @pdev must have been enabled with
1466 * pcim_enable_device().
1468 void pcim_pin_device(struct pci_dev *pdev)
1470 struct pci_devres *dr;
1472 dr = find_pci_dr(pdev);
1473 WARN_ON(!dr || !dr->enabled);
1477 EXPORT_SYMBOL(pcim_pin_device);
1480 * pcibios_add_device - provide arch specific hooks when adding device dev
1481 * @dev: the PCI device being added
1483 * Permits the platform to provide architecture specific functionality when
1484 * devices are added. This is the default implementation. Architecture
1485 * implementations can override this.
1487 int __weak pcibios_add_device(struct pci_dev *dev)
1493 * pcibios_release_device - provide arch specific hooks when releasing device dev
1494 * @dev: the PCI device being released
1496 * Permits the platform to provide architecture specific functionality when
1497 * devices are released. This is the default implementation. Architecture
1498 * implementations can override this.
1500 void __weak pcibios_release_device(struct pci_dev *dev) {}
1503 * pcibios_disable_device - disable arch specific PCI resources for device dev
1504 * @dev: the PCI device to disable
1506 * Disables architecture specific PCI resources for the device. This
1507 * is the default implementation. Architecture implementations can
1510 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1513 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1514 * @irq: ISA IRQ to penalize
1515 * @active: IRQ active or not
1517 * Permits the platform to provide architecture-specific functionality when
1518 * penalizing ISA IRQs. This is the default implementation. Architecture
1519 * implementations can override this.
1521 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1523 static void do_pci_disable_device(struct pci_dev *dev)
1527 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1528 if (pci_command & PCI_COMMAND_MASTER) {
1529 pci_command &= ~PCI_COMMAND_MASTER;
1530 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1533 pcibios_disable_device(dev);
1537 * pci_disable_enabled_device - Disable device without updating enable_cnt
1538 * @dev: PCI device to disable
1540 * NOTE: This function is a backend of PCI power management routines and is
1541 * not supposed to be called drivers.
1543 void pci_disable_enabled_device(struct pci_dev *dev)
1545 if (pci_is_enabled(dev))
1546 do_pci_disable_device(dev);
1550 * pci_disable_device - Disable PCI device after use
1551 * @dev: PCI device to be disabled
1553 * Signal to the system that the PCI device is not in use by the system
1554 * anymore. This only involves disabling PCI bus-mastering, if active.
1556 * Note we don't actually disable the device until all callers of
1557 * pci_enable_device() have called pci_disable_device().
1559 void pci_disable_device(struct pci_dev *dev)
1561 struct pci_devres *dr;
1563 dr = find_pci_dr(dev);
1567 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1568 "disabling already-disabled device");
1570 if (atomic_dec_return(&dev->enable_cnt) != 0)
1573 do_pci_disable_device(dev);
1575 dev->is_busmaster = 0;
1577 EXPORT_SYMBOL(pci_disable_device);
1580 * pcibios_set_pcie_reset_state - set reset state for device dev
1581 * @dev: the PCIe device reset
1582 * @state: Reset state to enter into
1585 * Sets the PCIe reset state for the device. This is the default
1586 * implementation. Architecture implementations can override this.
1588 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1589 enum pcie_reset_state state)
1595 * pci_set_pcie_reset_state - set reset state for device dev
1596 * @dev: the PCIe device reset
1597 * @state: Reset state to enter into
1600 * Sets the PCI reset state for the device.
1602 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1604 return pcibios_set_pcie_reset_state(dev, state);
1606 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1609 * pci_check_pme_status - Check if given device has generated PME.
1610 * @dev: Device to check.
1612 * Check the PME status of the device and if set, clear it and clear PME enable
1613 * (if set). Return 'true' if PME status and PME enable were both set or
1614 * 'false' otherwise.
1616 bool pci_check_pme_status(struct pci_dev *dev)
1625 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1626 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1627 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1630 /* Clear PME status. */
1631 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1632 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1633 /* Disable PME to avoid interrupt flood. */
1634 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1638 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1644 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1645 * @dev: Device to handle.
1646 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1648 * Check if @dev has generated PME and queue a resume request for it in that
1651 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1653 if (pme_poll_reset && dev->pme_poll)
1654 dev->pme_poll = false;
1656 if (pci_check_pme_status(dev)) {
1657 pci_wakeup_event(dev);
1658 pm_request_resume(&dev->dev);
1664 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1665 * @bus: Top bus of the subtree to walk.
1667 void pci_pme_wakeup_bus(struct pci_bus *bus)
1670 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1675 * pci_pme_capable - check the capability of PCI device to generate PME#
1676 * @dev: PCI device to handle.
1677 * @state: PCI state from which device will issue PME#.
1679 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1684 return !!(dev->pme_support & (1 << state));
1686 EXPORT_SYMBOL(pci_pme_capable);
1688 static void pci_pme_list_scan(struct work_struct *work)
1690 struct pci_pme_device *pme_dev, *n;
1692 mutex_lock(&pci_pme_list_mutex);
1693 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1694 if (pme_dev->dev->pme_poll) {
1695 struct pci_dev *bridge;
1697 bridge = pme_dev->dev->bus->self;
1699 * If bridge is in low power state, the
1700 * configuration space of subordinate devices
1701 * may be not accessible
1703 if (bridge && bridge->current_state != PCI_D0)
1705 pci_pme_wakeup(pme_dev->dev, NULL);
1707 list_del(&pme_dev->list);
1711 if (!list_empty(&pci_pme_list))
1712 schedule_delayed_work(&pci_pme_work,
1713 msecs_to_jiffies(PME_TIMEOUT));
1714 mutex_unlock(&pci_pme_list_mutex);
1718 * pci_pme_active - enable or disable PCI device's PME# function
1719 * @dev: PCI device to handle.
1720 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1722 * The caller must verify that the device is capable of generating PME# before
1723 * calling this function with @enable equal to 'true'.
1725 void pci_pme_active(struct pci_dev *dev, bool enable)
1729 if (!dev->pme_support)
1732 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1733 /* Clear PME_Status by writing 1 to it and enable PME# */
1734 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1736 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1738 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1741 * PCI (as opposed to PCIe) PME requires that the device have
1742 * its PME# line hooked up correctly. Not all hardware vendors
1743 * do this, so the PME never gets delivered and the device
1744 * remains asleep. The easiest way around this is to
1745 * periodically walk the list of suspended devices and check
1746 * whether any have their PME flag set. The assumption is that
1747 * we'll wake up often enough anyway that this won't be a huge
1748 * hit, and the power savings from the devices will still be a
1751 * Although PCIe uses in-band PME message instead of PME# line
1752 * to report PME, PME does not work for some PCIe devices in
1753 * reality. For example, there are devices that set their PME
1754 * status bits, but don't really bother to send a PME message;
1755 * there are PCI Express Root Ports that don't bother to
1756 * trigger interrupts when they receive PME messages from the
1757 * devices below. So PME poll is used for PCIe devices too.
1760 if (dev->pme_poll) {
1761 struct pci_pme_device *pme_dev;
1763 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1766 dev_warn(&dev->dev, "can't enable PME#\n");
1770 mutex_lock(&pci_pme_list_mutex);
1771 list_add(&pme_dev->list, &pci_pme_list);
1772 if (list_is_singular(&pci_pme_list))
1773 schedule_delayed_work(&pci_pme_work,
1774 msecs_to_jiffies(PME_TIMEOUT));
1775 mutex_unlock(&pci_pme_list_mutex);
1777 mutex_lock(&pci_pme_list_mutex);
1778 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1779 if (pme_dev->dev == dev) {
1780 list_del(&pme_dev->list);
1785 mutex_unlock(&pci_pme_list_mutex);
1789 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1791 EXPORT_SYMBOL(pci_pme_active);
1794 * __pci_enable_wake - enable PCI device as wakeup event source
1795 * @dev: PCI device affected
1796 * @state: PCI state from which device will issue wakeup events
1797 * @runtime: True if the events are to be generated at run time
1798 * @enable: True to enable event generation; false to disable
1800 * This enables the device as a wakeup event source, or disables it.
1801 * When such events involves platform-specific hooks, those hooks are
1802 * called automatically by this routine.
1804 * Devices with legacy power management (no standard PCI PM capabilities)
1805 * always require such platform hooks.
1808 * 0 is returned on success
1809 * -EINVAL is returned if device is not supposed to wake up the system
1810 * Error code depending on the platform is returned if both the platform and
1811 * the native mechanism fail to enable the generation of wake-up events
1813 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1814 bool runtime, bool enable)
1818 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1821 /* Don't do the same thing twice in a row for one device. */
1822 if (!!enable == !!dev->wakeup_prepared)
1826 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1827 * Anderson we should be doing PME# wake enable followed by ACPI wake
1828 * enable. To disable wake-up we call the platform first, for symmetry.
1834 if (pci_pme_capable(dev, state))
1835 pci_pme_active(dev, true);
1838 error = runtime ? platform_pci_run_wake(dev, true) :
1839 platform_pci_sleep_wake(dev, true);
1843 dev->wakeup_prepared = true;
1846 platform_pci_run_wake(dev, false);
1848 platform_pci_sleep_wake(dev, false);
1849 pci_pme_active(dev, false);
1850 dev->wakeup_prepared = false;
1855 EXPORT_SYMBOL(__pci_enable_wake);
1858 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1859 * @dev: PCI device to prepare
1860 * @enable: True to enable wake-up event generation; false to disable
1862 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1863 * and this function allows them to set that up cleanly - pci_enable_wake()
1864 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1865 * ordering constraints.
1867 * This function only returns error code if the device is not capable of
1868 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1869 * enable wake-up power for it.
1871 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1873 return pci_pme_capable(dev, PCI_D3cold) ?
1874 pci_enable_wake(dev, PCI_D3cold, enable) :
1875 pci_enable_wake(dev, PCI_D3hot, enable);
1877 EXPORT_SYMBOL(pci_wake_from_d3);
1880 * pci_target_state - find an appropriate low power state for a given PCI dev
1883 * Use underlying platform code to find a supported low power state for @dev.
1884 * If the platform can't manage @dev, return the deepest state from which it
1885 * can generate wake events, based on any available PME info.
1887 static pci_power_t pci_target_state(struct pci_dev *dev)
1889 pci_power_t target_state = PCI_D3hot;
1891 if (platform_pci_power_manageable(dev)) {
1893 * Call the platform to choose the target state of the device
1894 * and enable wake-up from this state if supported.
1896 pci_power_t state = platform_pci_choose_state(dev);
1899 case PCI_POWER_ERROR:
1904 if (pci_no_d1d2(dev))
1907 target_state = state;
1909 } else if (!dev->pm_cap) {
1910 target_state = PCI_D0;
1911 } else if (device_may_wakeup(&dev->dev)) {
1913 * Find the deepest state from which the device can generate
1914 * wake-up events, make it the target state and enable device
1917 if (dev->pme_support) {
1919 && !(dev->pme_support & (1 << target_state)))
1924 return target_state;
1928 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1929 * @dev: Device to handle.
1931 * Choose the power state appropriate for the device depending on whether
1932 * it can wake up the system and/or is power manageable by the platform
1933 * (PCI_D3hot is the default) and put the device into that state.
1935 int pci_prepare_to_sleep(struct pci_dev *dev)
1937 pci_power_t target_state = pci_target_state(dev);
1940 if (target_state == PCI_POWER_ERROR)
1943 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1945 error = pci_set_power_state(dev, target_state);
1948 pci_enable_wake(dev, target_state, false);
1952 EXPORT_SYMBOL(pci_prepare_to_sleep);
1955 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1956 * @dev: Device to handle.
1958 * Disable device's system wake-up capability and put it into D0.
1960 int pci_back_from_sleep(struct pci_dev *dev)
1962 pci_enable_wake(dev, PCI_D0, false);
1963 return pci_set_power_state(dev, PCI_D0);
1965 EXPORT_SYMBOL(pci_back_from_sleep);
1968 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1969 * @dev: PCI device being suspended.
1971 * Prepare @dev to generate wake-up events at run time and put it into a low
1974 int pci_finish_runtime_suspend(struct pci_dev *dev)
1976 pci_power_t target_state = pci_target_state(dev);
1979 if (target_state == PCI_POWER_ERROR)
1982 dev->runtime_d3cold = target_state == PCI_D3cold;
1984 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1986 error = pci_set_power_state(dev, target_state);
1989 __pci_enable_wake(dev, target_state, true, false);
1990 dev->runtime_d3cold = false;
1997 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1998 * @dev: Device to check.
2000 * Return true if the device itself is capable of generating wake-up events
2001 * (through the platform or using the native PCIe PME) or if the device supports
2002 * PME and one of its upstream bridges can generate wake-up events.
2004 bool pci_dev_run_wake(struct pci_dev *dev)
2006 struct pci_bus *bus = dev->bus;
2008 if (device_run_wake(&dev->dev))
2011 if (!dev->pme_support)
2014 while (bus->parent) {
2015 struct pci_dev *bridge = bus->self;
2017 if (device_run_wake(&bridge->dev))
2023 /* We have reached the root bus. */
2025 return device_run_wake(bus->bridge);
2029 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2032 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2033 * @pci_dev: Device to check.
2035 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2036 * reconfigured due to wakeup settings difference between system and runtime
2037 * suspend and the current power state of it is suitable for the upcoming
2038 * (system) transition.
2040 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2042 struct device *dev = &pci_dev->dev;
2044 if (!pm_runtime_suspended(dev)
2045 || (device_can_wakeup(dev) && !device_may_wakeup(dev))
2046 || platform_pci_need_resume(pci_dev))
2049 return pci_target_state(pci_dev) == pci_dev->current_state;
2052 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2054 struct device *dev = &pdev->dev;
2055 struct device *parent = dev->parent;
2058 pm_runtime_get_sync(parent);
2059 pm_runtime_get_noresume(dev);
2061 * pdev->current_state is set to PCI_D3cold during suspending,
2062 * so wait until suspending completes
2064 pm_runtime_barrier(dev);
2066 * Only need to resume devices in D3cold, because config
2067 * registers are still accessible for devices suspended but
2070 if (pdev->current_state == PCI_D3cold)
2071 pm_runtime_resume(dev);
2074 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2076 struct device *dev = &pdev->dev;
2077 struct device *parent = dev->parent;
2079 pm_runtime_put(dev);
2081 pm_runtime_put_sync(parent);
2085 * pci_pm_init - Initialize PM functions of given PCI device
2086 * @dev: PCI device to handle.
2088 void pci_pm_init(struct pci_dev *dev)
2093 pm_runtime_forbid(&dev->dev);
2094 pm_runtime_set_active(&dev->dev);
2095 pm_runtime_enable(&dev->dev);
2096 device_enable_async_suspend(&dev->dev);
2097 dev->wakeup_prepared = false;
2100 dev->pme_support = 0;
2102 /* find PCI PM capability in list */
2103 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2106 /* Check device's ability to generate PME# */
2107 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2109 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2110 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2111 pmc & PCI_PM_CAP_VER_MASK);
2116 dev->d3_delay = PCI_PM_D3_WAIT;
2117 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2118 dev->d3cold_allowed = true;
2120 dev->d1_support = false;
2121 dev->d2_support = false;
2122 if (!pci_no_d1d2(dev)) {
2123 if (pmc & PCI_PM_CAP_D1)
2124 dev->d1_support = true;
2125 if (pmc & PCI_PM_CAP_D2)
2126 dev->d2_support = true;
2128 if (dev->d1_support || dev->d2_support)
2129 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2130 dev->d1_support ? " D1" : "",
2131 dev->d2_support ? " D2" : "");
2134 pmc &= PCI_PM_CAP_PME_MASK;
2136 dev_printk(KERN_DEBUG, &dev->dev,
2137 "PME# supported from%s%s%s%s%s\n",
2138 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2139 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2140 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2141 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2142 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2143 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2144 dev->pme_poll = true;
2146 * Make device's PM flags reflect the wake-up capability, but
2147 * let the user space enable it to wake up the system as needed.
2149 device_set_wakeup_capable(&dev->dev, true);
2150 /* Disable the PME# generation functionality */
2151 pci_pme_active(dev, false);
2155 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2156 struct pci_cap_saved_state *new_cap)
2158 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2162 * _pci_add_cap_save_buffer - allocate buffer for saving given
2163 * capability registers
2164 * @dev: the PCI device
2165 * @cap: the capability to allocate the buffer for
2166 * @extended: Standard or Extended capability ID
2167 * @size: requested size of the buffer
2169 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2170 bool extended, unsigned int size)
2173 struct pci_cap_saved_state *save_state;
2176 pos = pci_find_ext_capability(dev, cap);
2178 pos = pci_find_capability(dev, cap);
2183 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2187 save_state->cap.cap_nr = cap;
2188 save_state->cap.cap_extended = extended;
2189 save_state->cap.size = size;
2190 pci_add_saved_cap(dev, save_state);
2195 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2197 return _pci_add_cap_save_buffer(dev, cap, false, size);
2200 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2202 return _pci_add_cap_save_buffer(dev, cap, true, size);
2206 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2207 * @dev: the PCI device
2209 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2213 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2214 PCI_EXP_SAVE_REGS * sizeof(u16));
2217 "unable to preallocate PCI Express save buffer\n");
2219 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2222 "unable to preallocate PCI-X save buffer\n");
2224 pci_allocate_vc_save_buffers(dev);
2227 void pci_free_cap_save_buffers(struct pci_dev *dev)
2229 struct pci_cap_saved_state *tmp;
2230 struct hlist_node *n;
2232 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2237 * pci_configure_ari - enable or disable ARI forwarding
2238 * @dev: the PCI device
2240 * If @dev and its upstream bridge both support ARI, enable ARI in the
2241 * bridge. Otherwise, disable ARI in the bridge.
2243 void pci_configure_ari(struct pci_dev *dev)
2246 struct pci_dev *bridge;
2248 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2251 bridge = dev->bus->self;
2255 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2256 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2259 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2260 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2261 PCI_EXP_DEVCTL2_ARI);
2262 bridge->ari_enabled = 1;
2264 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2265 PCI_EXP_DEVCTL2_ARI);
2266 bridge->ari_enabled = 0;
2270 static int pci_acs_enable;
2273 * pci_request_acs - ask for ACS to be enabled if supported
2275 void pci_request_acs(void)
2281 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2282 * @dev: the PCI device
2284 static int pci_std_enable_acs(struct pci_dev *dev)
2290 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2294 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2295 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2297 /* Source Validation */
2298 ctrl |= (cap & PCI_ACS_SV);
2300 /* P2P Request Redirect */
2301 ctrl |= (cap & PCI_ACS_RR);
2303 /* P2P Completion Redirect */
2304 ctrl |= (cap & PCI_ACS_CR);
2306 /* Upstream Forwarding */
2307 ctrl |= (cap & PCI_ACS_UF);
2309 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2315 * pci_enable_acs - enable ACS if hardware support it
2316 * @dev: the PCI device
2318 void pci_enable_acs(struct pci_dev *dev)
2320 if (!pci_acs_enable)
2323 if (!pci_std_enable_acs(dev))
2326 pci_dev_specific_enable_acs(dev);
2329 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2334 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2339 * Except for egress control, capabilities are either required
2340 * or only required if controllable. Features missing from the
2341 * capability field can therefore be assumed as hard-wired enabled.
2343 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2344 acs_flags &= (cap | PCI_ACS_EC);
2346 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2347 return (ctrl & acs_flags) == acs_flags;
2351 * pci_acs_enabled - test ACS against required flags for a given device
2352 * @pdev: device to test
2353 * @acs_flags: required PCI ACS flags
2355 * Return true if the device supports the provided flags. Automatically
2356 * filters out flags that are not implemented on multifunction devices.
2358 * Note that this interface checks the effective ACS capabilities of the
2359 * device rather than the actual capabilities. For instance, most single
2360 * function endpoints are not required to support ACS because they have no
2361 * opportunity for peer-to-peer access. We therefore return 'true'
2362 * regardless of whether the device exposes an ACS capability. This makes
2363 * it much easier for callers of this function to ignore the actual type
2364 * or topology of the device when testing ACS support.
2366 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2370 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2375 * Conventional PCI and PCI-X devices never support ACS, either
2376 * effectively or actually. The shared bus topology implies that
2377 * any device on the bus can receive or snoop DMA.
2379 if (!pci_is_pcie(pdev))
2382 switch (pci_pcie_type(pdev)) {
2384 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2385 * but since their primary interface is PCI/X, we conservatively
2386 * handle them as we would a non-PCIe device.
2388 case PCI_EXP_TYPE_PCIE_BRIDGE:
2390 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2391 * applicable... must never implement an ACS Extended Capability...".
2392 * This seems arbitrary, but we take a conservative interpretation
2393 * of this statement.
2395 case PCI_EXP_TYPE_PCI_BRIDGE:
2396 case PCI_EXP_TYPE_RC_EC:
2399 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2400 * implement ACS in order to indicate their peer-to-peer capabilities,
2401 * regardless of whether they are single- or multi-function devices.
2403 case PCI_EXP_TYPE_DOWNSTREAM:
2404 case PCI_EXP_TYPE_ROOT_PORT:
2405 return pci_acs_flags_enabled(pdev, acs_flags);
2407 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2408 * implemented by the remaining PCIe types to indicate peer-to-peer
2409 * capabilities, but only when they are part of a multifunction
2410 * device. The footnote for section 6.12 indicates the specific
2411 * PCIe types included here.
2413 case PCI_EXP_TYPE_ENDPOINT:
2414 case PCI_EXP_TYPE_UPSTREAM:
2415 case PCI_EXP_TYPE_LEG_END:
2416 case PCI_EXP_TYPE_RC_END:
2417 if (!pdev->multifunction)
2420 return pci_acs_flags_enabled(pdev, acs_flags);
2424 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2425 * to single function devices with the exception of downstream ports.
2431 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2432 * @start: starting downstream device
2433 * @end: ending upstream device or NULL to search to the root bus
2434 * @acs_flags: required flags
2436 * Walk up a device tree from start to end testing PCI ACS support. If
2437 * any step along the way does not support the required flags, return false.
2439 bool pci_acs_path_enabled(struct pci_dev *start,
2440 struct pci_dev *end, u16 acs_flags)
2442 struct pci_dev *pdev, *parent = start;
2447 if (!pci_acs_enabled(pdev, acs_flags))
2450 if (pci_is_root_bus(pdev->bus))
2451 return (end == NULL);
2453 parent = pdev->bus->self;
2454 } while (pdev != end);
2460 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2461 * @dev: the PCI device
2462 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2464 * Perform INTx swizzling for a device behind one level of bridge. This is
2465 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2466 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2467 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2468 * the PCI Express Base Specification, Revision 2.1)
2470 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2474 if (pci_ari_enabled(dev->bus))
2477 slot = PCI_SLOT(dev->devfn);
2479 return (((pin - 1) + slot) % 4) + 1;
2482 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2490 while (!pci_is_root_bus(dev->bus)) {
2491 pin = pci_swizzle_interrupt_pin(dev, pin);
2492 dev = dev->bus->self;
2499 * pci_common_swizzle - swizzle INTx all the way to root bridge
2500 * @dev: the PCI device
2501 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2503 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2504 * bridges all the way up to a PCI root bus.
2506 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2510 while (!pci_is_root_bus(dev->bus)) {
2511 pin = pci_swizzle_interrupt_pin(dev, pin);
2512 dev = dev->bus->self;
2515 return PCI_SLOT(dev->devfn);
2517 EXPORT_SYMBOL_GPL(pci_common_swizzle);
2520 * pci_release_region - Release a PCI bar
2521 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2522 * @bar: BAR to release
2524 * Releases the PCI I/O and memory resources previously reserved by a
2525 * successful call to pci_request_region. Call this function only
2526 * after all use of the PCI regions has ceased.
2528 void pci_release_region(struct pci_dev *pdev, int bar)
2530 struct pci_devres *dr;
2532 if (pci_resource_len(pdev, bar) == 0)
2534 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2535 release_region(pci_resource_start(pdev, bar),
2536 pci_resource_len(pdev, bar));
2537 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2538 release_mem_region(pci_resource_start(pdev, bar),
2539 pci_resource_len(pdev, bar));
2541 dr = find_pci_dr(pdev);
2543 dr->region_mask &= ~(1 << bar);
2545 EXPORT_SYMBOL(pci_release_region);
2548 * __pci_request_region - Reserved PCI I/O and memory resource
2549 * @pdev: PCI device whose resources are to be reserved
2550 * @bar: BAR to be reserved
2551 * @res_name: Name to be associated with resource.
2552 * @exclusive: whether the region access is exclusive or not
2554 * Mark the PCI region associated with PCI device @pdev BR @bar as
2555 * being reserved by owner @res_name. Do not access any
2556 * address inside the PCI regions unless this call returns
2559 * If @exclusive is set, then the region is marked so that userspace
2560 * is explicitly not allowed to map the resource via /dev/mem or
2561 * sysfs MMIO access.
2563 * Returns 0 on success, or %EBUSY on error. A warning
2564 * message is also printed on failure.
2566 static int __pci_request_region(struct pci_dev *pdev, int bar,
2567 const char *res_name, int exclusive)
2569 struct pci_devres *dr;
2571 if (pci_resource_len(pdev, bar) == 0)
2574 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2575 if (!request_region(pci_resource_start(pdev, bar),
2576 pci_resource_len(pdev, bar), res_name))
2578 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2579 if (!__request_mem_region(pci_resource_start(pdev, bar),
2580 pci_resource_len(pdev, bar), res_name,
2585 dr = find_pci_dr(pdev);
2587 dr->region_mask |= 1 << bar;
2592 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2593 &pdev->resource[bar]);
2598 * pci_request_region - Reserve PCI I/O and memory resource
2599 * @pdev: PCI device whose resources are to be reserved
2600 * @bar: BAR to be reserved
2601 * @res_name: Name to be associated with resource
2603 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2604 * being reserved by owner @res_name. Do not access any
2605 * address inside the PCI regions unless this call returns
2608 * Returns 0 on success, or %EBUSY on error. A warning
2609 * message is also printed on failure.
2611 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2613 return __pci_request_region(pdev, bar, res_name, 0);
2615 EXPORT_SYMBOL(pci_request_region);
2618 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2619 * @pdev: PCI device whose resources are to be reserved
2620 * @bar: BAR to be reserved
2621 * @res_name: Name to be associated with resource.
2623 * Mark the PCI region associated with PCI device @pdev BR @bar as
2624 * being reserved by owner @res_name. Do not access any
2625 * address inside the PCI regions unless this call returns
2628 * Returns 0 on success, or %EBUSY on error. A warning
2629 * message is also printed on failure.
2631 * The key difference that _exclusive makes it that userspace is
2632 * explicitly not allowed to map the resource via /dev/mem or
2635 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
2636 const char *res_name)
2638 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2640 EXPORT_SYMBOL(pci_request_region_exclusive);
2643 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2644 * @pdev: PCI device whose resources were previously reserved
2645 * @bars: Bitmask of BARs to be released
2647 * Release selected PCI I/O and memory resources previously reserved.
2648 * Call this function only after all use of the PCI regions has ceased.
2650 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2654 for (i = 0; i < 6; i++)
2655 if (bars & (1 << i))
2656 pci_release_region(pdev, i);
2658 EXPORT_SYMBOL(pci_release_selected_regions);
2660 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2661 const char *res_name, int excl)
2665 for (i = 0; i < 6; i++)
2666 if (bars & (1 << i))
2667 if (__pci_request_region(pdev, i, res_name, excl))
2673 if (bars & (1 << i))
2674 pci_release_region(pdev, i);
2681 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2682 * @pdev: PCI device whose resources are to be reserved
2683 * @bars: Bitmask of BARs to be requested
2684 * @res_name: Name to be associated with resource
2686 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2687 const char *res_name)
2689 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2691 EXPORT_SYMBOL(pci_request_selected_regions);
2693 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
2694 const char *res_name)
2696 return __pci_request_selected_regions(pdev, bars, res_name,
2697 IORESOURCE_EXCLUSIVE);
2699 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2702 * pci_release_regions - Release reserved PCI I/O and memory resources
2703 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2705 * Releases all PCI I/O and memory resources previously reserved by a
2706 * successful call to pci_request_regions. Call this function only
2707 * after all use of the PCI regions has ceased.
2710 void pci_release_regions(struct pci_dev *pdev)
2712 pci_release_selected_regions(pdev, (1 << 6) - 1);
2714 EXPORT_SYMBOL(pci_release_regions);
2717 * pci_request_regions - Reserved PCI I/O and memory resources
2718 * @pdev: PCI device whose resources are to be reserved
2719 * @res_name: Name to be associated with resource.
2721 * Mark all PCI regions associated with PCI device @pdev as
2722 * being reserved by owner @res_name. Do not access any
2723 * address inside the PCI regions unless this call returns
2726 * Returns 0 on success, or %EBUSY on error. A warning
2727 * message is also printed on failure.
2729 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2731 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2733 EXPORT_SYMBOL(pci_request_regions);
2736 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2737 * @pdev: PCI device whose resources are to be reserved
2738 * @res_name: Name to be associated with resource.
2740 * Mark all PCI regions associated with PCI device @pdev as
2741 * being reserved by owner @res_name. Do not access any
2742 * address inside the PCI regions unless this call returns
2745 * pci_request_regions_exclusive() will mark the region so that
2746 * /dev/mem and the sysfs MMIO access will not be allowed.
2748 * Returns 0 on success, or %EBUSY on error. A warning
2749 * message is also printed on failure.
2751 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2753 return pci_request_selected_regions_exclusive(pdev,
2754 ((1 << 6) - 1), res_name);
2756 EXPORT_SYMBOL(pci_request_regions_exclusive);
2759 * pci_remap_iospace - Remap the memory mapped I/O space
2760 * @res: Resource describing the I/O space
2761 * @phys_addr: physical address of range to be mapped
2763 * Remap the memory mapped I/O space described by the @res
2764 * and the CPU physical address @phys_addr into virtual address space.
2765 * Only architectures that have memory mapped IO functions defined
2766 * (and the PCI_IOBASE value defined) should call this function.
2768 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
2770 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
2771 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
2773 if (!(res->flags & IORESOURCE_IO))
2776 if (res->end > IO_SPACE_LIMIT)
2779 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
2780 pgprot_device(PAGE_KERNEL));
2782 /* this architecture does not have memory mapped I/O space,
2783 so this function should never be called */
2784 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
2789 static void __pci_set_master(struct pci_dev *dev, bool enable)
2793 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2795 cmd = old_cmd | PCI_COMMAND_MASTER;
2797 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2798 if (cmd != old_cmd) {
2799 dev_dbg(&dev->dev, "%s bus mastering\n",
2800 enable ? "enabling" : "disabling");
2801 pci_write_config_word(dev, PCI_COMMAND, cmd);
2803 dev->is_busmaster = enable;
2807 * pcibios_setup - process "pci=" kernel boot arguments
2808 * @str: string used to pass in "pci=" kernel boot arguments
2810 * Process kernel boot arguments. This is the default implementation.
2811 * Architecture specific implementations can override this as necessary.
2813 char * __weak __init pcibios_setup(char *str)
2819 * pcibios_set_master - enable PCI bus-mastering for device dev
2820 * @dev: the PCI device to enable
2822 * Enables PCI bus-mastering for the device. This is the default
2823 * implementation. Architecture specific implementations can override
2824 * this if necessary.
2826 void __weak pcibios_set_master(struct pci_dev *dev)
2830 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2831 if (pci_is_pcie(dev))
2834 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2836 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2837 else if (lat > pcibios_max_latency)
2838 lat = pcibios_max_latency;
2842 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2846 * pci_set_master - enables bus-mastering for device dev
2847 * @dev: the PCI device to enable
2849 * Enables bus-mastering on the device and calls pcibios_set_master()
2850 * to do the needed arch specific settings.
2852 void pci_set_master(struct pci_dev *dev)
2854 __pci_set_master(dev, true);
2855 pcibios_set_master(dev);
2857 EXPORT_SYMBOL(pci_set_master);
2860 * pci_clear_master - disables bus-mastering for device dev
2861 * @dev: the PCI device to disable
2863 void pci_clear_master(struct pci_dev *dev)
2865 __pci_set_master(dev, false);
2867 EXPORT_SYMBOL(pci_clear_master);
2870 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2871 * @dev: the PCI device for which MWI is to be enabled
2873 * Helper function for pci_set_mwi.
2874 * Originally copied from drivers/net/acenic.c.
2875 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2877 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2879 int pci_set_cacheline_size(struct pci_dev *dev)
2883 if (!pci_cache_line_size)
2886 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2887 equal to or multiple of the right value. */
2888 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2889 if (cacheline_size >= pci_cache_line_size &&
2890 (cacheline_size % pci_cache_line_size) == 0)
2893 /* Write the correct value. */
2894 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2896 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2897 if (cacheline_size == pci_cache_line_size)
2900 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
2901 pci_cache_line_size << 2);
2905 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2908 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2909 * @dev: the PCI device for which MWI is enabled
2911 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2913 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2915 int pci_set_mwi(struct pci_dev *dev)
2917 #ifdef PCI_DISABLE_MWI
2923 rc = pci_set_cacheline_size(dev);
2927 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2928 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
2929 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2930 cmd |= PCI_COMMAND_INVALIDATE;
2931 pci_write_config_word(dev, PCI_COMMAND, cmd);
2936 EXPORT_SYMBOL(pci_set_mwi);
2939 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2940 * @dev: the PCI device for which MWI is enabled
2942 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2943 * Callers are not required to check the return value.
2945 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2947 int pci_try_set_mwi(struct pci_dev *dev)
2949 #ifdef PCI_DISABLE_MWI
2952 return pci_set_mwi(dev);
2955 EXPORT_SYMBOL(pci_try_set_mwi);
2958 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2959 * @dev: the PCI device to disable
2961 * Disables PCI Memory-Write-Invalidate transaction on the device
2963 void pci_clear_mwi(struct pci_dev *dev)
2965 #ifndef PCI_DISABLE_MWI
2968 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2969 if (cmd & PCI_COMMAND_INVALIDATE) {
2970 cmd &= ~PCI_COMMAND_INVALIDATE;
2971 pci_write_config_word(dev, PCI_COMMAND, cmd);
2975 EXPORT_SYMBOL(pci_clear_mwi);
2978 * pci_intx - enables/disables PCI INTx for device dev
2979 * @pdev: the PCI device to operate on
2980 * @enable: boolean: whether to enable or disable PCI INTx
2982 * Enables/disables PCI INTx for device dev
2984 void pci_intx(struct pci_dev *pdev, int enable)
2986 u16 pci_command, new;
2988 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2991 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2993 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2995 if (new != pci_command) {
2996 struct pci_devres *dr;
2998 pci_write_config_word(pdev, PCI_COMMAND, new);
3000 dr = find_pci_dr(pdev);
3001 if (dr && !dr->restore_intx) {
3002 dr->restore_intx = 1;
3003 dr->orig_intx = !enable;
3007 EXPORT_SYMBOL_GPL(pci_intx);
3010 * pci_intx_mask_supported - probe for INTx masking support
3011 * @dev: the PCI device to operate on
3013 * Check if the device dev support INTx masking via the config space
3016 bool pci_intx_mask_supported(struct pci_dev *dev)
3018 bool mask_supported = false;
3021 if (dev->broken_intx_masking)
3024 pci_cfg_access_lock(dev);
3026 pci_read_config_word(dev, PCI_COMMAND, &orig);
3027 pci_write_config_word(dev, PCI_COMMAND,
3028 orig ^ PCI_COMMAND_INTX_DISABLE);
3029 pci_read_config_word(dev, PCI_COMMAND, &new);
3032 * There's no way to protect against hardware bugs or detect them
3033 * reliably, but as long as we know what the value should be, let's
3034 * go ahead and check it.
3036 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3037 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3039 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3040 mask_supported = true;
3041 pci_write_config_word(dev, PCI_COMMAND, orig);
3044 pci_cfg_access_unlock(dev);
3045 return mask_supported;
3047 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3049 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3051 struct pci_bus *bus = dev->bus;
3052 bool mask_updated = true;
3053 u32 cmd_status_dword;
3054 u16 origcmd, newcmd;
3055 unsigned long flags;
3059 * We do a single dword read to retrieve both command and status.
3060 * Document assumptions that make this possible.
3062 BUILD_BUG_ON(PCI_COMMAND % 4);
3063 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3065 raw_spin_lock_irqsave(&pci_lock, flags);
3067 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3069 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3072 * Check interrupt status register to see whether our device
3073 * triggered the interrupt (when masking) or the next IRQ is
3074 * already pending (when unmasking).
3076 if (mask != irq_pending) {
3077 mask_updated = false;
3081 origcmd = cmd_status_dword;
3082 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3084 newcmd |= PCI_COMMAND_INTX_DISABLE;
3085 if (newcmd != origcmd)
3086 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3089 raw_spin_unlock_irqrestore(&pci_lock, flags);
3091 return mask_updated;
3095 * pci_check_and_mask_intx - mask INTx on pending interrupt
3096 * @dev: the PCI device to operate on
3098 * Check if the device dev has its INTx line asserted, mask it and
3099 * return true in that case. False is returned if not interrupt was
3102 bool pci_check_and_mask_intx(struct pci_dev *dev)
3104 return pci_check_and_set_intx_mask(dev, true);
3106 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3109 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3110 * @dev: the PCI device to operate on
3112 * Check if the device dev has its INTx line asserted, unmask it if not
3113 * and return true. False is returned and the mask remains active if
3114 * there was still an interrupt pending.
3116 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3118 return pci_check_and_set_intx_mask(dev, false);
3120 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3122 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3124 return dma_set_max_seg_size(&dev->dev, size);
3126 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3128 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3130 return dma_set_seg_boundary(&dev->dev, mask);
3132 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3135 * pci_wait_for_pending_transaction - waits for pending transaction
3136 * @dev: the PCI device to operate on
3138 * Return 0 if transaction is pending 1 otherwise.
3140 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3142 if (!pci_is_pcie(dev))
3145 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3146 PCI_EXP_DEVSTA_TRPND);
3148 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3150 static int pcie_flr(struct pci_dev *dev, int probe)
3154 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3155 if (!(cap & PCI_EXP_DEVCAP_FLR))
3161 if (!pci_wait_for_pending_transaction(dev))
3162 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3164 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3169 static int pci_af_flr(struct pci_dev *dev, int probe)
3174 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3178 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3179 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3186 * Wait for Transaction Pending bit to clear. A word-aligned test
3187 * is used, so we use the conrol offset rather than status and shift
3188 * the test bit to match.
3190 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3191 PCI_AF_STATUS_TP << 8))
3192 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3194 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3200 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3201 * @dev: Device to reset.
3202 * @probe: If set, only check if the device can be reset this way.
3204 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3205 * unset, it will be reinitialized internally when going from PCI_D3hot to
3206 * PCI_D0. If that's the case and the device is not in a low-power state
3207 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3209 * NOTE: This causes the caller to sleep for twice the device power transition
3210 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3211 * by default (i.e. unless the @dev's d3_delay field has a different value).
3212 * Moreover, only devices in D0 can be reset by this function.
3214 static int pci_pm_reset(struct pci_dev *dev, int probe)
3218 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3221 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3222 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3228 if (dev->current_state != PCI_D0)
3231 csr &= ~PCI_PM_CTRL_STATE_MASK;
3233 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3234 pci_dev_d3_sleep(dev);
3236 csr &= ~PCI_PM_CTRL_STATE_MASK;
3238 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3239 pci_dev_d3_sleep(dev);
3244 void pci_reset_secondary_bus(struct pci_dev *dev)
3248 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3249 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3250 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3252 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3253 * this to 2ms to ensure that we meet the minimum requirement.
3257 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3258 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3261 * Trhfa for conventional PCI is 2^25 clock cycles.
3262 * Assuming a minimum 33MHz clock this results in a 1s
3263 * delay before we can consider subordinate devices to
3264 * be re-initialized. PCIe has some ways to shorten this,
3265 * but we don't make use of them yet.
3270 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3272 pci_reset_secondary_bus(dev);
3276 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3277 * @dev: Bridge device
3279 * Use the bridge control register to assert reset on the secondary bus.
3280 * Devices on the secondary bus are left in power-on state.
3282 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3284 pcibios_reset_secondary_bus(dev);
3286 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3288 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3290 struct pci_dev *pdev;
3292 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3293 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3296 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3303 pci_reset_bridge_secondary_bus(dev->bus->self);
3308 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3312 if (!hotplug || !try_module_get(hotplug->ops->owner))
3315 if (hotplug->ops->reset_slot)
3316 rc = hotplug->ops->reset_slot(hotplug, probe);
3318 module_put(hotplug->ops->owner);
3323 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3325 struct pci_dev *pdev;
3327 if (dev->subordinate || !dev->slot ||
3328 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3331 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3332 if (pdev != dev && pdev->slot == dev->slot)
3335 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3338 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3344 rc = pci_dev_specific_reset(dev, probe);
3348 rc = pcie_flr(dev, probe);
3352 rc = pci_af_flr(dev, probe);
3356 rc = pci_pm_reset(dev, probe);
3360 rc = pci_dev_reset_slot_function(dev, probe);
3364 rc = pci_parent_bus_reset(dev, probe);
3369 static void pci_dev_lock(struct pci_dev *dev)
3371 pci_cfg_access_lock(dev);
3372 /* block PM suspend, driver probe, etc. */
3373 device_lock(&dev->dev);
3376 /* Return 1 on successful lock, 0 on contention */
3377 static int pci_dev_trylock(struct pci_dev *dev)
3379 if (pci_cfg_access_trylock(dev)) {
3380 if (device_trylock(&dev->dev))
3382 pci_cfg_access_unlock(dev);
3388 static void pci_dev_unlock(struct pci_dev *dev)
3390 device_unlock(&dev->dev);
3391 pci_cfg_access_unlock(dev);
3395 * pci_reset_notify - notify device driver of reset
3396 * @dev: device to be notified of reset
3397 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3400 * Must be called prior to device access being disabled and after device
3401 * access is restored.
3403 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3405 const struct pci_error_handlers *err_handler =
3406 dev->driver ? dev->driver->err_handler : NULL;
3407 if (err_handler && err_handler->reset_notify)
3408 err_handler->reset_notify(dev, prepare);
3411 static void pci_dev_save_and_disable(struct pci_dev *dev)
3413 pci_reset_notify(dev, true);
3416 * Wake-up device prior to save. PM registers default to D0 after
3417 * reset and a simple register restore doesn't reliably return
3418 * to a non-D0 state anyway.
3420 pci_set_power_state(dev, PCI_D0);
3422 pci_save_state(dev);
3424 * Disable the device by clearing the Command register, except for
3425 * INTx-disable which is set. This not only disables MMIO and I/O port
3426 * BARs, but also prevents the device from being Bus Master, preventing
3427 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3428 * compliant devices, INTx-disable prevents legacy interrupts.
3430 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3433 static void pci_dev_restore(struct pci_dev *dev)
3435 pci_restore_state(dev);
3436 pci_reset_notify(dev, false);
3439 static int pci_dev_reset(struct pci_dev *dev, int probe)
3446 rc = __pci_dev_reset(dev, probe);
3449 pci_dev_unlock(dev);
3455 * __pci_reset_function - reset a PCI device function
3456 * @dev: PCI device to reset
3458 * Some devices allow an individual function to be reset without affecting
3459 * other functions in the same device. The PCI device must be responsive
3460 * to PCI config space in order to use this function.
3462 * The device function is presumed to be unused when this function is called.
3463 * Resetting the device will make the contents of PCI configuration space
3464 * random, so any caller of this must be prepared to reinitialise the
3465 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3468 * Returns 0 if the device function was successfully reset or negative if the
3469 * device doesn't support resetting a single function.
3471 int __pci_reset_function(struct pci_dev *dev)
3473 return pci_dev_reset(dev, 0);
3475 EXPORT_SYMBOL_GPL(__pci_reset_function);
3478 * __pci_reset_function_locked - reset a PCI device function while holding
3479 * the @dev mutex lock.
3480 * @dev: PCI device to reset
3482 * Some devices allow an individual function to be reset without affecting
3483 * other functions in the same device. The PCI device must be responsive
3484 * to PCI config space in order to use this function.
3486 * The device function is presumed to be unused and the caller is holding
3487 * the device mutex lock when this function is called.
3488 * Resetting the device will make the contents of PCI configuration space
3489 * random, so any caller of this must be prepared to reinitialise the
3490 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3493 * Returns 0 if the device function was successfully reset or negative if the
3494 * device doesn't support resetting a single function.
3496 int __pci_reset_function_locked(struct pci_dev *dev)
3498 return __pci_dev_reset(dev, 0);
3500 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3503 * pci_probe_reset_function - check whether the device can be safely reset
3504 * @dev: PCI device to reset
3506 * Some devices allow an individual function to be reset without affecting
3507 * other functions in the same device. The PCI device must be responsive
3508 * to PCI config space in order to use this function.
3510 * Returns 0 if the device function can be reset or negative if the
3511 * device doesn't support resetting a single function.
3513 int pci_probe_reset_function(struct pci_dev *dev)
3515 return pci_dev_reset(dev, 1);
3519 * pci_reset_function - quiesce and reset a PCI device function
3520 * @dev: PCI device to reset
3522 * Some devices allow an individual function to be reset without affecting
3523 * other functions in the same device. The PCI device must be responsive
3524 * to PCI config space in order to use this function.
3526 * This function does not just reset the PCI portion of a device, but
3527 * clears all the state associated with the device. This function differs
3528 * from __pci_reset_function in that it saves and restores device state
3531 * Returns 0 if the device function was successfully reset or negative if the
3532 * device doesn't support resetting a single function.
3534 int pci_reset_function(struct pci_dev *dev)
3538 rc = pci_dev_reset(dev, 1);
3542 pci_dev_save_and_disable(dev);
3544 rc = pci_dev_reset(dev, 0);
3546 pci_dev_restore(dev);
3550 EXPORT_SYMBOL_GPL(pci_reset_function);
3553 * pci_try_reset_function - quiesce and reset a PCI device function
3554 * @dev: PCI device to reset
3556 * Same as above, except return -EAGAIN if unable to lock device.
3558 int pci_try_reset_function(struct pci_dev *dev)
3562 rc = pci_dev_reset(dev, 1);
3566 pci_dev_save_and_disable(dev);
3568 if (pci_dev_trylock(dev)) {
3569 rc = __pci_dev_reset(dev, 0);
3570 pci_dev_unlock(dev);
3574 pci_dev_restore(dev);
3578 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3580 /* Do any devices on or below this bus prevent a bus reset? */
3581 static bool pci_bus_resetable(struct pci_bus *bus)
3583 struct pci_dev *dev;
3585 list_for_each_entry(dev, &bus->devices, bus_list) {
3586 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3587 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3594 /* Lock devices from the top of the tree down */
3595 static void pci_bus_lock(struct pci_bus *bus)
3597 struct pci_dev *dev;
3599 list_for_each_entry(dev, &bus->devices, bus_list) {
3601 if (dev->subordinate)
3602 pci_bus_lock(dev->subordinate);
3606 /* Unlock devices from the bottom of the tree up */
3607 static void pci_bus_unlock(struct pci_bus *bus)
3609 struct pci_dev *dev;
3611 list_for_each_entry(dev, &bus->devices, bus_list) {
3612 if (dev->subordinate)
3613 pci_bus_unlock(dev->subordinate);
3614 pci_dev_unlock(dev);
3618 /* Return 1 on successful lock, 0 on contention */
3619 static int pci_bus_trylock(struct pci_bus *bus)
3621 struct pci_dev *dev;
3623 list_for_each_entry(dev, &bus->devices, bus_list) {
3624 if (!pci_dev_trylock(dev))
3626 if (dev->subordinate) {
3627 if (!pci_bus_trylock(dev->subordinate)) {
3628 pci_dev_unlock(dev);
3636 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3637 if (dev->subordinate)
3638 pci_bus_unlock(dev->subordinate);
3639 pci_dev_unlock(dev);
3644 /* Do any devices on or below this slot prevent a bus reset? */
3645 static bool pci_slot_resetable(struct pci_slot *slot)
3647 struct pci_dev *dev;
3649 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3650 if (!dev->slot || dev->slot != slot)
3652 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
3653 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
3660 /* Lock devices from the top of the tree down */
3661 static void pci_slot_lock(struct pci_slot *slot)
3663 struct pci_dev *dev;
3665 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3666 if (!dev->slot || dev->slot != slot)
3669 if (dev->subordinate)
3670 pci_bus_lock(dev->subordinate);
3674 /* Unlock devices from the bottom of the tree up */
3675 static void pci_slot_unlock(struct pci_slot *slot)
3677 struct pci_dev *dev;
3679 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3680 if (!dev->slot || dev->slot != slot)
3682 if (dev->subordinate)
3683 pci_bus_unlock(dev->subordinate);
3684 pci_dev_unlock(dev);
3688 /* Return 1 on successful lock, 0 on contention */
3689 static int pci_slot_trylock(struct pci_slot *slot)
3691 struct pci_dev *dev;
3693 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3694 if (!dev->slot || dev->slot != slot)
3696 if (!pci_dev_trylock(dev))
3698 if (dev->subordinate) {
3699 if (!pci_bus_trylock(dev->subordinate)) {
3700 pci_dev_unlock(dev);
3708 list_for_each_entry_continue_reverse(dev,
3709 &slot->bus->devices, bus_list) {
3710 if (!dev->slot || dev->slot != slot)
3712 if (dev->subordinate)
3713 pci_bus_unlock(dev->subordinate);
3714 pci_dev_unlock(dev);
3719 /* Save and disable devices from the top of the tree down */
3720 static void pci_bus_save_and_disable(struct pci_bus *bus)
3722 struct pci_dev *dev;
3724 list_for_each_entry(dev, &bus->devices, bus_list) {
3725 pci_dev_save_and_disable(dev);
3726 if (dev->subordinate)
3727 pci_bus_save_and_disable(dev->subordinate);
3732 * Restore devices from top of the tree down - parent bridges need to be
3733 * restored before we can get to subordinate devices.
3735 static void pci_bus_restore(struct pci_bus *bus)
3737 struct pci_dev *dev;
3739 list_for_each_entry(dev, &bus->devices, bus_list) {
3740 pci_dev_restore(dev);
3741 if (dev->subordinate)
3742 pci_bus_restore(dev->subordinate);
3746 /* Save and disable devices from the top of the tree down */
3747 static void pci_slot_save_and_disable(struct pci_slot *slot)
3749 struct pci_dev *dev;
3751 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3752 if (!dev->slot || dev->slot != slot)
3754 pci_dev_save_and_disable(dev);
3755 if (dev->subordinate)
3756 pci_bus_save_and_disable(dev->subordinate);
3761 * Restore devices from top of the tree down - parent bridges need to be
3762 * restored before we can get to subordinate devices.
3764 static void pci_slot_restore(struct pci_slot *slot)
3766 struct pci_dev *dev;
3768 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3769 if (!dev->slot || dev->slot != slot)
3771 pci_dev_restore(dev);
3772 if (dev->subordinate)
3773 pci_bus_restore(dev->subordinate);
3777 static int pci_slot_reset(struct pci_slot *slot, int probe)
3781 if (!slot || !pci_slot_resetable(slot))
3785 pci_slot_lock(slot);
3789 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3792 pci_slot_unlock(slot);
3798 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3799 * @slot: PCI slot to probe
3801 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3803 int pci_probe_reset_slot(struct pci_slot *slot)
3805 return pci_slot_reset(slot, 1);
3807 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3810 * pci_reset_slot - reset a PCI slot
3811 * @slot: PCI slot to reset
3813 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3814 * independent of other slots. For instance, some slots may support slot power
3815 * control. In the case of a 1:1 bus to slot architecture, this function may
3816 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3817 * Generally a slot reset should be attempted before a bus reset. All of the
3818 * function of the slot and any subordinate buses behind the slot are reset
3819 * through this function. PCI config space of all devices in the slot and
3820 * behind the slot is saved before and restored after reset.
3822 * Return 0 on success, non-zero on error.
3824 int pci_reset_slot(struct pci_slot *slot)
3828 rc = pci_slot_reset(slot, 1);
3832 pci_slot_save_and_disable(slot);
3834 rc = pci_slot_reset(slot, 0);
3836 pci_slot_restore(slot);
3840 EXPORT_SYMBOL_GPL(pci_reset_slot);
3843 * pci_try_reset_slot - Try to reset a PCI slot
3844 * @slot: PCI slot to reset
3846 * Same as above except return -EAGAIN if the slot cannot be locked
3848 int pci_try_reset_slot(struct pci_slot *slot)
3852 rc = pci_slot_reset(slot, 1);
3856 pci_slot_save_and_disable(slot);
3858 if (pci_slot_trylock(slot)) {
3860 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3861 pci_slot_unlock(slot);
3865 pci_slot_restore(slot);
3869 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3871 static int pci_bus_reset(struct pci_bus *bus, int probe)
3873 if (!bus->self || !pci_bus_resetable(bus))
3883 pci_reset_bridge_secondary_bus(bus->self);
3885 pci_bus_unlock(bus);
3891 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3892 * @bus: PCI bus to probe
3894 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3896 int pci_probe_reset_bus(struct pci_bus *bus)
3898 return pci_bus_reset(bus, 1);
3900 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3903 * pci_reset_bus - reset a PCI bus
3904 * @bus: top level PCI bus to reset
3906 * Do a bus reset on the given bus and any subordinate buses, saving
3907 * and restoring state of all devices.
3909 * Return 0 on success, non-zero on error.
3911 int pci_reset_bus(struct pci_bus *bus)
3915 rc = pci_bus_reset(bus, 1);
3919 pci_bus_save_and_disable(bus);
3921 rc = pci_bus_reset(bus, 0);
3923 pci_bus_restore(bus);
3927 EXPORT_SYMBOL_GPL(pci_reset_bus);
3930 * pci_try_reset_bus - Try to reset a PCI bus
3931 * @bus: top level PCI bus to reset
3933 * Same as above except return -EAGAIN if the bus cannot be locked
3935 int pci_try_reset_bus(struct pci_bus *bus)
3939 rc = pci_bus_reset(bus, 1);
3943 pci_bus_save_and_disable(bus);
3945 if (pci_bus_trylock(bus)) {
3947 pci_reset_bridge_secondary_bus(bus->self);
3948 pci_bus_unlock(bus);
3952 pci_bus_restore(bus);
3956 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3959 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3960 * @dev: PCI device to query
3962 * Returns mmrbc: maximum designed memory read count in bytes
3963 * or appropriate error value.
3965 int pcix_get_max_mmrbc(struct pci_dev *dev)
3970 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3974 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3977 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3979 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3982 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3983 * @dev: PCI device to query
3985 * Returns mmrbc: maximum memory read count in bytes
3986 * or appropriate error value.
3988 int pcix_get_mmrbc(struct pci_dev *dev)
3993 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3997 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4000 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4002 EXPORT_SYMBOL(pcix_get_mmrbc);
4005 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4006 * @dev: PCI device to query
4007 * @mmrbc: maximum memory read count in bytes
4008 * valid values are 512, 1024, 2048, 4096
4010 * If possible sets maximum memory read byte count, some bridges have erratas
4011 * that prevent this.
4013 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4019 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4022 v = ffs(mmrbc) - 10;
4024 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4028 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4031 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4034 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4037 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4039 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4042 cmd &= ~PCI_X_CMD_MAX_READ;
4044 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4049 EXPORT_SYMBOL(pcix_set_mmrbc);
4052 * pcie_get_readrq - get PCI Express read request size
4053 * @dev: PCI device to query
4055 * Returns maximum memory read request in bytes
4056 * or appropriate error value.
4058 int pcie_get_readrq(struct pci_dev *dev)
4062 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4064 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4066 EXPORT_SYMBOL(pcie_get_readrq);
4069 * pcie_set_readrq - set PCI Express maximum memory read request
4070 * @dev: PCI device to query
4071 * @rq: maximum memory read count in bytes
4072 * valid values are 128, 256, 512, 1024, 2048, 4096
4074 * If possible sets maximum memory read request in bytes
4076 int pcie_set_readrq(struct pci_dev *dev, int rq)
4080 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4084 * If using the "performance" PCIe config, we clamp the
4085 * read rq size to the max packet size to prevent the
4086 * host bridge generating requests larger than we can
4089 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4090 int mps = pcie_get_mps(dev);
4096 v = (ffs(rq) - 8) << 12;
4098 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4099 PCI_EXP_DEVCTL_READRQ, v);
4101 EXPORT_SYMBOL(pcie_set_readrq);
4104 * pcie_get_mps - get PCI Express maximum payload size
4105 * @dev: PCI device to query
4107 * Returns maximum payload size in bytes
4109 int pcie_get_mps(struct pci_dev *dev)
4113 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4115 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4117 EXPORT_SYMBOL(pcie_get_mps);
4120 * pcie_set_mps - set PCI Express maximum payload size
4121 * @dev: PCI device to query
4122 * @mps: maximum payload size in bytes
4123 * valid values are 128, 256, 512, 1024, 2048, 4096
4125 * If possible sets maximum payload size
4127 int pcie_set_mps(struct pci_dev *dev, int mps)
4131 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4135 if (v > dev->pcie_mpss)
4139 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4140 PCI_EXP_DEVCTL_PAYLOAD, v);
4142 EXPORT_SYMBOL(pcie_set_mps);
4145 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4146 * @dev: PCI device to query
4147 * @speed: storage for minimum speed
4148 * @width: storage for minimum width
4150 * This function will walk up the PCI device chain and determine the minimum
4151 * link width and speed of the device.
4153 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4154 enum pcie_link_width *width)
4158 *speed = PCI_SPEED_UNKNOWN;
4159 *width = PCIE_LNK_WIDTH_UNKNOWN;
4163 enum pci_bus_speed next_speed;
4164 enum pcie_link_width next_width;
4166 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4170 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4171 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4172 PCI_EXP_LNKSTA_NLW_SHIFT;
4174 if (next_speed < *speed)
4175 *speed = next_speed;
4177 if (next_width < *width)
4178 *width = next_width;
4180 dev = dev->bus->self;
4185 EXPORT_SYMBOL(pcie_get_minimum_link);
4188 * pci_select_bars - Make BAR mask from the type of resource
4189 * @dev: the PCI device for which BAR mask is made
4190 * @flags: resource type mask to be selected
4192 * This helper routine makes bar mask from the type of resource.
4194 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4197 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4198 if (pci_resource_flags(dev, i) & flags)
4202 EXPORT_SYMBOL(pci_select_bars);
4205 * pci_resource_bar - get position of the BAR associated with a resource
4206 * @dev: the PCI device
4207 * @resno: the resource number
4208 * @type: the BAR type to be filled in
4210 * Returns BAR position in config space, or 0 if the BAR is invalid.
4212 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4216 if (resno < PCI_ROM_RESOURCE) {
4217 *type = pci_bar_unknown;
4218 return PCI_BASE_ADDRESS_0 + 4 * resno;
4219 } else if (resno == PCI_ROM_RESOURCE) {
4220 *type = pci_bar_mem32;
4221 return dev->rom_base_reg;
4222 } else if (resno < PCI_BRIDGE_RESOURCES) {
4223 /* device specific resource */
4224 *type = pci_bar_unknown;
4225 reg = pci_iov_resource_bar(dev, resno);
4230 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4234 /* Some architectures require additional programming to enable VGA */
4235 static arch_set_vga_state_t arch_set_vga_state;
4237 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4239 arch_set_vga_state = func; /* NULL disables */
4242 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4243 unsigned int command_bits, u32 flags)
4245 if (arch_set_vga_state)
4246 return arch_set_vga_state(dev, decode, command_bits,
4252 * pci_set_vga_state - set VGA decode state on device and parents if requested
4253 * @dev: the PCI device
4254 * @decode: true = enable decoding, false = disable decoding
4255 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4256 * @flags: traverse ancestors and change bridges
4257 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4259 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4260 unsigned int command_bits, u32 flags)
4262 struct pci_bus *bus;
4263 struct pci_dev *bridge;
4267 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4269 /* ARCH specific VGA enables */
4270 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4274 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4275 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4277 cmd |= command_bits;
4279 cmd &= ~command_bits;
4280 pci_write_config_word(dev, PCI_COMMAND, cmd);
4283 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4290 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4293 cmd |= PCI_BRIDGE_CTL_VGA;
4295 cmd &= ~PCI_BRIDGE_CTL_VGA;
4296 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4304 bool pci_device_is_present(struct pci_dev *pdev)
4308 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4310 EXPORT_SYMBOL_GPL(pci_device_is_present);
4312 void pci_ignore_hotplug(struct pci_dev *dev)
4314 struct pci_dev *bridge = dev->bus->self;
4316 dev->ignore_hotplug = 1;
4317 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4319 bridge->ignore_hotplug = 1;
4321 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4323 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4324 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4325 static DEFINE_SPINLOCK(resource_alignment_lock);
4328 * pci_specified_resource_alignment - get resource alignment specified by user.
4329 * @dev: the PCI device to get
4331 * RETURNS: Resource alignment if it is specified.
4332 * Zero if it is not specified.
4334 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4336 int seg, bus, slot, func, align_order, count;
4337 resource_size_t align = 0;
4340 spin_lock(&resource_alignment_lock);
4341 p = resource_alignment_param;
4344 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4350 if (sscanf(p, "%x:%x:%x.%x%n",
4351 &seg, &bus, &slot, &func, &count) != 4) {
4353 if (sscanf(p, "%x:%x.%x%n",
4354 &bus, &slot, &func, &count) != 3) {
4355 /* Invalid format */
4356 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4362 if (seg == pci_domain_nr(dev->bus) &&
4363 bus == dev->bus->number &&
4364 slot == PCI_SLOT(dev->devfn) &&
4365 func == PCI_FUNC(dev->devfn)) {
4366 if (align_order == -1)
4369 align = 1 << align_order;
4373 if (*p != ';' && *p != ',') {
4374 /* End of param or invalid format */
4379 spin_unlock(&resource_alignment_lock);
4384 * This function disables memory decoding and releases memory resources
4385 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4386 * It also rounds up size to specified alignment.
4387 * Later on, the kernel will assign page-aligned memory resource back
4390 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4394 resource_size_t align, size;
4397 /* check if specified PCI is target device to reassign */
4398 align = pci_specified_resource_alignment(dev);
4402 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4403 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4405 "Can't reassign resources to host bridge.\n");
4410 "Disabling memory decoding and releasing memory resources.\n");
4411 pci_read_config_word(dev, PCI_COMMAND, &command);
4412 command &= ~PCI_COMMAND_MEMORY;
4413 pci_write_config_word(dev, PCI_COMMAND, command);
4415 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4416 r = &dev->resource[i];
4417 if (!(r->flags & IORESOURCE_MEM))
4419 size = resource_size(r);
4423 "Rounding up size of resource #%d to %#llx.\n",
4424 i, (unsigned long long)size);
4426 r->flags |= IORESOURCE_UNSET;
4430 /* Need to disable bridge's resource window,
4431 * to enable the kernel to reassign new resource
4434 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4435 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4436 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4437 r = &dev->resource[i];
4438 if (!(r->flags & IORESOURCE_MEM))
4440 r->flags |= IORESOURCE_UNSET;
4441 r->end = resource_size(r) - 1;
4444 pci_disable_bridge_window(dev);
4448 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4450 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4451 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4452 spin_lock(&resource_alignment_lock);
4453 strncpy(resource_alignment_param, buf, count);
4454 resource_alignment_param[count] = '\0';
4455 spin_unlock(&resource_alignment_lock);
4459 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4462 spin_lock(&resource_alignment_lock);
4463 count = snprintf(buf, size, "%s", resource_alignment_param);
4464 spin_unlock(&resource_alignment_lock);
4468 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4470 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4473 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4474 const char *buf, size_t count)
4476 return pci_set_resource_alignment_param(buf, count);
4479 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4480 pci_resource_alignment_store);
4482 static int __init pci_resource_alignment_sysfs_init(void)
4484 return bus_create_file(&pci_bus_type,
4485 &bus_attr_resource_alignment);
4487 late_initcall(pci_resource_alignment_sysfs_init);
4489 static void pci_no_domains(void)
4491 #ifdef CONFIG_PCI_DOMAINS
4492 pci_domains_supported = 0;
4496 #ifdef CONFIG_PCI_DOMAINS
4497 static atomic_t __domain_nr = ATOMIC_INIT(-1);
4499 int pci_get_new_domain_nr(void)
4501 return atomic_inc_return(&__domain_nr);
4504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
4505 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
4507 static int use_dt_domains = -1;
4508 int domain = of_get_pci_domain_nr(parent->of_node);
4511 * Check DT domain and use_dt_domains values.
4513 * If DT domain property is valid (domain >= 0) and
4514 * use_dt_domains != 0, the DT assignment is valid since this means
4515 * we have not previously allocated a domain number by using
4516 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4517 * 1, to indicate that we have just assigned a domain number from
4520 * If DT domain property value is not valid (ie domain < 0), and we
4521 * have not previously assigned a domain number from DT
4522 * (use_dt_domains != 1) we should assign a domain number by
4525 * pci_get_new_domain_nr()
4527 * API and update the use_dt_domains value to keep track of method we
4528 * are using to assign domain numbers (use_dt_domains = 0).
4530 * All other combinations imply we have a platform that is trying
4531 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4532 * which is a recipe for domain mishandling and it is prevented by
4533 * invalidating the domain value (domain = -1) and printing a
4534 * corresponding error.
4536 if (domain >= 0 && use_dt_domains) {
4538 } else if (domain < 0 && use_dt_domains != 1) {
4540 domain = pci_get_new_domain_nr();
4542 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4543 parent->of_node->full_name);
4547 bus->domain_nr = domain;
4553 * pci_ext_cfg_avail - can we access extended PCI config space?
4555 * Returns 1 if we can access PCI extended config space (offsets
4556 * greater than 0xff). This is the default implementation. Architecture
4557 * implementations can override this.
4559 int __weak pci_ext_cfg_avail(void)
4564 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4567 EXPORT_SYMBOL(pci_fixup_cardbus);
4569 static int __init pci_setup(char *str)
4572 char *k = strchr(str, ',');
4575 if (*str && (str = pcibios_setup(str)) && *str) {
4576 if (!strcmp(str, "nomsi")) {
4578 } else if (!strcmp(str, "noaer")) {
4580 } else if (!strncmp(str, "realloc=", 8)) {
4581 pci_realloc_get_opt(str + 8);
4582 } else if (!strncmp(str, "realloc", 7)) {
4583 pci_realloc_get_opt("on");
4584 } else if (!strcmp(str, "nodomains")) {
4586 } else if (!strncmp(str, "noari", 5)) {
4587 pcie_ari_disabled = true;
4588 } else if (!strncmp(str, "cbiosize=", 9)) {
4589 pci_cardbus_io_size = memparse(str + 9, &str);
4590 } else if (!strncmp(str, "cbmemsize=", 10)) {
4591 pci_cardbus_mem_size = memparse(str + 10, &str);
4592 } else if (!strncmp(str, "resource_alignment=", 19)) {
4593 pci_set_resource_alignment_param(str + 19,
4595 } else if (!strncmp(str, "ecrc=", 5)) {
4596 pcie_ecrc_get_policy(str + 5);
4597 } else if (!strncmp(str, "hpiosize=", 9)) {
4598 pci_hotplug_io_size = memparse(str + 9, &str);
4599 } else if (!strncmp(str, "hpmemsize=", 10)) {
4600 pci_hotplug_mem_size = memparse(str + 10, &str);
4601 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4602 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4603 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4604 pcie_bus_config = PCIE_BUS_SAFE;
4605 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4606 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4607 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4608 pcie_bus_config = PCIE_BUS_PEER2PEER;
4609 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4610 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4612 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4620 early_param("pci", pci_setup);