drivers/pci/intel-iommu.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  * Author: Fenghua Yu <fenghua.yu@intel.com>
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/bitmap.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/slab.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/mempool.h>
  35 #include <linux/timer.h>
  36 #include <linux/iova.h>
  37 #include <linux/iommu.h>
  38 #include <linux/intel-iommu.h>
  39 #include <linux/sysdev.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/iommu.h>
  42 #include "pci.h"
  43
  44 #define ROOT_SIZE               VTD_PAGE_SIZE
  45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
  46
  47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
  48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
  49
  50 #define IOAPIC_RANGE_START      (0xfee00000)
  51 #define IOAPIC_RANGE_END        (0xfeefffff)
  52 #define IOVA_START_ADDR         (0x1000)
  53
  54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
  55
  56 #define MAX_AGAW_WIDTH 64
  57
  58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
  59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
  60
  61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
  62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
  63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
  64
  65
  66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
  67    are never going to work. */
  68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
  69 {
  70         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
  71 }
  72
  73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
  74 {
  75         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
  76 }
  77 static inline unsigned long page_to_dma_pfn(struct page *pg)
  78 {
  79         return mm_to_dma_pfn(page_to_pfn(pg));
  80 }
  81 static inline unsigned long virt_to_dma_pfn(void *p)
  82 {
  83         return page_to_dma_pfn(virt_to_page(p));
  84 }
  85
  86 /* global iommu list, set NULL for ignored DMAR units */
  87 static struct intel_iommu **g_iommus;
  88
  89 static int rwbf_quirk;
  90
  91 /*
  92  * 0: Present
  93  * 1-11: Reserved
  94  * 12-63: Context Ptr (12 - (haw-1))
  95  * 64-127: Reserved
  96  */
  97 struct root_entry {
  98         u64     val;
  99         u64     rsvd1;
 100 };
 101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
 102 static inline bool root_present(struct root_entry *root)
 103 {
 104         return (root->val & 1);
 105 }
 106 static inline void set_root_present(struct root_entry *root)
 107 {
 108         root->val |= 1;
 109 }
 110 static inline void set_root_value(struct root_entry *root, unsigned long value)
 111 {
 112         root->val |= value & VTD_PAGE_MASK;
 113 }
 114
 115 static inline struct context_entry *
 116 get_context_addr_from_root(struct root_entry *root)
 117 {
 118         return (struct context_entry *)
 119                 (root_present(root)?phys_to_virt(
 120                 root->val & VTD_PAGE_MASK) :
 121                 NULL);
 122 }
 123
 124 /*
 125  * low 64 bits:
 126  * 0: present
 127  * 1: fault processing disable
 128  * 2-3: translation type
 129  * 12-63: address space root
 130  * high 64 bits:
 131  * 0-2: address width
 132  * 3-6: aval
 133  * 8-23: domain id
 134  */
 135 struct context_entry {
 136         u64 lo;
 137         u64 hi;
 138 };
 139
 140 static inline bool context_present(struct context_entry *context)
 141 {
 142         return (context->lo & 1);
 143 }
 144 static inline void context_set_present(struct context_entry *context)
 145 {
 146         context->lo |= 1;
 147 }
 148
 149 static inline void context_set_fault_enable(struct context_entry *context)
 150 {
 151         context->lo &= (((u64)-1) << 2) | 1;
 152 }
 153
 154 static inline void context_set_translation_type(struct context_entry *context,
 155                                                 unsigned long value)
 156 {
 157         context->lo &= (((u64)-1) << 4) | 3;
 158         context->lo |= (value & 3) << 2;
 159 }
 160
 161 static inline void context_set_address_root(struct context_entry *context,
 162                                             unsigned long value)
 163 {
 164         context->lo |= value & VTD_PAGE_MASK;
 165 }
 166
 167 static inline void context_set_address_width(struct context_entry *context,
 168                                              unsigned long value)
 169 {
 170         context->hi |= value & 7;
 171 }
 172
 173 static inline void context_set_domain_id(struct context_entry *context,
 174                                          unsigned long value)
 175 {
 176         context->hi |= (value & ((1 << 16) - 1)) << 8;
 177 }
 178
 179 static inline void context_clear_entry(struct context_entry *context)
 180 {
 181         context->lo = 0;
 182         context->hi = 0;
 183 }
 184
 185 /*
 186  * 0: readable
 187  * 1: writable
 188  * 2-6: reserved
 189  * 7: super page
 190  * 8-10: available
 191  * 11: snoop behavior
 192  * 12-63: Host physcial address
 193  */
 194 struct dma_pte {
 195         u64 val;
 196 };
 197
 198 static inline void dma_clear_pte(struct dma_pte *pte)
 199 {
 200         pte->val = 0;
 201 }
 202
 203 static inline void dma_set_pte_readable(struct dma_pte *pte)
 204 {
 205         pte->val |= DMA_PTE_READ;
 206 }
 207
 208 static inline void dma_set_pte_writable(struct dma_pte *pte)
 209 {
 210         pte->val |= DMA_PTE_WRITE;
 211 }
 212
 213 static inline void dma_set_pte_snp(struct dma_pte *pte)
 214 {
 215         pte->val |= DMA_PTE_SNP;
 216 }
 217
 218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
 219 {
 220         pte->val = (pte->val & ~3) | (prot & 3);
 221 }
 222
 223 static inline u64 dma_pte_addr(struct dma_pte *pte)
 224 {
 225         return (pte->val & VTD_PAGE_MASK);
 226 }
 227
 228 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
 229 {
 230         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
 231 }
 232
 233 static inline bool dma_pte_present(struct dma_pte *pte)
 234 {
 235         return (pte->val & 3) != 0;
 236 }
 237
 238 /*
 239  * This domain is a statically identity mapping domain.
 240  *      1. This domain creats a static 1:1 mapping to all usable memory.
 241  *      2. It maps to each iommu if successful.
 242  *      3. Each iommu mapps to this domain if successful.
 243  */
 244 struct dmar_domain *si_domain;
 245
 246 /* devices under the same p2p bridge are owned in one domain */
 247 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
 248
 249 /* domain represents a virtual machine, more than one devices
 250  * across iommus may be owned in one domain, e.g. kvm guest.
 251  */
 252 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
 253
 254 /* si_domain contains mulitple devices */
 255 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
 256
 257 struct dmar_domain {
 258         int     id;                     /* domain id */
 259         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
 260
 261         struct list_head devices;       /* all devices' list */
 262         struct iova_domain iovad;       /* iova's that belong to this domain */
 263
 264         struct dma_pte  *pgd;           /* virtual address */
 265         spinlock_t      mapping_lock;   /* page table lock */
 266         int             gaw;            /* max guest address width */
 267
 268         /* adjusted guest address width, 0 is level 2 30-bit */
 269         int             agaw;
 270
 271         int             flags;          /* flags to find out type of domain */
 272
 273         int             iommu_coherency;/* indicate coherency of iommu access */
 274         int             iommu_snooping; /* indicate snooping control feature*/
 275         int             iommu_count;    /* reference count of iommu */
 276         spinlock_t      iommu_lock;     /* protect iommu set in domain */
 277         u64             max_addr;       /* maximum mapped address */
 278 };
 279
 280 /* PCI domain-device relationship */
 281 struct device_domain_info {
 282         struct list_head link;  /* link to domain siblings */
 283         struct list_head global; /* link to global list */
 284         int segment;            /* PCI domain */
 285         u8 bus;                 /* PCI bus number */
 286         u8 devfn;               /* PCI devfn number */
 287         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
 288         struct intel_iommu *iommu; /* IOMMU used by this device */
 289         struct dmar_domain *domain; /* pointer to domain */
 290 };
 291
 292 static void flush_unmaps_timeout(unsigned long data);
 293
 294 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
 295
 296 #define HIGH_WATER_MARK 250
 297 struct deferred_flush_tables {
 298         int next;
 299         struct iova *iova[HIGH_WATER_MARK];
 300         struct dmar_domain *domain[HIGH_WATER_MARK];
 301 };
 302
 303 static struct deferred_flush_tables *deferred_flush;
 304
 305 /* bitmap for indexing intel_iommus */
 306 static int g_num_of_iommus;
 307
 308 static DEFINE_SPINLOCK(async_umap_flush_lock);
 309 static LIST_HEAD(unmaps_to_do);
 310
 311 static int timer_on;
 312 static long list_size;
 313
 314 static void domain_remove_dev_info(struct dmar_domain *domain);
 315
 316 #ifdef CONFIG_DMAR_DEFAULT_ON
 317 int dmar_disabled = 0;
 318 #else
 319 int dmar_disabled = 1;
 320 #endif /*CONFIG_DMAR_DEFAULT_ON*/
 321
 322 static int __initdata dmar_map_gfx = 1;
 323 static int dmar_forcedac;
 324 static int intel_iommu_strict;
 325
 326 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
 327 static DEFINE_SPINLOCK(device_domain_lock);
 328 static LIST_HEAD(device_domain_list);
 329
 330 static struct iommu_ops intel_iommu_ops;
 331
 332 static int __init intel_iommu_setup(char *str)
 333 {
 334         if (!str)
 335                 return -EINVAL;
 336         while (*str) {
 337                 if (!strncmp(str, "on", 2)) {
 338                         dmar_disabled = 0;
 339                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
 340                 } else if (!strncmp(str, "off", 3)) {
 341                         dmar_disabled = 1;
 342                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
 343                 } else if (!strncmp(str, "igfx_off", 8)) {
 344                         dmar_map_gfx = 0;
 345                         printk(KERN_INFO
 346                                 "Intel-IOMMU: disable GFX device mapping\n");
 347                 } else if (!strncmp(str, "forcedac", 8)) {
 348                         printk(KERN_INFO
 349                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
 350                         dmar_forcedac = 1;
 351                 } else if (!strncmp(str, "strict", 6)) {
 352                         printk(KERN_INFO
 353                                 "Intel-IOMMU: disable batched IOTLB flush\n");
 354                         intel_iommu_strict = 1;
 355                 }
 356
 357                 str += strcspn(str, ",");
 358                 while (*str == ',')
 359                         str++;
 360         }
 361         return 0;
 362 }
 363 __setup("intel_iommu=", intel_iommu_setup);
 364
 365 static struct kmem_cache *iommu_domain_cache;
 366 static struct kmem_cache *iommu_devinfo_cache;
 367 static struct kmem_cache *iommu_iova_cache;
 368
 369 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
 370 {
 371         unsigned int flags;
 372         void *vaddr;
 373
 374         /* trying to avoid low memory issues */
 375         flags = current->flags & PF_MEMALLOC;
 376         current->flags |= PF_MEMALLOC;
 377         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
 378         current->flags &= (~PF_MEMALLOC | flags);
 379         return vaddr;
 380 }
 381
 382
 383 static inline void *alloc_pgtable_page(void)
 384 {
 385         unsigned int flags;
 386         void *vaddr;
 387
 388         /* trying to avoid low memory issues */
 389         flags = current->flags & PF_MEMALLOC;
 390         current->flags |= PF_MEMALLOC;
 391         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
 392         current->flags &= (~PF_MEMALLOC | flags);
 393         return vaddr;
 394 }
 395
 396 static inline void free_pgtable_page(void *vaddr)
 397 {
 398         free_page((unsigned long)vaddr);
 399 }
 400
 401 static inline void *alloc_domain_mem(void)
 402 {
 403         return iommu_kmem_cache_alloc(iommu_domain_cache);
 404 }
 405
 406 static void free_domain_mem(void *vaddr)
 407 {
 408         kmem_cache_free(iommu_domain_cache, vaddr);
 409 }
 410
 411 static inline void * alloc_devinfo_mem(void)
 412 {
 413         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
 414 }
 415
 416 static inline void free_devinfo_mem(void *vaddr)
 417 {
 418         kmem_cache_free(iommu_devinfo_cache, vaddr);
 419 }
 420
 421 struct iova *alloc_iova_mem(void)
 422 {
 423         return iommu_kmem_cache_alloc(iommu_iova_cache);
 424 }
 425
 426 void free_iova_mem(struct iova *iova)
 427 {
 428         kmem_cache_free(iommu_iova_cache, iova);
 429 }
 430
 431
 432 static inline int width_to_agaw(int width);
 433
 434 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
 435 {
 436         unsigned long sagaw;
 437         int agaw = -1;
 438
 439         sagaw = cap_sagaw(iommu->cap);
 440         for (agaw = width_to_agaw(max_gaw);
 441              agaw >= 0; agaw--) {
 442                 if (test_bit(agaw, &sagaw))
 443                         break;
 444         }
 445
 446         return agaw;
 447 }
 448
 449 /*
 450  * Calculate max SAGAW for each iommu.
 451  */
 452 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
 453 {
 454         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
 455 }
 456
 457 /*
 458  * calculate agaw for each iommu.
 459  * "SAGAW" may be different across iommus, use a default agaw, and
 460  * get a supported less agaw for iommus that don't support the default agaw.
 461  */
 462 int iommu_calculate_agaw(struct intel_iommu *iommu)
 463 {
 464         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
 465 }
 466
 467 /* This functionin only returns single iommu in a domain */
 468 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
 469 {
 470         int iommu_id;
 471
 472         /* si_domain and vm domain should not get here. */
 473         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
 474         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
 475
 476         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 477         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
 478                 return NULL;
 479
 480         return g_iommus[iommu_id];
 481 }
 482
 483 static void domain_update_iommu_coherency(struct dmar_domain *domain)
 484 {
 485         int i;
 486
 487         domain->iommu_coherency = 1;
 488
 489         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 490         for (; i < g_num_of_iommus; ) {
 491                 if (!ecap_coherent(g_iommus[i]->ecap)) {
 492                         domain->iommu_coherency = 0;
 493                         break;
 494                 }
 495                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 496         }
 497 }
 498
 499 static void domain_update_iommu_snooping(struct dmar_domain *domain)
 500 {
 501         int i;
 502
 503         domain->iommu_snooping = 1;
 504
 505         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 506         for (; i < g_num_of_iommus; ) {
 507                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
 508                         domain->iommu_snooping = 0;
 509                         break;
 510                 }
 511                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 512         }
 513 }
 514
 515 /* Some capabilities may be different across iommus */
 516 static void domain_update_iommu_cap(struct dmar_domain *domain)
 517 {
 518         domain_update_iommu_coherency(domain);
 519         domain_update_iommu_snooping(domain);
 520 }
 521
 522 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
 523 {
 524         struct dmar_drhd_unit *drhd = NULL;
 525         int i;
 526
 527         for_each_drhd_unit(drhd) {
 528                 if (drhd->ignored)
 529                         continue;
 530                 if (segment != drhd->segment)
 531                         continue;
 532
 533                 for (i = 0; i < drhd->devices_cnt; i++) {
 534                         if (drhd->devices[i] &&
 535                             drhd->devices[i]->bus->number == bus &&
 536                             drhd->devices[i]->devfn == devfn)
 537                                 return drhd->iommu;
 538                         if (drhd->devices[i] &&
 539                             drhd->devices[i]->subordinate &&
 540                             drhd->devices[i]->subordinate->number <= bus &&
 541                             drhd->devices[i]->subordinate->subordinate >= bus)
 542                                 return drhd->iommu;
 543                 }
 544
 545                 if (drhd->include_all)
 546                         return drhd->iommu;
 547         }
 548
 549         return NULL;
 550 }
 551
 552 static void domain_flush_cache(struct dmar_domain *domain,
 553                                void *addr, int size)
 554 {
 555         if (!domain->iommu_coherency)
 556                 clflush_cache_range(addr, size);
 557 }
 558
 559 /* Gets context entry for a given bus and devfn */
 560 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
 561                 u8 bus, u8 devfn)
 562 {
 563         struct root_entry *root;
 564         struct context_entry *context;
 565         unsigned long phy_addr;
 566         unsigned long flags;
 567
 568         spin_lock_irqsave(&iommu->lock, flags);
 569         root = &iommu->root_entry[bus];
 570         context = get_context_addr_from_root(root);
 571         if (!context) {
 572                 context = (struct context_entry *)alloc_pgtable_page();
 573                 if (!context) {
 574                         spin_unlock_irqrestore(&iommu->lock, flags);
 575                         return NULL;
 576                 }
 577                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
 578                 phy_addr = virt_to_phys((void *)context);
 579                 set_root_value(root, phy_addr);
 580                 set_root_present(root);
 581                 __iommu_flush_cache(iommu, root, sizeof(*root));
 582         }
 583         spin_unlock_irqrestore(&iommu->lock, flags);
 584         return &context[devfn];
 585 }
 586
 587 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
 588 {
 589         struct root_entry *root;
 590         struct context_entry *context;
 591         int ret;
 592         unsigned long flags;
 593
 594         spin_lock_irqsave(&iommu->lock, flags);
 595         root = &iommu->root_entry[bus];
 596         context = get_context_addr_from_root(root);
 597         if (!context) {
 598                 ret = 0;
 599                 goto out;
 600         }
 601         ret = context_present(&context[devfn]);
 602 out:
 603         spin_unlock_irqrestore(&iommu->lock, flags);
 604         return ret;
 605 }
 606
 607 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
 608 {
 609         struct root_entry *root;
 610         struct context_entry *context;
 611         unsigned long flags;
 612
 613         spin_lock_irqsave(&iommu->lock, flags);
 614         root = &iommu->root_entry[bus];
 615         context = get_context_addr_from_root(root);
 616         if (context) {
 617                 context_clear_entry(&context[devfn]);
 618                 __iommu_flush_cache(iommu, &context[devfn], \
 619                         sizeof(*context));
 620         }
 621         spin_unlock_irqrestore(&iommu->lock, flags);
 622 }
 623
 624 static void free_context_table(struct intel_iommu *iommu)
 625 {
 626         struct root_entry *root;
 627         int i;
 628         unsigned long flags;
 629         struct context_entry *context;
 630
 631         spin_lock_irqsave(&iommu->lock, flags);
 632         if (!iommu->root_entry) {
 633                 goto out;
 634         }
 635         for (i = 0; i < ROOT_ENTRY_NR; i++) {
 636                 root = &iommu->root_entry[i];
 637                 context = get_context_addr_from_root(root);
 638                 if (context)
 639                         free_pgtable_page(context);
 640         }
 641         free_pgtable_page(iommu->root_entry);
 642         iommu->root_entry = NULL;
 643 out:
 644         spin_unlock_irqrestore(&iommu->lock, flags);
 645 }
 646
 647 /* page table handling */
 648 #define LEVEL_STRIDE            (9)
 649 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
 650
 651 static inline int agaw_to_level(int agaw)
 652 {
 653         return agaw + 2;
 654 }
 655
 656 static inline int agaw_to_width(int agaw)
 657 {
 658         return 30 + agaw * LEVEL_STRIDE;
 659
 660 }
 661
 662 static inline int width_to_agaw(int width)
 663 {
 664         return (width - 30) / LEVEL_STRIDE;
 665 }
 666
 667 static inline unsigned int level_to_offset_bits(int level)
 668 {
 669         return (level - 1) * LEVEL_STRIDE;
 670 }
 671
 672 static inline int pfn_level_offset(unsigned long pfn, int level)
 673 {
 674         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
 675 }
 676
 677 static inline unsigned long level_mask(int level)
 678 {
 679         return -1UL << level_to_offset_bits(level);
 680 }
 681
 682 static inline unsigned long level_size(int level)
 683 {
 684         return 1UL << level_to_offset_bits(level);
 685 }
 686
 687 static inline unsigned long align_to_level(unsigned long pfn, int level)
 688 {
 689         return (pfn + level_size(level) - 1) & level_mask(level);
 690 }
 691
 692 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
 693                                       unsigned long pfn)
 694 {
 695         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 696         struct dma_pte *parent, *pte = NULL;
 697         int level = agaw_to_level(domain->agaw);
 698         int offset;
 699         unsigned long flags;
 700
 701         BUG_ON(!domain->pgd);
 702         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
 703         parent = domain->pgd;
 704
 705         spin_lock_irqsave(&domain->mapping_lock, flags);
 706         while (level > 0) {
 707                 void *tmp_page;
 708
 709                 offset = pfn_level_offset(pfn, level);
 710                 pte = &parent[offset];
 711                 if (level == 1)
 712                         break;
 713
 714                 if (!dma_pte_present(pte)) {
 715                         tmp_page = alloc_pgtable_page();
 716
 717                         if (!tmp_page) {
 718                                 spin_unlock_irqrestore(&domain->mapping_lock,
 719                                         flags);
 720                                 return NULL;
 721                         }
 722                         domain_flush_cache(domain, tmp_page, PAGE_SIZE);
 723                         dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page));
 724                         /*
 725                          * high level table always sets r/w, last level page
 726                          * table control read/write
 727                          */
 728                         dma_set_pte_readable(pte);
 729                         dma_set_pte_writable(pte);
 730                         domain_flush_cache(domain, pte, sizeof(*pte));
 731                 }
 732                 parent = phys_to_virt(dma_pte_addr(pte));
 733                 level--;
 734         }
 735
 736         spin_unlock_irqrestore(&domain->mapping_lock, flags);
 737         return pte;
 738 }
 739
 740 /* return address's pte at specific level */
 741 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
 742                                          unsigned long pfn,
 743                                          int level)
 744 {
 745         struct dma_pte *parent, *pte = NULL;
 746         int total = agaw_to_level(domain->agaw);
 747         int offset;
 748
 749         parent = domain->pgd;
 750         while (level <= total) {
 751                 offset = pfn_level_offset(pfn, total);
 752                 pte = &parent[offset];
 753                 if (level == total)
 754                         return pte;
 755
 756                 if (!dma_pte_present(pte))
 757                         break;
 758                 parent = phys_to_virt(dma_pte_addr(pte));
 759                 total--;
 760         }
 761         return NULL;
 762 }
 763
 764 /* clear last level pte, a tlb flush should be followed */
 765 static void dma_pte_clear_range(struct dmar_domain *domain,
 766                                 unsigned long start_pfn,
 767                                 unsigned long last_pfn)
 768 {
 769         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 770         struct dma_pte *first_pte, *pte;
 771
 772         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
 773         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
 774
 775         /* we don't need lock here; nobody else touches the iova range */
 776         while (start_pfn <= last_pfn) {
 777                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
 778                 if (!pte) {
 779                         start_pfn = align_to_level(start_pfn + 1, 2);
 780                         continue;
 781                 }
 782                 while (start_pfn <= last_pfn &&
 783                        (unsigned long)pte >> VTD_PAGE_SHIFT ==
 784                        (unsigned long)first_pte >> VTD_PAGE_SHIFT) {
 785                         dma_clear_pte(pte);
 786                         start_pfn++;
 787                         pte++;
 788                 }
 789                 domain_flush_cache(domain, first_pte,
 790                                    (void *)pte - (void *)first_pte);
 791         }
 792 }
 793
 794 /* free page table pages. last level pte should already be cleared */
 795 static void dma_pte_free_pagetable(struct dmar_domain *domain,
 796                                    unsigned long start_pfn,
 797                                    unsigned long last_pfn)
 798 {
 799         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 800         struct dma_pte *pte;
 801         int total = agaw_to_level(domain->agaw);
 802         int level;
 803         unsigned long tmp;
 804
 805         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
 806         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
 807
 808         /* we don't need lock here, nobody else touches the iova range */
 809         level = 2;
 810         while (level <= total) {
 811                 tmp = align_to_level(start_pfn, level);
 812
 813                 /* Only clear this pte/pmd if we're asked to clear its
 814                    _whole_ range */
 815                 if (tmp + level_size(level) - 1 > last_pfn)
 816                         return;
 817
 818                 while (tmp <= last_pfn) {
 819                         pte = dma_pfn_level_pte(domain, tmp, level);
 820                         if (pte) {
 821                                 free_pgtable_page(
 822                                         phys_to_virt(dma_pte_addr(pte)));
 823                                 dma_clear_pte(pte);
 824                                 domain_flush_cache(domain, pte, sizeof(*pte));
 825                         }
 826                         tmp += level_size(level);
 827                 }
 828                 level++;
 829         }
 830         /* free pgd */
 831         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
 832                 free_pgtable_page(domain->pgd);
 833                 domain->pgd = NULL;
 834         }
 835 }
 836
 837 /* iommu handling */
 838 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
 839 {
 840         struct root_entry *root;
 841         unsigned long flags;
 842
 843         root = (struct root_entry *)alloc_pgtable_page();
 844         if (!root)
 845                 return -ENOMEM;
 846
 847         __iommu_flush_cache(iommu, root, ROOT_SIZE);
 848
 849         spin_lock_irqsave(&iommu->lock, flags);
 850         iommu->root_entry = root;
 851         spin_unlock_irqrestore(&iommu->lock, flags);
 852
 853         return 0;
 854 }
 855
 856 static void iommu_set_root_entry(struct intel_iommu *iommu)
 857 {
 858         void *addr;
 859         u32 sts;
 860         unsigned long flag;
 861
 862         addr = iommu->root_entry;
 863
 864         spin_lock_irqsave(&iommu->register_lock, flag);
 865         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 866
 867         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
 868
 869         /* Make sure hardware complete it */
 870         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 871                       readl, (sts & DMA_GSTS_RTPS), sts);
 872
 873         spin_unlock_irqrestore(&iommu->register_lock, flag);
 874 }
 875
 876 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
 877 {
 878         u32 val;
 879         unsigned long flag;
 880
 881         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
 882                 return;
 883
 884         spin_lock_irqsave(&iommu->register_lock, flag);
 885         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 886
 887         /* Make sure hardware complete it */
 888         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 889                       readl, (!(val & DMA_GSTS_WBFS)), val);
 890
 891         spin_unlock_irqrestore(&iommu->register_lock, flag);
 892 }
 893
 894 /* return value determine if we need a write buffer flush */
 895 static void __iommu_flush_context(struct intel_iommu *iommu,
 896                                   u16 did, u16 source_id, u8 function_mask,
 897                                   u64 type)
 898 {
 899         u64 val = 0;
 900         unsigned long flag;
 901
 902         switch (type) {
 903         case DMA_CCMD_GLOBAL_INVL:
 904                 val = DMA_CCMD_GLOBAL_INVL;
 905                 break;
 906         case DMA_CCMD_DOMAIN_INVL:
 907                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
 908                 break;
 909         case DMA_CCMD_DEVICE_INVL:
 910                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
 911                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
 912                 break;
 913         default:
 914                 BUG();
 915         }
 916         val |= DMA_CCMD_ICC;
 917
 918         spin_lock_irqsave(&iommu->register_lock, flag);
 919         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 920
 921         /* Make sure hardware complete it */
 922         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
 923                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 924
 925         spin_unlock_irqrestore(&iommu->register_lock, flag);
 926 }
 927
 928 /* return value determine if we need a write buffer flush */
 929 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
 930                                 u64 addr, unsigned int size_order, u64 type)
 931 {
 932         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
 933         u64 val = 0, val_iva = 0;
 934         unsigned long flag;
 935
 936         switch (type) {
 937         case DMA_TLB_GLOBAL_FLUSH:
 938                 /* global flush doesn't need set IVA_REG */
 939                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
 940                 break;
 941         case DMA_TLB_DSI_FLUSH:
 942                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 943                 break;
 944         case DMA_TLB_PSI_FLUSH:
 945                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 946                 /* Note: always flush non-leaf currently */
 947                 val_iva = size_order | addr;
 948                 break;
 949         default:
 950                 BUG();
 951         }
 952         /* Note: set drain read/write */
 953 #if 0
 954         /*
 955          * This is probably to be super secure.. Looks like we can
 956          * ignore it without any impact.
 957          */
 958         if (cap_read_drain(iommu->cap))
 959                 val |= DMA_TLB_READ_DRAIN;
 960 #endif
 961         if (cap_write_drain(iommu->cap))
 962                 val |= DMA_TLB_WRITE_DRAIN;
 963
 964         spin_lock_irqsave(&iommu->register_lock, flag);
 965         /* Note: Only uses first TLB reg currently */
 966         if (val_iva)
 967                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
 968         dmar_writeq(iommu->reg + tlb_offset + 8, val);
 969
 970         /* Make sure hardware complete it */
 971         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
 972                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
 973
 974         spin_unlock_irqrestore(&iommu->register_lock, flag);
 975
 976         /* check IOTLB invalidation granularity */
 977         if (DMA_TLB_IAIG(val) == 0)
 978                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
 979         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
 980                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
 981                         (unsigned long long)DMA_TLB_IIRG(type),
 982                         (unsigned long long)DMA_TLB_IAIG(val));
 983 }
 984
 985 static struct device_domain_info *iommu_support_dev_iotlb(
 986         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
 987 {
 988         int found = 0;
 989         unsigned long flags;
 990         struct device_domain_info *info;
 991         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
 992
 993         if (!ecap_dev_iotlb_support(iommu->ecap))
 994                 return NULL;
 995
 996         if (!iommu->qi)
 997                 return NULL;
 998
 999         spin_lock_irqsave(&device_domain_lock, flags);
1000         list_for_each_entry(info, &domain->devices, link)
1001                 if (info->bus == bus && info->devfn == devfn) {
1002                         found = 1;
1003                         break;
1004                 }
1005         spin_unlock_irqrestore(&device_domain_lock, flags);
1006
1007         if (!found || !info->dev)
1008                 return NULL;
1009
1010         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1011                 return NULL;
1012
1013         if (!dmar_find_matched_atsr_unit(info->dev))
1014                 return NULL;
1015
1016         info->iommu = iommu;
1017
1018         return info;
1019 }
1020
1021 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1022 {
1023         if (!info)
1024                 return;
1025
1026         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1027 }
1028
1029 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1030 {
1031         if (!info->dev || !pci_ats_enabled(info->dev))
1032                 return;
1033
1034         pci_disable_ats(info->dev);
1035 }
1036
1037 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1038                                   u64 addr, unsigned mask)
1039 {
1040         u16 sid, qdep;
1041         unsigned long flags;
1042         struct device_domain_info *info;
1043
1044         spin_lock_irqsave(&device_domain_lock, flags);
1045         list_for_each_entry(info, &domain->devices, link) {
1046                 if (!info->dev || !pci_ats_enabled(info->dev))
1047                         continue;
1048
1049                 sid = info->bus << 8 | info->devfn;
1050                 qdep = pci_ats_queue_depth(info->dev);
1051                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1052         }
1053         spin_unlock_irqrestore(&device_domain_lock, flags);
1054 }
1055
1056 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1057                                   unsigned long pfn, unsigned int pages)
1058 {
1059         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1060         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1061
1062         BUG_ON(pages == 0);
1063
1064         /*
1065          * Fallback to domain selective flush if no PSI support or the size is
1066          * too big.
1067          * PSI requires page size to be 2 ^ x, and the base address is naturally
1068          * aligned to the size
1069          */
1070         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1071                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1072                                                 DMA_TLB_DSI_FLUSH);
1073         else
1074                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1075                                                 DMA_TLB_PSI_FLUSH);
1076
1077         /*
1078          * In caching mode, domain ID 0 is reserved for non-present to present
1079          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1080          */
1081         if (!cap_caching_mode(iommu->cap) || did)
1082                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1083 }
1084
1085 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1086 {
1087         u32 pmen;
1088         unsigned long flags;
1089
1090         spin_lock_irqsave(&iommu->register_lock, flags);
1091         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1092         pmen &= ~DMA_PMEN_EPM;
1093         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1094
1095         /* wait for the protected region status bit to clear */
1096         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1097                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1098
1099         spin_unlock_irqrestore(&iommu->register_lock, flags);
1100 }
1101
1102 static int iommu_enable_translation(struct intel_iommu *iommu)
1103 {
1104         u32 sts;
1105         unsigned long flags;
1106
1107         spin_lock_irqsave(&iommu->register_lock, flags);
1108         iommu->gcmd |= DMA_GCMD_TE;
1109         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1110
1111         /* Make sure hardware complete it */
1112         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1113                       readl, (sts & DMA_GSTS_TES), sts);
1114
1115         spin_unlock_irqrestore(&iommu->register_lock, flags);
1116         return 0;
1117 }
1118
1119 static int iommu_disable_translation(struct intel_iommu *iommu)
1120 {
1121         u32 sts;
1122         unsigned long flag;
1123
1124         spin_lock_irqsave(&iommu->register_lock, flag);
1125         iommu->gcmd &= ~DMA_GCMD_TE;
1126         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1127
1128         /* Make sure hardware complete it */
1129         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1130                       readl, (!(sts & DMA_GSTS_TES)), sts);
1131
1132         spin_unlock_irqrestore(&iommu->register_lock, flag);
1133         return 0;
1134 }
1135
1136
1137 static int iommu_init_domains(struct intel_iommu *iommu)
1138 {
1139         unsigned long ndomains;
1140         unsigned long nlongs;
1141
1142         ndomains = cap_ndoms(iommu->cap);
1143         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1144         nlongs = BITS_TO_LONGS(ndomains);
1145
1146         /* TBD: there might be 64K domains,
1147          * consider other allocation for future chip
1148          */
1149         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1150         if (!iommu->domain_ids) {
1151                 printk(KERN_ERR "Allocating domain id array failed\n");
1152                 return -ENOMEM;
1153         }
1154         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1155                         GFP_KERNEL);
1156         if (!iommu->domains) {
1157                 printk(KERN_ERR "Allocating domain array failed\n");
1158                 kfree(iommu->domain_ids);
1159                 return -ENOMEM;
1160         }
1161
1162         spin_lock_init(&iommu->lock);
1163
1164         /*
1165          * if Caching mode is set, then invalid translations are tagged
1166          * with domainid 0. Hence we need to pre-allocate it.
1167          */
1168         if (cap_caching_mode(iommu->cap))
1169                 set_bit(0, iommu->domain_ids);
1170         return 0;
1171 }
1172
1173
1174 static void domain_exit(struct dmar_domain *domain);
1175 static void vm_domain_exit(struct dmar_domain *domain);
1176
1177 void free_dmar_iommu(struct intel_iommu *iommu)
1178 {
1179         struct dmar_domain *domain;
1180         int i;
1181         unsigned long flags;
1182
1183         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1184         for (; i < cap_ndoms(iommu->cap); ) {
1185                 domain = iommu->domains[i];
1186                 clear_bit(i, iommu->domain_ids);
1187
1188                 spin_lock_irqsave(&domain->iommu_lock, flags);
1189                 if (--domain->iommu_count == 0) {
1190                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1191                                 vm_domain_exit(domain);
1192                         else
1193                                 domain_exit(domain);
1194                 }
1195                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1196
1197                 i = find_next_bit(iommu->domain_ids,
1198                         cap_ndoms(iommu->cap), i+1);
1199         }
1200
1201         if (iommu->gcmd & DMA_GCMD_TE)
1202                 iommu_disable_translation(iommu);
1203
1204         if (iommu->irq) {
1205                 set_irq_data(iommu->irq, NULL);
1206                 /* This will mask the irq */
1207                 free_irq(iommu->irq, iommu);
1208                 destroy_irq(iommu->irq);
1209         }
1210
1211         kfree(iommu->domains);
1212         kfree(iommu->domain_ids);
1213
1214         g_iommus[iommu->seq_id] = NULL;
1215
1216         /* if all iommus are freed, free g_iommus */
1217         for (i = 0; i < g_num_of_iommus; i++) {
1218                 if (g_iommus[i])
1219                         break;
1220         }
1221
1222         if (i == g_num_of_iommus)
1223                 kfree(g_iommus);
1224
1225         /* free context mapping */
1226         free_context_table(iommu);
1227 }
1228
1229 static struct dmar_domain *alloc_domain(void)
1230 {
1231         struct dmar_domain *domain;
1232
1233         domain = alloc_domain_mem();
1234         if (!domain)
1235                 return NULL;
1236
1237         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1238         domain->flags = 0;
1239
1240         return domain;
1241 }
1242
1243 static int iommu_attach_domain(struct dmar_domain *domain,
1244                                struct intel_iommu *iommu)
1245 {
1246         int num;
1247         unsigned long ndomains;
1248         unsigned long flags;
1249
1250         ndomains = cap_ndoms(iommu->cap);
1251
1252         spin_lock_irqsave(&iommu->lock, flags);
1253
1254         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1255         if (num >= ndomains) {
1256                 spin_unlock_irqrestore(&iommu->lock, flags);
1257                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1258                 return -ENOMEM;
1259         }
1260
1261         domain->id = num;
1262         set_bit(num, iommu->domain_ids);
1263         set_bit(iommu->seq_id, &domain->iommu_bmp);
1264         iommu->domains[num] = domain;
1265         spin_unlock_irqrestore(&iommu->lock, flags);
1266
1267         return 0;
1268 }
1269
1270 static void iommu_detach_domain(struct dmar_domain *domain,
1271                                 struct intel_iommu *iommu)
1272 {
1273         unsigned long flags;
1274         int num, ndomains;
1275         int found = 0;
1276
1277         spin_lock_irqsave(&iommu->lock, flags);
1278         ndomains = cap_ndoms(iommu->cap);
1279         num = find_first_bit(iommu->domain_ids, ndomains);
1280         for (; num < ndomains; ) {
1281                 if (iommu->domains[num] == domain) {
1282                         found = 1;
1283                         break;
1284                 }
1285                 num = find_next_bit(iommu->domain_ids,
1286                                     cap_ndoms(iommu->cap), num+1);
1287         }
1288
1289         if (found) {
1290                 clear_bit(num, iommu->domain_ids);
1291                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1292                 iommu->domains[num] = NULL;
1293         }
1294         spin_unlock_irqrestore(&iommu->lock, flags);
1295 }
1296
1297 static struct iova_domain reserved_iova_list;
1298 static struct lock_class_key reserved_alloc_key;
1299 static struct lock_class_key reserved_rbtree_key;
1300
1301 static void dmar_init_reserved_ranges(void)
1302 {
1303         struct pci_dev *pdev = NULL;
1304         struct iova *iova;
1305         int i;
1306
1307         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1308
1309         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1310                 &reserved_alloc_key);
1311         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1312                 &reserved_rbtree_key);
1313
1314         /* IOAPIC ranges shouldn't be accessed by DMA */
1315         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1316                 IOVA_PFN(IOAPIC_RANGE_END));
1317         if (!iova)
1318                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1319
1320         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1321         for_each_pci_dev(pdev) {
1322                 struct resource *r;
1323
1324                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1325                         r = &pdev->resource[i];
1326                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1327                                 continue;
1328                         iova = reserve_iova(&reserved_iova_list,
1329                                             IOVA_PFN(r->start),
1330                                             IOVA_PFN(r->end));
1331                         if (!iova)
1332                                 printk(KERN_ERR "Reserve iova failed\n");
1333                 }
1334         }
1335
1336 }
1337
1338 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1339 {
1340         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1341 }
1342
1343 static inline int guestwidth_to_adjustwidth(int gaw)
1344 {
1345         int agaw;
1346         int r = (gaw - 12) % 9;
1347
1348         if (r == 0)
1349                 agaw = gaw;
1350         else
1351                 agaw = gaw + 9 - r;
1352         if (agaw > 64)
1353                 agaw = 64;
1354         return agaw;
1355 }
1356
1357 static int domain_init(struct dmar_domain *domain, int guest_width)
1358 {
1359         struct intel_iommu *iommu;
1360         int adjust_width, agaw;
1361         unsigned long sagaw;
1362
1363         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1364         spin_lock_init(&domain->mapping_lock);
1365         spin_lock_init(&domain->iommu_lock);
1366
1367         domain_reserve_special_ranges(domain);
1368
1369         /* calculate AGAW */
1370         iommu = domain_get_iommu(domain);
1371         if (guest_width > cap_mgaw(iommu->cap))
1372                 guest_width = cap_mgaw(iommu->cap);
1373         domain->gaw = guest_width;
1374         adjust_width = guestwidth_to_adjustwidth(guest_width);
1375         agaw = width_to_agaw(adjust_width);
1376         sagaw = cap_sagaw(iommu->cap);
1377         if (!test_bit(agaw, &sagaw)) {
1378                 /* hardware doesn't support it, choose a bigger one */
1379                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1380                 agaw = find_next_bit(&sagaw, 5, agaw);
1381                 if (agaw >= 5)
1382                         return -ENODEV;
1383         }
1384         domain->agaw = agaw;
1385         INIT_LIST_HEAD(&domain->devices);
1386
1387         if (ecap_coherent(iommu->ecap))
1388                 domain->iommu_coherency = 1;
1389         else
1390                 domain->iommu_coherency = 0;
1391
1392         if (ecap_sc_support(iommu->ecap))
1393                 domain->iommu_snooping = 1;
1394         else
1395                 domain->iommu_snooping = 0;
1396
1397         domain->iommu_count = 1;
1398
1399         /* always allocate the top pgd */
1400         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1401         if (!domain->pgd)
1402                 return -ENOMEM;
1403         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1404         return 0;
1405 }
1406
1407 static void domain_exit(struct dmar_domain *domain)
1408 {
1409         struct dmar_drhd_unit *drhd;
1410         struct intel_iommu *iommu;
1411
1412         /* Domain 0 is reserved, so dont process it */
1413         if (!domain)
1414                 return;
1415
1416         domain_remove_dev_info(domain);
1417         /* destroy iovas */
1418         put_iova_domain(&domain->iovad);
1419
1420         /* clear ptes */
1421         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1422
1423         /* free page tables */
1424         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1425
1426         for_each_active_iommu(iommu, drhd)
1427                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1428                         iommu_detach_domain(domain, iommu);
1429
1430         free_domain_mem(domain);
1431 }
1432
1433 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1434                                  u8 bus, u8 devfn, int translation)
1435 {
1436         struct context_entry *context;
1437         unsigned long flags;
1438         struct intel_iommu *iommu;
1439         struct dma_pte *pgd;
1440         unsigned long num;
1441         unsigned long ndomains;
1442         int id;
1443         int agaw;
1444         struct device_domain_info *info = NULL;
1445
1446         pr_debug("Set context mapping for %02x:%02x.%d\n",
1447                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1448
1449         BUG_ON(!domain->pgd);
1450         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1451                translation != CONTEXT_TT_MULTI_LEVEL);
1452
1453         iommu = device_to_iommu(segment, bus, devfn);
1454         if (!iommu)
1455                 return -ENODEV;
1456
1457         context = device_to_context_entry(iommu, bus, devfn);
1458         if (!context)
1459                 return -ENOMEM;
1460         spin_lock_irqsave(&iommu->lock, flags);
1461         if (context_present(context)) {
1462                 spin_unlock_irqrestore(&iommu->lock, flags);
1463                 return 0;
1464         }
1465
1466         id = domain->id;
1467         pgd = domain->pgd;
1468
1469         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1470             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1471                 int found = 0;
1472
1473                 /* find an available domain id for this device in iommu */
1474                 ndomains = cap_ndoms(iommu->cap);
1475                 num = find_first_bit(iommu->domain_ids, ndomains);
1476                 for (; num < ndomains; ) {
1477                         if (iommu->domains[num] == domain) {
1478                                 id = num;
1479                                 found = 1;
1480                                 break;
1481                         }
1482                         num = find_next_bit(iommu->domain_ids,
1483                                             cap_ndoms(iommu->cap), num+1);
1484                 }
1485
1486                 if (found == 0) {
1487                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1488                         if (num >= ndomains) {
1489                                 spin_unlock_irqrestore(&iommu->lock, flags);
1490                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1491                                 return -EFAULT;
1492                         }
1493
1494                         set_bit(num, iommu->domain_ids);
1495                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1496                         iommu->domains[num] = domain;
1497                         id = num;
1498                 }
1499
1500                 /* Skip top levels of page tables for
1501                  * iommu which has less agaw than default.
1502                  */
1503                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1504                         pgd = phys_to_virt(dma_pte_addr(pgd));
1505                         if (!dma_pte_present(pgd)) {
1506                                 spin_unlock_irqrestore(&iommu->lock, flags);
1507                                 return -ENOMEM;
1508                         }
1509                 }
1510         }
1511
1512         context_set_domain_id(context, id);
1513
1514         if (translation != CONTEXT_TT_PASS_THROUGH) {
1515                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1516                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1517                                      CONTEXT_TT_MULTI_LEVEL;
1518         }
1519         /*
1520          * In pass through mode, AW must be programmed to indicate the largest
1521          * AGAW value supported by hardware. And ASR is ignored by hardware.
1522          */
1523         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1524                 context_set_address_width(context, iommu->msagaw);
1525         else {
1526                 context_set_address_root(context, virt_to_phys(pgd));
1527                 context_set_address_width(context, iommu->agaw);
1528         }
1529
1530         context_set_translation_type(context, translation);
1531         context_set_fault_enable(context);
1532         context_set_present(context);
1533         domain_flush_cache(domain, context, sizeof(*context));
1534
1535         /*
1536          * It's a non-present to present mapping. If hardware doesn't cache
1537          * non-present entry we only need to flush the write-buffer. If the
1538          * _does_ cache non-present entries, then it does so in the special
1539          * domain #0, which we have to flush:
1540          */
1541         if (cap_caching_mode(iommu->cap)) {
1542                 iommu->flush.flush_context(iommu, 0,
1543                                            (((u16)bus) << 8) | devfn,
1544                                            DMA_CCMD_MASK_NOBIT,
1545                                            DMA_CCMD_DEVICE_INVL);
1546                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1547         } else {
1548                 iommu_flush_write_buffer(iommu);
1549         }
1550         iommu_enable_dev_iotlb(info);
1551         spin_unlock_irqrestore(&iommu->lock, flags);
1552
1553         spin_lock_irqsave(&domain->iommu_lock, flags);
1554         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1555                 domain->iommu_count++;
1556                 domain_update_iommu_cap(domain);
1557         }
1558         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1559         return 0;
1560 }
1561
1562 static int
1563 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1564                         int translation)
1565 {
1566         int ret;
1567         struct pci_dev *tmp, *parent;
1568
1569         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1570                                          pdev->bus->number, pdev->devfn,
1571                                          translation);
1572         if (ret)
1573                 return ret;
1574
1575         /* dependent device mapping */
1576         tmp = pci_find_upstream_pcie_bridge(pdev);
1577         if (!tmp)
1578                 return 0;
1579         /* Secondary interface's bus number and devfn 0 */
1580         parent = pdev->bus->self;
1581         while (parent != tmp) {
1582                 ret = domain_context_mapping_one(domain,
1583                                                  pci_domain_nr(parent->bus),
1584                                                  parent->bus->number,
1585                                                  parent->devfn, translation);
1586                 if (ret)
1587                         return ret;
1588                 parent = parent->bus->self;
1589         }
1590         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1591                 return domain_context_mapping_one(domain,
1592                                         pci_domain_nr(tmp->subordinate),
1593                                         tmp->subordinate->number, 0,
1594                                         translation);
1595         else /* this is a legacy PCI bridge */
1596                 return domain_context_mapping_one(domain,
1597                                                   pci_domain_nr(tmp->bus),
1598                                                   tmp->bus->number,
1599                                                   tmp->devfn,
1600                                                   translation);
1601 }
1602
1603 static int domain_context_mapped(struct pci_dev *pdev)
1604 {
1605         int ret;
1606         struct pci_dev *tmp, *parent;
1607         struct intel_iommu *iommu;
1608
1609         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1610                                 pdev->devfn);
1611         if (!iommu)
1612                 return -ENODEV;
1613
1614         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1615         if (!ret)
1616                 return ret;
1617         /* dependent device mapping */
1618         tmp = pci_find_upstream_pcie_bridge(pdev);
1619         if (!tmp)
1620                 return ret;
1621         /* Secondary interface's bus number and devfn 0 */
1622         parent = pdev->bus->self;
1623         while (parent != tmp) {
1624                 ret = device_context_mapped(iommu, parent->bus->number,
1625                                             parent->devfn);
1626                 if (!ret)
1627                         return ret;
1628                 parent = parent->bus->self;
1629         }
1630         if (tmp->is_pcie)
1631                 return device_context_mapped(iommu, tmp->subordinate->number,
1632                                              0);
1633         else
1634                 return device_context_mapped(iommu, tmp->bus->number,
1635                                              tmp->devfn);
1636 }
1637
1638 static int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1639                               unsigned long phys_pfn, unsigned long nr_pages,
1640                               int prot)
1641 {
1642         struct dma_pte *first_pte = NULL, *pte = NULL;
1643         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1644
1645         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1646
1647         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1648                 return -EINVAL;
1649
1650         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1651
1652         while (nr_pages--) {
1653                 if (!pte) {
1654                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1655                         if (!pte)
1656                                 return -ENOMEM;
1657                 }
1658                 /* We don't need lock here, nobody else
1659                  * touches the iova range
1660                  */
1661                 BUG_ON(dma_pte_addr(pte));
1662                 pte->val = (phys_pfn << VTD_PAGE_SHIFT) | prot;
1663                 pte++;
1664                 if (!nr_pages ||
1665                     (unsigned long)pte >> VTD_PAGE_SHIFT !=
1666                     (unsigned long)first_pte >> VTD_PAGE_SHIFT) {
1667                         domain_flush_cache(domain, first_pte,
1668                                            (void *)pte - (void *)first_pte);
1669                         pte = NULL;
1670                 }
1671                 iov_pfn++;
1672                 phys_pfn++;
1673         }
1674         return 0;
1675 }
1676
1677 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1678 {
1679         if (!iommu)
1680                 return;
1681
1682         clear_context_table(iommu, bus, devfn);
1683         iommu->flush.flush_context(iommu, 0, 0, 0,
1684                                            DMA_CCMD_GLOBAL_INVL);
1685         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1686 }
1687
1688 static void domain_remove_dev_info(struct dmar_domain *domain)
1689 {
1690         struct device_domain_info *info;
1691         unsigned long flags;
1692         struct intel_iommu *iommu;
1693
1694         spin_lock_irqsave(&device_domain_lock, flags);
1695         while (!list_empty(&domain->devices)) {
1696                 info = list_entry(domain->devices.next,
1697                         struct device_domain_info, link);
1698                 list_del(&info->link);
1699                 list_del(&info->global);
1700                 if (info->dev)
1701                         info->dev->dev.archdata.iommu = NULL;
1702                 spin_unlock_irqrestore(&device_domain_lock, flags);
1703
1704                 iommu_disable_dev_iotlb(info);
1705                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1706                 iommu_detach_dev(iommu, info->bus, info->devfn);
1707                 free_devinfo_mem(info);
1708
1709                 spin_lock_irqsave(&device_domain_lock, flags);
1710         }
1711         spin_unlock_irqrestore(&device_domain_lock, flags);
1712 }
1713
1714 /*
1715  * find_domain
1716  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1717  */
1718 static struct dmar_domain *
1719 find_domain(struct pci_dev *pdev)
1720 {
1721         struct device_domain_info *info;
1722
1723         /* No lock here, assumes no domain exit in normal case */
1724         info = pdev->dev.archdata.iommu;
1725         if (info)
1726                 return info->domain;
1727         return NULL;
1728 }
1729
1730 /* domain is initialized */
1731 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1732 {
1733         struct dmar_domain *domain, *found = NULL;
1734         struct intel_iommu *iommu;
1735         struct dmar_drhd_unit *drhd;
1736         struct device_domain_info *info, *tmp;
1737         struct pci_dev *dev_tmp;
1738         unsigned long flags;
1739         int bus = 0, devfn = 0;
1740         int segment;
1741         int ret;
1742
1743         domain = find_domain(pdev);
1744         if (domain)
1745                 return domain;
1746
1747         segment = pci_domain_nr(pdev->bus);
1748
1749         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1750         if (dev_tmp) {
1751                 if (dev_tmp->is_pcie) {
1752                         bus = dev_tmp->subordinate->number;
1753                         devfn = 0;
1754                 } else {
1755                         bus = dev_tmp->bus->number;
1756                         devfn = dev_tmp->devfn;
1757                 }
1758                 spin_lock_irqsave(&device_domain_lock, flags);
1759                 list_for_each_entry(info, &device_domain_list, global) {
1760                         if (info->segment == segment &&
1761                             info->bus == bus && info->devfn == devfn) {
1762                                 found = info->domain;
1763                                 break;
1764                         }
1765                 }
1766                 spin_unlock_irqrestore(&device_domain_lock, flags);
1767                 /* pcie-pci bridge already has a domain, uses it */
1768                 if (found) {
1769                         domain = found;
1770                         goto found_domain;
1771                 }
1772         }
1773
1774         domain = alloc_domain();
1775         if (!domain)
1776                 goto error;
1777
1778         /* Allocate new domain for the device */
1779         drhd = dmar_find_matched_drhd_unit(pdev);
1780         if (!drhd) {
1781                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1782                         pci_name(pdev));
1783                 return NULL;
1784         }
1785         iommu = drhd->iommu;
1786
1787         ret = iommu_attach_domain(domain, iommu);
1788         if (ret) {
1789                 domain_exit(domain);
1790                 goto error;
1791         }
1792
1793         if (domain_init(domain, gaw)) {
1794                 domain_exit(domain);
1795                 goto error;
1796         }
1797
1798         /* register pcie-to-pci device */
1799         if (dev_tmp) {
1800                 info = alloc_devinfo_mem();
1801                 if (!info) {
1802                         domain_exit(domain);
1803                         goto error;
1804                 }
1805                 info->segment = segment;
1806                 info->bus = bus;
1807                 info->devfn = devfn;
1808                 info->dev = NULL;
1809                 info->domain = domain;
1810                 /* This domain is shared by devices under p2p bridge */
1811                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1812
1813                 /* pcie-to-pci bridge already has a domain, uses it */
1814                 found = NULL;
1815                 spin_lock_irqsave(&device_domain_lock, flags);
1816                 list_for_each_entry(tmp, &device_domain_list, global) {
1817                         if (tmp->segment == segment &&
1818                             tmp->bus == bus && tmp->devfn == devfn) {
1819                                 found = tmp->domain;
1820                                 break;
1821                         }
1822                 }
1823                 if (found) {
1824                         free_devinfo_mem(info);
1825                         domain_exit(domain);
1826                         domain = found;
1827                 } else {
1828                         list_add(&info->link, &domain->devices);
1829                         list_add(&info->global, &device_domain_list);
1830                 }
1831                 spin_unlock_irqrestore(&device_domain_lock, flags);
1832         }
1833
1834 found_domain:
1835         info = alloc_devinfo_mem();
1836         if (!info)
1837                 goto error;
1838         info->segment = segment;
1839         info->bus = pdev->bus->number;
1840         info->devfn = pdev->devfn;
1841         info->dev = pdev;
1842         info->domain = domain;
1843         spin_lock_irqsave(&device_domain_lock, flags);
1844         /* somebody is fast */
1845         found = find_domain(pdev);
1846         if (found != NULL) {
1847                 spin_unlock_irqrestore(&device_domain_lock, flags);
1848                 if (found != domain) {
1849                         domain_exit(domain);
1850                         domain = found;
1851                 }
1852                 free_devinfo_mem(info);
1853                 return domain;
1854         }
1855         list_add(&info->link, &domain->devices);
1856         list_add(&info->global, &device_domain_list);
1857         pdev->dev.archdata.iommu = info;
1858         spin_unlock_irqrestore(&device_domain_lock, flags);
1859         return domain;
1860 error:
1861         /* recheck it here, maybe others set it */
1862         return find_domain(pdev);
1863 }
1864
1865 static int iommu_identity_mapping;
1866
1867 static int iommu_domain_identity_map(struct dmar_domain *domain,
1868                                      unsigned long long start,
1869                                      unsigned long long end)
1870 {
1871         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1872         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1873
1874         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1875                           dma_to_mm_pfn(last_vpfn))) {
1876                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1877                 return -ENOMEM;
1878         }
1879
1880         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1881                  start, end, domain->id);
1882         /*
1883          * RMRR range might have overlap with physical memory range,
1884          * clear it first
1885          */
1886         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1887
1888         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1889                                   last_vpfn - first_vpfn + 1,
1890                                   DMA_PTE_READ|DMA_PTE_WRITE);
1891 }
1892
1893 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1894                                       unsigned long long start,
1895                                       unsigned long long end)
1896 {
1897         struct dmar_domain *domain;
1898         int ret;
1899
1900         printk(KERN_INFO
1901                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1902                pci_name(pdev), start, end);
1903
1904         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1905         if (!domain)
1906                 return -ENOMEM;
1907
1908         ret = iommu_domain_identity_map(domain, start, end);
1909         if (ret)
1910                 goto error;
1911
1912         /* context entry init */
1913         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1914         if (ret)
1915                 goto error;
1916
1917         return 0;
1918
1919  error:
1920         domain_exit(domain);
1921         return ret;
1922 }
1923
1924 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1925         struct pci_dev *pdev)
1926 {
1927         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1928                 return 0;
1929         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1930                 rmrr->end_address + 1);
1931 }
1932
1933 #ifdef CONFIG_DMAR_FLOPPY_WA
1934 static inline void iommu_prepare_isa(void)
1935 {
1936         struct pci_dev *pdev;
1937         int ret;
1938
1939         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1940         if (!pdev)
1941                 return;
1942
1943         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1944         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1945
1946         if (ret)
1947                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1948                        "floppy might not work\n");
1949
1950 }
1951 #else
1952 static inline void iommu_prepare_isa(void)
1953 {
1954         return;
1955 }
1956 #endif /* !CONFIG_DMAR_FLPY_WA */
1957
1958 /* Initialize each context entry as pass through.*/
1959 static int __init init_context_pass_through(void)
1960 {
1961         struct pci_dev *pdev = NULL;
1962         struct dmar_domain *domain;
1963         int ret;
1964
1965         for_each_pci_dev(pdev) {
1966                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1967                 ret = domain_context_mapping(domain, pdev,
1968                                              CONTEXT_TT_PASS_THROUGH);
1969                 if (ret)
1970                         return ret;
1971         }
1972         return 0;
1973 }
1974
1975 static int md_domain_init(struct dmar_domain *domain, int guest_width);
1976
1977 static int __init si_domain_work_fn(unsigned long start_pfn,
1978                                     unsigned long end_pfn, void *datax)
1979 {
1980         int *ret = datax;
1981
1982         *ret = iommu_domain_identity_map(si_domain,
1983                                          (uint64_t)start_pfn << PAGE_SHIFT,
1984                                          (uint64_t)end_pfn << PAGE_SHIFT);
1985         return *ret;
1986
1987 }
1988
1989 static int si_domain_init(void)
1990 {
1991         struct dmar_drhd_unit *drhd;
1992         struct intel_iommu *iommu;
1993         int nid, ret = 0;
1994
1995         si_domain = alloc_domain();
1996         if (!si_domain)
1997                 return -EFAULT;
1998
1999         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2000
2001         for_each_active_iommu(iommu, drhd) {
2002                 ret = iommu_attach_domain(si_domain, iommu);
2003                 if (ret) {
2004                         domain_exit(si_domain);
2005                         return -EFAULT;
2006                 }
2007         }
2008
2009         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2010                 domain_exit(si_domain);
2011                 return -EFAULT;
2012         }
2013
2014         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2015
2016         for_each_online_node(nid) {
2017                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2018                 if (ret)
2019                         return ret;
2020         }
2021
2022         return 0;
2023 }
2024
2025 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2026                                           struct pci_dev *pdev);
2027 static int identity_mapping(struct pci_dev *pdev)
2028 {
2029         struct device_domain_info *info;
2030
2031         if (likely(!iommu_identity_mapping))
2032                 return 0;
2033
2034
2035         list_for_each_entry(info, &si_domain->devices, link)
2036                 if (info->dev == pdev)
2037                         return 1;
2038         return 0;
2039 }
2040
2041 static int domain_add_dev_info(struct dmar_domain *domain,
2042                                   struct pci_dev *pdev)
2043 {
2044         struct device_domain_info *info;
2045         unsigned long flags;
2046
2047         info = alloc_devinfo_mem();
2048         if (!info)
2049                 return -ENOMEM;
2050
2051         info->segment = pci_domain_nr(pdev->bus);
2052         info->bus = pdev->bus->number;
2053         info->devfn = pdev->devfn;
2054         info->dev = pdev;
2055         info->domain = domain;
2056
2057         spin_lock_irqsave(&device_domain_lock, flags);
2058         list_add(&info->link, &domain->devices);
2059         list_add(&info->global, &device_domain_list);
2060         pdev->dev.archdata.iommu = info;
2061         spin_unlock_irqrestore(&device_domain_lock, flags);
2062
2063         return 0;
2064 }
2065
2066 static int iommu_prepare_static_identity_mapping(void)
2067 {
2068         struct pci_dev *pdev = NULL;
2069         int ret;
2070
2071         ret = si_domain_init();
2072         if (ret)
2073                 return -EFAULT;
2074
2075         for_each_pci_dev(pdev) {
2076                 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2077                        pci_name(pdev));
2078
2079                 ret = domain_context_mapping(si_domain, pdev,
2080                                              CONTEXT_TT_MULTI_LEVEL);
2081                 if (ret)
2082                         return ret;
2083                 ret = domain_add_dev_info(si_domain, pdev);
2084                 if (ret)
2085                         return ret;
2086         }
2087
2088         return 0;
2089 }
2090
2091 int __init init_dmars(void)
2092 {
2093         struct dmar_drhd_unit *drhd;
2094         struct dmar_rmrr_unit *rmrr;
2095         struct pci_dev *pdev;
2096         struct intel_iommu *iommu;
2097         int i, ret;
2098         int pass_through = 1;
2099
2100         /*
2101          * In case pass through can not be enabled, iommu tries to use identity
2102          * mapping.
2103          */
2104         if (iommu_pass_through)
2105                 iommu_identity_mapping = 1;
2106
2107         /*
2108          * for each drhd
2109          *    allocate root
2110          *    initialize and program root entry to not present
2111          * endfor
2112          */
2113         for_each_drhd_unit(drhd) {
2114                 g_num_of_iommus++;
2115                 /*
2116                  * lock not needed as this is only incremented in the single
2117                  * threaded kernel __init code path all other access are read
2118                  * only
2119                  */
2120         }
2121
2122         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2123                         GFP_KERNEL);
2124         if (!g_iommus) {
2125                 printk(KERN_ERR "Allocating global iommu array failed\n");
2126                 ret = -ENOMEM;
2127                 goto error;
2128         }
2129
2130         deferred_flush = kzalloc(g_num_of_iommus *
2131                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2132         if (!deferred_flush) {
2133                 kfree(g_iommus);
2134                 ret = -ENOMEM;
2135                 goto error;
2136         }
2137
2138         for_each_drhd_unit(drhd) {
2139                 if (drhd->ignored)
2140                         continue;
2141
2142                 iommu = drhd->iommu;
2143                 g_iommus[iommu->seq_id] = iommu;
2144
2145                 ret = iommu_init_domains(iommu);
2146                 if (ret)
2147                         goto error;
2148
2149                 /*
2150                  * TBD:
2151                  * we could share the same root & context tables
2152                  * amoung all IOMMU's. Need to Split it later.
2153                  */
2154                 ret = iommu_alloc_root_entry(iommu);
2155                 if (ret) {
2156                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2157                         goto error;
2158                 }
2159                 if (!ecap_pass_through(iommu->ecap))
2160                         pass_through = 0;
2161         }
2162         if (iommu_pass_through)
2163                 if (!pass_through) {
2164                         printk(KERN_INFO
2165                                "Pass Through is not supported by hardware.\n");
2166                         iommu_pass_through = 0;
2167                 }
2168
2169         /*
2170          * Start from the sane iommu hardware state.
2171          */
2172         for_each_drhd_unit(drhd) {
2173                 if (drhd->ignored)
2174                         continue;
2175
2176                 iommu = drhd->iommu;
2177
2178                 /*
2179                  * If the queued invalidation is already initialized by us
2180                  * (for example, while enabling interrupt-remapping) then
2181                  * we got the things already rolling from a sane state.
2182                  */
2183                 if (iommu->qi)
2184                         continue;
2185
2186                 /*
2187                  * Clear any previous faults.
2188                  */
2189                 dmar_fault(-1, iommu);
2190                 /*
2191                  * Disable queued invalidation if supported and already enabled
2192                  * before OS handover.
2193                  */
2194                 dmar_disable_qi(iommu);
2195         }
2196
2197         for_each_drhd_unit(drhd) {
2198                 if (drhd->ignored)
2199                         continue;
2200
2201                 iommu = drhd->iommu;
2202
2203                 if (dmar_enable_qi(iommu)) {
2204                         /*
2205                          * Queued Invalidate not enabled, use Register Based
2206                          * Invalidate
2207                          */
2208                         iommu->flush.flush_context = __iommu_flush_context;
2209                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2210                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2211                                "invalidation\n",
2212                                (unsigned long long)drhd->reg_base_addr);
2213                 } else {
2214                         iommu->flush.flush_context = qi_flush_context;
2215                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2216                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2217                                "invalidation\n",
2218                                (unsigned long long)drhd->reg_base_addr);
2219                 }
2220         }
2221
2222         /*
2223          * If pass through is set and enabled, context entries of all pci
2224          * devices are intialized by pass through translation type.
2225          */
2226         if (iommu_pass_through) {
2227                 ret = init_context_pass_through();
2228                 if (ret) {
2229                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2230                         iommu_pass_through = 0;
2231                 }
2232         }
2233
2234         /*
2235          * If pass through is not set or not enabled, setup context entries for
2236          * identity mappings for rmrr, gfx, and isa and may fall back to static
2237          * identity mapping if iommu_identity_mapping is set.
2238          */
2239         if (!iommu_pass_through) {
2240                 if (iommu_identity_mapping)
2241                         iommu_prepare_static_identity_mapping();
2242                 /*
2243                  * For each rmrr
2244                  *   for each dev attached to rmrr
2245                  *   do
2246                  *     locate drhd for dev, alloc domain for dev
2247                  *     allocate free domain
2248                  *     allocate page table entries for rmrr
2249                  *     if context not allocated for bus
2250                  *           allocate and init context
2251                  *           set present in root table for this bus
2252                  *     init context with domain, translation etc
2253                  *    endfor
2254                  * endfor
2255                  */
2256                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2257                 for_each_rmrr_units(rmrr) {
2258                         for (i = 0; i < rmrr->devices_cnt; i++) {
2259                                 pdev = rmrr->devices[i];
2260                                 /*
2261                                  * some BIOS lists non-exist devices in DMAR
2262                                  * table.
2263                                  */
2264                                 if (!pdev)
2265                                         continue;
2266                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2267                                 if (ret)
2268                                         printk(KERN_ERR
2269                                  "IOMMU: mapping reserved region failed\n");
2270                         }
2271                 }
2272
2273                 iommu_prepare_isa();
2274         }
2275
2276         /*
2277          * for each drhd
2278          *   enable fault log
2279          *   global invalidate context cache
2280          *   global invalidate iotlb
2281          *   enable translation
2282          */
2283         for_each_drhd_unit(drhd) {
2284                 if (drhd->ignored)
2285                         continue;
2286                 iommu = drhd->iommu;
2287
2288                 iommu_flush_write_buffer(iommu);
2289
2290                 ret = dmar_set_interrupt(iommu);
2291                 if (ret)
2292                         goto error;
2293
2294                 iommu_set_root_entry(iommu);
2295
2296                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2297                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2298                 iommu_disable_protect_mem_regions(iommu);
2299
2300                 ret = iommu_enable_translation(iommu);
2301                 if (ret)
2302                         goto error;
2303         }
2304
2305         return 0;
2306 error:
2307         for_each_drhd_unit(drhd) {
2308                 if (drhd->ignored)
2309                         continue;
2310                 iommu = drhd->iommu;
2311                 free_iommu(iommu);
2312         }
2313         kfree(g_iommus);
2314         return ret;
2315 }
2316
2317 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2318                                             size_t size)
2319 {
2320         host_addr &= ~PAGE_MASK;
2321         host_addr += size + PAGE_SIZE - 1;
2322
2323         return host_addr >> VTD_PAGE_SHIFT;
2324 }
2325
2326 struct iova *
2327 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2328 {
2329         struct iova *piova;
2330
2331         /* Make sure it's in range */
2332         end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2333         if (!size || (IOVA_START_ADDR + size > end))
2334                 return NULL;
2335
2336         piova = alloc_iova(&domain->iovad,
2337                         size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2338         return piova;
2339 }
2340
2341 static struct iova *
2342 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2343                    size_t size, u64 dma_mask)
2344 {
2345         struct pci_dev *pdev = to_pci_dev(dev);
2346         struct iova *iova = NULL;
2347
2348         if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2349                 iova = iommu_alloc_iova(domain, size, dma_mask);
2350         else {
2351                 /*
2352                  * First try to allocate an io virtual address in
2353                  * DMA_BIT_MASK(32) and if that fails then try allocating
2354                  * from higher range
2355                  */
2356                 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2357                 if (!iova)
2358                         iova = iommu_alloc_iova(domain, size, dma_mask);
2359         }
2360
2361         if (!iova) {
2362                 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2363                 return NULL;
2364         }
2365
2366         return iova;
2367 }
2368
2369 static struct dmar_domain *
2370 get_valid_domain_for_dev(struct pci_dev *pdev)
2371 {
2372         struct dmar_domain *domain;
2373         int ret;
2374
2375         domain = get_domain_for_dev(pdev,
2376                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2377         if (!domain) {
2378                 printk(KERN_ERR
2379                         "Allocating domain for %s failed", pci_name(pdev));
2380                 return NULL;
2381         }
2382
2383         /* make sure context mapping is ok */
2384         if (unlikely(!domain_context_mapped(pdev))) {
2385                 ret = domain_context_mapping(domain, pdev,
2386                                              CONTEXT_TT_MULTI_LEVEL);
2387                 if (ret) {
2388                         printk(KERN_ERR
2389                                 "Domain context map for %s failed",
2390                                 pci_name(pdev));
2391                         return NULL;
2392                 }
2393         }
2394
2395         return domain;
2396 }
2397
2398 static int iommu_dummy(struct pci_dev *pdev)
2399 {
2400         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2401 }
2402
2403 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2404 static int iommu_no_mapping(struct pci_dev *pdev)
2405 {
2406         int found;
2407
2408         if (!iommu_identity_mapping)
2409                 return iommu_dummy(pdev);
2410
2411         found = identity_mapping(pdev);
2412         if (found) {
2413                 if (pdev->dma_mask > DMA_BIT_MASK(32))
2414                         return 1;
2415                 else {
2416                         /*
2417                          * 32 bit DMA is removed from si_domain and fall back
2418                          * to non-identity mapping.
2419                          */
2420                         domain_remove_one_dev_info(si_domain, pdev);
2421                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2422                                pci_name(pdev));
2423                         return 0;
2424                 }
2425         } else {
2426                 /*
2427                  * In case of a detached 64 bit DMA device from vm, the device
2428                  * is put into si_domain for identity mapping.
2429                  */
2430                 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2431                         int ret;
2432                         ret = domain_add_dev_info(si_domain, pdev);
2433                         if (!ret) {
2434                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2435                                        pci_name(pdev));
2436                                 return 1;
2437                         }
2438                 }
2439         }
2440
2441         return iommu_dummy(pdev);
2442 }
2443
2444 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2445                                      size_t size, int dir, u64 dma_mask)
2446 {
2447         struct pci_dev *pdev = to_pci_dev(hwdev);
2448         struct dmar_domain *domain;
2449         phys_addr_t start_paddr;
2450         struct iova *iova;
2451         int prot = 0;
2452         int ret;
2453         struct intel_iommu *iommu;
2454
2455         BUG_ON(dir == DMA_NONE);
2456
2457         if (iommu_no_mapping(pdev))
2458                 return paddr;
2459
2460         domain = get_valid_domain_for_dev(pdev);
2461         if (!domain)
2462                 return 0;
2463
2464         iommu = domain_get_iommu(domain);
2465         size = aligned_nrpages(paddr, size);
2466
2467         iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT, pdev->dma_mask);
2468         if (!iova)
2469                 goto error;
2470
2471         /*
2472          * Check if DMAR supports zero-length reads on write only
2473          * mappings..
2474          */
2475         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2476                         !cap_zlr(iommu->cap))
2477                 prot |= DMA_PTE_READ;
2478         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2479                 prot |= DMA_PTE_WRITE;
2480         /*
2481          * paddr - (paddr + size) might be partial page, we should map the whole
2482          * page.  Note: if two part of one page are separately mapped, we
2483          * might have two guest_addr mapping to the same host paddr, but this
2484          * is not a big problem
2485          */
2486         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2487                                  paddr >> VTD_PAGE_SHIFT, size, prot);
2488         if (ret)
2489                 goto error;
2490
2491         /* it's a non-present to present mapping. Only flush if caching mode */
2492         if (cap_caching_mode(iommu->cap))
2493                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2494         else
2495                 iommu_flush_write_buffer(iommu);
2496
2497         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2498         start_paddr += paddr & ~PAGE_MASK;
2499         return start_paddr;
2500
2501 error:
2502         if (iova)
2503                 __free_iova(&domain->iovad, iova);
2504         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2505                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2506         return 0;
2507 }
2508
2509 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2510                                  unsigned long offset, size_t size,
2511                                  enum dma_data_direction dir,
2512                                  struct dma_attrs *attrs)
2513 {
2514         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2515                                   dir, to_pci_dev(dev)->dma_mask);
2516 }
2517
2518 static void flush_unmaps(void)
2519 {
2520         int i, j;
2521
2522         timer_on = 0;
2523
2524         /* just flush them all */
2525         for (i = 0; i < g_num_of_iommus; i++) {
2526                 struct intel_iommu *iommu = g_iommus[i];
2527                 if (!iommu)
2528                         continue;
2529
2530                 if (!deferred_flush[i].next)
2531                         continue;
2532
2533                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2534                                          DMA_TLB_GLOBAL_FLUSH);
2535                 for (j = 0; j < deferred_flush[i].next; j++) {
2536                         unsigned long mask;
2537                         struct iova *iova = deferred_flush[i].iova[j];
2538
2539                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2540                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2541                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2542                                         iova->pfn_lo << PAGE_SHIFT, mask);
2543                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2544                 }
2545                 deferred_flush[i].next = 0;
2546         }
2547
2548         list_size = 0;
2549 }
2550
2551 static void flush_unmaps_timeout(unsigned long data)
2552 {
2553         unsigned long flags;
2554
2555         spin_lock_irqsave(&async_umap_flush_lock, flags);
2556         flush_unmaps();
2557         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2558 }
2559
2560 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2561 {
2562         unsigned long flags;
2563         int next, iommu_id;
2564         struct intel_iommu *iommu;
2565
2566         spin_lock_irqsave(&async_umap_flush_lock, flags);
2567         if (list_size == HIGH_WATER_MARK)
2568                 flush_unmaps();
2569
2570         iommu = domain_get_iommu(dom);
2571         iommu_id = iommu->seq_id;
2572
2573         next = deferred_flush[iommu_id].next;
2574         deferred_flush[iommu_id].domain[next] = dom;
2575         deferred_flush[iommu_id].iova[next] = iova;
2576         deferred_flush[iommu_id].next++;
2577
2578         if (!timer_on) {
2579                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2580                 timer_on = 1;
2581         }
2582         list_size++;
2583         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2584 }
2585
2586 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2587                              size_t size, enum dma_data_direction dir,
2588                              struct dma_attrs *attrs)
2589 {
2590         struct pci_dev *pdev = to_pci_dev(dev);
2591         struct dmar_domain *domain;
2592         unsigned long start_pfn, last_pfn;
2593         struct iova *iova;
2594         struct intel_iommu *iommu;
2595
2596         if (iommu_no_mapping(pdev))
2597                 return;
2598
2599         domain = find_domain(pdev);
2600         BUG_ON(!domain);
2601
2602         iommu = domain_get_iommu(domain);
2603
2604         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2605         if (!iova)
2606                 return;
2607
2608         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2609         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2610
2611         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2612                  pci_name(pdev), start_pfn, last_pfn);
2613
2614         /*  clear the whole page */
2615         dma_pte_clear_range(domain, start_pfn, last_pfn);
2616
2617         /* free page tables */
2618         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2619
2620         if (intel_iommu_strict) {
2621                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2622                                       last_pfn - start_pfn + 1);
2623                 /* free iova */
2624                 __free_iova(&domain->iovad, iova);
2625         } else {
2626                 add_unmap(domain, iova);
2627                 /*
2628                  * queue up the release of the unmap to save the 1/6th of the
2629                  * cpu used up by the iotlb flush operation...
2630                  */
2631         }
2632 }
2633
2634 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2635                                int dir)
2636 {
2637         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2638 }
2639
2640 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2641                                   dma_addr_t *dma_handle, gfp_t flags)
2642 {
2643         void *vaddr;
2644         int order;
2645
2646         size = PAGE_ALIGN(size);
2647         order = get_order(size);
2648         flags &= ~(GFP_DMA | GFP_DMA32);
2649
2650         vaddr = (void *)__get_free_pages(flags, order);
2651         if (!vaddr)
2652                 return NULL;
2653         memset(vaddr, 0, size);
2654
2655         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2656                                          DMA_BIDIRECTIONAL,
2657                                          hwdev->coherent_dma_mask);
2658         if (*dma_handle)
2659                 return vaddr;
2660         free_pages((unsigned long)vaddr, order);
2661         return NULL;
2662 }
2663
2664 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2665                                 dma_addr_t dma_handle)
2666 {
2667         int order;
2668
2669         size = PAGE_ALIGN(size);
2670         order = get_order(size);
2671
2672         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2673         free_pages((unsigned long)vaddr, order);
2674 }
2675
2676 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2677                            int nelems, enum dma_data_direction dir,
2678                            struct dma_attrs *attrs)
2679 {
2680         struct pci_dev *pdev = to_pci_dev(hwdev);
2681         struct dmar_domain *domain;
2682         unsigned long start_pfn, last_pfn;
2683         struct iova *iova;
2684         struct intel_iommu *iommu;
2685
2686         if (iommu_no_mapping(pdev))
2687                 return;
2688
2689         domain = find_domain(pdev);
2690         BUG_ON(!domain);
2691
2692         iommu = domain_get_iommu(domain);
2693
2694         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2695         if (!iova)
2696                 return;
2697
2698         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2699         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2700
2701         /*  clear the whole page */
2702         dma_pte_clear_range(domain, start_pfn, last_pfn);
2703
2704         /* free page tables */
2705         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2706
2707         iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2708                               (last_pfn - start_pfn + 1));
2709
2710         /* free iova */
2711         __free_iova(&domain->iovad, iova);
2712 }
2713
2714 static int intel_nontranslate_map_sg(struct device *hddev,
2715         struct scatterlist *sglist, int nelems, int dir)
2716 {
2717         int i;
2718         struct scatterlist *sg;
2719
2720         for_each_sg(sglist, sg, nelems, i) {
2721                 BUG_ON(!sg_page(sg));
2722                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2723                 sg->dma_length = sg->length;
2724         }
2725         return nelems;
2726 }
2727
2728 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2729                         enum dma_data_direction dir, struct dma_attrs *attrs)
2730 {
2731         int i;
2732         struct pci_dev *pdev = to_pci_dev(hwdev);
2733         struct dmar_domain *domain;
2734         size_t size = 0;
2735         int prot = 0;
2736         size_t offset_pfn = 0;
2737         struct iova *iova = NULL;
2738         int ret;
2739         struct scatterlist *sg;
2740         unsigned long start_vpfn;
2741         struct intel_iommu *iommu;
2742
2743         BUG_ON(dir == DMA_NONE);
2744         if (iommu_no_mapping(pdev))
2745                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2746
2747         domain = get_valid_domain_for_dev(pdev);
2748         if (!domain)
2749                 return 0;
2750
2751         iommu = domain_get_iommu(domain);
2752
2753         for_each_sg(sglist, sg, nelems, i)
2754                 size += aligned_nrpages(sg->offset, sg->length);
2755
2756         iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT,
2757                                   pdev->dma_mask);
2758         if (!iova) {
2759                 sglist->dma_length = 0;
2760                 return 0;
2761         }
2762
2763         /*
2764          * Check if DMAR supports zero-length reads on write only
2765          * mappings..
2766          */
2767         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2768                         !cap_zlr(iommu->cap))
2769                 prot |= DMA_PTE_READ;
2770         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2771                 prot |= DMA_PTE_WRITE;
2772
2773         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2774         offset_pfn = 0;
2775         for_each_sg(sglist, sg, nelems, i) {
2776                 int nr_pages = aligned_nrpages(sg->offset, sg->length);
2777                 ret = domain_pfn_mapping(domain, start_vpfn + offset_pfn,
2778                                          page_to_dma_pfn(sg_page(sg)),
2779                                          nr_pages, prot);
2780                 if (ret) {
2781                         /*  clear the page */
2782                         dma_pte_clear_range(domain, start_vpfn,
2783                                             start_vpfn + offset_pfn);
2784                         /* free page tables */
2785                         dma_pte_free_pagetable(domain, start_vpfn,
2786                                                start_vpfn + offset_pfn);
2787                         /* free iova */
2788                         __free_iova(&domain->iovad, iova);
2789                         return 0;
2790                 }
2791                 sg->dma_address = ((dma_addr_t)(start_vpfn + offset_pfn)
2792                                    << VTD_PAGE_SHIFT) + sg->offset;
2793                 sg->dma_length = sg->length;
2794                 offset_pfn += nr_pages;
2795         }
2796
2797         /* it's a non-present to present mapping. Only flush if caching mode */
2798         if (cap_caching_mode(iommu->cap))
2799                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2800         else
2801                 iommu_flush_write_buffer(iommu);
2802
2803         return nelems;
2804 }
2805
2806 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2807 {
2808         return !dma_addr;
2809 }
2810
2811 struct dma_map_ops intel_dma_ops = {
2812         .alloc_coherent = intel_alloc_coherent,
2813         .free_coherent = intel_free_coherent,
2814         .map_sg = intel_map_sg,
2815         .unmap_sg = intel_unmap_sg,
2816         .map_page = intel_map_page,
2817         .unmap_page = intel_unmap_page,
2818         .mapping_error = intel_mapping_error,
2819 };
2820
2821 static inline int iommu_domain_cache_init(void)
2822 {
2823         int ret = 0;
2824
2825         iommu_domain_cache = kmem_cache_create("iommu_domain",
2826                                          sizeof(struct dmar_domain),
2827                                          0,
2828                                          SLAB_HWCACHE_ALIGN,
2829
2830                                          NULL);
2831         if (!iommu_domain_cache) {
2832                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2833                 ret = -ENOMEM;
2834         }
2835
2836         return ret;
2837 }
2838
2839 static inline int iommu_devinfo_cache_init(void)
2840 {
2841         int ret = 0;
2842
2843         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2844                                          sizeof(struct device_domain_info),
2845                                          0,
2846                                          SLAB_HWCACHE_ALIGN,
2847                                          NULL);
2848         if (!iommu_devinfo_cache) {
2849                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2850                 ret = -ENOMEM;
2851         }
2852
2853         return ret;
2854 }
2855
2856 static inline int iommu_iova_cache_init(void)
2857 {
2858         int ret = 0;
2859
2860         iommu_iova_cache = kmem_cache_create("iommu_iova",
2861                                          sizeof(struct iova),
2862                                          0,
2863                                          SLAB_HWCACHE_ALIGN,
2864                                          NULL);
2865         if (!iommu_iova_cache) {
2866                 printk(KERN_ERR "Couldn't create iova cache\n");
2867                 ret = -ENOMEM;
2868         }
2869
2870         return ret;
2871 }
2872
2873 static int __init iommu_init_mempool(void)
2874 {
2875         int ret;
2876         ret = iommu_iova_cache_init();
2877         if (ret)
2878                 return ret;
2879
2880         ret = iommu_domain_cache_init();
2881         if (ret)
2882                 goto domain_error;
2883
2884         ret = iommu_devinfo_cache_init();
2885         if (!ret)
2886                 return ret;
2887
2888         kmem_cache_destroy(iommu_domain_cache);
2889 domain_error:
2890         kmem_cache_destroy(iommu_iova_cache);
2891
2892         return -ENOMEM;
2893 }
2894
2895 static void __init iommu_exit_mempool(void)
2896 {
2897         kmem_cache_destroy(iommu_devinfo_cache);
2898         kmem_cache_destroy(iommu_domain_cache);
2899         kmem_cache_destroy(iommu_iova_cache);
2900
2901 }
2902
2903 static void __init init_no_remapping_devices(void)
2904 {
2905         struct dmar_drhd_unit *drhd;
2906
2907         for_each_drhd_unit(drhd) {
2908                 if (!drhd->include_all) {
2909                         int i;
2910                         for (i = 0; i < drhd->devices_cnt; i++)
2911                                 if (drhd->devices[i] != NULL)
2912                                         break;
2913                         /* ignore DMAR unit if no pci devices exist */
2914                         if (i == drhd->devices_cnt)
2915                                 drhd->ignored = 1;
2916                 }
2917         }
2918
2919         if (dmar_map_gfx)
2920                 return;
2921
2922         for_each_drhd_unit(drhd) {
2923                 int i;
2924                 if (drhd->ignored || drhd->include_all)
2925                         continue;
2926
2927                 for (i = 0; i < drhd->devices_cnt; i++)
2928                         if (drhd->devices[i] &&
2929                                 !IS_GFX_DEVICE(drhd->devices[i]))
2930                                 break;
2931
2932                 if (i < drhd->devices_cnt)
2933                         continue;
2934
2935                 /* bypass IOMMU if it is just for gfx devices */
2936                 drhd->ignored = 1;
2937                 for (i = 0; i < drhd->devices_cnt; i++) {
2938                         if (!drhd->devices[i])
2939                                 continue;
2940                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2941                 }
2942         }
2943 }
2944
2945 #ifdef CONFIG_SUSPEND
2946 static int init_iommu_hw(void)
2947 {
2948         struct dmar_drhd_unit *drhd;
2949         struct intel_iommu *iommu = NULL;
2950
2951         for_each_active_iommu(iommu, drhd)
2952                 if (iommu->qi)
2953                         dmar_reenable_qi(iommu);
2954
2955         for_each_active_iommu(iommu, drhd) {
2956                 iommu_flush_write_buffer(iommu);
2957
2958                 iommu_set_root_entry(iommu);
2959
2960                 iommu->flush.flush_context(iommu, 0, 0, 0,
2961                                            DMA_CCMD_GLOBAL_INVL);
2962                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2963                                          DMA_TLB_GLOBAL_FLUSH);
2964                 iommu_disable_protect_mem_regions(iommu);
2965                 iommu_enable_translation(iommu);
2966         }
2967
2968         return 0;
2969 }
2970
2971 static void iommu_flush_all(void)
2972 {
2973         struct dmar_drhd_unit *drhd;
2974         struct intel_iommu *iommu;
2975
2976         for_each_active_iommu(iommu, drhd) {
2977                 iommu->flush.flush_context(iommu, 0, 0, 0,
2978                                            DMA_CCMD_GLOBAL_INVL);
2979                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2980                                          DMA_TLB_GLOBAL_FLUSH);
2981         }
2982 }
2983
2984 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
2985 {
2986         struct dmar_drhd_unit *drhd;
2987         struct intel_iommu *iommu = NULL;
2988         unsigned long flag;
2989
2990         for_each_active_iommu(iommu, drhd) {
2991                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
2992                                                  GFP_ATOMIC);
2993                 if (!iommu->iommu_state)
2994                         goto nomem;
2995         }
2996
2997         iommu_flush_all();
2998
2999         for_each_active_iommu(iommu, drhd) {
3000                 iommu_disable_translation(iommu);
3001
3002                 spin_lock_irqsave(&iommu->register_lock, flag);
3003
3004                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3005                         readl(iommu->reg + DMAR_FECTL_REG);
3006                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3007                         readl(iommu->reg + DMAR_FEDATA_REG);
3008                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3009                         readl(iommu->reg + DMAR_FEADDR_REG);
3010                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3011                         readl(iommu->reg + DMAR_FEUADDR_REG);
3012
3013                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3014         }
3015         return 0;
3016
3017 nomem:
3018         for_each_active_iommu(iommu, drhd)
3019                 kfree(iommu->iommu_state);
3020
3021         return -ENOMEM;
3022 }
3023
3024 static int iommu_resume(struct sys_device *dev)
3025 {
3026         struct dmar_drhd_unit *drhd;
3027         struct intel_iommu *iommu = NULL;
3028         unsigned long flag;
3029
3030         if (init_iommu_hw()) {
3031                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3032                 return -EIO;
3033         }
3034
3035         for_each_active_iommu(iommu, drhd) {
3036
3037                 spin_lock_irqsave(&iommu->register_lock, flag);
3038
3039                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3040                         iommu->reg + DMAR_FECTL_REG);
3041                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3042                         iommu->reg + DMAR_FEDATA_REG);
3043                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3044                         iommu->reg + DMAR_FEADDR_REG);
3045                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3046                         iommu->reg + DMAR_FEUADDR_REG);
3047
3048                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3049         }
3050
3051         for_each_active_iommu(iommu, drhd)
3052                 kfree(iommu->iommu_state);
3053
3054         return 0;
3055 }
3056
3057 static struct sysdev_class iommu_sysclass = {
3058         .name           = "iommu",
3059         .resume         = iommu_resume,
3060         .suspend        = iommu_suspend,
3061 };
3062
3063 static struct sys_device device_iommu = {
3064         .cls    = &iommu_sysclass,
3065 };
3066
3067 static int __init init_iommu_sysfs(void)
3068 {
3069         int error;
3070
3071         error = sysdev_class_register(&iommu_sysclass);
3072         if (error)
3073                 return error;
3074
3075         error = sysdev_register(&device_iommu);
3076         if (error)
3077                 sysdev_class_unregister(&iommu_sysclass);
3078
3079         return error;
3080 }
3081
3082 #else
3083 static int __init init_iommu_sysfs(void)
3084 {
3085         return 0;
3086 }
3087 #endif  /* CONFIG_PM */
3088
3089 int __init intel_iommu_init(void)
3090 {
3091         int ret = 0;
3092
3093         if (dmar_table_init())
3094                 return  -ENODEV;
3095
3096         if (dmar_dev_scope_init())
3097                 return  -ENODEV;
3098
3099         /*
3100          * Check the need for DMA-remapping initialization now.
3101          * Above initialization will also be used by Interrupt-remapping.
3102          */
3103         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3104                 return -ENODEV;
3105
3106         iommu_init_mempool();
3107         dmar_init_reserved_ranges();
3108
3109         init_no_remapping_devices();
3110
3111         ret = init_dmars();
3112         if (ret) {
3113                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3114                 put_iova_domain(&reserved_iova_list);
3115                 iommu_exit_mempool();
3116                 return ret;
3117         }
3118         printk(KERN_INFO
3119         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3120
3121         init_timer(&unmap_timer);
3122         force_iommu = 1;
3123
3124         if (!iommu_pass_through) {
3125                 printk(KERN_INFO
3126                        "Multi-level page-table translation for DMAR.\n");
3127                 dma_ops = &intel_dma_ops;
3128         } else
3129                 printk(KERN_INFO
3130                        "DMAR: Pass through translation for DMAR.\n");
3131
3132         init_iommu_sysfs();
3133
3134         register_iommu(&intel_iommu_ops);
3135
3136         return 0;
3137 }
3138
3139 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3140                                            struct pci_dev *pdev)
3141 {
3142         struct pci_dev *tmp, *parent;
3143
3144         if (!iommu || !pdev)
3145                 return;
3146
3147         /* dependent device detach */
3148         tmp = pci_find_upstream_pcie_bridge(pdev);
3149         /* Secondary interface's bus number and devfn 0 */
3150         if (tmp) {
3151                 parent = pdev->bus->self;
3152                 while (parent != tmp) {
3153                         iommu_detach_dev(iommu, parent->bus->number,
3154                                          parent->devfn);
3155                         parent = parent->bus->self;
3156                 }
3157                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3158                         iommu_detach_dev(iommu,
3159                                 tmp->subordinate->number, 0);
3160                 else /* this is a legacy PCI bridge */
3161                         iommu_detach_dev(iommu, tmp->bus->number,
3162                                          tmp->devfn);
3163         }
3164 }
3165
3166 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3167                                           struct pci_dev *pdev)
3168 {
3169         struct device_domain_info *info;
3170         struct intel_iommu *iommu;
3171         unsigned long flags;
3172         int found = 0;
3173         struct list_head *entry, *tmp;
3174
3175         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3176                                 pdev->devfn);
3177         if (!iommu)
3178                 return;
3179
3180         spin_lock_irqsave(&device_domain_lock, flags);
3181         list_for_each_safe(entry, tmp, &domain->devices) {
3182                 info = list_entry(entry, struct device_domain_info, link);
3183                 /* No need to compare PCI domain; it has to be the same */
3184                 if (info->bus == pdev->bus->number &&
3185                     info->devfn == pdev->devfn) {
3186                         list_del(&info->link);
3187                         list_del(&info->global);
3188                         if (info->dev)
3189                                 info->dev->dev.archdata.iommu = NULL;
3190                         spin_unlock_irqrestore(&device_domain_lock, flags);
3191
3192                         iommu_disable_dev_iotlb(info);
3193                         iommu_detach_dev(iommu, info->bus, info->devfn);
3194                         iommu_detach_dependent_devices(iommu, pdev);
3195                         free_devinfo_mem(info);
3196
3197                         spin_lock_irqsave(&device_domain_lock, flags);
3198
3199                         if (found)
3200                                 break;
3201                         else
3202                                 continue;
3203                 }
3204
3205                 /* if there is no other devices under the same iommu
3206                  * owned by this domain, clear this iommu in iommu_bmp
3207                  * update iommu count and coherency
3208                  */
3209                 if (iommu == device_to_iommu(info->segment, info->bus,
3210                                             info->devfn))
3211                         found = 1;
3212         }
3213
3214         if (found == 0) {
3215                 unsigned long tmp_flags;
3216                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3217                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3218                 domain->iommu_count--;
3219                 domain_update_iommu_cap(domain);
3220                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3221         }
3222
3223         spin_unlock_irqrestore(&device_domain_lock, flags);
3224 }
3225
3226 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3227 {
3228         struct device_domain_info *info;
3229         struct intel_iommu *iommu;
3230         unsigned long flags1, flags2;
3231
3232         spin_lock_irqsave(&device_domain_lock, flags1);
3233         while (!list_empty(&domain->devices)) {
3234                 info = list_entry(domain->devices.next,
3235                         struct device_domain_info, link);
3236                 list_del(&info->link);
3237                 list_del(&info->global);
3238                 if (info->dev)
3239                         info->dev->dev.archdata.iommu = NULL;
3240
3241                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3242
3243                 iommu_disable_dev_iotlb(info);
3244                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3245                 iommu_detach_dev(iommu, info->bus, info->devfn);
3246                 iommu_detach_dependent_devices(iommu, info->dev);
3247
3248                 /* clear this iommu in iommu_bmp, update iommu count
3249                  * and capabilities
3250                  */
3251                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3252                 if (test_and_clear_bit(iommu->seq_id,
3253                                        &domain->iommu_bmp)) {
3254                         domain->iommu_count--;
3255                         domain_update_iommu_cap(domain);
3256                 }
3257                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3258
3259                 free_devinfo_mem(info);
3260                 spin_lock_irqsave(&device_domain_lock, flags1);
3261         }
3262         spin_unlock_irqrestore(&device_domain_lock, flags1);
3263 }
3264
3265 /* domain id for virtual machine, it won't be set in context */
3266 static unsigned long vm_domid;
3267
3268 static int vm_domain_min_agaw(struct dmar_domain *domain)
3269 {
3270         int i;
3271         int min_agaw = domain->agaw;
3272
3273         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3274         for (; i < g_num_of_iommus; ) {
3275                 if (min_agaw > g_iommus[i]->agaw)
3276                         min_agaw = g_iommus[i]->agaw;
3277
3278                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3279         }
3280
3281         return min_agaw;
3282 }
3283
3284 static struct dmar_domain *iommu_alloc_vm_domain(void)
3285 {
3286         struct dmar_domain *domain;
3287
3288         domain = alloc_domain_mem();
3289         if (!domain)
3290                 return NULL;
3291
3292         domain->id = vm_domid++;
3293         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3294         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3295
3296         return domain;
3297 }
3298
3299 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3300 {
3301         int adjust_width;
3302
3303         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3304         spin_lock_init(&domain->mapping_lock);
3305         spin_lock_init(&domain->iommu_lock);
3306
3307         domain_reserve_special_ranges(domain);
3308
3309         /* calculate AGAW */
3310         domain->gaw = guest_width;
3311         adjust_width = guestwidth_to_adjustwidth(guest_width);
3312         domain->agaw = width_to_agaw(adjust_width);
3313
3314         INIT_LIST_HEAD(&domain->devices);
3315
3316         domain->iommu_count = 0;
3317         domain->iommu_coherency = 0;
3318         domain->max_addr = 0;
3319
3320         /* always allocate the top pgd */
3321         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3322         if (!domain->pgd)
3323                 return -ENOMEM;
3324         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3325         return 0;
3326 }
3327
3328 static void iommu_free_vm_domain(struct dmar_domain *domain)
3329 {
3330         unsigned long flags;
3331         struct dmar_drhd_unit *drhd;
3332         struct intel_iommu *iommu;
3333         unsigned long i;
3334         unsigned long ndomains;
3335
3336         for_each_drhd_unit(drhd) {
3337                 if (drhd->ignored)
3338                         continue;
3339                 iommu = drhd->iommu;
3340
3341                 ndomains = cap_ndoms(iommu->cap);
3342                 i = find_first_bit(iommu->domain_ids, ndomains);
3343                 for (; i < ndomains; ) {
3344                         if (iommu->domains[i] == domain) {
3345                                 spin_lock_irqsave(&iommu->lock, flags);
3346                                 clear_bit(i, iommu->domain_ids);
3347                                 iommu->domains[i] = NULL;
3348                                 spin_unlock_irqrestore(&iommu->lock, flags);
3349                                 break;
3350                         }
3351                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3352                 }
3353         }
3354 }
3355
3356 static void vm_domain_exit(struct dmar_domain *domain)
3357 {
3358         /* Domain 0 is reserved, so dont process it */
3359         if (!domain)
3360                 return;
3361
3362         vm_domain_remove_all_dev_info(domain);
3363         /* destroy iovas */
3364         put_iova_domain(&domain->iovad);
3365
3366         /* clear ptes */
3367         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3368
3369         /* free page tables */
3370         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3371
3372         iommu_free_vm_domain(domain);
3373         free_domain_mem(domain);
3374 }
3375
3376 static int intel_iommu_domain_init(struct iommu_domain *domain)
3377 {
3378         struct dmar_domain *dmar_domain;
3379
3380         dmar_domain = iommu_alloc_vm_domain();
3381         if (!dmar_domain) {
3382                 printk(KERN_ERR
3383                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3384                 return -ENOMEM;
3385         }
3386         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3387                 printk(KERN_ERR
3388                         "intel_iommu_domain_init() failed\n");
3389                 vm_domain_exit(dmar_domain);
3390                 return -ENOMEM;
3391         }
3392         domain->priv = dmar_domain;
3393
3394         return 0;
3395 }
3396
3397 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3398 {
3399         struct dmar_domain *dmar_domain = domain->priv;
3400
3401         domain->priv = NULL;
3402         vm_domain_exit(dmar_domain);
3403 }
3404
3405 static int intel_iommu_attach_device(struct iommu_domain *domain,
3406                                      struct device *dev)
3407 {
3408         struct dmar_domain *dmar_domain = domain->priv;
3409         struct pci_dev *pdev = to_pci_dev(dev);
3410         struct intel_iommu *iommu;
3411         int addr_width;
3412         u64 end;
3413         int ret;
3414
3415         /* normally pdev is not mapped */
3416         if (unlikely(domain_context_mapped(pdev))) {
3417                 struct dmar_domain *old_domain;
3418
3419                 old_domain = find_domain(pdev);
3420                 if (old_domain) {
3421                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3422                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3423                                 domain_remove_one_dev_info(old_domain, pdev);
3424                         else
3425                                 domain_remove_dev_info(old_domain);
3426                 }
3427         }
3428
3429         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3430                                 pdev->devfn);
3431         if (!iommu)
3432                 return -ENODEV;
3433
3434         /* check if this iommu agaw is sufficient for max mapped address */
3435         addr_width = agaw_to_width(iommu->agaw);
3436         end = DOMAIN_MAX_ADDR(addr_width);
3437         end = end & VTD_PAGE_MASK;
3438         if (end < dmar_domain->max_addr) {
3439                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3440                        "sufficient for the mapped address (%llx)\n",
3441                        __func__, iommu->agaw, dmar_domain->max_addr);
3442                 return -EFAULT;
3443         }
3444
3445         ret = domain_add_dev_info(dmar_domain, pdev);
3446         if (ret)
3447                 return ret;
3448
3449         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3450         return ret;
3451 }
3452
3453 static void intel_iommu_detach_device(struct iommu_domain *domain,
3454                                       struct device *dev)
3455 {
3456         struct dmar_domain *dmar_domain = domain->priv;
3457         struct pci_dev *pdev = to_pci_dev(dev);
3458
3459         domain_remove_one_dev_info(dmar_domain, pdev);
3460 }
3461
3462 static int intel_iommu_map_range(struct iommu_domain *domain,
3463                                  unsigned long iova, phys_addr_t hpa,
3464                                  size_t size, int iommu_prot)
3465 {
3466         struct dmar_domain *dmar_domain = domain->priv;
3467         u64 max_addr;
3468         int addr_width;
3469         int prot = 0;
3470         int ret;
3471
3472         if (iommu_prot & IOMMU_READ)
3473                 prot |= DMA_PTE_READ;
3474         if (iommu_prot & IOMMU_WRITE)
3475                 prot |= DMA_PTE_WRITE;
3476         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3477                 prot |= DMA_PTE_SNP;
3478
3479         max_addr = iova + size;
3480         if (dmar_domain->max_addr < max_addr) {
3481                 int min_agaw;
3482                 u64 end;
3483
3484                 /* check if minimum agaw is sufficient for mapped address */
3485                 min_agaw = vm_domain_min_agaw(dmar_domain);
3486                 addr_width = agaw_to_width(min_agaw);
3487                 end = DOMAIN_MAX_ADDR(addr_width);
3488                 end = end & VTD_PAGE_MASK;
3489                 if (end < max_addr) {
3490                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3491                                "sufficient for the mapped address (%llx)\n",
3492                                __func__, min_agaw, max_addr);
3493                         return -EFAULT;
3494                 }
3495                 dmar_domain->max_addr = max_addr;
3496         }
3497         /* Round up size to next multiple of PAGE_SIZE, if it and
3498            the low bits of hpa would take us onto the next page */
3499         size = aligned_nrpages(hpa, size);
3500         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3501                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3502         return ret;
3503 }
3504
3505 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3506                                     unsigned long iova, size_t size)
3507 {
3508         struct dmar_domain *dmar_domain = domain->priv;
3509
3510         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3511                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3512
3513         if (dmar_domain->max_addr == iova + size)
3514                 dmar_domain->max_addr = iova;
3515 }
3516
3517 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3518                                             unsigned long iova)
3519 {
3520         struct dmar_domain *dmar_domain = domain->priv;
3521         struct dma_pte *pte;
3522         u64 phys = 0;
3523
3524         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3525         if (pte)
3526                 phys = dma_pte_addr(pte);
3527
3528         return phys;
3529 }
3530
3531 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3532                                       unsigned long cap)
3533 {
3534         struct dmar_domain *dmar_domain = domain->priv;
3535
3536         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3537                 return dmar_domain->iommu_snooping;
3538
3539         return 0;
3540 }
3541
3542 static struct iommu_ops intel_iommu_ops = {
3543         .domain_init    = intel_iommu_domain_init,
3544         .domain_destroy = intel_iommu_domain_destroy,
3545         .attach_dev     = intel_iommu_attach_device,
3546         .detach_dev     = intel_iommu_detach_device,
3547         .map            = intel_iommu_map_range,
3548         .unmap          = intel_iommu_unmap_range,
3549         .iova_to_phys   = intel_iommu_iova_to_phys,
3550         .domain_has_cap = intel_iommu_domain_has_cap,
3551 };
3552
3553 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3554 {
3555         /*
3556          * Mobile 4 Series Chipset neglects to set RWBF capability,
3557          * but needs it:
3558          */
3559         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3560         rwbf_quirk = 1;
3561 }
3562
3563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);