drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/aer.h>
   8 #include <linux/async.h>
   9 #include <linux/blkdev.h>
  10 #include <linux/blk-mq.h>
  11 #include <linux/blk-mq-pci.h>
  12 #include <linux/dmi.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/mm.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <linux/once.h>
  20 #include <linux/pci.h>
  21 #include <linux/t10-pi.h>
  22 #include <linux/types.h>
  23 #include <linux/io-64-nonatomic-lo-hi.h>
  24 #include <linux/sed-opal.h>
  25 #include <linux/pci-p2pdma.h>
  26
  27 #include "trace.h"
  28 #include "nvme.h"
  29
  30 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  31 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  32
  33 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  34
  35 /*
  36  * These can be higher, but we need to ensure that any command doesn't
  37  * require an sg allocation that needs more than a page of data.
  38  */
  39 #define NVME_MAX_KB_SZ  4096
  40 #define NVME_MAX_SEGS   127
  41
  42 static int use_threaded_interrupts;
  43 module_param(use_threaded_interrupts, int, 0);
  44
  45 static bool use_cmb_sqes = true;
  46 module_param(use_cmb_sqes, bool, 0444);
  47 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  48
  49 static unsigned int max_host_mem_size_mb = 128;
  50 module_param(max_host_mem_size_mb, uint, 0444);
  51 MODULE_PARM_DESC(max_host_mem_size_mb,
  52         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  53
  54 static unsigned int sgl_threshold = SZ_32K;
  55 module_param(sgl_threshold, uint, 0644);
  56 MODULE_PARM_DESC(sgl_threshold,
  57                 "Use SGLs when average request segment size is larger or equal to "
  58                 "this size. Use 0 to disable SGLs.");
  59
  60 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  61 static const struct kernel_param_ops io_queue_depth_ops = {
  62         .set = io_queue_depth_set,
  63         .get = param_get_int,
  64 };
  65
  66 static int io_queue_depth = 1024;
  67 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  68 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  69
  70 static int queue_count_set(const char *val, const struct kernel_param *kp);
  71 static const struct kernel_param_ops queue_count_ops = {
  72         .set = queue_count_set,
  73         .get = param_get_int,
  74 };
  75
  76 static int write_queues;
  77 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
  78 MODULE_PARM_DESC(write_queues,
  79         "Number of queues to use for writes. If not set, reads and writes "
  80         "will share a queue set.");
  81
  82 static int poll_queues = 0;
  83 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
  84 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  85
  86 struct nvme_dev;
  87 struct nvme_queue;
  88
  89 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  90 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
  91
  92 /*
  93  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  94  */
  95 struct nvme_dev {
  96         struct nvme_queue *queues;
  97         struct blk_mq_tag_set tagset;
  98         struct blk_mq_tag_set admin_tagset;
  99         u32 __iomem *dbs;
 100         struct device *dev;
 101         struct dma_pool *prp_page_pool;
 102         struct dma_pool *prp_small_pool;
 103         unsigned online_queues;
 104         unsigned max_qid;
 105         unsigned io_queues[HCTX_MAX_TYPES];
 106         unsigned int num_vecs;
 107         int q_depth;
 108         u32 db_stride;
 109         void __iomem *bar;
 110         unsigned long bar_mapped_size;
 111         struct work_struct remove_work;
 112         struct mutex shutdown_lock;
 113         bool subsystem;
 114         u64 cmb_size;
 115         bool cmb_use_sqes;
 116         u32 cmbsz;
 117         u32 cmbloc;
 118         struct nvme_ctrl ctrl;
 119
 120         mempool_t *iod_mempool;
 121
 122         /* shadow doorbell buffer support: */
 123         u32 *dbbuf_dbs;
 124         dma_addr_t dbbuf_dbs_dma_addr;
 125         u32 *dbbuf_eis;
 126         dma_addr_t dbbuf_eis_dma_addr;
 127
 128         /* host memory buffer support: */
 129         u64 host_mem_size;
 130         u32 nr_host_mem_descs;
 131         dma_addr_t host_mem_descs_dma;
 132         struct nvme_host_mem_buf_desc *host_mem_descs;
 133         void **host_mem_desc_bufs;
 134 };
 135
 136 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 137 {
 138         int n = 0, ret;
 139
 140         ret = kstrtoint(val, 10, &n);
 141         if (ret != 0 || n < 2)
 142                 return -EINVAL;
 143
 144         return param_set_int(val, kp);
 145 }
 146
 147 static int queue_count_set(const char *val, const struct kernel_param *kp)
 148 {
 149         int n = 0, ret;
 150
 151         ret = kstrtoint(val, 10, &n);
 152         if (ret)
 153                 return ret;
 154         if (n > num_possible_cpus())
 155                 n = num_possible_cpus();
 156
 157         return param_set_int(val, kp);
 158 }
 159
 160 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 161 {
 162         return qid * 2 * stride;
 163 }
 164
 165 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 166 {
 167         return (qid * 2 + 1) * stride;
 168 }
 169
 170 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 171 {
 172         return container_of(ctrl, struct nvme_dev, ctrl);
 173 }
 174
 175 /*
 176  * An NVM Express queue.  Each device has at least two (one for admin
 177  * commands and one for I/O commands).
 178  */
 179 struct nvme_queue {
 180         struct device *q_dmadev;
 181         struct nvme_dev *dev;
 182         spinlock_t sq_lock;
 183         struct nvme_command *sq_cmds;
 184          /* only used for poll queues: */
 185         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 186         volatile struct nvme_completion *cqes;
 187         struct blk_mq_tags **tags;
 188         dma_addr_t sq_dma_addr;
 189         dma_addr_t cq_dma_addr;
 190         u32 __iomem *q_db;
 191         u16 q_depth;
 192         s16 cq_vector;
 193         u16 sq_tail;
 194         u16 last_sq_tail;
 195         u16 cq_head;
 196         u16 last_cq_head;
 197         u16 qid;
 198         u8 cq_phase;
 199         unsigned long flags;
 200 #define NVMEQ_ENABLED           0
 201 #define NVMEQ_SQ_CMB            1
 202 #define NVMEQ_DELETE_ERROR      2
 203         u32 *dbbuf_sq_db;
 204         u32 *dbbuf_cq_db;
 205         u32 *dbbuf_sq_ei;
 206         u32 *dbbuf_cq_ei;
 207         struct completion delete_done;
 208 };
 209
 210 /*
 211  * The nvme_iod describes the data in an I/O, including the list of PRP
 212  * entries.  You can't see it in this data structure because C doesn't let
 213  * me express that.  Use nvme_init_iod to ensure there's enough space
 214  * allocated to store the PRP list.
 215  */
 216 struct nvme_iod {
 217         struct nvme_request req;
 218         struct nvme_queue *nvmeq;
 219         bool use_sgl;
 220         int aborted;
 221         int npages;             /* In the PRP list. 0 means small pool in use */
 222         int nents;              /* Used in scatterlist */
 223         int length;             /* Of data, in bytes */
 224         dma_addr_t first_dma;
 225         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 226         struct scatterlist *sg;
 227         struct scatterlist inline_sg[0];
 228 };
 229
 230 /*
 231  * Check we didin't inadvertently grow the command struct
 232  */
 233 static inline void _nvme_check_size(void)
 234 {
 235         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 236         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 237         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 238         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 239         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 240         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 241         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 242         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 243         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 244         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 245         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 246         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 247         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 248 }
 249
 250 static unsigned int max_io_queues(void)
 251 {
 252         return num_possible_cpus() + write_queues + poll_queues;
 253 }
 254
 255 static unsigned int max_queue_count(void)
 256 {
 257         /* IO queues + admin queue */
 258         return 1 + max_io_queues();
 259 }
 260
 261 static inline unsigned int nvme_dbbuf_size(u32 stride)
 262 {
 263         return (max_queue_count() * 8 * stride);
 264 }
 265
 266 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 267 {
 268         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 269
 270         if (dev->dbbuf_dbs)
 271                 return 0;
 272
 273         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 274                                             &dev->dbbuf_dbs_dma_addr,
 275                                             GFP_KERNEL);
 276         if (!dev->dbbuf_dbs)
 277                 return -ENOMEM;
 278         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 279                                             &dev->dbbuf_eis_dma_addr,
 280                                             GFP_KERNEL);
 281         if (!dev->dbbuf_eis) {
 282                 dma_free_coherent(dev->dev, mem_size,
 283                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 284                 dev->dbbuf_dbs = NULL;
 285                 return -ENOMEM;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 292 {
 293         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 294
 295         if (dev->dbbuf_dbs) {
 296                 dma_free_coherent(dev->dev, mem_size,
 297                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 298                 dev->dbbuf_dbs = NULL;
 299         }
 300         if (dev->dbbuf_eis) {
 301                 dma_free_coherent(dev->dev, mem_size,
 302                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 303                 dev->dbbuf_eis = NULL;
 304         }
 305 }
 306
 307 static void nvme_dbbuf_init(struct nvme_dev *dev,
 308                             struct nvme_queue *nvmeq, int qid)
 309 {
 310         if (!dev->dbbuf_dbs || !qid)
 311                 return;
 312
 313         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 314         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 315         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 316         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 317 }
 318
 319 static void nvme_dbbuf_set(struct nvme_dev *dev)
 320 {
 321         struct nvme_command c;
 322
 323         if (!dev->dbbuf_dbs)
 324                 return;
 325
 326         memset(&c, 0, sizeof(c));
 327         c.dbbuf.opcode = nvme_admin_dbbuf;
 328         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 329         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 330
 331         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 332                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 333                 /* Free memory and continue on */
 334                 nvme_dbbuf_dma_free(dev);
 335         }
 336 }
 337
 338 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 339 {
 340         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 341 }
 342
 343 /* Update dbbuf and return true if an MMIO is required */
 344 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 345                                               volatile u32 *dbbuf_ei)
 346 {
 347         if (dbbuf_db) {
 348                 u16 old_value;
 349
 350                 /*
 351                  * Ensure that the queue is written before updating
 352                  * the doorbell in memory
 353                  */
 354                 wmb();
 355
 356                 old_value = *dbbuf_db;
 357                 *dbbuf_db = value;
 358
 359                 /*
 360                  * Ensure that the doorbell is updated before reading the event
 361                  * index from memory.  The controller needs to provide similar
 362                  * ordering to ensure the envent index is updated before reading
 363                  * the doorbell.
 364                  */
 365                 mb();
 366
 367                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 368                         return false;
 369         }
 370
 371         return true;
 372 }
 373
 374 /*
 375  * Max size of iod being embedded in the request payload
 376  */
 377 #define NVME_INT_PAGES          2
 378 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 379
 380 /*
 381  * Will slightly overestimate the number of pages needed.  This is OK
 382  * as it only leads to a small amount of wasted memory for the lifetime of
 383  * the I/O.
 384  */
 385 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 386 {
 387         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 388                                       dev->ctrl.page_size);
 389         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 390 }
 391
 392 /*
 393  * Calculates the number of pages needed for the SGL segments. For example a 4k
 394  * page can accommodate 256 SGL descriptors.
 395  */
 396 static int nvme_pci_npages_sgl(unsigned int num_seg)
 397 {
 398         return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
 399 }
 400
 401 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
 402                 unsigned int size, unsigned int nseg, bool use_sgl)
 403 {
 404         size_t alloc_size;
 405
 406         if (use_sgl)
 407                 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
 408         else
 409                 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
 410
 411         return alloc_size + sizeof(struct scatterlist) * nseg;
 412 }
 413
 414 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
 415 {
 416         unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
 417                                     NVME_INT_BYTES(dev), NVME_INT_PAGES,
 418                                     use_sgl);
 419
 420         return sizeof(struct nvme_iod) + alloc_size;
 421 }
 422
 423 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 424                                 unsigned int hctx_idx)
 425 {
 426         struct nvme_dev *dev = data;
 427         struct nvme_queue *nvmeq = &dev->queues[0];
 428
 429         WARN_ON(hctx_idx != 0);
 430         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 431         WARN_ON(nvmeq->tags);
 432
 433         hctx->driver_data = nvmeq;
 434         nvmeq->tags = &dev->admin_tagset.tags[0];
 435         return 0;
 436 }
 437
 438 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 439 {
 440         struct nvme_queue *nvmeq = hctx->driver_data;
 441
 442         nvmeq->tags = NULL;
 443 }
 444
 445 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 446                           unsigned int hctx_idx)
 447 {
 448         struct nvme_dev *dev = data;
 449         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 450
 451         if (!nvmeq->tags)
 452                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 453
 454         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 455         hctx->driver_data = nvmeq;
 456         return 0;
 457 }
 458
 459 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 460                 unsigned int hctx_idx, unsigned int numa_node)
 461 {
 462         struct nvme_dev *dev = set->driver_data;
 463         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 464         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 465         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 466
 467         BUG_ON(!nvmeq);
 468         iod->nvmeq = nvmeq;
 469
 470         nvme_req(req)->ctrl = &dev->ctrl;
 471         return 0;
 472 }
 473
 474 static int queue_irq_offset(struct nvme_dev *dev)
 475 {
 476         /* if we have more than 1 vec, admin queue offsets us by 1 */
 477         if (dev->num_vecs > 1)
 478                 return 1;
 479
 480         return 0;
 481 }
 482
 483 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 484 {
 485         struct nvme_dev *dev = set->driver_data;
 486         int i, qoff, offset;
 487
 488         offset = queue_irq_offset(dev);
 489         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 490                 struct blk_mq_queue_map *map = &set->map[i];
 491
 492                 map->nr_queues = dev->io_queues[i];
 493                 if (!map->nr_queues) {
 494                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 495                         continue;
 496                 }
 497
 498                 /*
 499                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 500                  * affinity), so use the regular blk-mq cpu mapping
 501                  */
 502                 map->queue_offset = qoff;
 503                 if (i != HCTX_TYPE_POLL)
 504                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 505                 else
 506                         blk_mq_map_queues(map);
 507                 qoff += map->nr_queues;
 508                 offset += map->nr_queues;
 509         }
 510
 511         return 0;
 512 }
 513
 514 /*
 515  * Write sq tail if we are asked to, or if the next command would wrap.
 516  */
 517 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 518 {
 519         if (!write_sq) {
 520                 u16 next_tail = nvmeq->sq_tail + 1;
 521
 522                 if (next_tail == nvmeq->q_depth)
 523                         next_tail = 0;
 524                 if (next_tail != nvmeq->last_sq_tail)
 525                         return;
 526         }
 527
 528         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 529                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 530                 writel(nvmeq->sq_tail, nvmeq->q_db);
 531         nvmeq->last_sq_tail = nvmeq->sq_tail;
 532 }
 533
 534 /**
 535  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 536  * @nvmeq: The queue to use
 537  * @cmd: The command to send
 538  * @write_sq: whether to write to the SQ doorbell
 539  */
 540 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 541                             bool write_sq)
 542 {
 543         spin_lock(&nvmeq->sq_lock);
 544         memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
 545         if (++nvmeq->sq_tail == nvmeq->q_depth)
 546                 nvmeq->sq_tail = 0;
 547         nvme_write_sq_db(nvmeq, write_sq);
 548         spin_unlock(&nvmeq->sq_lock);
 549 }
 550
 551 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 552 {
 553         struct nvme_queue *nvmeq = hctx->driver_data;
 554
 555         spin_lock(&nvmeq->sq_lock);
 556         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 557                 nvme_write_sq_db(nvmeq, true);
 558         spin_unlock(&nvmeq->sq_lock);
 559 }
 560
 561 static void **nvme_pci_iod_list(struct request *req)
 562 {
 563         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 564         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 565 }
 566
 567 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 568 {
 569         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 570         int nseg = blk_rq_nr_phys_segments(req);
 571         unsigned int avg_seg_size;
 572
 573         if (nseg == 0)
 574                 return false;
 575
 576         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 577
 578         if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
 579                 return false;
 580         if (!iod->nvmeq->qid)
 581                 return false;
 582         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 583                 return false;
 584         return true;
 585 }
 586
 587 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 588 {
 589         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 590         int nseg = blk_rq_nr_phys_segments(rq);
 591         unsigned int size = blk_rq_payload_bytes(rq);
 592
 593         iod->use_sgl = nvme_pci_use_sgls(dev, rq);
 594
 595         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 596                 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 597                 if (!iod->sg)
 598                         return BLK_STS_RESOURCE;
 599         } else {
 600                 iod->sg = iod->inline_sg;
 601         }
 602
 603         iod->aborted = 0;
 604         iod->npages = -1;
 605         iod->nents = 0;
 606         iod->length = size;
 607
 608         return BLK_STS_OK;
 609 }
 610
 611 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 612 {
 613         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 614         const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
 615         dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
 616
 617         int i;
 618
 619         if (iod->npages == 0)
 620                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 621                         dma_addr);
 622
 623         for (i = 0; i < iod->npages; i++) {
 624                 void *addr = nvme_pci_iod_list(req)[i];
 625
 626                 if (iod->use_sgl) {
 627                         struct nvme_sgl_desc *sg_list = addr;
 628
 629                         next_dma_addr =
 630                             le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
 631                 } else {
 632                         __le64 *prp_list = addr;
 633
 634                         next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 635                 }
 636
 637                 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
 638                 dma_addr = next_dma_addr;
 639         }
 640
 641         if (iod->sg != iod->inline_sg)
 642                 mempool_free(iod->sg, dev->iod_mempool);
 643 }
 644
 645 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 646 {
 647         int i;
 648         struct scatterlist *sg;
 649
 650         for_each_sg(sgl, sg, nents, i) {
 651                 dma_addr_t phys = sg_phys(sg);
 652                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 653                         "dma_address:%pad dma_length:%d\n",
 654                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 655                         sg_dma_len(sg));
 656         }
 657 }
 658
 659 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 660                 struct request *req, struct nvme_rw_command *cmnd)
 661 {
 662         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 663         struct dma_pool *pool;
 664         int length = blk_rq_payload_bytes(req);
 665         struct scatterlist *sg = iod->sg;
 666         int dma_len = sg_dma_len(sg);
 667         u64 dma_addr = sg_dma_address(sg);
 668         u32 page_size = dev->ctrl.page_size;
 669         int offset = dma_addr & (page_size - 1);
 670         __le64 *prp_list;
 671         void **list = nvme_pci_iod_list(req);
 672         dma_addr_t prp_dma;
 673         int nprps, i;
 674
 675         length -= (page_size - offset);
 676         if (length <= 0) {
 677                 iod->first_dma = 0;
 678                 goto done;
 679         }
 680
 681         dma_len -= (page_size - offset);
 682         if (dma_len) {
 683                 dma_addr += (page_size - offset);
 684         } else {
 685                 sg = sg_next(sg);
 686                 dma_addr = sg_dma_address(sg);
 687                 dma_len = sg_dma_len(sg);
 688         }
 689
 690         if (length <= page_size) {
 691                 iod->first_dma = dma_addr;
 692                 goto done;
 693         }
 694
 695         nprps = DIV_ROUND_UP(length, page_size);
 696         if (nprps <= (256 / 8)) {
 697                 pool = dev->prp_small_pool;
 698                 iod->npages = 0;
 699         } else {
 700                 pool = dev->prp_page_pool;
 701                 iod->npages = 1;
 702         }
 703
 704         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 705         if (!prp_list) {
 706                 iod->first_dma = dma_addr;
 707                 iod->npages = -1;
 708                 return BLK_STS_RESOURCE;
 709         }
 710         list[0] = prp_list;
 711         iod->first_dma = prp_dma;
 712         i = 0;
 713         for (;;) {
 714                 if (i == page_size >> 3) {
 715                         __le64 *old_prp_list = prp_list;
 716                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 717                         if (!prp_list)
 718                                 return BLK_STS_RESOURCE;
 719                         list[iod->npages++] = prp_list;
 720                         prp_list[0] = old_prp_list[i - 1];
 721                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 722                         i = 1;
 723                 }
 724                 prp_list[i++] = cpu_to_le64(dma_addr);
 725                 dma_len -= page_size;
 726                 dma_addr += page_size;
 727                 length -= page_size;
 728                 if (length <= 0)
 729                         break;
 730                 if (dma_len > 0)
 731                         continue;
 732                 if (unlikely(dma_len < 0))
 733                         goto bad_sgl;
 734                 sg = sg_next(sg);
 735                 dma_addr = sg_dma_address(sg);
 736                 dma_len = sg_dma_len(sg);
 737         }
 738
 739 done:
 740         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 741         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 742
 743         return BLK_STS_OK;
 744
 745  bad_sgl:
 746         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 747                         "Invalid SGL for payload:%d nents:%d\n",
 748                         blk_rq_payload_bytes(req), iod->nents);
 749         return BLK_STS_IOERR;
 750 }
 751
 752 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 753                 struct scatterlist *sg)
 754 {
 755         sge->addr = cpu_to_le64(sg_dma_address(sg));
 756         sge->length = cpu_to_le32(sg_dma_len(sg));
 757         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 758 }
 759
 760 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 761                 dma_addr_t dma_addr, int entries)
 762 {
 763         sge->addr = cpu_to_le64(dma_addr);
 764         if (entries < SGES_PER_PAGE) {
 765                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 766                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 767         } else {
 768                 sge->length = cpu_to_le32(PAGE_SIZE);
 769                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 770         }
 771 }
 772
 773 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 774                 struct request *req, struct nvme_rw_command *cmd, int entries)
 775 {
 776         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 777         struct dma_pool *pool;
 778         struct nvme_sgl_desc *sg_list;
 779         struct scatterlist *sg = iod->sg;
 780         dma_addr_t sgl_dma;
 781         int i = 0;
 782
 783         /* setting the transfer type as SGL */
 784         cmd->flags = NVME_CMD_SGL_METABUF;
 785
 786         if (entries == 1) {
 787                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 788                 return BLK_STS_OK;
 789         }
 790
 791         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 792                 pool = dev->prp_small_pool;
 793                 iod->npages = 0;
 794         } else {
 795                 pool = dev->prp_page_pool;
 796                 iod->npages = 1;
 797         }
 798
 799         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 800         if (!sg_list) {
 801                 iod->npages = -1;
 802                 return BLK_STS_RESOURCE;
 803         }
 804
 805         nvme_pci_iod_list(req)[0] = sg_list;
 806         iod->first_dma = sgl_dma;
 807
 808         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 809
 810         do {
 811                 if (i == SGES_PER_PAGE) {
 812                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 813                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 814
 815                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 816                         if (!sg_list)
 817                                 return BLK_STS_RESOURCE;
 818
 819                         i = 0;
 820                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 821                         sg_list[i++] = *link;
 822                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 823                 }
 824
 825                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 826                 sg = sg_next(sg);
 827         } while (--entries > 0);
 828
 829         return BLK_STS_OK;
 830 }
 831
 832 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 833                 struct nvme_command *cmnd)
 834 {
 835         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 836         struct request_queue *q = req->q;
 837         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 838                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 839         blk_status_t ret = BLK_STS_IOERR;
 840         int nr_mapped;
 841
 842         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 843         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 844         if (!iod->nents)
 845                 goto out;
 846
 847         ret = BLK_STS_RESOURCE;
 848
 849         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 850                 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
 851                                           dma_dir);
 852         else
 853                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 854                                              dma_dir,  DMA_ATTR_NO_WARN);
 855         if (!nr_mapped)
 856                 goto out;
 857
 858         if (iod->use_sgl)
 859                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 860         else
 861                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 862
 863         if (ret != BLK_STS_OK)
 864                 goto out_unmap;
 865
 866         ret = BLK_STS_IOERR;
 867         if (blk_integrity_rq(req)) {
 868                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 869                         goto out_unmap;
 870
 871                 sg_init_table(&iod->meta_sg, 1);
 872                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 873                         goto out_unmap;
 874
 875                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 876                         goto out_unmap;
 877
 878                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 879         }
 880
 881         return BLK_STS_OK;
 882
 883 out_unmap:
 884         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 885 out:
 886         return ret;
 887 }
 888
 889 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 890 {
 891         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 892         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 893                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 894
 895         if (iod->nents) {
 896                 /* P2PDMA requests do not need to be unmapped */
 897                 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
 898                         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 899
 900                 if (blk_integrity_rq(req))
 901                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 902         }
 903
 904         nvme_cleanup_cmd(req);
 905         nvme_free_iod(dev, req);
 906 }
 907
 908 /*
 909  * NOTE: ns is NULL when called on the admin queue.
 910  */
 911 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 912                          const struct blk_mq_queue_data *bd)
 913 {
 914         struct nvme_ns *ns = hctx->queue->queuedata;
 915         struct nvme_queue *nvmeq = hctx->driver_data;
 916         struct nvme_dev *dev = nvmeq->dev;
 917         struct request *req = bd->rq;
 918         struct nvme_command cmnd;
 919         blk_status_t ret;
 920
 921         /*
 922          * We should not need to do this, but we're still using this to
 923          * ensure we can drain requests on a dying queue.
 924          */
 925         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 926                 return BLK_STS_IOERR;
 927
 928         ret = nvme_setup_cmd(ns, req, &cmnd);
 929         if (ret)
 930                 return ret;
 931
 932         ret = nvme_init_iod(req, dev);
 933         if (ret)
 934                 goto out_free_cmd;
 935
 936         if (blk_rq_nr_phys_segments(req)) {
 937                 ret = nvme_map_data(dev, req, &cmnd);
 938                 if (ret)
 939                         goto out_cleanup_iod;
 940         }
 941
 942         blk_mq_start_request(req);
 943         nvme_submit_cmd(nvmeq, &cmnd, bd->last);
 944         return BLK_STS_OK;
 945 out_cleanup_iod:
 946         nvme_free_iod(dev, req);
 947 out_free_cmd:
 948         nvme_cleanup_cmd(req);
 949         return ret;
 950 }
 951
 952 static void nvme_pci_complete_rq(struct request *req)
 953 {
 954         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 955
 956         nvme_unmap_data(iod->nvmeq->dev, req);
 957         nvme_complete_rq(req);
 958 }
 959
 960 /* We read the CQE phase first to check if the rest of the entry is valid */
 961 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 962 {
 963         return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 964                         nvmeq->cq_phase;
 965 }
 966
 967 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 968 {
 969         u16 head = nvmeq->cq_head;
 970
 971         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 972                                               nvmeq->dbbuf_cq_ei))
 973                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 974 }
 975
 976 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 977 {
 978         volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
 979         struct request *req;
 980
 981         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
 982                 dev_warn(nvmeq->dev->ctrl.device,
 983                         "invalid id %d completed on queue %d\n",
 984                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 985                 return;
 986         }
 987
 988         /*
 989          * AEN requests are special as they don't time out and can
 990          * survive any kind of queue freeze and often don't respond to
 991          * aborts.  We don't even bother to allocate a struct request
 992          * for them but rather special case them here.
 993          */
 994         if (unlikely(nvmeq->qid == 0 &&
 995                         cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
 996                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 997                                 cqe->status, &cqe->result);
 998                 return;
 999         }
1000
1001         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1002         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1003         nvme_end_request(req, cqe->status, cqe->result);
1004 }
1005
1006 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
1007 {
1008         while (start != end) {
1009                 nvme_handle_cqe(nvmeq, start);
1010                 if (++start == nvmeq->q_depth)
1011                         start = 0;
1012         }
1013 }
1014
1015 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1016 {
1017         if (nvmeq->cq_head == nvmeq->q_depth - 1) {
1018                 nvmeq->cq_head = 0;
1019                 nvmeq->cq_phase = !nvmeq->cq_phase;
1020         } else {
1021                 nvmeq->cq_head++;
1022         }
1023 }
1024
1025 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1026                                   u16 *end, unsigned int tag)
1027 {
1028         int found = 0;
1029
1030         *start = nvmeq->cq_head;
1031         while (nvme_cqe_pending(nvmeq)) {
1032                 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1033                         found++;
1034                 nvme_update_cq_head(nvmeq);
1035         }
1036         *end = nvmeq->cq_head;
1037
1038         if (*start != *end)
1039                 nvme_ring_cq_doorbell(nvmeq);
1040         return found;
1041 }
1042
1043 static irqreturn_t nvme_irq(int irq, void *data)
1044 {
1045         struct nvme_queue *nvmeq = data;
1046         irqreturn_t ret = IRQ_NONE;
1047         u16 start, end;
1048
1049         /*
1050          * The rmb/wmb pair ensures we see all updates from a previous run of
1051          * the irq handler, even if that was on another CPU.
1052          */
1053         rmb();
1054         if (nvmeq->cq_head != nvmeq->last_cq_head)
1055                 ret = IRQ_HANDLED;
1056         nvme_process_cq(nvmeq, &start, &end, -1);
1057         nvmeq->last_cq_head = nvmeq->cq_head;
1058         wmb();
1059
1060         if (start != end) {
1061                 nvme_complete_cqes(nvmeq, start, end);
1062                 return IRQ_HANDLED;
1063         }
1064
1065         return ret;
1066 }
1067
1068 static irqreturn_t nvme_irq_check(int irq, void *data)
1069 {
1070         struct nvme_queue *nvmeq = data;
1071         if (nvme_cqe_pending(nvmeq))
1072                 return IRQ_WAKE_THREAD;
1073         return IRQ_NONE;
1074 }
1075
1076 /*
1077  * Poll for completions any queue, including those not dedicated to polling.
1078  * Can be called from any context.
1079  */
1080 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
1081 {
1082         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1083         u16 start, end;
1084         int found;
1085
1086         /*
1087          * For a poll queue we need to protect against the polling thread
1088          * using the CQ lock.  For normal interrupt driven threads we have
1089          * to disable the interrupt to avoid racing with it.
1090          */
1091         if (nvmeq->cq_vector == -1) {
1092                 spin_lock(&nvmeq->cq_poll_lock);
1093                 found = nvme_process_cq(nvmeq, &start, &end, tag);
1094                 spin_unlock(&nvmeq->cq_poll_lock);
1095         } else {
1096                 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1097                 found = nvme_process_cq(nvmeq, &start, &end, tag);
1098                 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1099         }
1100
1101         nvme_complete_cqes(nvmeq, start, end);
1102         return found;
1103 }
1104
1105 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1106 {
1107         struct nvme_queue *nvmeq = hctx->driver_data;
1108         u16 start, end;
1109         bool found;
1110
1111         if (!nvme_cqe_pending(nvmeq))
1112                 return 0;
1113
1114         spin_lock(&nvmeq->cq_poll_lock);
1115         found = nvme_process_cq(nvmeq, &start, &end, -1);
1116         spin_unlock(&nvmeq->cq_poll_lock);
1117
1118         nvme_complete_cqes(nvmeq, start, end);
1119         return found;
1120 }
1121
1122 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1123 {
1124         struct nvme_dev *dev = to_nvme_dev(ctrl);
1125         struct nvme_queue *nvmeq = &dev->queues[0];
1126         struct nvme_command c;
1127
1128         memset(&c, 0, sizeof(c));
1129         c.common.opcode = nvme_admin_async_event;
1130         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1131         nvme_submit_cmd(nvmeq, &c, true);
1132 }
1133
1134 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1135 {
1136         struct nvme_command c;
1137
1138         memset(&c, 0, sizeof(c));
1139         c.delete_queue.opcode = opcode;
1140         c.delete_queue.qid = cpu_to_le16(id);
1141
1142         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1143 }
1144
1145 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1146                 struct nvme_queue *nvmeq, s16 vector)
1147 {
1148         struct nvme_command c;
1149         int flags = NVME_QUEUE_PHYS_CONTIG;
1150
1151         if (vector != -1)
1152                 flags |= NVME_CQ_IRQ_ENABLED;
1153
1154         /*
1155          * Note: we (ab)use the fact that the prp fields survive if no data
1156          * is attached to the request.
1157          */
1158         memset(&c, 0, sizeof(c));
1159         c.create_cq.opcode = nvme_admin_create_cq;
1160         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1161         c.create_cq.cqid = cpu_to_le16(qid);
1162         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1163         c.create_cq.cq_flags = cpu_to_le16(flags);
1164         if (vector != -1)
1165                 c.create_cq.irq_vector = cpu_to_le16(vector);
1166         else
1167                 c.create_cq.irq_vector = 0;
1168
1169         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1170 }
1171
1172 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1173                                                 struct nvme_queue *nvmeq)
1174 {
1175         struct nvme_ctrl *ctrl = &dev->ctrl;
1176         struct nvme_command c;
1177         int flags = NVME_QUEUE_PHYS_CONTIG;
1178
1179         /*
1180          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1181          * set. Since URGENT priority is zeroes, it makes all queues
1182          * URGENT.
1183          */
1184         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1185                 flags |= NVME_SQ_PRIO_MEDIUM;
1186
1187         /*
1188          * Note: we (ab)use the fact that the prp fields survive if no data
1189          * is attached to the request.
1190          */
1191         memset(&c, 0, sizeof(c));
1192         c.create_sq.opcode = nvme_admin_create_sq;
1193         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1194         c.create_sq.sqid = cpu_to_le16(qid);
1195         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1196         c.create_sq.sq_flags = cpu_to_le16(flags);
1197         c.create_sq.cqid = cpu_to_le16(qid);
1198
1199         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1200 }
1201
1202 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1203 {
1204         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1205 }
1206
1207 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1208 {
1209         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1210 }
1211
1212 static void abort_endio(struct request *req, blk_status_t error)
1213 {
1214         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1215         struct nvme_queue *nvmeq = iod->nvmeq;
1216
1217         dev_warn(nvmeq->dev->ctrl.device,
1218                  "Abort status: 0x%x", nvme_req(req)->status);
1219         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1220         blk_mq_free_request(req);
1221 }
1222
1223 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1224 {
1225
1226         /* If true, indicates loss of adapter communication, possibly by a
1227          * NVMe Subsystem reset.
1228          */
1229         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1230
1231         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1232         switch (dev->ctrl.state) {
1233         case NVME_CTRL_RESETTING:
1234         case NVME_CTRL_CONNECTING:
1235                 return false;
1236         default:
1237                 break;
1238         }
1239
1240         /* We shouldn't reset unless the controller is on fatal error state
1241          * _or_ if we lost the communication with it.
1242          */
1243         if (!(csts & NVME_CSTS_CFS) && !nssro)
1244                 return false;
1245
1246         return true;
1247 }
1248
1249 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1250 {
1251         /* Read a config register to help see what died. */
1252         u16 pci_status;
1253         int result;
1254
1255         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1256                                       &pci_status);
1257         if (result == PCIBIOS_SUCCESSFUL)
1258                 dev_warn(dev->ctrl.device,
1259                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1260                          csts, pci_status);
1261         else
1262                 dev_warn(dev->ctrl.device,
1263                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1264                          csts, result);
1265 }
1266
1267 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1268 {
1269         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1270         struct nvme_queue *nvmeq = iod->nvmeq;
1271         struct nvme_dev *dev = nvmeq->dev;
1272         struct request *abort_req;
1273         struct nvme_command cmd;
1274         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1275
1276         /* If PCI error recovery process is happening, we cannot reset or
1277          * the recovery mechanism will surely fail.
1278          */
1279         mb();
1280         if (pci_channel_offline(to_pci_dev(dev->dev)))
1281                 return BLK_EH_RESET_TIMER;
1282
1283         /*
1284          * Reset immediately if the controller is failed
1285          */
1286         if (nvme_should_reset(dev, csts)) {
1287                 nvme_warn_reset(dev, csts);
1288                 nvme_dev_disable(dev, false);
1289                 nvme_reset_ctrl(&dev->ctrl);
1290                 return BLK_EH_DONE;
1291         }
1292
1293         /*
1294          * Did we miss an interrupt?
1295          */
1296         if (nvme_poll_irqdisable(nvmeq, req->tag)) {
1297                 dev_warn(dev->ctrl.device,
1298                          "I/O %d QID %d timeout, completion polled\n",
1299                          req->tag, nvmeq->qid);
1300                 return BLK_EH_DONE;
1301         }
1302
1303         /*
1304          * Shutdown immediately if controller times out while starting. The
1305          * reset work will see the pci device disabled when it gets the forced
1306          * cancellation error. All outstanding requests are completed on
1307          * shutdown, so we return BLK_EH_DONE.
1308          */
1309         switch (dev->ctrl.state) {
1310         case NVME_CTRL_CONNECTING:
1311         case NVME_CTRL_RESETTING:
1312                 dev_warn_ratelimited(dev->ctrl.device,
1313                          "I/O %d QID %d timeout, disable controller\n",
1314                          req->tag, nvmeq->qid);
1315                 nvme_dev_disable(dev, false);
1316                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1317                 return BLK_EH_DONE;
1318         default:
1319                 break;
1320         }
1321
1322         /*
1323          * Shutdown the controller immediately and schedule a reset if the
1324          * command was already aborted once before and still hasn't been
1325          * returned to the driver, or if this is the admin queue.
1326          */
1327         if (!nvmeq->qid || iod->aborted) {
1328                 dev_warn(dev->ctrl.device,
1329                          "I/O %d QID %d timeout, reset controller\n",
1330                          req->tag, nvmeq->qid);
1331                 nvme_dev_disable(dev, false);
1332                 nvme_reset_ctrl(&dev->ctrl);
1333
1334                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1335                 return BLK_EH_DONE;
1336         }
1337
1338         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1339                 atomic_inc(&dev->ctrl.abort_limit);
1340                 return BLK_EH_RESET_TIMER;
1341         }
1342         iod->aborted = 1;
1343
1344         memset(&cmd, 0, sizeof(cmd));
1345         cmd.abort.opcode = nvme_admin_abort_cmd;
1346         cmd.abort.cid = req->tag;
1347         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1348
1349         dev_warn(nvmeq->dev->ctrl.device,
1350                 "I/O %d QID %d timeout, aborting\n",
1351                  req->tag, nvmeq->qid);
1352
1353         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1354                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1355         if (IS_ERR(abort_req)) {
1356                 atomic_inc(&dev->ctrl.abort_limit);
1357                 return BLK_EH_RESET_TIMER;
1358         }
1359
1360         abort_req->timeout = ADMIN_TIMEOUT;
1361         abort_req->end_io_data = NULL;
1362         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1363
1364         /*
1365          * The aborted req will be completed on receiving the abort req.
1366          * We enable the timer again. If hit twice, it'll cause a device reset,
1367          * as the device then is in a faulty state.
1368          */
1369         return BLK_EH_RESET_TIMER;
1370 }
1371
1372 static void nvme_free_queue(struct nvme_queue *nvmeq)
1373 {
1374         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1375                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1376         if (!nvmeq->sq_cmds)
1377                 return;
1378
1379         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1380                 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1381                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1382         } else {
1383                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1384                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1385         }
1386 }
1387
1388 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1389 {
1390         int i;
1391
1392         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1393                 dev->ctrl.queue_count--;
1394                 nvme_free_queue(&dev->queues[i]);
1395         }
1396 }
1397
1398 /**
1399  * nvme_suspend_queue - put queue into suspended state
1400  * @nvmeq: queue to suspend
1401  */
1402 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1403 {
1404         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1405                 return 1;
1406
1407         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1408         mb();
1409
1410         nvmeq->dev->online_queues--;
1411         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1412                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1413         if (nvmeq->cq_vector == -1)
1414                 return 0;
1415         pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1416         nvmeq->cq_vector = -1;
1417         return 0;
1418 }
1419
1420 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1421 {
1422         int i;
1423
1424         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1425                 nvme_suspend_queue(&dev->queues[i]);
1426 }
1427
1428 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1429 {
1430         struct nvme_queue *nvmeq = &dev->queues[0];
1431
1432         if (shutdown)
1433                 nvme_shutdown_ctrl(&dev->ctrl);
1434         else
1435                 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1436
1437         nvme_poll_irqdisable(nvmeq, -1);
1438 }
1439
1440 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1441                                 int entry_size)
1442 {
1443         int q_depth = dev->q_depth;
1444         unsigned q_size_aligned = roundup(q_depth * entry_size,
1445                                           dev->ctrl.page_size);
1446
1447         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1448                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1449                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1450                 q_depth = div_u64(mem_per_q, entry_size);
1451
1452                 /*
1453                  * Ensure the reduced q_depth is above some threshold where it
1454                  * would be better to map queues in system memory with the
1455                  * original depth
1456                  */
1457                 if (q_depth < 64)
1458                         return -ENOMEM;
1459         }
1460
1461         return q_depth;
1462 }
1463
1464 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1465                                 int qid, int depth)
1466 {
1467         struct pci_dev *pdev = to_pci_dev(dev->dev);
1468
1469         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1470                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1471                 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1472                                                 nvmeq->sq_cmds);
1473                 if (nvmeq->sq_dma_addr) {
1474                         set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1475                         return 0;
1476                 }
1477         }
1478
1479         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1480                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1481         if (!nvmeq->sq_cmds)
1482                 return -ENOMEM;
1483         return 0;
1484 }
1485
1486 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1487 {
1488         struct nvme_queue *nvmeq = &dev->queues[qid];
1489
1490         if (dev->ctrl.queue_count > qid)
1491                 return 0;
1492
1493         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1494                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1495         if (!nvmeq->cqes)
1496                 goto free_nvmeq;
1497
1498         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1499                 goto free_cqdma;
1500
1501         nvmeq->q_dmadev = dev->dev;
1502         nvmeq->dev = dev;
1503         spin_lock_init(&nvmeq->sq_lock);
1504         spin_lock_init(&nvmeq->cq_poll_lock);
1505         nvmeq->cq_head = 0;
1506         nvmeq->cq_phase = 1;
1507         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1508         nvmeq->q_depth = depth;
1509         nvmeq->qid = qid;
1510         nvmeq->cq_vector = -1;
1511         dev->ctrl.queue_count++;
1512
1513         return 0;
1514
1515  free_cqdma:
1516         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1517                                                         nvmeq->cq_dma_addr);
1518  free_nvmeq:
1519         return -ENOMEM;
1520 }
1521
1522 static int queue_request_irq(struct nvme_queue *nvmeq)
1523 {
1524         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1525         int nr = nvmeq->dev->ctrl.instance;
1526
1527         if (use_threaded_interrupts) {
1528                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1529                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1530         } else {
1531                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1532                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1533         }
1534 }
1535
1536 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1537 {
1538         struct nvme_dev *dev = nvmeq->dev;
1539
1540         nvmeq->sq_tail = 0;
1541         nvmeq->last_sq_tail = 0;
1542         nvmeq->cq_head = 0;
1543         nvmeq->cq_phase = 1;
1544         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1545         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1546         nvme_dbbuf_init(dev, nvmeq, qid);
1547         dev->online_queues++;
1548         wmb(); /* ensure the first interrupt sees the initialization */
1549 }
1550
1551 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1552 {
1553         struct nvme_dev *dev = nvmeq->dev;
1554         int result;
1555         s16 vector;
1556
1557         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1558
1559         /*
1560          * A queue's vector matches the queue identifier unless the controller
1561          * has only one vector available.
1562          */
1563         if (!polled)
1564                 vector = dev->num_vecs == 1 ? 0 : qid;
1565         else
1566                 vector = -1;
1567
1568         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1569         if (result)
1570                 return result;
1571
1572         result = adapter_alloc_sq(dev, qid, nvmeq);
1573         if (result < 0)
1574                 return result;
1575         else if (result)
1576                 goto release_cq;
1577
1578         nvmeq->cq_vector = vector;
1579         nvme_init_queue(nvmeq, qid);
1580
1581         if (vector != -1) {
1582                 result = queue_request_irq(nvmeq);
1583                 if (result < 0)
1584                         goto release_sq;
1585         }
1586
1587         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1588         return result;
1589
1590 release_sq:
1591         nvmeq->cq_vector = -1;
1592         dev->online_queues--;
1593         adapter_delete_sq(dev, qid);
1594 release_cq:
1595         adapter_delete_cq(dev, qid);
1596         return result;
1597 }
1598
1599 static const struct blk_mq_ops nvme_mq_admin_ops = {
1600         .queue_rq       = nvme_queue_rq,
1601         .complete       = nvme_pci_complete_rq,
1602         .init_hctx      = nvme_admin_init_hctx,
1603         .exit_hctx      = nvme_admin_exit_hctx,
1604         .init_request   = nvme_init_request,
1605         .timeout        = nvme_timeout,
1606 };
1607
1608 static const struct blk_mq_ops nvme_mq_ops = {
1609         .queue_rq       = nvme_queue_rq,
1610         .complete       = nvme_pci_complete_rq,
1611         .commit_rqs     = nvme_commit_rqs,
1612         .init_hctx      = nvme_init_hctx,
1613         .init_request   = nvme_init_request,
1614         .map_queues     = nvme_pci_map_queues,
1615         .timeout        = nvme_timeout,
1616         .poll           = nvme_poll,
1617 };
1618
1619 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1620 {
1621         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1622                 /*
1623                  * If the controller was reset during removal, it's possible
1624                  * user requests may be waiting on a stopped queue. Start the
1625                  * queue to flush these to completion.
1626                  */
1627                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1628                 blk_cleanup_queue(dev->ctrl.admin_q);
1629                 blk_mq_free_tag_set(&dev->admin_tagset);
1630         }
1631 }
1632
1633 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1634 {
1635         if (!dev->ctrl.admin_q) {
1636                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1637                 dev->admin_tagset.nr_hw_queues = 1;
1638
1639                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1640                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1641                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1642                 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1643                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1644                 dev->admin_tagset.driver_data = dev;
1645
1646                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1647                         return -ENOMEM;
1648                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1649
1650                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1651                 if (IS_ERR(dev->ctrl.admin_q)) {
1652                         blk_mq_free_tag_set(&dev->admin_tagset);
1653                         return -ENOMEM;
1654                 }
1655                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1656                         nvme_dev_remove_admin(dev);
1657                         dev->ctrl.admin_q = NULL;
1658                         return -ENODEV;
1659                 }
1660         } else
1661                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1662
1663         return 0;
1664 }
1665
1666 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1667 {
1668         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1669 }
1670
1671 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1672 {
1673         struct pci_dev *pdev = to_pci_dev(dev->dev);
1674
1675         if (size <= dev->bar_mapped_size)
1676                 return 0;
1677         if (size > pci_resource_len(pdev, 0))
1678                 return -ENOMEM;
1679         if (dev->bar)
1680                 iounmap(dev->bar);
1681         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1682         if (!dev->bar) {
1683                 dev->bar_mapped_size = 0;
1684                 return -ENOMEM;
1685         }
1686         dev->bar_mapped_size = size;
1687         dev->dbs = dev->bar + NVME_REG_DBS;
1688
1689         return 0;
1690 }
1691
1692 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1693 {
1694         int result;
1695         u32 aqa;
1696         struct nvme_queue *nvmeq;
1697
1698         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1699         if (result < 0)
1700                 return result;
1701
1702         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1703                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1704
1705         if (dev->subsystem &&
1706             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1707                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1708
1709         result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
1710         if (result < 0)
1711                 return result;
1712
1713         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1714         if (result)
1715                 return result;
1716
1717         nvmeq = &dev->queues[0];
1718         aqa = nvmeq->q_depth - 1;
1719         aqa |= aqa << 16;
1720
1721         writel(aqa, dev->bar + NVME_REG_AQA);
1722         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1723         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1724
1725         result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
1726         if (result)
1727                 return result;
1728
1729         nvmeq->cq_vector = 0;
1730         nvme_init_queue(nvmeq, 0);
1731         result = queue_request_irq(nvmeq);
1732         if (result) {
1733                 nvmeq->cq_vector = -1;
1734                 return result;
1735         }
1736
1737         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1738         return result;
1739 }
1740
1741 static int nvme_create_io_queues(struct nvme_dev *dev)
1742 {
1743         unsigned i, max, rw_queues;
1744         int ret = 0;
1745
1746         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1747                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1748                         ret = -ENOMEM;
1749                         break;
1750                 }
1751         }
1752
1753         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1754         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1755                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1756                                 dev->io_queues[HCTX_TYPE_READ];
1757         } else {
1758                 rw_queues = max;
1759         }
1760
1761         for (i = dev->online_queues; i <= max; i++) {
1762                 bool polled = i > rw_queues;
1763
1764                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1765                 if (ret)
1766                         break;
1767         }
1768
1769         /*
1770          * Ignore failing Create SQ/CQ commands, we can continue with less
1771          * than the desired amount of queues, and even a controller without
1772          * I/O queues can still be used to issue admin commands.  This might
1773          * be useful to upgrade a buggy firmware for example.
1774          */
1775         return ret >= 0 ? 0 : ret;
1776 }
1777
1778 static ssize_t nvme_cmb_show(struct device *dev,
1779                              struct device_attribute *attr,
1780                              char *buf)
1781 {
1782         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1783
1784         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1785                        ndev->cmbloc, ndev->cmbsz);
1786 }
1787 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1788
1789 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1790 {
1791         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1792
1793         return 1ULL << (12 + 4 * szu);
1794 }
1795
1796 static u32 nvme_cmb_size(struct nvme_dev *dev)
1797 {
1798         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1799 }
1800
1801 static void nvme_map_cmb(struct nvme_dev *dev)
1802 {
1803         u64 size, offset;
1804         resource_size_t bar_size;
1805         struct pci_dev *pdev = to_pci_dev(dev->dev);
1806         int bar;
1807
1808         if (dev->cmb_size)
1809                 return;
1810
1811         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1812         if (!dev->cmbsz)
1813                 return;
1814         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1815
1816         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1817         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1818         bar = NVME_CMB_BIR(dev->cmbloc);
1819         bar_size = pci_resource_len(pdev, bar);
1820
1821         if (offset > bar_size)
1822                 return;
1823
1824         /*
1825          * Controllers may support a CMB size larger than their BAR,
1826          * for example, due to being behind a bridge. Reduce the CMB to
1827          * the reported size of the BAR
1828          */
1829         if (size > bar_size - offset)
1830                 size = bar_size - offset;
1831
1832         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1833                 dev_warn(dev->ctrl.device,
1834                          "failed to register the CMB\n");
1835                 return;
1836         }
1837
1838         dev->cmb_size = size;
1839         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1840
1841         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1842                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1843                 pci_p2pmem_publish(pdev, true);
1844
1845         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1846                                     &dev_attr_cmb.attr, NULL))
1847                 dev_warn(dev->ctrl.device,
1848                          "failed to add sysfs attribute for CMB\n");
1849 }
1850
1851 static inline void nvme_release_cmb(struct nvme_dev *dev)
1852 {
1853         if (dev->cmb_size) {
1854                 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1855                                              &dev_attr_cmb.attr, NULL);
1856                 dev->cmb_size = 0;
1857         }
1858 }
1859
1860 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1861 {
1862         u64 dma_addr = dev->host_mem_descs_dma;
1863         struct nvme_command c;
1864         int ret;
1865
1866         memset(&c, 0, sizeof(c));
1867         c.features.opcode       = nvme_admin_set_features;
1868         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1869         c.features.dword11      = cpu_to_le32(bits);
1870         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1871                                               ilog2(dev->ctrl.page_size));
1872         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1873         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1874         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1875
1876         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1877         if (ret) {
1878                 dev_warn(dev->ctrl.device,
1879                          "failed to set host mem (err %d, flags %#x).\n",
1880                          ret, bits);
1881         }
1882         return ret;
1883 }
1884
1885 static void nvme_free_host_mem(struct nvme_dev *dev)
1886 {
1887         int i;
1888
1889         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1890                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1891                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1892
1893                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1894                                le64_to_cpu(desc->addr),
1895                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1896         }
1897
1898         kfree(dev->host_mem_desc_bufs);
1899         dev->host_mem_desc_bufs = NULL;
1900         dma_free_coherent(dev->dev,
1901                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1902                         dev->host_mem_descs, dev->host_mem_descs_dma);
1903         dev->host_mem_descs = NULL;
1904         dev->nr_host_mem_descs = 0;
1905 }
1906
1907 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1908                 u32 chunk_size)
1909 {
1910         struct nvme_host_mem_buf_desc *descs;
1911         u32 max_entries, len;
1912         dma_addr_t descs_dma;
1913         int i = 0;
1914         void **bufs;
1915         u64 size, tmp;
1916
1917         tmp = (preferred + chunk_size - 1);
1918         do_div(tmp, chunk_size);
1919         max_entries = tmp;
1920
1921         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1922                 max_entries = dev->ctrl.hmmaxd;
1923
1924         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1925                                    &descs_dma, GFP_KERNEL);
1926         if (!descs)
1927                 goto out;
1928
1929         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1930         if (!bufs)
1931                 goto out_free_descs;
1932
1933         for (size = 0; size < preferred && i < max_entries; size += len) {
1934                 dma_addr_t dma_addr;
1935
1936                 len = min_t(u64, chunk_size, preferred - size);
1937                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1938                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1939                 if (!bufs[i])
1940                         break;
1941
1942                 descs[i].addr = cpu_to_le64(dma_addr);
1943                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1944                 i++;
1945         }
1946
1947         if (!size)
1948                 goto out_free_bufs;
1949
1950         dev->nr_host_mem_descs = i;
1951         dev->host_mem_size = size;
1952         dev->host_mem_descs = descs;
1953         dev->host_mem_descs_dma = descs_dma;
1954         dev->host_mem_desc_bufs = bufs;
1955         return 0;
1956
1957 out_free_bufs:
1958         while (--i >= 0) {
1959                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1960
1961                 dma_free_attrs(dev->dev, size, bufs[i],
1962                                le64_to_cpu(descs[i].addr),
1963                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1964         }
1965
1966         kfree(bufs);
1967 out_free_descs:
1968         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1969                         descs_dma);
1970 out:
1971         dev->host_mem_descs = NULL;
1972         return -ENOMEM;
1973 }
1974
1975 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1976 {
1977         u32 chunk_size;
1978
1979         /* start big and work our way down */
1980         for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1981              chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1982              chunk_size /= 2) {
1983                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1984                         if (!min || dev->host_mem_size >= min)
1985                                 return 0;
1986                         nvme_free_host_mem(dev);
1987                 }
1988         }
1989
1990         return -ENOMEM;
1991 }
1992
1993 static int nvme_setup_host_mem(struct nvme_dev *dev)
1994 {
1995         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1996         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1997         u64 min = (u64)dev->ctrl.hmmin * 4096;
1998         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1999         int ret;
2000
2001         preferred = min(preferred, max);
2002         if (min > max) {
2003                 dev_warn(dev->ctrl.device,
2004                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2005                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2006                 nvme_free_host_mem(dev);
2007                 return 0;
2008         }
2009
2010         /*
2011          * If we already have a buffer allocated check if we can reuse it.
2012          */
2013         if (dev->host_mem_descs) {
2014                 if (dev->host_mem_size >= min)
2015                         enable_bits |= NVME_HOST_MEM_RETURN;
2016                 else
2017                         nvme_free_host_mem(dev);
2018         }
2019
2020         if (!dev->host_mem_descs) {
2021                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2022                         dev_warn(dev->ctrl.device,
2023                                 "failed to allocate host memory buffer.\n");
2024                         return 0; /* controller must work without HMB */
2025                 }
2026
2027                 dev_info(dev->ctrl.device,
2028                         "allocated %lld MiB host memory buffer.\n",
2029                         dev->host_mem_size >> ilog2(SZ_1M));
2030         }
2031
2032         ret = nvme_set_host_mem(dev, enable_bits);
2033         if (ret)
2034                 nvme_free_host_mem(dev);
2035         return ret;
2036 }
2037
2038 /*
2039  * nirqs is the number of interrupts available for write and read
2040  * queues. The core already reserved an interrupt for the admin queue.
2041  */
2042 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2043 {
2044         struct nvme_dev *dev = affd->priv;
2045         unsigned int nr_read_queues;
2046
2047         /*
2048          * If there is no interupt available for queues, ensure that
2049          * the default queue is set to 1. The affinity set size is
2050          * also set to one, but the irq core ignores it for this case.
2051          *
2052          * If only one interrupt is available or 'write_queue' == 0, combine
2053          * write and read queues.
2054          *
2055          * If 'write_queues' > 0, ensure it leaves room for at least one read
2056          * queue.
2057          */
2058         if (!nrirqs) {
2059                 nrirqs = 1;
2060                 nr_read_queues = 0;
2061         } else if (nrirqs == 1 || !write_queues) {
2062                 nr_read_queues = 0;
2063         } else if (write_queues >= nrirqs) {
2064                 nr_read_queues = 1;
2065         } else {
2066                 nr_read_queues = nrirqs - write_queues;
2067         }
2068
2069         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2070         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2071         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2072         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2073         affd->nr_sets = nr_read_queues ? 2 : 1;
2074 }
2075
2076 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2077 {
2078         struct pci_dev *pdev = to_pci_dev(dev->dev);
2079         struct irq_affinity affd = {
2080                 .pre_vectors    = 1,
2081                 .calc_sets      = nvme_calc_irq_sets,
2082                 .priv           = dev,
2083         };
2084         unsigned int irq_queues, this_p_queues;
2085
2086         /*
2087          * Poll queues don't need interrupts, but we need at least one IO
2088          * queue left over for non-polled IO.
2089          */
2090         this_p_queues = poll_queues;
2091         if (this_p_queues >= nr_io_queues) {
2092                 this_p_queues = nr_io_queues - 1;
2093                 irq_queues = 1;
2094         } else {
2095                 irq_queues = nr_io_queues - this_p_queues + 1;
2096         }
2097         dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2098
2099         /* Initialize for the single interrupt case */
2100         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2101         dev->io_queues[HCTX_TYPE_READ] = 0;
2102
2103         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2104                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2105 }
2106
2107 static void nvme_disable_io_queues(struct nvme_dev *dev)
2108 {
2109         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2110                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2111 }
2112
2113 static int nvme_setup_io_queues(struct nvme_dev *dev)
2114 {
2115         struct nvme_queue *adminq = &dev->queues[0];
2116         struct pci_dev *pdev = to_pci_dev(dev->dev);
2117         int result, nr_io_queues;
2118         unsigned long size;
2119
2120         nr_io_queues = max_io_queues();
2121         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2122         if (result < 0)
2123                 return result;
2124
2125         if (nr_io_queues == 0)
2126                 return 0;
2127
2128         clear_bit(NVMEQ_ENABLED, &adminq->flags);
2129
2130         if (dev->cmb_use_sqes) {
2131                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2132                                 sizeof(struct nvme_command));
2133                 if (result > 0)
2134                         dev->q_depth = result;
2135                 else
2136                         dev->cmb_use_sqes = false;
2137         }
2138
2139         do {
2140                 size = db_bar_size(dev, nr_io_queues);
2141                 result = nvme_remap_bar(dev, size);
2142                 if (!result)
2143                         break;
2144                 if (!--nr_io_queues)
2145                         return -ENOMEM;
2146         } while (1);
2147         adminq->q_db = dev->dbs;
2148
2149  retry:
2150         /* Deregister the admin queue's interrupt */
2151         pci_free_irq(pdev, 0, adminq);
2152
2153         /*
2154          * If we enable msix early due to not intx, disable it again before
2155          * setting up the full range we need.
2156          */
2157         pci_free_irq_vectors(pdev);
2158
2159         result = nvme_setup_irqs(dev, nr_io_queues);
2160         if (result <= 0)
2161                 return -EIO;
2162
2163         dev->num_vecs = result;
2164         result = max(result - 1, 1);
2165         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2166
2167         /*
2168          * Should investigate if there's a performance win from allocating
2169          * more queues than interrupt vectors; it might allow the submission
2170          * path to scale better, even if the receive path is limited by the
2171          * number of interrupts.
2172          */
2173         result = queue_request_irq(adminq);
2174         if (result) {
2175                 adminq->cq_vector = -1;
2176                 return result;
2177         }
2178         set_bit(NVMEQ_ENABLED, &adminq->flags);
2179
2180         result = nvme_create_io_queues(dev);
2181         if (result || dev->online_queues < 2)
2182                 return result;
2183
2184         if (dev->online_queues - 1 < dev->max_qid) {
2185                 nr_io_queues = dev->online_queues - 1;
2186                 nvme_disable_io_queues(dev);
2187                 nvme_suspend_io_queues(dev);
2188                 goto retry;
2189         }
2190         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2191                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2192                                         dev->io_queues[HCTX_TYPE_READ],
2193                                         dev->io_queues[HCTX_TYPE_POLL]);
2194         return 0;
2195 }
2196
2197 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2198 {
2199         struct nvme_queue *nvmeq = req->end_io_data;
2200
2201         blk_mq_free_request(req);
2202         complete(&nvmeq->delete_done);
2203 }
2204
2205 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2206 {
2207         struct nvme_queue *nvmeq = req->end_io_data;
2208
2209         if (error)
2210                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2211
2212         nvme_del_queue_end(req, error);
2213 }
2214
2215 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2216 {
2217         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2218         struct request *req;
2219         struct nvme_command cmd;
2220
2221         memset(&cmd, 0, sizeof(cmd));
2222         cmd.delete_queue.opcode = opcode;
2223         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2224
2225         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2226         if (IS_ERR(req))
2227                 return PTR_ERR(req);
2228
2229         req->timeout = ADMIN_TIMEOUT;
2230         req->end_io_data = nvmeq;
2231
2232         init_completion(&nvmeq->delete_done);
2233         blk_execute_rq_nowait(q, NULL, req, false,
2234                         opcode == nvme_admin_delete_cq ?
2235                                 nvme_del_cq_end : nvme_del_queue_end);
2236         return 0;
2237 }
2238
2239 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2240 {
2241         int nr_queues = dev->online_queues - 1, sent = 0;
2242         unsigned long timeout;
2243
2244  retry:
2245         timeout = ADMIN_TIMEOUT;
2246         while (nr_queues > 0) {
2247                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2248                         break;
2249                 nr_queues--;
2250                 sent++;
2251         }
2252         while (sent) {
2253                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2254
2255                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2256                                 timeout);
2257                 if (timeout == 0)
2258                         return false;
2259
2260                 /* handle any remaining CQEs */
2261                 if (opcode == nvme_admin_delete_cq &&
2262                     !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2263                         nvme_poll_irqdisable(nvmeq, -1);
2264
2265                 sent--;
2266                 if (nr_queues)
2267                         goto retry;
2268         }
2269         return true;
2270 }
2271
2272 /*
2273  * return error value only when tagset allocation failed
2274  */
2275 static int nvme_dev_add(struct nvme_dev *dev)
2276 {
2277         int ret;
2278
2279         if (!dev->ctrl.tagset) {
2280                 dev->tagset.ops = &nvme_mq_ops;
2281                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2282                 dev->tagset.nr_maps = 2; /* default + read */
2283                 if (dev->io_queues[HCTX_TYPE_POLL])
2284                         dev->tagset.nr_maps++;
2285                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2286                 dev->tagset.numa_node = dev_to_node(dev->dev);
2287                 dev->tagset.queue_depth =
2288                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2289                 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2290                 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2291                         dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2292                                         nvme_pci_cmd_size(dev, true));
2293                 }
2294                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2295                 dev->tagset.driver_data = dev;
2296
2297                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2298                 if (ret) {
2299                         dev_warn(dev->ctrl.device,
2300                                 "IO queues tagset allocation failed %d\n", ret);
2301                         return ret;
2302                 }
2303                 dev->ctrl.tagset = &dev->tagset;
2304
2305                 nvme_dbbuf_set(dev);
2306         } else {
2307                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2308
2309                 /* Free previously allocated queues that are no longer usable */
2310                 nvme_free_queues(dev, dev->online_queues);
2311         }
2312
2313         return 0;
2314 }
2315
2316 static int nvme_pci_enable(struct nvme_dev *dev)
2317 {
2318         int result = -ENOMEM;
2319         struct pci_dev *pdev = to_pci_dev(dev->dev);
2320
2321         if (pci_enable_device_mem(pdev))
2322                 return result;
2323
2324         pci_set_master(pdev);
2325
2326         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2327             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2328                 goto disable;
2329
2330         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2331                 result = -ENODEV;
2332                 goto disable;
2333         }
2334
2335         /*
2336          * Some devices and/or platforms don't advertise or work with INTx
2337          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2338          * adjust this later.
2339          */
2340         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2341         if (result < 0)
2342                 return result;
2343
2344         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2345
2346         dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2347                                 io_queue_depth);
2348         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2349         dev->dbs = dev->bar + 4096;
2350
2351         /*
2352          * Temporary fix for the Apple controller found in the MacBook8,1 and
2353          * some MacBook7,1 to avoid controller resets and data loss.
2354          */
2355         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2356                 dev->q_depth = 2;
2357                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2358                         "set queue depth=%u to work around controller resets\n",
2359                         dev->q_depth);
2360         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2361                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2362                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2363                 dev->q_depth = 64;
2364                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2365                         "set queue depth=%u\n", dev->q_depth);
2366         }
2367
2368         nvme_map_cmb(dev);
2369
2370         pci_enable_pcie_error_reporting(pdev);
2371         pci_save_state(pdev);
2372         return 0;
2373
2374  disable:
2375         pci_disable_device(pdev);
2376         return result;
2377 }
2378
2379 static void nvme_dev_unmap(struct nvme_dev *dev)
2380 {
2381         if (dev->bar)
2382                 iounmap(dev->bar);
2383         pci_release_mem_regions(to_pci_dev(dev->dev));
2384 }
2385
2386 static void nvme_pci_disable(struct nvme_dev *dev)
2387 {
2388         struct pci_dev *pdev = to_pci_dev(dev->dev);
2389
2390         pci_free_irq_vectors(pdev);
2391
2392         if (pci_is_enabled(pdev)) {
2393                 pci_disable_pcie_error_reporting(pdev);
2394                 pci_disable_device(pdev);
2395         }
2396 }
2397
2398 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2399 {
2400         bool dead = true;
2401         struct pci_dev *pdev = to_pci_dev(dev->dev);
2402
2403         mutex_lock(&dev->shutdown_lock);
2404         if (pci_is_enabled(pdev)) {
2405                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2406
2407                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2408                     dev->ctrl.state == NVME_CTRL_RESETTING)
2409                         nvme_start_freeze(&dev->ctrl);
2410                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2411                         pdev->error_state  != pci_channel_io_normal);
2412         }
2413
2414         /*
2415          * Give the controller a chance to complete all entered requests if
2416          * doing a safe shutdown.
2417          */
2418         if (!dead) {
2419                 if (shutdown)
2420                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2421         }
2422
2423         nvme_stop_queues(&dev->ctrl);
2424
2425         if (!dead && dev->ctrl.queue_count > 0) {
2426                 nvme_disable_io_queues(dev);
2427                 nvme_disable_admin_queue(dev, shutdown);
2428         }
2429         nvme_suspend_io_queues(dev);
2430         nvme_suspend_queue(&dev->queues[0]);
2431         nvme_pci_disable(dev);
2432
2433         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2434         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2435
2436         /*
2437          * The driver will not be starting up queues again if shutting down so
2438          * must flush all entered requests to their failed completion to avoid
2439          * deadlocking blk-mq hot-cpu notifier.
2440          */
2441         if (shutdown)
2442                 nvme_start_queues(&dev->ctrl);
2443         mutex_unlock(&dev->shutdown_lock);
2444 }
2445
2446 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2447 {
2448         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2449                                                 PAGE_SIZE, PAGE_SIZE, 0);
2450         if (!dev->prp_page_pool)
2451                 return -ENOMEM;
2452
2453         /* Optimisation for I/Os between 4k and 128k */
2454         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2455                                                 256, 256, 0);
2456         if (!dev->prp_small_pool) {
2457                 dma_pool_destroy(dev->prp_page_pool);
2458                 return -ENOMEM;
2459         }
2460         return 0;
2461 }
2462
2463 static void nvme_release_prp_pools(struct nvme_dev *dev)
2464 {
2465         dma_pool_destroy(dev->prp_page_pool);
2466         dma_pool_destroy(dev->prp_small_pool);
2467 }
2468
2469 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2470 {
2471         struct nvme_dev *dev = to_nvme_dev(ctrl);
2472
2473         nvme_dbbuf_dma_free(dev);
2474         put_device(dev->dev);
2475         if (dev->tagset.tags)
2476                 blk_mq_free_tag_set(&dev->tagset);
2477         if (dev->ctrl.admin_q)
2478                 blk_put_queue(dev->ctrl.admin_q);
2479         kfree(dev->queues);
2480         free_opal_dev(dev->ctrl.opal_dev);
2481         mempool_destroy(dev->iod_mempool);
2482         kfree(dev);
2483 }
2484
2485 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2486 {
2487         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2488
2489         nvme_get_ctrl(&dev->ctrl);
2490         nvme_dev_disable(dev, false);
2491         nvme_kill_queues(&dev->ctrl);
2492         if (!queue_work(nvme_wq, &dev->remove_work))
2493                 nvme_put_ctrl(&dev->ctrl);
2494 }
2495
2496 static void nvme_reset_work(struct work_struct *work)
2497 {
2498         struct nvme_dev *dev =
2499                 container_of(work, struct nvme_dev, ctrl.reset_work);
2500         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2501         int result = -ENODEV;
2502         enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
2503
2504         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2505                 goto out;
2506
2507         /*
2508          * If we're called to reset a live controller first shut it down before
2509          * moving on.
2510          */
2511         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2512                 nvme_dev_disable(dev, false);
2513
2514         mutex_lock(&dev->shutdown_lock);
2515         result = nvme_pci_enable(dev);
2516         if (result)
2517                 goto out_unlock;
2518
2519         result = nvme_pci_configure_admin_queue(dev);
2520         if (result)
2521                 goto out_unlock;
2522
2523         result = nvme_alloc_admin_tags(dev);
2524         if (result)
2525                 goto out_unlock;
2526
2527         /*
2528          * Limit the max command size to prevent iod->sg allocations going
2529          * over a single page.
2530          */
2531         dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2532         dev->ctrl.max_segments = NVME_MAX_SEGS;
2533         mutex_unlock(&dev->shutdown_lock);
2534
2535         /*
2536          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2537          * initializing procedure here.
2538          */
2539         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2540                 dev_warn(dev->ctrl.device,
2541                         "failed to mark controller CONNECTING\n");
2542                 goto out;
2543         }
2544
2545         result = nvme_init_identify(&dev->ctrl);
2546         if (result)
2547                 goto out;
2548
2549         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2550                 if (!dev->ctrl.opal_dev)
2551                         dev->ctrl.opal_dev =
2552                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2553                 else if (was_suspend)
2554                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2555         } else {
2556                 free_opal_dev(dev->ctrl.opal_dev);
2557                 dev->ctrl.opal_dev = NULL;
2558         }
2559
2560         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2561                 result = nvme_dbbuf_dma_alloc(dev);
2562                 if (result)
2563                         dev_warn(dev->dev,
2564                                  "unable to allocate dma for dbbuf\n");
2565         }
2566
2567         if (dev->ctrl.hmpre) {
2568                 result = nvme_setup_host_mem(dev);
2569                 if (result < 0)
2570                         goto out;
2571         }
2572
2573         result = nvme_setup_io_queues(dev);
2574         if (result)
2575                 goto out;
2576
2577         /*
2578          * Keep the controller around but remove all namespaces if we don't have
2579          * any working I/O queue.
2580          */
2581         if (dev->online_queues < 2) {
2582                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2583                 nvme_kill_queues(&dev->ctrl);
2584                 nvme_remove_namespaces(&dev->ctrl);
2585                 new_state = NVME_CTRL_ADMIN_ONLY;
2586         } else {
2587                 nvme_start_queues(&dev->ctrl);
2588                 nvme_wait_freeze(&dev->ctrl);
2589                 /* hit this only when allocate tagset fails */
2590                 if (nvme_dev_add(dev))
2591                         new_state = NVME_CTRL_ADMIN_ONLY;
2592                 nvme_unfreeze(&dev->ctrl);
2593         }
2594
2595         /*
2596          * If only admin queue live, keep it to do further investigation or
2597          * recovery.
2598          */
2599         if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2600                 dev_warn(dev->ctrl.device,
2601                         "failed to mark controller state %d\n", new_state);
2602                 goto out;
2603         }
2604
2605         nvme_start_ctrl(&dev->ctrl);
2606         return;
2607
2608  out_unlock:
2609         mutex_unlock(&dev->shutdown_lock);
2610  out:
2611         nvme_remove_dead_ctrl(dev, result);
2612 }
2613
2614 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2615 {
2616         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2617         struct pci_dev *pdev = to_pci_dev(dev->dev);
2618
2619         if (pci_get_drvdata(pdev))
2620                 device_release_driver(&pdev->dev);
2621         nvme_put_ctrl(&dev->ctrl);
2622 }
2623
2624 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2625 {
2626         *val = readl(to_nvme_dev(ctrl)->bar + off);
2627         return 0;
2628 }
2629
2630 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2631 {
2632         writel(val, to_nvme_dev(ctrl)->bar + off);
2633         return 0;
2634 }
2635
2636 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2637 {
2638         *val = readq(to_nvme_dev(ctrl)->bar + off);
2639         return 0;
2640 }
2641
2642 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2643 {
2644         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2645
2646         return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2647 }
2648
2649 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2650         .name                   = "pcie",
2651         .module                 = THIS_MODULE,
2652         .flags                  = NVME_F_METADATA_SUPPORTED |
2653                                   NVME_F_PCI_P2PDMA,
2654         .reg_read32             = nvme_pci_reg_read32,
2655         .reg_write32            = nvme_pci_reg_write32,
2656         .reg_read64             = nvme_pci_reg_read64,
2657         .free_ctrl              = nvme_pci_free_ctrl,
2658         .submit_async_event     = nvme_pci_submit_async_event,
2659         .get_address            = nvme_pci_get_address,
2660 };
2661
2662 static int nvme_dev_map(struct nvme_dev *dev)
2663 {
2664         struct pci_dev *pdev = to_pci_dev(dev->dev);
2665
2666         if (pci_request_mem_regions(pdev, "nvme"))
2667                 return -ENODEV;
2668
2669         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2670                 goto release;
2671
2672         return 0;
2673   release:
2674         pci_release_mem_regions(pdev);
2675         return -ENODEV;
2676 }
2677
2678 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2679 {
2680         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2681                 /*
2682                  * Several Samsung devices seem to drop off the PCIe bus
2683                  * randomly when APST is on and uses the deepest sleep state.
2684                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2685                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2686                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2687                  * laptops.
2688                  */
2689                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2690                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2691                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2692                         return NVME_QUIRK_NO_DEEPEST_PS;
2693         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2694                 /*
2695                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2696                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2697                  * within few minutes after bootup on a Coffee Lake board -
2698                  * ASUS PRIME Z370-A
2699                  */
2700                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2701                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2702                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2703                         return NVME_QUIRK_NO_APST;
2704         }
2705
2706         return 0;
2707 }
2708
2709 static void nvme_async_probe(void *data, async_cookie_t cookie)
2710 {
2711         struct nvme_dev *dev = data;
2712
2713         nvme_reset_ctrl_sync(&dev->ctrl);
2714         flush_work(&dev->ctrl.scan_work);
2715         nvme_put_ctrl(&dev->ctrl);
2716 }
2717
2718 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2719 {
2720         int node, result = -ENOMEM;
2721         struct nvme_dev *dev;
2722         unsigned long quirks = id->driver_data;
2723         size_t alloc_size;
2724
2725         node = dev_to_node(&pdev->dev);
2726         if (node == NUMA_NO_NODE)
2727                 set_dev_node(&pdev->dev, first_memory_node);
2728
2729         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2730         if (!dev)
2731                 return -ENOMEM;
2732
2733         dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2734                                         GFP_KERNEL, node);
2735         if (!dev->queues)
2736                 goto free;
2737
2738         dev->dev = get_device(&pdev->dev);
2739         pci_set_drvdata(pdev, dev);
2740
2741         result = nvme_dev_map(dev);
2742         if (result)
2743                 goto put_pci;
2744
2745         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2746         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2747         mutex_init(&dev->shutdown_lock);
2748
2749         result = nvme_setup_prp_pools(dev);
2750         if (result)
2751                 goto unmap;
2752
2753         quirks |= check_vendor_combination_bug(pdev);
2754
2755         /*
2756          * Double check that our mempool alloc size will cover the biggest
2757          * command we support.
2758          */
2759         alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2760                                                 NVME_MAX_SEGS, true);
2761         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2762
2763         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2764                                                 mempool_kfree,
2765                                                 (void *) alloc_size,
2766                                                 GFP_KERNEL, node);
2767         if (!dev->iod_mempool) {
2768                 result = -ENOMEM;
2769                 goto release_pools;
2770         }
2771
2772         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2773                         quirks);
2774         if (result)
2775                 goto release_mempool;
2776
2777         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2778
2779         nvme_get_ctrl(&dev->ctrl);
2780         async_schedule(nvme_async_probe, dev);
2781
2782         return 0;
2783
2784  release_mempool:
2785         mempool_destroy(dev->iod_mempool);
2786  release_pools:
2787         nvme_release_prp_pools(dev);
2788  unmap:
2789         nvme_dev_unmap(dev);
2790  put_pci:
2791         put_device(dev->dev);
2792  free:
2793         kfree(dev->queues);
2794         kfree(dev);
2795         return result;
2796 }
2797
2798 static void nvme_reset_prepare(struct pci_dev *pdev)
2799 {
2800         struct nvme_dev *dev = pci_get_drvdata(pdev);
2801         nvme_dev_disable(dev, false);
2802 }
2803
2804 static void nvme_reset_done(struct pci_dev *pdev)
2805 {
2806         struct nvme_dev *dev = pci_get_drvdata(pdev);
2807         nvme_reset_ctrl_sync(&dev->ctrl);
2808 }
2809
2810 static void nvme_shutdown(struct pci_dev *pdev)
2811 {
2812         struct nvme_dev *dev = pci_get_drvdata(pdev);
2813         nvme_dev_disable(dev, true);
2814 }
2815
2816 /*
2817  * The driver's remove may be called on a device in a partially initialized
2818  * state. This function must not have any dependencies on the device state in
2819  * order to proceed.
2820  */
2821 static void nvme_remove(struct pci_dev *pdev)
2822 {
2823         struct nvme_dev *dev = pci_get_drvdata(pdev);
2824
2825         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2826         pci_set_drvdata(pdev, NULL);
2827
2828         if (!pci_device_is_present(pdev)) {
2829                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2830                 nvme_dev_disable(dev, true);
2831                 nvme_dev_remove_admin(dev);
2832         }
2833
2834         flush_work(&dev->ctrl.reset_work);
2835         nvme_stop_ctrl(&dev->ctrl);
2836         nvme_remove_namespaces(&dev->ctrl);
2837         nvme_dev_disable(dev, true);
2838         nvme_release_cmb(dev);
2839         nvme_free_host_mem(dev);
2840         nvme_dev_remove_admin(dev);
2841         nvme_free_queues(dev, 0);
2842         nvme_uninit_ctrl(&dev->ctrl);
2843         nvme_release_prp_pools(dev);
2844         nvme_dev_unmap(dev);
2845         nvme_put_ctrl(&dev->ctrl);
2846 }
2847
2848 #ifdef CONFIG_PM_SLEEP
2849 static int nvme_suspend(struct device *dev)
2850 {
2851         struct pci_dev *pdev = to_pci_dev(dev);
2852         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2853
2854         nvme_dev_disable(ndev, true);
2855         return 0;
2856 }
2857
2858 static int nvme_resume(struct device *dev)
2859 {
2860         struct pci_dev *pdev = to_pci_dev(dev);
2861         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2862
2863         nvme_reset_ctrl(&ndev->ctrl);
2864         return 0;
2865 }
2866 #endif
2867
2868 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2869
2870 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2871                                                 pci_channel_state_t state)
2872 {
2873         struct nvme_dev *dev = pci_get_drvdata(pdev);
2874
2875         /*
2876          * A frozen channel requires a reset. When detected, this method will
2877          * shutdown the controller to quiesce. The controller will be restarted
2878          * after the slot reset through driver's slot_reset callback.
2879          */
2880         switch (state) {
2881         case pci_channel_io_normal:
2882                 return PCI_ERS_RESULT_CAN_RECOVER;
2883         case pci_channel_io_frozen:
2884                 dev_warn(dev->ctrl.device,
2885                         "frozen state error detected, reset controller\n");
2886                 nvme_dev_disable(dev, false);
2887                 return PCI_ERS_RESULT_NEED_RESET;
2888         case pci_channel_io_perm_failure:
2889                 dev_warn(dev->ctrl.device,
2890                         "failure state error detected, request disconnect\n");
2891                 return PCI_ERS_RESULT_DISCONNECT;
2892         }
2893         return PCI_ERS_RESULT_NEED_RESET;
2894 }
2895
2896 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2897 {
2898         struct nvme_dev *dev = pci_get_drvdata(pdev);
2899
2900         dev_info(dev->ctrl.device, "restart after slot reset\n");
2901         pci_restore_state(pdev);
2902         nvme_reset_ctrl(&dev->ctrl);
2903         return PCI_ERS_RESULT_RECOVERED;
2904 }
2905
2906 static void nvme_error_resume(struct pci_dev *pdev)
2907 {
2908         struct nvme_dev *dev = pci_get_drvdata(pdev);
2909
2910         flush_work(&dev->ctrl.reset_work);
2911 }
2912
2913 static const struct pci_error_handlers nvme_err_handler = {
2914         .error_detected = nvme_error_detected,
2915         .slot_reset     = nvme_slot_reset,
2916         .resume         = nvme_error_resume,
2917         .reset_prepare  = nvme_reset_prepare,
2918         .reset_done     = nvme_reset_done,
2919 };
2920
2921 static const struct pci_device_id nvme_id_table[] = {
2922         { PCI_VDEVICE(INTEL, 0x0953),
2923                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2924                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2925         { PCI_VDEVICE(INTEL, 0x0a53),
2926                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2927                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2928         { PCI_VDEVICE(INTEL, 0x0a54),
2929                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2930                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2931         { PCI_VDEVICE(INTEL, 0x0a55),
2932                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2933                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2934         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2935                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2936                                 NVME_QUIRK_MEDIUM_PRIO_SQ },
2937         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
2938                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2939         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2940                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2941         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
2942                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2943         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2944                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2945         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
2946                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2947         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2948                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2949         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
2950                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2951         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
2952                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2953         { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
2954                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2955         { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
2956                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2957         { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
2958                 .driver_data = NVME_QUIRK_LIGHTNVM, },
2959         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2960         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2961         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2962         { 0, }
2963 };
2964 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2965
2966 static struct pci_driver nvme_driver = {
2967         .name           = "nvme",
2968         .id_table       = nvme_id_table,
2969         .probe          = nvme_probe,
2970         .remove         = nvme_remove,
2971         .shutdown       = nvme_shutdown,
2972         .driver         = {
2973                 .pm     = &nvme_dev_pm_ops,
2974         },
2975         .sriov_configure = pci_sriov_configure_simple,
2976         .err_handler    = &nvme_err_handler,
2977 };
2978
2979 static int __init nvme_init(void)
2980 {
2981         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
2982         return pci_register_driver(&nvme_driver);
2983 }
2984
2985 static void __exit nvme_exit(void)
2986 {
2987         pci_unregister_driver(&nvme_driver);
2988         flush_workqueue(nvme_wq);
2989         _nvme_check_size();
2990 }
2991
2992 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2993 MODULE_LICENSE("GPL");
2994 MODULE_VERSION("1.0");
2995 module_init(nvme_init);
2996 module_exit(nvme_exit);