drivers/net/wireless/rtlwifi/rtl8723ae/dm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  ****************************************************************************
  29  */
  30
  31 #ifndef __RTL8723E_DM_H__
  32 #define __RTL8723E_DM_H__
  33
  34 #define HAL_DM_HIPWR_DISABLE                    BIT(1)
  35
  36 #define OFDM_TABLE_SIZE                         37
  37 #define CCK_TABLE_SIZE                          33
  38
  39 #define DM_DIG_THRESH_HIGH                      40
  40 #define DM_DIG_THRESH_LOW                       35
  41
  42 #define DM_FALSEALARM_THRESH_LOW                400
  43 #define DM_FALSEALARM_THRESH_HIGH               1000
  44
  45 #define DM_DIG_MAX                              0x3e
  46 #define DM_DIG_MIN                              0x1e
  47
  48 #define DM_DIG_FA_UPPER                         0x32
  49 #define DM_DIG_FA_LOWER                         0x20
  50 #define DM_DIG_FA_TH0                           0x20
  51 #define DM_DIG_FA_TH1                           0x100
  52 #define DM_DIG_FA_TH2                           0x200
  53
  54 #define DM_DIG_BACKOFF_MAX                      12
  55 #define DM_DIG_BACKOFF_MIN                      -4
  56 #define DM_DIG_BACKOFF_DEFAULT                  10
  57
  58 #define DM_RATR_STA_INIT                        0
  59
  60 #define TXHIGHPWRLEVEL_NORMAL                   0
  61 #define TXHIGHPWRLEVEL_LEVEL1                   1
  62 #define TXHIGHPWRLEVEL_LEVEL2                   2
  63 #define TXHIGHPWRLEVEL_BT1                      3
  64 #define TXHIGHPWRLEVEL_BT2                      4
  65
  66 #define DM_TYPE_BYDRIVER                        1
  67
  68 #define TX_POWER_NEAR_FIELD_THRESH_LVL2         74
  69 #define TX_POWER_NEAR_FIELD_THRESH_LVL1         67
  70
  71 struct swat_t {
  72         u8 failure_cnt;
  73         u8 try_flag;
  74         u8 stop_trying;
  75         long pre_rssi;
  76         long trying_threshold;
  77         u8 cur_antenna;
  78         u8 pre_antenna;
  79 };
  80
  81 enum tag_dynamic_init_gain_operation_type_definition {
  82         DIG_TYPE_THRESH_HIGH = 0,
  83         DIG_TYPE_THRESH_LOW = 1,
  84         DIG_TYPE_BACKOFF = 2,
  85         DIG_TYPE_RX_GAIN_MIN = 3,
  86         DIG_TYPE_RX_GAIN_MAX = 4,
  87         DIG_TYPE_ENABLE = 5,
  88         DIG_TYPE_DISABLE = 6,
  89         DIG_OP_TYPE_MAX
  90 };
  91
  92 enum tag_cck_packet_detection_threshold_type_definition {
  93         CCK_PD_STAGE_LowRssi = 0,
  94         CCK_PD_STAGE_HighRssi = 1,
  95         CCK_FA_STAGE_Low = 2,
  96         CCK_FA_STAGE_High = 3,
  97         CCK_PD_STAGE_MAX = 4,
  98 };
  99
 100 enum dm_1r_cca_e {
 101         CCA_1R = 0,
 102         CCA_2R = 1,
 103         CCA_MAX = 2,
 104 };
 105
 106 enum dm_rf_e {
 107         RF_SAVE = 0,
 108         RF_NORMAL = 1,
 109         RF_MAX = 2,
 110 };
 111
 112 enum dm_sw_ant_switch_e {
 113         ANS_ANTENNA_B = 1,
 114         ANS_ANTENNA_A = 2,
 115         ANS_ANTENNA_MAX = 3,
 116 };
 117
 118 enum dm_dig_ext_port_alg_e {
 119         DIG_EXT_PORT_STAGE_0 = 0,
 120         DIG_EXT_PORT_STAGE_1 = 1,
 121         DIG_EXT_PORT_STAGE_2 = 2,
 122         DIG_EXT_PORT_STAGE_3 = 3,
 123         DIG_EXT_PORT_STAGE_MAX = 4,
 124 };
 125
 126 enum dm_dig_connect_e {
 127         DIG_STA_DISCONNECT = 0,
 128         DIG_STA_CONNECT = 1,
 129         DIG_STA_BEFORE_CONNECT = 2,
 130         DIG_MULTISTA_DISCONNECT = 3,
 131         DIG_MULTISTA_CONNECT = 4,
 132         DIG_CONNECT_MAX
 133 };
 134
 135 #define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
 136         ((((struct rtl_priv *)(_priv))->mac80211.opmode ==      \
 137         NL80211_IFTYPE_ADHOC) ?  \
 138         (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) \
 139         : (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb))
 140
 141 void rtl8723ae_dm_init(struct ieee80211_hw *hw);
 142 void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw);
 143 void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw);
 144 void rtl8723ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
 145 void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
 146 void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
 147 void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw);
 148
 149 #endif