drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
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  29  *  Intel Linux Wireless <ilw@linux.intel.com>
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  33  *
  34  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  35  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
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  39  * modification, are permitted provided that the following conditions
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  43  *    notice, this list of conditions and the following disclaimer.
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  45  *    notice, this list of conditions and the following disclaimer in
  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
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  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/pci.h>
  66 #include <linux/pci-aspm.h>
  67 #include <linux/interrupt.h>
  68 #include <linux/debugfs.h>
  69 #include <linux/sched.h>
  70 #include <linux/bitops.h>
  71 #include <linux/gfp.h>
  72 #include <linux/vmalloc.h>
  73
  74 #include "iwl-drv.h"
  75 #include "iwl-trans.h"
  76 #include "iwl-csr.h"
  77 #include "iwl-prph.h"
  78 #include "iwl-scd.h"
  79 #include "iwl-agn-hw.h"
  80 #include "iwl-fw-error-dump.h"
  81 #include "internal.h"
  82 #include "iwl-fh.h"
  83
  84 /* extended range in FW SRAM */
  85 #define IWL_FW_MEM_EXTENDED_START       0x40000
  86 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  87
  88 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  89 {
  90         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  91
  92         if (!trans_pcie->fw_mon_page)
  93                 return;
  94
  95         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  96                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
  97         __free_pages(trans_pcie->fw_mon_page,
  98                      get_order(trans_pcie->fw_mon_size));
  99         trans_pcie->fw_mon_page = NULL;
 100         trans_pcie->fw_mon_phys = 0;
 101         trans_pcie->fw_mon_size = 0;
 102 }
 103
 104 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
 105 {
 106         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 107         struct page *page;
 108         dma_addr_t phys;
 109         u32 size;
 110         u8 power;
 111
 112         if (trans_pcie->fw_mon_page) {
 113                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 114                                            trans_pcie->fw_mon_size,
 115                                            DMA_FROM_DEVICE);
 116                 return;
 117         }
 118
 119         phys = 0;
 120         for (power = 26; power >= 11; power--) {
 121                 int order;
 122
 123                 size = BIT(power);
 124                 order = get_order(size);
 125                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 126                                    order);
 127                 if (!page)
 128                         continue;
 129
 130                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 131                                     DMA_FROM_DEVICE);
 132                 if (dma_mapping_error(trans->dev, phys)) {
 133                         __free_pages(page, order);
 134                         continue;
 135                 }
 136                 IWL_INFO(trans,
 137                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 138                          size, order);
 139                 break;
 140         }
 141
 142         if (WARN_ON_ONCE(!page))
 143                 return;
 144
 145         trans_pcie->fw_mon_page = page;
 146         trans_pcie->fw_mon_phys = phys;
 147         trans_pcie->fw_mon_size = size;
 148 }
 149
 150 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 151 {
 152         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 153                     ((reg & 0x0000ffff) | (2 << 28)));
 154         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 155 }
 156
 157 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 158 {
 159         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 160         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 161                     ((reg & 0x0000ffff) | (3 << 28)));
 162 }
 163
 164 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 165 {
 166         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 167                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 168                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 169                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 170         else
 171                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 172                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 173                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 174 }
 175
 176 /* PCI registers */
 177 #define PCI_CFG_RETRY_TIMEOUT   0x041
 178
 179 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 180 {
 181         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 182         u16 lctl;
 183         u16 cap;
 184
 185         /*
 186          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 187          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 188          * If so (likely), disable L0S, so device moves directly L0->L1;
 189          *    costs negligible amount of power savings.
 190          * If not (unlikely), enable L0S, so there is at least some
 191          *    power savings, even without L1.
 192          */
 193         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 194         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 195                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 196         else
 197                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 198         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 199
 200         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 201         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 202         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 203                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 204                  trans->ltr_enabled ? "En" : "Dis");
 205 }
 206
 207 /*
 208  * Start up NIC's basic functionality after it has been reset
 209  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 210  * NOTE:  This does not load uCode nor start the embedded processor
 211  */
 212 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 213 {
 214         int ret = 0;
 215         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 216
 217         /*
 218          * Use "set_bit" below rather than "write", to preserve any hardware
 219          * bits already set by default after reset.
 220          */
 221
 222         /* Disable L0S exit timer (platform NMI Work/Around) */
 223         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 224                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 225                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 226
 227         /*
 228          * Disable L0s without affecting L1;
 229          *  don't wait for ICH L0s (ICH bug W/A)
 230          */
 231         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 232                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 233
 234         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 235         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 236
 237         /*
 238          * Enable HAP INTA (interrupt from management bus) to
 239          * wake device's PCI Express link L1a -> L0s
 240          */
 241         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 242                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 243
 244         iwl_pcie_apm_config(trans);
 245
 246         /* Configure analog phase-lock-loop before activating to D0A */
 247         if (trans->cfg->base_params->pll_cfg_val)
 248                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 249                             trans->cfg->base_params->pll_cfg_val);
 250
 251         /*
 252          * Set "initialization complete" bit to move adapter from
 253          * D0U* --> D0A* (powered-up active) state.
 254          */
 255         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 256
 257         /*
 258          * Wait for clock stabilization; once stabilized, access to
 259          * device-internal resources is supported, e.g. iwl_write_prph()
 260          * and accesses to uCode SRAM.
 261          */
 262         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 263                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 264                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 265         if (ret < 0) {
 266                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 267                 goto out;
 268         }
 269
 270         if (trans->cfg->host_interrupt_operation_mode) {
 271                 /*
 272                  * This is a bit of an abuse - This is needed for 7260 / 3160
 273                  * only check host_interrupt_operation_mode even if this is
 274                  * not related to host_interrupt_operation_mode.
 275                  *
 276                  * Enable the oscillator to count wake up time for L1 exit. This
 277                  * consumes slightly more power (100uA) - but allows to be sure
 278                  * that we wake up from L1 on time.
 279                  *
 280                  * This looks weird: read twice the same register, discard the
 281                  * value, set a bit, and yet again, read that same register
 282                  * just to discard the value. But that's the way the hardware
 283                  * seems to like it.
 284                  */
 285                 iwl_read_prph(trans, OSC_CLK);
 286                 iwl_read_prph(trans, OSC_CLK);
 287                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 288                 iwl_read_prph(trans, OSC_CLK);
 289                 iwl_read_prph(trans, OSC_CLK);
 290         }
 291
 292         /*
 293          * Enable DMA clock and wait for it to stabilize.
 294          *
 295          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 296          * bits do not disable clocks.  This preserves any hardware
 297          * bits already set by default in "CLK_CTRL_REG" after reset.
 298          */
 299         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
 300                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 301                                APMG_CLK_VAL_DMA_CLK_RQT);
 302                 udelay(20);
 303
 304                 /* Disable L1-Active */
 305                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 306                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 307
 308                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 309                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 310                                APMG_RTC_INT_STT_RFKILL);
 311         }
 312
 313         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 314
 315 out:
 316         return ret;
 317 }
 318
 319 /*
 320  * Enable LP XTAL to avoid HW bug where device may consume much power if
 321  * FW is not loaded after device reset. LP XTAL is disabled by default
 322  * after device HW reset. Do it only if XTAL is fed by internal source.
 323  * Configure device's "persistence" mode to avoid resetting XTAL again when
 324  * SHRD_HW_RST occurs in S3.
 325  */
 326 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 327 {
 328         int ret;
 329         u32 apmg_gp1_reg;
 330         u32 apmg_xtal_cfg_reg;
 331         u32 dl_cfg_reg;
 332
 333         /* Force XTAL ON */
 334         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 335                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 336
 337         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 338         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 339
 340         udelay(10);
 341
 342         /*
 343          * Set "initialization complete" bit to move adapter from
 344          * D0U* --> D0A* (powered-up active) state.
 345          */
 346         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 347
 348         /*
 349          * Wait for clock stabilization; once stabilized, access to
 350          * device-internal resources is possible.
 351          */
 352         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 353                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 354                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 355                            25000);
 356         if (WARN_ON(ret < 0)) {
 357                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 358                 /* Release XTAL ON request */
 359                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 360                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 361                 return;
 362         }
 363
 364         /*
 365          * Clear "disable persistence" to avoid LP XTAL resetting when
 366          * SHRD_HW_RST is applied in S3.
 367          */
 368         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 369                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 370
 371         /*
 372          * Force APMG XTAL to be active to prevent its disabling by HW
 373          * caused by APMG idle state.
 374          */
 375         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 376                                                     SHR_APMG_XTAL_CFG_REG);
 377         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 378                                  apmg_xtal_cfg_reg |
 379                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 380
 381         /*
 382          * Reset entire device again - do controller reset (results in
 383          * SHRD_HW_RST). Turn MAC off before proceeding.
 384          */
 385         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 386
 387         udelay(10);
 388
 389         /* Enable LP XTAL by indirect access through CSR */
 390         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 391         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 392                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 393                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 394
 395         /* Clear delay line clock power up */
 396         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 397         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 398                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 399
 400         /*
 401          * Enable persistence mode to avoid LP XTAL resetting when
 402          * SHRD_HW_RST is applied in S3.
 403          */
 404         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 405                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 406
 407         /*
 408          * Clear "initialization complete" bit to move adapter from
 409          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 410          */
 411         iwl_clear_bit(trans, CSR_GP_CNTRL,
 412                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 413
 414         /* Activates XTAL resources monitor */
 415         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 416                                  CSR_MONITOR_XTAL_RESOURCES);
 417
 418         /* Release XTAL ON request */
 419         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 420                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 421         udelay(10);
 422
 423         /* Release APMG XTAL */
 424         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 425                                  apmg_xtal_cfg_reg &
 426                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 427 }
 428
 429 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 430 {
 431         int ret = 0;
 432
 433         /* stop device's busmaster DMA activity */
 434         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 435
 436         ret = iwl_poll_bit(trans, CSR_RESET,
 437                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 438                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 439         if (ret < 0)
 440                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 441
 442         IWL_DEBUG_INFO(trans, "stop master\n");
 443
 444         return ret;
 445 }
 446
 447 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 448 {
 449         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 450
 451         if (op_mode_leave) {
 452                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 453                         iwl_pcie_apm_init(trans);
 454
 455                 /* inform ME that we are leaving */
 456                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 457                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 458                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 459                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 460                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 461                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 462                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 463                 mdelay(5);
 464         }
 465
 466         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 467
 468         /* Stop device's DMA activity */
 469         iwl_pcie_apm_stop_master(trans);
 470
 471         if (trans->cfg->lp_xtal_workaround) {
 472                 iwl_pcie_apm_lp_xtal_enable(trans);
 473                 return;
 474         }
 475
 476         /* Reset the entire device */
 477         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 478
 479         udelay(10);
 480
 481         /*
 482          * Clear "initialization complete" bit to move adapter from
 483          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 484          */
 485         iwl_clear_bit(trans, CSR_GP_CNTRL,
 486                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 487 }
 488
 489 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 490 {
 491         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 492
 493         /* nic_init */
 494         spin_lock(&trans_pcie->irq_lock);
 495         iwl_pcie_apm_init(trans);
 496
 497         spin_unlock(&trans_pcie->irq_lock);
 498
 499         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 500                 iwl_pcie_set_pwr(trans, false);
 501
 502         iwl_op_mode_nic_config(trans->op_mode);
 503
 504         /* Allocate the RX queue, or reset if it is already allocated */
 505         iwl_pcie_rx_init(trans);
 506
 507         /* Allocate or reset and init all Tx and Command queues */
 508         if (iwl_pcie_tx_init(trans))
 509                 return -ENOMEM;
 510
 511         if (trans->cfg->base_params->shadow_reg_enable) {
 512                 /* enable shadow regs in HW */
 513                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 514                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 515         }
 516
 517         return 0;
 518 }
 519
 520 #define HW_READY_TIMEOUT (50)
 521
 522 /* Note: returns poll_bit return value, which is >= 0 if success */
 523 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 524 {
 525         int ret;
 526
 527         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 528                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 529
 530         /* See if we got it */
 531         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 532                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 533                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 534                            HW_READY_TIMEOUT);
 535
 536         if (ret >= 0)
 537                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 538
 539         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 540         return ret;
 541 }
 542
 543 /* Note: returns standard 0/-ERROR code */
 544 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 545 {
 546         int ret;
 547         int t = 0;
 548         int iter;
 549
 550         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 551
 552         ret = iwl_pcie_set_hw_ready(trans);
 553         /* If the card is ready, exit 0 */
 554         if (ret >= 0)
 555                 return 0;
 556
 557         for (iter = 0; iter < 10; iter++) {
 558                 /* If HW is not ready, prepare the conditions to check again */
 559                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 560                             CSR_HW_IF_CONFIG_REG_PREPARE);
 561
 562                 do {
 563                         ret = iwl_pcie_set_hw_ready(trans);
 564                         if (ret >= 0)
 565                                 return 0;
 566
 567                         usleep_range(200, 1000);
 568                         t += 200;
 569                 } while (t < 150000);
 570                 msleep(25);
 571         }
 572
 573         IWL_ERR(trans, "Couldn't prepare the card\n");
 574
 575         return ret;
 576 }
 577
 578 /*
 579  * ucode
 580  */
 581 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 582                                    dma_addr_t phy_addr, u32 byte_cnt)
 583 {
 584         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 585         int ret;
 586
 587         trans_pcie->ucode_write_complete = false;
 588
 589         iwl_write_direct32(trans,
 590                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 591                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 592
 593         iwl_write_direct32(trans,
 594                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 595                            dst_addr);
 596
 597         iwl_write_direct32(trans,
 598                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 599                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 600
 601         iwl_write_direct32(trans,
 602                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 603                            (iwl_get_dma_hi_addr(phy_addr)
 604                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 605
 606         iwl_write_direct32(trans,
 607                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 608                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 609                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 610                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 611
 612         iwl_write_direct32(trans,
 613                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 614                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 615                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 616                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 617
 618         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 619                                  trans_pcie->ucode_write_complete, 5 * HZ);
 620         if (!ret) {
 621                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 622                 return -ETIMEDOUT;
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 629                             const struct fw_desc *section)
 630 {
 631         u8 *v_addr;
 632         dma_addr_t p_addr;
 633         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 634         int ret = 0;
 635
 636         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 637                      section_num);
 638
 639         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 640                                     GFP_KERNEL | __GFP_NOWARN);
 641         if (!v_addr) {
 642                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 643                 chunk_sz = PAGE_SIZE;
 644                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 645                                             &p_addr, GFP_KERNEL);
 646                 if (!v_addr)
 647                         return -ENOMEM;
 648         }
 649
 650         for (offset = 0; offset < section->len; offset += chunk_sz) {
 651                 u32 copy_size, dst_addr;
 652                 bool extended_addr = false;
 653
 654                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 655                 dst_addr = section->offset + offset;
 656
 657                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 658                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 659                         extended_addr = true;
 660
 661                 if (extended_addr)
 662                         iwl_set_bits_prph(trans, LMPM_CHICK,
 663                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 664
 665                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 666                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 667                                                    copy_size);
 668
 669                 if (extended_addr)
 670                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 671                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 672
 673                 if (ret) {
 674                         IWL_ERR(trans,
 675                                 "Could not load the [%d] uCode section\n",
 676                                 section_num);
 677                         break;
 678                 }
 679         }
 680
 681         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 682         return ret;
 683 }
 684
 685 /*
 686  * Driver Takes the ownership on secure machine before FW load
 687  * and prevent race with the BT load.
 688  * W/A for ROM bug. (should be remove in the next Si step)
 689  */
 690 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 691 {
 692         u32 val, loop = 1000;
 693
 694         /*
 695          * Check the RSA semaphore is accessible.
 696          * If the HW isn't locked and the rsa semaphore isn't accessible,
 697          * we are in trouble.
 698          */
 699         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 700         if (val & (BIT(1) | BIT(17))) {
 701                 IWL_INFO(trans,
 702                          "can't access the RSA semaphore it is write protected\n");
 703                 return 0;
 704         }
 705
 706         /* take ownership on the AUX IF */
 707         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 708         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 709
 710         do {
 711                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 712                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 713                 if (val == 0x1) {
 714                         iwl_write_prph(trans, RSA_ENABLE, 0);
 715                         return 0;
 716                 }
 717
 718                 udelay(10);
 719                 loop--;
 720         } while (loop > 0);
 721
 722         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 723         return -EIO;
 724 }
 725
 726 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 727                                            const struct fw_img *image,
 728                                            int cpu,
 729                                            int *first_ucode_section)
 730 {
 731         int shift_param;
 732         int i, ret = 0, sec_num = 0x1;
 733         u32 val, last_read_idx = 0;
 734
 735         if (cpu == 1) {
 736                 shift_param = 0;
 737                 *first_ucode_section = 0;
 738         } else {
 739                 shift_param = 16;
 740                 (*first_ucode_section)++;
 741         }
 742
 743         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 744                 last_read_idx = i;
 745
 746                 if (!image->sec[i].data ||
 747                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 748                         IWL_DEBUG_FW(trans,
 749                                      "Break since Data not valid or Empty section, sec = %d\n",
 750                                      i);
 751                         break;
 752                 }
 753
 754                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 755                 if (ret)
 756                         return ret;
 757
 758                 /* Notify the ucode of the loaded section number and status */
 759                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 760                 val = val | (sec_num << shift_param);
 761                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 762                 sec_num = (sec_num << 1) | 0x1;
 763         }
 764
 765         *first_ucode_section = last_read_idx;
 766
 767         if (cpu == 1)
 768                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF);
 769         else
 770                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
 771
 772         return 0;
 773 }
 774
 775 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 776                                       const struct fw_img *image,
 777                                       int cpu,
 778                                       int *first_ucode_section)
 779 {
 780         int shift_param;
 781         int i, ret = 0;
 782         u32 last_read_idx = 0;
 783
 784         if (cpu == 1) {
 785                 shift_param = 0;
 786                 *first_ucode_section = 0;
 787         } else {
 788                 shift_param = 16;
 789                 (*first_ucode_section)++;
 790         }
 791
 792         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 793                 last_read_idx = i;
 794
 795                 if (!image->sec[i].data ||
 796                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
 797                         IWL_DEBUG_FW(trans,
 798                                      "Break since Data not valid or Empty section, sec = %d\n",
 799                                      i);
 800                         break;
 801                 }
 802
 803                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 804                 if (ret)
 805                         return ret;
 806         }
 807
 808         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 809                 iwl_set_bits_prph(trans,
 810                                   CSR_UCODE_LOAD_STATUS_ADDR,
 811                                   (LMPM_CPU_UCODE_LOADING_COMPLETED |
 812                                    LMPM_CPU_HDRS_LOADING_COMPLETED |
 813                                    LMPM_CPU_UCODE_LOADING_STARTED) <<
 814                                         shift_param);
 815
 816         *first_ucode_section = last_read_idx;
 817
 818         return 0;
 819 }
 820
 821 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 822 {
 823         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 824         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 825         int i;
 826
 827         if (dest->version)
 828                 IWL_ERR(trans,
 829                         "DBG DEST version is %d - expect issues\n",
 830                         dest->version);
 831
 832         IWL_INFO(trans, "Applying debug destination %s\n",
 833                  get_fw_dbg_mode_string(dest->monitor_mode));
 834
 835         if (dest->monitor_mode == EXTERNAL_MODE)
 836                 iwl_pcie_alloc_fw_monitor(trans);
 837         else
 838                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 839
 840         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 841                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 842                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 843
 844                 switch (dest->reg_ops[i].op) {
 845                 case CSR_ASSIGN:
 846                         iwl_write32(trans, addr, val);
 847                         break;
 848                 case CSR_SETBIT:
 849                         iwl_set_bit(trans, addr, BIT(val));
 850                         break;
 851                 case CSR_CLEARBIT:
 852                         iwl_clear_bit(trans, addr, BIT(val));
 853                         break;
 854                 case PRPH_ASSIGN:
 855                         iwl_write_prph(trans, addr, val);
 856                         break;
 857                 case PRPH_SETBIT:
 858                         iwl_set_bits_prph(trans, addr, BIT(val));
 859                         break;
 860                 case PRPH_CLEARBIT:
 861                         iwl_clear_bits_prph(trans, addr, BIT(val));
 862                         break;
 863                 default:
 864                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 865                                 dest->reg_ops[i].op);
 866                         break;
 867                 }
 868         }
 869
 870         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 871                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 872                                trans_pcie->fw_mon_phys >> dest->base_shift);
 873                 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 874                                (trans_pcie->fw_mon_phys +
 875                                 trans_pcie->fw_mon_size) >> dest->end_shift);
 876         }
 877 }
 878
 879 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 880                                 const struct fw_img *image)
 881 {
 882         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 883         int ret = 0;
 884         int first_ucode_section;
 885
 886         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 887                      image->is_dual_cpus ? "Dual" : "Single");
 888
 889         /* load to FW the binary non secured sections of CPU1 */
 890         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 891         if (ret)
 892                 return ret;
 893
 894         if (image->is_dual_cpus) {
 895                 /* set CPU2 header address */
 896                 iwl_write_prph(trans,
 897                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 898                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 899
 900                 /* load to FW the binary sections of CPU2 */
 901                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 902                                                  &first_ucode_section);
 903                 if (ret)
 904                         return ret;
 905         }
 906
 907         /* supported for 7000 only for the moment */
 908         if (iwlwifi_mod_params.fw_monitor &&
 909             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 910                 iwl_pcie_alloc_fw_monitor(trans);
 911
 912                 if (trans_pcie->fw_mon_size) {
 913                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 914                                        trans_pcie->fw_mon_phys >> 4);
 915                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 916                                        (trans_pcie->fw_mon_phys +
 917                                         trans_pcie->fw_mon_size) >> 4);
 918                 }
 919         } else if (trans->dbg_dest_tlv) {
 920                 iwl_pcie_apply_destination(trans);
 921         }
 922
 923         /* release CPU reset */
 924         iwl_write32(trans, CSR_RESET, 0);
 925
 926         return 0;
 927 }
 928
 929 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 930                                           const struct fw_img *image)
 931 {
 932         int ret = 0;
 933         int first_ucode_section;
 934
 935         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 936                      image->is_dual_cpus ? "Dual" : "Single");
 937
 938         if (trans->dbg_dest_tlv)
 939                 iwl_pcie_apply_destination(trans);
 940
 941         /* TODO: remove in the next Si step */
 942         ret = iwl_pcie_rsa_race_bug_wa(trans);
 943         if (ret)
 944                 return ret;
 945
 946         /* configure the ucode to be ready to get the secured image */
 947         /* release CPU reset */
 948         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 949
 950         /* load to FW the binary Secured sections of CPU1 */
 951         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
 952                                               &first_ucode_section);
 953         if (ret)
 954                 return ret;
 955
 956         /* load to FW the binary sections of CPU2 */
 957         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 2,
 958                                               &first_ucode_section);
 959         if (ret)
 960                 return ret;
 961
 962         return 0;
 963 }
 964
 965 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 966                                    const struct fw_img *fw, bool run_in_rfkill)
 967 {
 968         int ret;
 969         bool hw_rfkill;
 970
 971         /* This may fail if AMT took ownership of the device */
 972         if (iwl_pcie_prepare_card_hw(trans)) {
 973                 IWL_WARN(trans, "Exit HW not ready\n");
 974                 return -EIO;
 975         }
 976
 977         iwl_enable_rfkill_int(trans);
 978
 979         /* If platform's RF_KILL switch is NOT set to KILL */
 980         hw_rfkill = iwl_is_rfkill_set(trans);
 981         if (hw_rfkill)
 982                 set_bit(STATUS_RFKILL, &trans->status);
 983         else
 984                 clear_bit(STATUS_RFKILL, &trans->status);
 985         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
 986         if (hw_rfkill && !run_in_rfkill)
 987                 return -ERFKILL;
 988
 989         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 990
 991         ret = iwl_pcie_nic_init(trans);
 992         if (ret) {
 993                 IWL_ERR(trans, "Unable to init nic\n");
 994                 return ret;
 995         }
 996
 997         /* make sure rfkill handshake bits are cleared */
 998         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 999         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1000                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1001
1002         /* clear (again), then enable host interrupts */
1003         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1004         iwl_enable_interrupts(trans);
1005
1006         /* really make sure rfkill handshake bits are cleared */
1007         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1008         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1009
1010         /* Load the given image to the HW */
1011         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1012                 return iwl_pcie_load_given_ucode_8000(trans, fw);
1013         else
1014                 return iwl_pcie_load_given_ucode(trans, fw);
1015 }
1016
1017 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1018 {
1019         iwl_pcie_reset_ict(trans);
1020         iwl_pcie_tx_start(trans, scd_addr);
1021 }
1022
1023 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1024 {
1025         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1026         bool hw_rfkill, was_hw_rfkill;
1027
1028         was_hw_rfkill = iwl_is_rfkill_set(trans);
1029
1030         /* tell the device to stop sending interrupts */
1031         spin_lock(&trans_pcie->irq_lock);
1032         iwl_disable_interrupts(trans);
1033         spin_unlock(&trans_pcie->irq_lock);
1034
1035         /* device going down, Stop using ICT table */
1036         iwl_pcie_disable_ict(trans);
1037
1038         /*
1039          * If a HW restart happens during firmware loading,
1040          * then the firmware loading might call this function
1041          * and later it might be called again due to the
1042          * restart. So don't process again if the device is
1043          * already dead.
1044          */
1045         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1046                 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1047                 iwl_pcie_tx_stop(trans);
1048                 iwl_pcie_rx_stop(trans);
1049
1050                 /* Power-down device's busmaster DMA clocks */
1051                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1052                                APMG_CLK_VAL_DMA_CLK_RQT);
1053                 udelay(5);
1054         }
1055
1056         /* Make sure (redundant) we've released our request to stay awake */
1057         iwl_clear_bit(trans, CSR_GP_CNTRL,
1058                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1059
1060         /* Stop the device, and put it in low power state */
1061         iwl_pcie_apm_stop(trans, false);
1062
1063         /* stop and reset the on-board processor */
1064         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1065         udelay(20);
1066
1067         /*
1068          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1069          * This is a bug in certain verions of the hardware.
1070          * Certain devices also keep sending HW RF kill interrupt all
1071          * the time, unless the interrupt is ACKed even if the interrupt
1072          * should be masked. Re-ACK all the interrupts here.
1073          */
1074         spin_lock(&trans_pcie->irq_lock);
1075         iwl_disable_interrupts(trans);
1076         spin_unlock(&trans_pcie->irq_lock);
1077
1078
1079         /* clear all status bits */
1080         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1081         clear_bit(STATUS_INT_ENABLED, &trans->status);
1082         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1083         clear_bit(STATUS_RFKILL, &trans->status);
1084
1085         /*
1086          * Even if we stop the HW, we still want the RF kill
1087          * interrupt
1088          */
1089         iwl_enable_rfkill_int(trans);
1090
1091         /*
1092          * Check again since the RF kill state may have changed while
1093          * all the interrupts were disabled, in this case we couldn't
1094          * receive the RF kill interrupt and update the state in the
1095          * op_mode.
1096          * Don't call the op_mode if the rkfill state hasn't changed.
1097          * This allows the op_mode to call stop_device from the rfkill
1098          * notification without endless recursion. Under very rare
1099          * circumstances, we might have a small recursion if the rfkill
1100          * state changed exactly now while we were called from stop_device.
1101          * This is very unlikely but can happen and is supported.
1102          */
1103         hw_rfkill = iwl_is_rfkill_set(trans);
1104         if (hw_rfkill)
1105                 set_bit(STATUS_RFKILL, &trans->status);
1106         else
1107                 clear_bit(STATUS_RFKILL, &trans->status);
1108         if (hw_rfkill != was_hw_rfkill)
1109                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1110
1111         /* re-take ownership to prevent other users from stealing the deivce */
1112         iwl_pcie_prepare_card_hw(trans);
1113 }
1114
1115 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1116 {
1117         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1118                 iwl_trans_pcie_stop_device(trans);
1119 }
1120
1121 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1122 {
1123         iwl_disable_interrupts(trans);
1124
1125         /*
1126          * in testing mode, the host stays awake and the
1127          * hardware won't be reset (not even partially)
1128          */
1129         if (test)
1130                 return;
1131
1132         iwl_pcie_disable_ict(trans);
1133
1134         iwl_clear_bit(trans, CSR_GP_CNTRL,
1135                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1136         iwl_clear_bit(trans, CSR_GP_CNTRL,
1137                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1138
1139         /*
1140          * reset TX queues -- some of their registers reset during S3
1141          * so if we don't reset everything here the D3 image would try
1142          * to execute some invalid memory upon resume
1143          */
1144         iwl_trans_pcie_tx_reset(trans);
1145
1146         iwl_pcie_set_pwr(trans, true);
1147 }
1148
1149 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1150                                     enum iwl_d3_status *status,
1151                                     bool test)
1152 {
1153         u32 val;
1154         int ret;
1155
1156         if (test) {
1157                 iwl_enable_interrupts(trans);
1158                 *status = IWL_D3_STATUS_ALIVE;
1159                 return 0;
1160         }
1161
1162         /*
1163          * Also enables interrupts - none will happen as the device doesn't
1164          * know we're waking it up, only when the opmode actually tells it
1165          * after this call.
1166          */
1167         iwl_pcie_reset_ict(trans);
1168
1169         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1170         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1171
1172         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1173                 udelay(2);
1174
1175         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1176                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1177                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1178                            25000);
1179         if (ret < 0) {
1180                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1181                 return ret;
1182         }
1183
1184         iwl_pcie_set_pwr(trans, false);
1185
1186         iwl_trans_pcie_tx_reset(trans);
1187
1188         ret = iwl_pcie_rx_init(trans);
1189         if (ret) {
1190                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1191                 return ret;
1192         }
1193
1194         val = iwl_read32(trans, CSR_RESET);
1195         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1196                 *status = IWL_D3_STATUS_RESET;
1197         else
1198                 *status = IWL_D3_STATUS_ALIVE;
1199
1200         return 0;
1201 }
1202
1203 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1204 {
1205         bool hw_rfkill;
1206         int err;
1207
1208         err = iwl_pcie_prepare_card_hw(trans);
1209         if (err) {
1210                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1211                 return err;
1212         }
1213
1214         /* Reset the entire device */
1215         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1216
1217         usleep_range(10, 15);
1218
1219         iwl_pcie_apm_init(trans);
1220
1221         /* From now on, the op_mode will be kept updated about RF kill state */
1222         iwl_enable_rfkill_int(trans);
1223
1224         hw_rfkill = iwl_is_rfkill_set(trans);
1225         if (hw_rfkill)
1226                 set_bit(STATUS_RFKILL, &trans->status);
1227         else
1228                 clear_bit(STATUS_RFKILL, &trans->status);
1229         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1230
1231         return 0;
1232 }
1233
1234 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1235 {
1236         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1237
1238         /* disable interrupts - don't enable HW RF kill interrupt */
1239         spin_lock(&trans_pcie->irq_lock);
1240         iwl_disable_interrupts(trans);
1241         spin_unlock(&trans_pcie->irq_lock);
1242
1243         iwl_pcie_apm_stop(trans, true);
1244
1245         spin_lock(&trans_pcie->irq_lock);
1246         iwl_disable_interrupts(trans);
1247         spin_unlock(&trans_pcie->irq_lock);
1248
1249         iwl_pcie_disable_ict(trans);
1250 }
1251
1252 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1253 {
1254         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1255 }
1256
1257 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1258 {
1259         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1260 }
1261
1262 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1263 {
1264         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1265 }
1266
1267 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1268 {
1269         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1270                                ((reg & 0x000FFFFF) | (3 << 24)));
1271         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1272 }
1273
1274 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1275                                       u32 val)
1276 {
1277         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1278                                ((addr & 0x000FFFFF) | (3 << 24)));
1279         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1280 }
1281
1282 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1283 {
1284         WARN_ON(1);
1285         return 0;
1286 }
1287
1288 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1289                                      const struct iwl_trans_config *trans_cfg)
1290 {
1291         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1292
1293         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1294         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1295         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1296         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1297                 trans_pcie->n_no_reclaim_cmds = 0;
1298         else
1299                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1300         if (trans_pcie->n_no_reclaim_cmds)
1301                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1302                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1303
1304         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1305         if (trans_pcie->rx_buf_size_8k)
1306                 trans_pcie->rx_page_order = get_order(8 * 1024);
1307         else
1308                 trans_pcie->rx_page_order = get_order(4 * 1024);
1309
1310         trans_pcie->command_names = trans_cfg->command_names;
1311         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1312         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1313
1314         /* init ref_count to 1 (should be cleared when ucode is loaded) */
1315         trans_pcie->ref_count = 1;
1316
1317         /* Initialize NAPI here - it should be before registering to mac80211
1318          * in the opmode but after the HW struct is allocated.
1319          * As this function may be called again in some corner cases don't
1320          * do anything if NAPI was already initialized.
1321          */
1322         if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1323                 init_dummy_netdev(&trans_pcie->napi_dev);
1324                 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1325                                      &trans_pcie->napi_dev,
1326                                      iwl_pcie_dummy_napi_poll, 64);
1327         }
1328 }
1329
1330 void iwl_trans_pcie_free(struct iwl_trans *trans)
1331 {
1332         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1333
1334         synchronize_irq(trans_pcie->pci_dev->irq);
1335
1336         iwl_pcie_tx_free(trans);
1337         iwl_pcie_rx_free(trans);
1338
1339         free_irq(trans_pcie->pci_dev->irq, trans);
1340         iwl_pcie_free_ict(trans);
1341
1342         pci_disable_msi(trans_pcie->pci_dev);
1343         iounmap(trans_pcie->hw_base);
1344         pci_release_regions(trans_pcie->pci_dev);
1345         pci_disable_device(trans_pcie->pci_dev);
1346         kmem_cache_destroy(trans->dev_cmd_pool);
1347
1348         if (trans_pcie->napi.poll)
1349                 netif_napi_del(&trans_pcie->napi);
1350
1351         iwl_pcie_free_fw_monitor(trans);
1352
1353         kfree(trans);
1354 }
1355
1356 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1357 {
1358         if (state)
1359                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1360         else
1361                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1362 }
1363
1364 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1365                                                 unsigned long *flags)
1366 {
1367         int ret;
1368         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1369
1370         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1371
1372         if (trans_pcie->cmd_in_flight)
1373                 goto out;
1374
1375         /* this bit wakes up the NIC */
1376         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1377                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1378         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1379                 udelay(2);
1380
1381         /*
1382          * These bits say the device is running, and should keep running for
1383          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1384          * but they do not indicate that embedded SRAM is restored yet;
1385          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1386          * to/from host DRAM when sleeping/waking for power-saving.
1387          * Each direction takes approximately 1/4 millisecond; with this
1388          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1389          * series of register accesses are expected (e.g. reading Event Log),
1390          * to keep device from sleeping.
1391          *
1392          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1393          * SRAM is okay/restored.  We don't check that here because this call
1394          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1395          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1396          *
1397          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1398          * and do not save/restore SRAM when power cycling.
1399          */
1400         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1401                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1402                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1403                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1404         if (unlikely(ret < 0)) {
1405                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1406                 if (!silent) {
1407                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1408                         WARN_ONCE(1,
1409                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1410                                   val);
1411                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1412                         return false;
1413                 }
1414         }
1415
1416 out:
1417         /*
1418          * Fool sparse by faking we release the lock - sparse will
1419          * track nic_access anyway.
1420          */
1421         __release(&trans_pcie->reg_lock);
1422         return true;
1423 }
1424
1425 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1426                                               unsigned long *flags)
1427 {
1428         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1429
1430         lockdep_assert_held(&trans_pcie->reg_lock);
1431
1432         /*
1433          * Fool sparse by faking we acquiring the lock - sparse will
1434          * track nic_access anyway.
1435          */
1436         __acquire(&trans_pcie->reg_lock);
1437
1438         if (trans_pcie->cmd_in_flight)
1439                 goto out;
1440
1441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1442                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1443         /*
1444          * Above we read the CSR_GP_CNTRL register, which will flush
1445          * any previous writes, but we need the write that clears the
1446          * MAC_ACCESS_REQ bit to be performed before any other writes
1447          * scheduled on different CPUs (after we drop reg_lock).
1448          */
1449         mmiowb();
1450 out:
1451         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1452 }
1453
1454 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1455                                    void *buf, int dwords)
1456 {
1457         unsigned long flags;
1458         int offs, ret = 0;
1459         u32 *vals = buf;
1460
1461         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1462                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1463                 for (offs = 0; offs < dwords; offs++)
1464                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1465                 iwl_trans_release_nic_access(trans, &flags);
1466         } else {
1467                 ret = -EBUSY;
1468         }
1469         return ret;
1470 }
1471
1472 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1473                                     const void *buf, int dwords)
1474 {
1475         unsigned long flags;
1476         int offs, ret = 0;
1477         const u32 *vals = buf;
1478
1479         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1480                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1481                 for (offs = 0; offs < dwords; offs++)
1482                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1483                                     vals ? vals[offs] : 0);
1484                 iwl_trans_release_nic_access(trans, &flags);
1485         } else {
1486                 ret = -EBUSY;
1487         }
1488         return ret;
1489 }
1490
1491 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1492                                             unsigned long txqs,
1493                                             bool freeze)
1494 {
1495         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1496         int queue;
1497
1498         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1499                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1500                 unsigned long now;
1501
1502                 spin_lock_bh(&txq->lock);
1503
1504                 now = jiffies;
1505
1506                 if (txq->frozen == freeze)
1507                         goto next_queue;
1508
1509                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1510                                     freeze ? "Freezing" : "Waking", queue);
1511
1512                 txq->frozen = freeze;
1513
1514                 if (txq->q.read_ptr == txq->q.write_ptr)
1515                         goto next_queue;
1516
1517                 if (freeze) {
1518                         if (unlikely(time_after(now,
1519                                                 txq->stuck_timer.expires))) {
1520                                 /*
1521                                  * The timer should have fired, maybe it is
1522                                  * spinning right now on the lock.
1523                                  */
1524                                 goto next_queue;
1525                         }
1526                         /* remember how long until the timer fires */
1527                         txq->frozen_expiry_remainder =
1528                                 txq->stuck_timer.expires - now;
1529                         del_timer(&txq->stuck_timer);
1530                         goto next_queue;
1531                 }
1532
1533                 /*
1534                  * Wake a non-empty queue -> arm timer with the
1535                  * remainder before it froze
1536                  */
1537                 mod_timer(&txq->stuck_timer,
1538                           now + txq->frozen_expiry_remainder);
1539
1540 next_queue:
1541                 spin_unlock_bh(&txq->lock);
1542         }
1543 }
1544
1545 #define IWL_FLUSH_WAIT_MS       2000
1546
1547 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1548 {
1549         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1550         struct iwl_txq *txq;
1551         struct iwl_queue *q;
1552         int cnt;
1553         unsigned long now = jiffies;
1554         u32 scd_sram_addr;
1555         u8 buf[16];
1556         int ret = 0;
1557
1558         /* waiting for all the tx frames complete might take a while */
1559         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1560                 u8 wr_ptr;
1561
1562                 if (cnt == trans_pcie->cmd_queue)
1563                         continue;
1564                 if (!test_bit(cnt, trans_pcie->queue_used))
1565                         continue;
1566                 if (!(BIT(cnt) & txq_bm))
1567                         continue;
1568
1569                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1570                 txq = &trans_pcie->txq[cnt];
1571                 q = &txq->q;
1572                 wr_ptr = ACCESS_ONCE(q->write_ptr);
1573
1574                 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1575                        !time_after(jiffies,
1576                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1577                         u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1578
1579                         if (WARN_ONCE(wr_ptr != write_ptr,
1580                                       "WR pointer moved while flushing %d -> %d\n",
1581                                       wr_ptr, write_ptr))
1582                                 return -ETIMEDOUT;
1583                         msleep(1);
1584                 }
1585
1586                 if (q->read_ptr != q->write_ptr) {
1587                         IWL_ERR(trans,
1588                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1589                         ret = -ETIMEDOUT;
1590                         break;
1591                 }
1592                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1593         }
1594
1595         if (!ret)
1596                 return 0;
1597
1598         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1599                 txq->q.read_ptr, txq->q.write_ptr);
1600
1601         scd_sram_addr = trans_pcie->scd_base_addr +
1602                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1603         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1604
1605         iwl_print_hex_error(trans, buf, sizeof(buf));
1606
1607         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1608                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1609                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1610
1611         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1612                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1613                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1614                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1615                 u32 tbl_dw =
1616                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1617                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1618
1619                 if (cnt & 0x1)
1620                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1621                 else
1622                         tbl_dw = tbl_dw & 0x0000FFFF;
1623
1624                 IWL_ERR(trans,
1625                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1626                         cnt, active ? "" : "in", fifo, tbl_dw,
1627                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1628                                 (TFD_QUEUE_SIZE_MAX - 1),
1629                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1630         }
1631
1632         return ret;
1633 }
1634
1635 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1636                                          u32 mask, u32 value)
1637 {
1638         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1639         unsigned long flags;
1640
1641         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1642         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1643         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1644 }
1645
1646 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1647 {
1648         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1649         unsigned long flags;
1650
1651         if (iwlwifi_mod_params.d0i3_disable)
1652                 return;
1653
1654         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1655         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1656         trans_pcie->ref_count++;
1657         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1658 }
1659
1660 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1661 {
1662         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1663         unsigned long flags;
1664
1665         if (iwlwifi_mod_params.d0i3_disable)
1666                 return;
1667
1668         spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1669         IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1670         if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1671                 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1672                 return;
1673         }
1674         trans_pcie->ref_count--;
1675         spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1676 }
1677
1678 static const char *get_csr_string(int cmd)
1679 {
1680 #define IWL_CMD(x) case x: return #x
1681         switch (cmd) {
1682         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1683         IWL_CMD(CSR_INT_COALESCING);
1684         IWL_CMD(CSR_INT);
1685         IWL_CMD(CSR_INT_MASK);
1686         IWL_CMD(CSR_FH_INT_STATUS);
1687         IWL_CMD(CSR_GPIO_IN);
1688         IWL_CMD(CSR_RESET);
1689         IWL_CMD(CSR_GP_CNTRL);
1690         IWL_CMD(CSR_HW_REV);
1691         IWL_CMD(CSR_EEPROM_REG);
1692         IWL_CMD(CSR_EEPROM_GP);
1693         IWL_CMD(CSR_OTP_GP_REG);
1694         IWL_CMD(CSR_GIO_REG);
1695         IWL_CMD(CSR_GP_UCODE_REG);
1696         IWL_CMD(CSR_GP_DRIVER_REG);
1697         IWL_CMD(CSR_UCODE_DRV_GP1);
1698         IWL_CMD(CSR_UCODE_DRV_GP2);
1699         IWL_CMD(CSR_LED_REG);
1700         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1701         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1702         IWL_CMD(CSR_ANA_PLL_CFG);
1703         IWL_CMD(CSR_HW_REV_WA_REG);
1704         IWL_CMD(CSR_MONITOR_STATUS_REG);
1705         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1706         default:
1707                 return "UNKNOWN";
1708         }
1709 #undef IWL_CMD
1710 }
1711
1712 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1713 {
1714         int i;
1715         static const u32 csr_tbl[] = {
1716                 CSR_HW_IF_CONFIG_REG,
1717                 CSR_INT_COALESCING,
1718                 CSR_INT,
1719                 CSR_INT_MASK,
1720                 CSR_FH_INT_STATUS,
1721                 CSR_GPIO_IN,
1722                 CSR_RESET,
1723                 CSR_GP_CNTRL,
1724                 CSR_HW_REV,
1725                 CSR_EEPROM_REG,
1726                 CSR_EEPROM_GP,
1727                 CSR_OTP_GP_REG,
1728                 CSR_GIO_REG,
1729                 CSR_GP_UCODE_REG,
1730                 CSR_GP_DRIVER_REG,
1731                 CSR_UCODE_DRV_GP1,
1732                 CSR_UCODE_DRV_GP2,
1733                 CSR_LED_REG,
1734                 CSR_DRAM_INT_TBL_REG,
1735                 CSR_GIO_CHICKEN_BITS,
1736                 CSR_ANA_PLL_CFG,
1737                 CSR_MONITOR_STATUS_REG,
1738                 CSR_HW_REV_WA_REG,
1739                 CSR_DBG_HPET_MEM_REG
1740         };
1741         IWL_ERR(trans, "CSR values:\n");
1742         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1743                 "CSR_INT_PERIODIC_REG)\n");
1744         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1745                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1746                         get_csr_string(csr_tbl[i]),
1747                         iwl_read32(trans, csr_tbl[i]));
1748         }
1749 }
1750
1751 #ifdef CONFIG_IWLWIFI_DEBUGFS
1752 /* create and remove of files */
1753 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1754         if (!debugfs_create_file(#name, mode, parent, trans,            \
1755                                  &iwl_dbgfs_##name##_ops))              \
1756                 goto err;                                               \
1757 } while (0)
1758
1759 /* file operation */
1760 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1761 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1762         .read = iwl_dbgfs_##name##_read,                                \
1763         .open = simple_open,                                            \
1764         .llseek = generic_file_llseek,                                  \
1765 };
1766
1767 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1768 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1769         .write = iwl_dbgfs_##name##_write,                              \
1770         .open = simple_open,                                            \
1771         .llseek = generic_file_llseek,                                  \
1772 };
1773
1774 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1775 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1776         .write = iwl_dbgfs_##name##_write,                              \
1777         .read = iwl_dbgfs_##name##_read,                                \
1778         .open = simple_open,                                            \
1779         .llseek = generic_file_llseek,                                  \
1780 };
1781
1782 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1783                                        char __user *user_buf,
1784                                        size_t count, loff_t *ppos)
1785 {
1786         struct iwl_trans *trans = file->private_data;
1787         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1788         struct iwl_txq *txq;
1789         struct iwl_queue *q;
1790         char *buf;
1791         int pos = 0;
1792         int cnt;
1793         int ret;
1794         size_t bufsz;
1795
1796         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
1797
1798         if (!trans_pcie->txq)
1799                 return -EAGAIN;
1800
1801         buf = kzalloc(bufsz, GFP_KERNEL);
1802         if (!buf)
1803                 return -ENOMEM;
1804
1805         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1806                 txq = &trans_pcie->txq[cnt];
1807                 q = &txq->q;
1808                 pos += scnprintf(buf + pos, bufsz - pos,
1809                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
1810                                 cnt, q->read_ptr, q->write_ptr,
1811                                 !!test_bit(cnt, trans_pcie->queue_used),
1812                                  !!test_bit(cnt, trans_pcie->queue_stopped),
1813                                  txq->need_update, txq->frozen,
1814                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1815         }
1816         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1817         kfree(buf);
1818         return ret;
1819 }
1820
1821 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1822                                        char __user *user_buf,
1823                                        size_t count, loff_t *ppos)
1824 {
1825         struct iwl_trans *trans = file->private_data;
1826         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1827         struct iwl_rxq *rxq = &trans_pcie->rxq;
1828         char buf[256];
1829         int pos = 0;
1830         const size_t bufsz = sizeof(buf);
1831
1832         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1833                                                 rxq->read);
1834         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1835                                                 rxq->write);
1836         pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1837                                                 rxq->write_actual);
1838         pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1839                                                 rxq->need_update);
1840         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1841                                                 rxq->free_count);
1842         if (rxq->rb_stts) {
1843                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1844                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1845         } else {
1846                 pos += scnprintf(buf + pos, bufsz - pos,
1847                                         "closed_rb_num: Not Allocated\n");
1848         }
1849         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1850 }
1851
1852 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1853                                         char __user *user_buf,
1854                                         size_t count, loff_t *ppos)
1855 {
1856         struct iwl_trans *trans = file->private_data;
1857         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1858         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1859
1860         int pos = 0;
1861         char *buf;
1862         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1863         ssize_t ret;
1864
1865         buf = kzalloc(bufsz, GFP_KERNEL);
1866         if (!buf)
1867                 return -ENOMEM;
1868
1869         pos += scnprintf(buf + pos, bufsz - pos,
1870                         "Interrupt Statistics Report:\n");
1871
1872         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1873                 isr_stats->hw);
1874         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1875                 isr_stats->sw);
1876         if (isr_stats->sw || isr_stats->hw) {
1877                 pos += scnprintf(buf + pos, bufsz - pos,
1878                         "\tLast Restarting Code:  0x%X\n",
1879                         isr_stats->err_code);
1880         }
1881 #ifdef CONFIG_IWLWIFI_DEBUG
1882         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1883                 isr_stats->sch);
1884         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1885                 isr_stats->alive);
1886 #endif
1887         pos += scnprintf(buf + pos, bufsz - pos,
1888                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1889
1890         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1891                 isr_stats->ctkill);
1892
1893         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1894                 isr_stats->wakeup);
1895
1896         pos += scnprintf(buf + pos, bufsz - pos,
1897                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1898
1899         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1900                 isr_stats->tx);
1901
1902         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1903                 isr_stats->unhandled);
1904
1905         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1906         kfree(buf);
1907         return ret;
1908 }
1909
1910 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1911                                          const char __user *user_buf,
1912                                          size_t count, loff_t *ppos)
1913 {
1914         struct iwl_trans *trans = file->private_data;
1915         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1916         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1917
1918         char buf[8];
1919         int buf_size;
1920         u32 reset_flag;
1921
1922         memset(buf, 0, sizeof(buf));
1923         buf_size = min(count, sizeof(buf) -  1);
1924         if (copy_from_user(buf, user_buf, buf_size))
1925                 return -EFAULT;
1926         if (sscanf(buf, "%x", &reset_flag) != 1)
1927                 return -EFAULT;
1928         if (reset_flag == 0)
1929                 memset(isr_stats, 0, sizeof(*isr_stats));
1930
1931         return count;
1932 }
1933
1934 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1935                                    const char __user *user_buf,
1936                                    size_t count, loff_t *ppos)
1937 {
1938         struct iwl_trans *trans = file->private_data;
1939         char buf[8];
1940         int buf_size;
1941         int csr;
1942
1943         memset(buf, 0, sizeof(buf));
1944         buf_size = min(count, sizeof(buf) -  1);
1945         if (copy_from_user(buf, user_buf, buf_size))
1946                 return -EFAULT;
1947         if (sscanf(buf, "%d", &csr) != 1)
1948                 return -EFAULT;
1949
1950         iwl_pcie_dump_csr(trans);
1951
1952         return count;
1953 }
1954
1955 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1956                                      char __user *user_buf,
1957                                      size_t count, loff_t *ppos)
1958 {
1959         struct iwl_trans *trans = file->private_data;
1960         char *buf = NULL;
1961         ssize_t ret;
1962
1963         ret = iwl_dump_fh(trans, &buf);
1964         if (ret < 0)
1965                 return ret;
1966         if (!buf)
1967                 return -EINVAL;
1968         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1969         kfree(buf);
1970         return ret;
1971 }
1972
1973 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1974 DEBUGFS_READ_FILE_OPS(fh_reg);
1975 DEBUGFS_READ_FILE_OPS(rx_queue);
1976 DEBUGFS_READ_FILE_OPS(tx_queue);
1977 DEBUGFS_WRITE_FILE_OPS(csr);
1978
1979 /*
1980  * Create the debugfs files and directories
1981  *
1982  */
1983 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1984                                          struct dentry *dir)
1985 {
1986         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1987         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1988         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1989         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1990         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1991         return 0;
1992
1993 err:
1994         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1995         return -ENOMEM;
1996 }
1997 #else
1998 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1999                                          struct dentry *dir)
2000 {
2001         return 0;
2002 }
2003 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2004
2005 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
2006 {
2007         u32 cmdlen = 0;
2008         int i;
2009
2010         for (i = 0; i < IWL_NUM_OF_TBS; i++)
2011                 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
2012
2013         return cmdlen;
2014 }
2015
2016 static const struct {
2017         u32 start, end;
2018 } iwl_prph_dump_addr[] = {
2019         { .start = 0x00a00000, .end = 0x00a00000 },
2020         { .start = 0x00a0000c, .end = 0x00a00024 },
2021         { .start = 0x00a0002c, .end = 0x00a0003c },
2022         { .start = 0x00a00410, .end = 0x00a00418 },
2023         { .start = 0x00a00420, .end = 0x00a00420 },
2024         { .start = 0x00a00428, .end = 0x00a00428 },
2025         { .start = 0x00a00430, .end = 0x00a0043c },
2026         { .start = 0x00a00444, .end = 0x00a00444 },
2027         { .start = 0x00a004c0, .end = 0x00a004cc },
2028         { .start = 0x00a004d8, .end = 0x00a004d8 },
2029         { .start = 0x00a004e0, .end = 0x00a004f0 },
2030         { .start = 0x00a00840, .end = 0x00a00840 },
2031         { .start = 0x00a00850, .end = 0x00a00858 },
2032         { .start = 0x00a01004, .end = 0x00a01008 },
2033         { .start = 0x00a01010, .end = 0x00a01010 },
2034         { .start = 0x00a01018, .end = 0x00a01018 },
2035         { .start = 0x00a01024, .end = 0x00a01024 },
2036         { .start = 0x00a0102c, .end = 0x00a01034 },
2037         { .start = 0x00a0103c, .end = 0x00a01040 },
2038         { .start = 0x00a01048, .end = 0x00a01094 },
2039         { .start = 0x00a01c00, .end = 0x00a01c20 },
2040         { .start = 0x00a01c58, .end = 0x00a01c58 },
2041         { .start = 0x00a01c7c, .end = 0x00a01c7c },
2042         { .start = 0x00a01c28, .end = 0x00a01c54 },
2043         { .start = 0x00a01c5c, .end = 0x00a01c5c },
2044         { .start = 0x00a01c60, .end = 0x00a01cdc },
2045         { .start = 0x00a01ce0, .end = 0x00a01d0c },
2046         { .start = 0x00a01d18, .end = 0x00a01d20 },
2047         { .start = 0x00a01d2c, .end = 0x00a01d30 },
2048         { .start = 0x00a01d40, .end = 0x00a01d5c },
2049         { .start = 0x00a01d80, .end = 0x00a01d80 },
2050         { .start = 0x00a01d98, .end = 0x00a01d9c },
2051         { .start = 0x00a01da8, .end = 0x00a01da8 },
2052         { .start = 0x00a01db8, .end = 0x00a01df4 },
2053         { .start = 0x00a01dc0, .end = 0x00a01dfc },
2054         { .start = 0x00a01e00, .end = 0x00a01e2c },
2055         { .start = 0x00a01e40, .end = 0x00a01e60 },
2056         { .start = 0x00a01e68, .end = 0x00a01e6c },
2057         { .start = 0x00a01e74, .end = 0x00a01e74 },
2058         { .start = 0x00a01e84, .end = 0x00a01e90 },
2059         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
2060         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
2061         { .start = 0x00a01f00, .end = 0x00a01f1c },
2062         { .start = 0x00a01f44, .end = 0x00a01ffc },
2063         { .start = 0x00a02000, .end = 0x00a02048 },
2064         { .start = 0x00a02068, .end = 0x00a020f0 },
2065         { .start = 0x00a02100, .end = 0x00a02118 },
2066         { .start = 0x00a02140, .end = 0x00a0214c },
2067         { .start = 0x00a02168, .end = 0x00a0218c },
2068         { .start = 0x00a021c0, .end = 0x00a021c0 },
2069         { .start = 0x00a02400, .end = 0x00a02410 },
2070         { .start = 0x00a02418, .end = 0x00a02420 },
2071         { .start = 0x00a02428, .end = 0x00a0242c },
2072         { .start = 0x00a02434, .end = 0x00a02434 },
2073         { .start = 0x00a02440, .end = 0x00a02460 },
2074         { .start = 0x00a02468, .end = 0x00a024b0 },
2075         { .start = 0x00a024c8, .end = 0x00a024cc },
2076         { .start = 0x00a02500, .end = 0x00a02504 },
2077         { .start = 0x00a0250c, .end = 0x00a02510 },
2078         { .start = 0x00a02540, .end = 0x00a02554 },
2079         { .start = 0x00a02580, .end = 0x00a025f4 },
2080         { .start = 0x00a02600, .end = 0x00a0260c },
2081         { .start = 0x00a02648, .end = 0x00a02650 },
2082         { .start = 0x00a02680, .end = 0x00a02680 },
2083         { .start = 0x00a026c0, .end = 0x00a026d0 },
2084         { .start = 0x00a02700, .end = 0x00a0270c },
2085         { .start = 0x00a02804, .end = 0x00a02804 },
2086         { .start = 0x00a02818, .end = 0x00a0281c },
2087         { .start = 0x00a02c00, .end = 0x00a02db4 },
2088         { .start = 0x00a02df4, .end = 0x00a02fb0 },
2089         { .start = 0x00a03000, .end = 0x00a03014 },
2090         { .start = 0x00a0301c, .end = 0x00a0302c },
2091         { .start = 0x00a03034, .end = 0x00a03038 },
2092         { .start = 0x00a03040, .end = 0x00a03048 },
2093         { .start = 0x00a03060, .end = 0x00a03068 },
2094         { .start = 0x00a03070, .end = 0x00a03074 },
2095         { .start = 0x00a0307c, .end = 0x00a0307c },
2096         { .start = 0x00a03080, .end = 0x00a03084 },
2097         { .start = 0x00a0308c, .end = 0x00a03090 },
2098         { .start = 0x00a03098, .end = 0x00a03098 },
2099         { .start = 0x00a030a0, .end = 0x00a030a0 },
2100         { .start = 0x00a030a8, .end = 0x00a030b4 },
2101         { .start = 0x00a030bc, .end = 0x00a030bc },
2102         { .start = 0x00a030c0, .end = 0x00a0312c },
2103         { .start = 0x00a03c00, .end = 0x00a03c5c },
2104         { .start = 0x00a04400, .end = 0x00a04454 },
2105         { .start = 0x00a04460, .end = 0x00a04474 },
2106         { .start = 0x00a044c0, .end = 0x00a044ec },
2107         { .start = 0x00a04500, .end = 0x00a04504 },
2108         { .start = 0x00a04510, .end = 0x00a04538 },
2109         { .start = 0x00a04540, .end = 0x00a04548 },
2110         { .start = 0x00a04560, .end = 0x00a0457c },
2111         { .start = 0x00a04590, .end = 0x00a04598 },
2112         { .start = 0x00a045c0, .end = 0x00a045f4 },
2113 };
2114
2115 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2116                                     struct iwl_fw_error_dump_data **data)
2117 {
2118         struct iwl_fw_error_dump_prph *prph;
2119         unsigned long flags;
2120         u32 prph_len = 0, i;
2121
2122         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2123                 return 0;
2124
2125         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2126                 /* The range includes both boundaries */
2127                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2128                          iwl_prph_dump_addr[i].start + 4;
2129                 int reg;
2130                 __le32 *val;
2131
2132                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2133
2134                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2135                 (*data)->len = cpu_to_le32(sizeof(*prph) +
2136                                         num_bytes_in_chunk);
2137                 prph = (void *)(*data)->data;
2138                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2139                 val = (void *)prph->data;
2140
2141                 for (reg = iwl_prph_dump_addr[i].start;
2142                      reg <= iwl_prph_dump_addr[i].end;
2143                      reg += 4)
2144                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2145                                                                       reg));
2146                 *data = iwl_fw_error_next_data(*data);
2147         }
2148
2149         iwl_trans_release_nic_access(trans, &flags);
2150
2151         return prph_len;
2152 }
2153
2154 #define IWL_CSR_TO_DUMP (0x250)
2155
2156 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2157                                    struct iwl_fw_error_dump_data **data)
2158 {
2159         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2160         __le32 *val;
2161         int i;
2162
2163         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2164         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2165         val = (void *)(*data)->data;
2166
2167         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2168                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2169
2170         *data = iwl_fw_error_next_data(*data);
2171
2172         return csr_len;
2173 }
2174
2175 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2176                                        struct iwl_fw_error_dump_data **data)
2177 {
2178         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2179         unsigned long flags;
2180         __le32 *val;
2181         int i;
2182
2183         if (!iwl_trans_grab_nic_access(trans, false, &flags))
2184                 return 0;
2185
2186         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2187         (*data)->len = cpu_to_le32(fh_regs_len);
2188         val = (void *)(*data)->data;
2189
2190         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2191                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2192
2193         iwl_trans_release_nic_access(trans, &flags);
2194
2195         *data = iwl_fw_error_next_data(*data);
2196
2197         return sizeof(**data) + fh_regs_len;
2198 }
2199
2200 static
2201 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2202 {
2203         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2204         struct iwl_fw_error_dump_data *data;
2205         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2206         struct iwl_fw_error_dump_txcmd *txcmd;
2207         struct iwl_trans_dump_data *dump_data;
2208         u32 len;
2209         u32 monitor_len;
2210         int i, ptr;
2211
2212         /* transport dump header */
2213         len = sizeof(*dump_data);
2214
2215         /* host commands */
2216         len += sizeof(*data) +
2217                 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2218
2219         /* CSR registers */
2220         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2221
2222         /* PRPH registers */
2223         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2224                 /* The range includes both boundaries */
2225                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2226                         iwl_prph_dump_addr[i].start + 4;
2227
2228                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2229                         num_bytes_in_chunk;
2230         }
2231
2232         /* FH registers */
2233         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2234
2235         /* FW monitor */
2236         if (trans_pcie->fw_mon_page) {
2237                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2238                        trans_pcie->fw_mon_size;
2239                 monitor_len = trans_pcie->fw_mon_size;
2240         } else if (trans->dbg_dest_tlv) {
2241                 u32 base, end;
2242
2243                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2244                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2245
2246                 base = iwl_read_prph(trans, base) <<
2247                        trans->dbg_dest_tlv->base_shift;
2248                 end = iwl_read_prph(trans, end) <<
2249                       trans->dbg_dest_tlv->end_shift;
2250
2251                 /* Make "end" point to the actual end */
2252                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2253                         end += (1 << trans->dbg_dest_tlv->end_shift);
2254                 monitor_len = end - base;
2255                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2256                        monitor_len;
2257         } else {
2258                 monitor_len = 0;
2259         }
2260
2261         dump_data = vzalloc(len);
2262         if (!dump_data)
2263                 return NULL;
2264
2265         len = 0;
2266         data = (void *)dump_data->data;
2267         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2268         txcmd = (void *)data->data;
2269         spin_lock_bh(&cmdq->lock);
2270         ptr = cmdq->q.write_ptr;
2271         for (i = 0; i < cmdq->q.n_window; i++) {
2272                 u8 idx = get_cmd_index(&cmdq->q, ptr);
2273                 u32 caplen, cmdlen;
2274
2275                 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2276                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2277
2278                 if (cmdlen) {
2279                         len += sizeof(*txcmd) + caplen;
2280                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2281                         txcmd->caplen = cpu_to_le32(caplen);
2282                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2283                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2284                 }
2285
2286                 ptr = iwl_queue_dec_wrap(ptr);
2287         }
2288         spin_unlock_bh(&cmdq->lock);
2289
2290         data->len = cpu_to_le32(len);
2291         len += sizeof(*data);
2292         data = iwl_fw_error_next_data(data);
2293
2294         len += iwl_trans_pcie_dump_prph(trans, &data);
2295         len += iwl_trans_pcie_dump_csr(trans, &data);
2296         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2297         /* data is already pointing to the next section */
2298
2299         if ((trans_pcie->fw_mon_page &&
2300              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2301             trans->dbg_dest_tlv) {
2302                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2303                 u32 base, write_ptr, wrap_cnt;
2304
2305                 /* If there was a dest TLV - use the values from there */
2306                 if (trans->dbg_dest_tlv) {
2307                         write_ptr =
2308                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2309                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2310                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2311                 } else {
2312                         base = MON_BUFF_BASE_ADDR;
2313                         write_ptr = MON_BUFF_WRPTR;
2314                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2315                 }
2316
2317                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2318                 fw_mon_data = (void *)data->data;
2319                 fw_mon_data->fw_mon_wr_ptr =
2320                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2321                 fw_mon_data->fw_mon_cycle_cnt =
2322                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2323                 fw_mon_data->fw_mon_base_ptr =
2324                         cpu_to_le32(iwl_read_prph(trans, base));
2325
2326                 len += sizeof(*data) + sizeof(*fw_mon_data);
2327                 if (trans_pcie->fw_mon_page) {
2328                         data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2329                                                 sizeof(*fw_mon_data));
2330
2331                         /*
2332                          * The firmware is now asserted, it won't write anything
2333                          * to the buffer. CPU can take ownership to fetch the
2334                          * data. The buffer will be handed back to the device
2335                          * before the firmware will be restarted.
2336                          */
2337                         dma_sync_single_for_cpu(trans->dev,
2338                                                 trans_pcie->fw_mon_phys,
2339                                                 trans_pcie->fw_mon_size,
2340                                                 DMA_FROM_DEVICE);
2341                         memcpy(fw_mon_data->data,
2342                                page_address(trans_pcie->fw_mon_page),
2343                                trans_pcie->fw_mon_size);
2344
2345                         len += trans_pcie->fw_mon_size;
2346                 } else {
2347                         /* If we are here then the buffer is internal */
2348
2349                         /*
2350                          * Update pointers to reflect actual values after
2351                          * shifting
2352                          */
2353                         base = iwl_read_prph(trans, base) <<
2354                                trans->dbg_dest_tlv->base_shift;
2355                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2356                                            monitor_len / sizeof(u32));
2357                         data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2358                                                 monitor_len);
2359                         len += monitor_len;
2360                 }
2361         }
2362
2363         dump_data->len = len;
2364
2365         return dump_data;
2366 }
2367
2368 static const struct iwl_trans_ops trans_ops_pcie = {
2369         .start_hw = iwl_trans_pcie_start_hw,
2370         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2371         .fw_alive = iwl_trans_pcie_fw_alive,
2372         .start_fw = iwl_trans_pcie_start_fw,
2373         .stop_device = iwl_trans_pcie_stop_device,
2374
2375         .d3_suspend = iwl_trans_pcie_d3_suspend,
2376         .d3_resume = iwl_trans_pcie_d3_resume,
2377
2378         .send_cmd = iwl_trans_pcie_send_hcmd,
2379
2380         .tx = iwl_trans_pcie_tx,
2381         .reclaim = iwl_trans_pcie_reclaim,
2382
2383         .txq_disable = iwl_trans_pcie_txq_disable,
2384         .txq_enable = iwl_trans_pcie_txq_enable,
2385
2386         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2387
2388         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2389         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2390
2391         .write8 = iwl_trans_pcie_write8,
2392         .write32 = iwl_trans_pcie_write32,
2393         .read32 = iwl_trans_pcie_read32,
2394         .read_prph = iwl_trans_pcie_read_prph,
2395         .write_prph = iwl_trans_pcie_write_prph,
2396         .read_mem = iwl_trans_pcie_read_mem,
2397         .write_mem = iwl_trans_pcie_write_mem,
2398         .configure = iwl_trans_pcie_configure,
2399         .set_pmi = iwl_trans_pcie_set_pmi,
2400         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2401         .release_nic_access = iwl_trans_pcie_release_nic_access,
2402         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2403
2404         .ref = iwl_trans_pcie_ref,
2405         .unref = iwl_trans_pcie_unref,
2406
2407         .dump_data = iwl_trans_pcie_dump_data,
2408 };
2409
2410 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2411                                        const struct pci_device_id *ent,
2412                                        const struct iwl_cfg *cfg)
2413 {
2414         struct iwl_trans_pcie *trans_pcie;
2415         struct iwl_trans *trans;
2416         u16 pci_cmd;
2417         int err;
2418
2419         trans = kzalloc(sizeof(struct iwl_trans) +
2420                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2421         if (!trans) {
2422                 err = -ENOMEM;
2423                 goto out;
2424         }
2425
2426         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2427
2428         trans->ops = &trans_ops_pcie;
2429         trans->cfg = cfg;
2430         trans_lockdep_init(trans);
2431         trans_pcie->trans = trans;
2432         spin_lock_init(&trans_pcie->irq_lock);
2433         spin_lock_init(&trans_pcie->reg_lock);
2434         spin_lock_init(&trans_pcie->ref_lock);
2435         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2436
2437         err = pci_enable_device(pdev);
2438         if (err)
2439                 goto out_no_pci;
2440
2441         if (!cfg->base_params->pcie_l1_allowed) {
2442                 /*
2443                  * W/A - seems to solve weird behavior. We need to remove this
2444                  * if we don't want to stay in L1 all the time. This wastes a
2445                  * lot of power.
2446                  */
2447                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2448                                        PCIE_LINK_STATE_L1 |
2449                                        PCIE_LINK_STATE_CLKPM);
2450         }
2451
2452         pci_set_master(pdev);
2453
2454         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2455         if (!err)
2456                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2457         if (err) {
2458                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2459                 if (!err)
2460                         err = pci_set_consistent_dma_mask(pdev,
2461                                                           DMA_BIT_MASK(32));
2462                 /* both attempts failed: */
2463                 if (err) {
2464                         dev_err(&pdev->dev, "No suitable DMA available\n");
2465                         goto out_pci_disable_device;
2466                 }
2467         }
2468
2469         err = pci_request_regions(pdev, DRV_NAME);
2470         if (err) {
2471                 dev_err(&pdev->dev, "pci_request_regions failed\n");
2472                 goto out_pci_disable_device;
2473         }
2474
2475         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2476         if (!trans_pcie->hw_base) {
2477                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2478                 err = -ENODEV;
2479                 goto out_pci_release_regions;
2480         }
2481
2482         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2483          * PCI Tx retries from interfering with C3 CPU state */
2484         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2485
2486         trans->dev = &pdev->dev;
2487         trans_pcie->pci_dev = pdev;
2488         iwl_disable_interrupts(trans);
2489
2490         err = pci_enable_msi(pdev);
2491         if (err) {
2492                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2493                 /* enable rfkill interrupt: hw bug w/a */
2494                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2495                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2496                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2497                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2498                 }
2499         }
2500
2501         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2502         /*
2503          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2504          * changed, and now the revision step also includes bit 0-1 (no more
2505          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2506          * in the old format.
2507          */
2508         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2509                 unsigned long flags;
2510                 int ret;
2511
2512                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2513                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2514
2515                 /*
2516                  * in-order to recognize C step driver should read chip version
2517                  * id located at the AUX bus MISC address space.
2518                  */
2519                 iwl_set_bit(trans, CSR_GP_CNTRL,
2520                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
2521                 udelay(2);
2522
2523                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2524                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2525                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
2526                                    25000);
2527                 if (ret < 0) {
2528                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
2529                         goto out_pci_disable_msi;
2530                 }
2531
2532                 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
2533                         u32 hw_step;
2534
2535                         hw_step = __iwl_read_prph(trans, WFPM_CTRL_REG);
2536                         hw_step |= ENABLE_WFPM;
2537                         __iwl_write_prph(trans, WFPM_CTRL_REG, hw_step);
2538                         hw_step = __iwl_read_prph(trans, AUX_MISC_REG);
2539                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
2540                         if (hw_step == 0x3)
2541                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
2542                                                 (SILICON_C_STEP << 2);
2543                         iwl_trans_release_nic_access(trans, &flags);
2544                 }
2545         }
2546
2547         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2548         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2549                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2550
2551         /* Initialize the wait queue for commands */
2552         init_waitqueue_head(&trans_pcie->wait_command_queue);
2553
2554         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2555                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2556
2557         trans->dev_cmd_headroom = 0;
2558         trans->dev_cmd_pool =
2559                 kmem_cache_create(trans->dev_cmd_pool_name,
2560                                   sizeof(struct iwl_device_cmd)
2561                                   + trans->dev_cmd_headroom,
2562                                   sizeof(void *),
2563                                   SLAB_HWCACHE_ALIGN,
2564                                   NULL);
2565
2566         if (!trans->dev_cmd_pool) {
2567                 err = -ENOMEM;
2568                 goto out_pci_disable_msi;
2569         }
2570
2571         if (iwl_pcie_alloc_ict(trans))
2572                 goto out_free_cmd_pool;
2573
2574         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2575                                    iwl_pcie_irq_handler,
2576                                    IRQF_SHARED, DRV_NAME, trans);
2577         if (err) {
2578                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2579                 goto out_free_ict;
2580         }
2581
2582         trans_pcie->inta_mask = CSR_INI_SET_MASK;
2583         trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2584
2585         return trans;
2586
2587 out_free_ict:
2588         iwl_pcie_free_ict(trans);
2589 out_free_cmd_pool:
2590         kmem_cache_destroy(trans->dev_cmd_pool);
2591 out_pci_disable_msi:
2592         pci_disable_msi(pdev);
2593 out_pci_release_regions:
2594         pci_release_regions(pdev);
2595 out_pci_disable_device:
2596         pci_disable_device(pdev);
2597 out_no_pci:
2598         kfree(trans);
2599 out:
2600         return ERR_PTR(err);
2601 }