drivers/net/wireless/intel/iwlwifi/mvm/fw-dbg.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program;
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  24  * The full GNU General Public License is included in this distribution
  25  * in the file called COPYING.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <linuxwifi@intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  34  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  35  * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
  36  * All rights reserved.
  37  *
  38  * Redistribution and use in source and binary forms, with or without
  39  * modification, are permitted provided that the following conditions
  40  * are met:
  41  *
  42  *  * Redistributions of source code must retain the above copyright
  43  *    notice, this list of conditions and the following disclaimer.
  44  *  * Redistributions in binary form must reproduce the above copyright
  45  *    notice, this list of conditions and the following disclaimer in
  46  *    the documentation and/or other materials provided with the
  47  *    distribution.
  48  *  * Neither the name Intel Corporation nor the names of its
  49  *    contributors may be used to endorse or promote products derived
  50  *    from this software without specific prior written permission.
  51  *
  52  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63  *
  64  *****************************************************************************/
  65 #include <linux/devcoredump.h>
  66
  67 #include "fw-dbg.h"
  68 #include "iwl-io.h"
  69 #include "mvm.h"
  70 #include "iwl-prph.h"
  71 #include "iwl-csr.h"
  72
  73 static ssize_t iwl_mvm_read_coredump(char *buffer, loff_t offset, size_t count,
  74                                      const void *data, size_t datalen)
  75 {
  76         const struct iwl_mvm_dump_ptrs *dump_ptrs = data;
  77         ssize_t bytes_read;
  78         ssize_t bytes_read_trans;
  79
  80         if (offset < dump_ptrs->op_mode_len) {
  81                 bytes_read = min_t(ssize_t, count,
  82                                    dump_ptrs->op_mode_len - offset);
  83                 memcpy(buffer, (u8 *)dump_ptrs->op_mode_ptr + offset,
  84                        bytes_read);
  85                 offset += bytes_read;
  86                 count -= bytes_read;
  87
  88                 if (count == 0)
  89                         return bytes_read;
  90         } else {
  91                 bytes_read = 0;
  92         }
  93
  94         if (!dump_ptrs->trans_ptr)
  95                 return bytes_read;
  96
  97         offset -= dump_ptrs->op_mode_len;
  98         bytes_read_trans = min_t(ssize_t, count,
  99                                  dump_ptrs->trans_ptr->len - offset);
 100         memcpy(buffer + bytes_read,
 101                (u8 *)dump_ptrs->trans_ptr->data + offset,
 102                bytes_read_trans);
 103
 104         return bytes_read + bytes_read_trans;
 105 }
 106
 107 static void iwl_mvm_free_coredump(const void *data)
 108 {
 109         const struct iwl_mvm_dump_ptrs *fw_error_dump = data;
 110
 111         vfree(fw_error_dump->op_mode_ptr);
 112         vfree(fw_error_dump->trans_ptr);
 113         kfree(fw_error_dump);
 114 }
 115
 116 #define RADIO_REG_MAX_READ 0x2ad
 117 static void iwl_mvm_read_radio_reg(struct iwl_mvm *mvm,
 118                                    struct iwl_fw_error_dump_data **dump_data)
 119 {
 120         u8 *pos = (void *)(*dump_data)->data;
 121         unsigned long flags;
 122         int i;
 123
 124         if (!iwl_trans_grab_nic_access(mvm->trans, &flags))
 125                 return;
 126
 127         (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG);
 128         (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ);
 129
 130         for (i = 0; i < RADIO_REG_MAX_READ; i++) {
 131                 u32 rd_cmd = RADIO_RSP_RD_CMD;
 132
 133                 rd_cmd |= i << RADIO_RSP_ADDR_POS;
 134                 iwl_write_prph_no_grab(mvm->trans, RSP_RADIO_CMD, rd_cmd);
 135                 *pos =  (u8)iwl_read_prph_no_grab(mvm->trans, RSP_RADIO_RDDAT);
 136
 137                 pos++;
 138         }
 139
 140         *dump_data = iwl_fw_error_next_data(*dump_data);
 141
 142         iwl_trans_release_nic_access(mvm->trans, &flags);
 143 }
 144
 145 static void iwl_mvm_dump_fifos(struct iwl_mvm *mvm,
 146                                struct iwl_fw_error_dump_data **dump_data)
 147 {
 148         struct iwl_fw_error_dump_fifo *fifo_hdr;
 149         u32 *fifo_data;
 150         u32 fifo_len;
 151         unsigned long flags;
 152         int i, j;
 153
 154         if (!iwl_trans_grab_nic_access(mvm->trans, &flags))
 155                 return;
 156
 157         /* Pull RXF data from all RXFs */
 158         for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++) {
 159                 /*
 160                  * Keep aside the additional offset that might be needed for
 161                  * next RXF
 162                  */
 163                 u32 offset_diff = RXF_DIFF_FROM_PREV * i;
 164
 165                 fifo_hdr = (void *)(*dump_data)->data;
 166                 fifo_data = (void *)fifo_hdr->data;
 167                 fifo_len = mvm->shared_mem_cfg.rxfifo_size[i];
 168
 169                 /* No need to try to read the data if the length is 0 */
 170                 if (fifo_len == 0)
 171                         continue;
 172
 173                 /* Add a TLV for the RXF */
 174                 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF);
 175                 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
 176
 177                 fifo_hdr->fifo_num = cpu_to_le32(i);
 178                 fifo_hdr->available_bytes =
 179                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 180                                                         RXF_RD_D_SPACE +
 181                                                         offset_diff));
 182                 fifo_hdr->wr_ptr =
 183                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 184                                                         RXF_RD_WR_PTR +
 185                                                         offset_diff));
 186                 fifo_hdr->rd_ptr =
 187                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 188                                                         RXF_RD_RD_PTR +
 189                                                         offset_diff));
 190                 fifo_hdr->fence_ptr =
 191                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 192                                                         RXF_RD_FENCE_PTR +
 193                                                         offset_diff));
 194                 fifo_hdr->fence_mode =
 195                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 196                                                         RXF_SET_FENCE_MODE +
 197                                                         offset_diff));
 198
 199                 /* Lock fence */
 200                 iwl_trans_write_prph(mvm->trans,
 201                                      RXF_SET_FENCE_MODE + offset_diff, 0x1);
 202                 /* Set fence pointer to the same place like WR pointer */
 203                 iwl_trans_write_prph(mvm->trans,
 204                                      RXF_LD_WR2FENCE + offset_diff, 0x1);
 205                 /* Set fence offset */
 206                 iwl_trans_write_prph(mvm->trans,
 207                                      RXF_LD_FENCE_OFFSET_ADDR + offset_diff,
 208                                      0x0);
 209
 210                 /* Read FIFO */
 211                 fifo_len /= sizeof(u32); /* Size in DWORDS */
 212                 for (j = 0; j < fifo_len; j++)
 213                         fifo_data[j] = iwl_trans_read_prph(mvm->trans,
 214                                                          RXF_FIFO_RD_FENCE_INC +
 215                                                          offset_diff);
 216                 *dump_data = iwl_fw_error_next_data(*dump_data);
 217         }
 218
 219         /* Pull TXF data from all TXFs */
 220         for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++) {
 221                 /* Mark the number of TXF we're pulling now */
 222                 iwl_trans_write_prph(mvm->trans, TXF_LARC_NUM, i);
 223
 224                 fifo_hdr = (void *)(*dump_data)->data;
 225                 fifo_data = (void *)fifo_hdr->data;
 226                 fifo_len = mvm->shared_mem_cfg.txfifo_size[i];
 227
 228                 /* No need to try to read the data if the length is 0 */
 229                 if (fifo_len == 0)
 230                         continue;
 231
 232                 /* Add a TLV for the FIFO */
 233                 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF);
 234                 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
 235
 236                 fifo_hdr->fifo_num = cpu_to_le32(i);
 237                 fifo_hdr->available_bytes =
 238                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 239                                                         TXF_FIFO_ITEM_CNT));
 240                 fifo_hdr->wr_ptr =
 241                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 242                                                         TXF_WR_PTR));
 243                 fifo_hdr->rd_ptr =
 244                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 245                                                         TXF_RD_PTR));
 246                 fifo_hdr->fence_ptr =
 247                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 248                                                         TXF_FENCE_PTR));
 249                 fifo_hdr->fence_mode =
 250                         cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 251                                                         TXF_LOCK_FENCE));
 252
 253                 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */
 254                 iwl_trans_write_prph(mvm->trans, TXF_READ_MODIFY_ADDR,
 255                                      TXF_WR_PTR);
 256
 257                 /* Dummy-read to advance the read pointer to the head */
 258                 iwl_trans_read_prph(mvm->trans, TXF_READ_MODIFY_DATA);
 259
 260                 /* Read FIFO */
 261                 fifo_len /= sizeof(u32); /* Size in DWORDS */
 262                 for (j = 0; j < fifo_len; j++)
 263                         fifo_data[j] = iwl_trans_read_prph(mvm->trans,
 264                                                           TXF_READ_MODIFY_DATA);
 265                 *dump_data = iwl_fw_error_next_data(*dump_data);
 266         }
 267
 268         if (fw_has_capa(&mvm->fw->ucode_capa,
 269                         IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
 270                 /* Pull UMAC internal TXF data from all TXFs */
 271                 for (i = 0;
 272                      i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
 273                      i++) {
 274                         /* Mark the number of TXF we're pulling now */
 275                         iwl_trans_write_prph(mvm->trans, TXF_CPU2_NUM, i);
 276
 277                         fifo_hdr = (void *)(*dump_data)->data;
 278                         fifo_data = (void *)fifo_hdr->data;
 279                         fifo_len = mvm->shared_mem_cfg.internal_txfifo_size[i];
 280
 281                         /* No need to try to read the data if the length is 0 */
 282                         if (fifo_len == 0)
 283                                 continue;
 284
 285                         /* Add a TLV for the internal FIFOs */
 286                         (*dump_data)->type =
 287                                 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF);
 288                         (*dump_data)->len =
 289                                 cpu_to_le32(fifo_len + sizeof(*fifo_hdr));
 290
 291                         fifo_hdr->fifo_num = cpu_to_le32(i);
 292                         fifo_hdr->available_bytes =
 293                                 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 294                                                                 TXF_CPU2_FIFO_ITEM_CNT));
 295                         fifo_hdr->wr_ptr =
 296                                 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 297                                                                 TXF_CPU2_WR_PTR));
 298                         fifo_hdr->rd_ptr =
 299                                 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 300                                                                 TXF_CPU2_RD_PTR));
 301                         fifo_hdr->fence_ptr =
 302                                 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 303                                                                 TXF_CPU2_FENCE_PTR));
 304                         fifo_hdr->fence_mode =
 305                                 cpu_to_le32(iwl_trans_read_prph(mvm->trans,
 306                                                                 TXF_CPU2_LOCK_FENCE));
 307
 308                         /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */
 309                         iwl_trans_write_prph(mvm->trans,
 310                                              TXF_CPU2_READ_MODIFY_ADDR,
 311                                              TXF_CPU2_WR_PTR);
 312
 313                         /* Dummy-read to advance the read pointer to head */
 314                         iwl_trans_read_prph(mvm->trans,
 315                                             TXF_CPU2_READ_MODIFY_DATA);
 316
 317                         /* Read FIFO */
 318                         fifo_len /= sizeof(u32); /* Size in DWORDS */
 319                         for (j = 0; j < fifo_len; j++)
 320                                 fifo_data[j] =
 321                                         iwl_trans_read_prph(mvm->trans,
 322                                                             TXF_CPU2_READ_MODIFY_DATA);
 323                         *dump_data = iwl_fw_error_next_data(*dump_data);
 324                 }
 325         }
 326
 327         iwl_trans_release_nic_access(mvm->trans, &flags);
 328 }
 329
 330 void iwl_mvm_free_fw_dump_desc(struct iwl_mvm *mvm)
 331 {
 332         if (mvm->fw_dump_desc == &iwl_mvm_dump_desc_assert)
 333                 return;
 334
 335         kfree(mvm->fw_dump_desc);
 336         mvm->fw_dump_desc = NULL;
 337 }
 338
 339 #define IWL8260_ICCM_OFFSET             0x44000 /* Only for B-step */
 340 #define IWL8260_ICCM_LEN                0xC000 /* Only for B-step */
 341
 342 static const struct {
 343         u32 start, end;
 344 } iwl_prph_dump_addr[] = {
 345         { .start = 0x00a00000, .end = 0x00a00000 },
 346         { .start = 0x00a0000c, .end = 0x00a00024 },
 347         { .start = 0x00a0002c, .end = 0x00a0003c },
 348         { .start = 0x00a00410, .end = 0x00a00418 },
 349         { .start = 0x00a00420, .end = 0x00a00420 },
 350         { .start = 0x00a00428, .end = 0x00a00428 },
 351         { .start = 0x00a00430, .end = 0x00a0043c },
 352         { .start = 0x00a00444, .end = 0x00a00444 },
 353         { .start = 0x00a004c0, .end = 0x00a004cc },
 354         { .start = 0x00a004d8, .end = 0x00a004d8 },
 355         { .start = 0x00a004e0, .end = 0x00a004f0 },
 356         { .start = 0x00a00840, .end = 0x00a00840 },
 357         { .start = 0x00a00850, .end = 0x00a00858 },
 358         { .start = 0x00a01004, .end = 0x00a01008 },
 359         { .start = 0x00a01010, .end = 0x00a01010 },
 360         { .start = 0x00a01018, .end = 0x00a01018 },
 361         { .start = 0x00a01024, .end = 0x00a01024 },
 362         { .start = 0x00a0102c, .end = 0x00a01034 },
 363         { .start = 0x00a0103c, .end = 0x00a01040 },
 364         { .start = 0x00a01048, .end = 0x00a01094 },
 365         { .start = 0x00a01c00, .end = 0x00a01c20 },
 366         { .start = 0x00a01c58, .end = 0x00a01c58 },
 367         { .start = 0x00a01c7c, .end = 0x00a01c7c },
 368         { .start = 0x00a01c28, .end = 0x00a01c54 },
 369         { .start = 0x00a01c5c, .end = 0x00a01c5c },
 370         { .start = 0x00a01c60, .end = 0x00a01cdc },
 371         { .start = 0x00a01ce0, .end = 0x00a01d0c },
 372         { .start = 0x00a01d18, .end = 0x00a01d20 },
 373         { .start = 0x00a01d2c, .end = 0x00a01d30 },
 374         { .start = 0x00a01d40, .end = 0x00a01d5c },
 375         { .start = 0x00a01d80, .end = 0x00a01d80 },
 376         { .start = 0x00a01d98, .end = 0x00a01d9c },
 377         { .start = 0x00a01da8, .end = 0x00a01da8 },
 378         { .start = 0x00a01db8, .end = 0x00a01df4 },
 379         { .start = 0x00a01dc0, .end = 0x00a01dfc },
 380         { .start = 0x00a01e00, .end = 0x00a01e2c },
 381         { .start = 0x00a01e40, .end = 0x00a01e60 },
 382         { .start = 0x00a01e68, .end = 0x00a01e6c },
 383         { .start = 0x00a01e74, .end = 0x00a01e74 },
 384         { .start = 0x00a01e84, .end = 0x00a01e90 },
 385         { .start = 0x00a01e9c, .end = 0x00a01ec4 },
 386         { .start = 0x00a01ed0, .end = 0x00a01ee0 },
 387         { .start = 0x00a01f00, .end = 0x00a01f1c },
 388         { .start = 0x00a01f44, .end = 0x00a01ffc },
 389         { .start = 0x00a02000, .end = 0x00a02048 },
 390         { .start = 0x00a02068, .end = 0x00a020f0 },
 391         { .start = 0x00a02100, .end = 0x00a02118 },
 392         { .start = 0x00a02140, .end = 0x00a0214c },
 393         { .start = 0x00a02168, .end = 0x00a0218c },
 394         { .start = 0x00a021c0, .end = 0x00a021c0 },
 395         { .start = 0x00a02400, .end = 0x00a02410 },
 396         { .start = 0x00a02418, .end = 0x00a02420 },
 397         { .start = 0x00a02428, .end = 0x00a0242c },
 398         { .start = 0x00a02434, .end = 0x00a02434 },
 399         { .start = 0x00a02440, .end = 0x00a02460 },
 400         { .start = 0x00a02468, .end = 0x00a024b0 },
 401         { .start = 0x00a024c8, .end = 0x00a024cc },
 402         { .start = 0x00a02500, .end = 0x00a02504 },
 403         { .start = 0x00a0250c, .end = 0x00a02510 },
 404         { .start = 0x00a02540, .end = 0x00a02554 },
 405         { .start = 0x00a02580, .end = 0x00a025f4 },
 406         { .start = 0x00a02600, .end = 0x00a0260c },
 407         { .start = 0x00a02648, .end = 0x00a02650 },
 408         { .start = 0x00a02680, .end = 0x00a02680 },
 409         { .start = 0x00a026c0, .end = 0x00a026d0 },
 410         { .start = 0x00a02700, .end = 0x00a0270c },
 411         { .start = 0x00a02804, .end = 0x00a02804 },
 412         { .start = 0x00a02818, .end = 0x00a0281c },
 413         { .start = 0x00a02c00, .end = 0x00a02db4 },
 414         { .start = 0x00a02df4, .end = 0x00a02fb0 },
 415         { .start = 0x00a03000, .end = 0x00a03014 },
 416         { .start = 0x00a0301c, .end = 0x00a0302c },
 417         { .start = 0x00a03034, .end = 0x00a03038 },
 418         { .start = 0x00a03040, .end = 0x00a03048 },
 419         { .start = 0x00a03060, .end = 0x00a03068 },
 420         { .start = 0x00a03070, .end = 0x00a03074 },
 421         { .start = 0x00a0307c, .end = 0x00a0307c },
 422         { .start = 0x00a03080, .end = 0x00a03084 },
 423         { .start = 0x00a0308c, .end = 0x00a03090 },
 424         { .start = 0x00a03098, .end = 0x00a03098 },
 425         { .start = 0x00a030a0, .end = 0x00a030a0 },
 426         { .start = 0x00a030a8, .end = 0x00a030b4 },
 427         { .start = 0x00a030bc, .end = 0x00a030bc },
 428         { .start = 0x00a030c0, .end = 0x00a0312c },
 429         { .start = 0x00a03c00, .end = 0x00a03c5c },
 430         { .start = 0x00a04400, .end = 0x00a04454 },
 431         { .start = 0x00a04460, .end = 0x00a04474 },
 432         { .start = 0x00a044c0, .end = 0x00a044ec },
 433         { .start = 0x00a04500, .end = 0x00a04504 },
 434         { .start = 0x00a04510, .end = 0x00a04538 },
 435         { .start = 0x00a04540, .end = 0x00a04548 },
 436         { .start = 0x00a04560, .end = 0x00a0457c },
 437         { .start = 0x00a04590, .end = 0x00a04598 },
 438         { .start = 0x00a045c0, .end = 0x00a045f4 },
 439         { .start = 0x00a44000, .end = 0x00a7bf80 },
 440 };
 441
 442 static u32 iwl_dump_prph(struct iwl_trans *trans,
 443                          struct iwl_fw_error_dump_data **data)
 444 {
 445         struct iwl_fw_error_dump_prph *prph;
 446         unsigned long flags;
 447         u32 prph_len = 0, i;
 448
 449         if (!iwl_trans_grab_nic_access(trans, &flags))
 450                 return 0;
 451
 452         for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
 453                 /* The range includes both boundaries */
 454                 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
 455                          iwl_prph_dump_addr[i].start + 4;
 456                 int reg;
 457                 __le32 *val;
 458
 459                 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
 460
 461                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
 462                 (*data)->len = cpu_to_le32(sizeof(*prph) +
 463                                         num_bytes_in_chunk);
 464                 prph = (void *)(*data)->data;
 465                 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
 466                 val = (void *)prph->data;
 467
 468                 for (reg = iwl_prph_dump_addr[i].start;
 469                      reg <= iwl_prph_dump_addr[i].end;
 470                      reg += 4)
 471                         *val++ = cpu_to_le32(iwl_read_prph_no_grab(trans,
 472                                                                    reg));
 473
 474                 *data = iwl_fw_error_next_data(*data);
 475         }
 476
 477         iwl_trans_release_nic_access(trans, &flags);
 478
 479         return prph_len;
 480 }
 481
 482 void iwl_mvm_fw_error_dump(struct iwl_mvm *mvm)
 483 {
 484         struct iwl_fw_error_dump_file *dump_file;
 485         struct iwl_fw_error_dump_data *dump_data;
 486         struct iwl_fw_error_dump_info *dump_info;
 487         struct iwl_fw_error_dump_mem *dump_mem;
 488         struct iwl_fw_error_dump_trigger_desc *dump_trig;
 489         struct iwl_mvm_dump_ptrs *fw_error_dump;
 490         u32 sram_len, sram_ofs;
 491         struct iwl_fw_dbg_mem_seg_tlv * const *fw_dbg_mem =
 492                 mvm->fw->dbg_mem_tlv;
 493         u32 file_len, fifo_data_len = 0, prph_len = 0, radio_len = 0;
 494         u32 smem_len = mvm->fw->dbg_dynamic_mem ? 0 : mvm->cfg->smem_len;
 495         u32 sram2_len = mvm->fw->dbg_dynamic_mem ? 0 : mvm->cfg->dccm2_len;
 496         bool monitor_dump_only = false;
 497         int i;
 498
 499         if (!IWL_MVM_COLLECT_FW_ERR_DUMP &&
 500             !mvm->trans->dbg_dest_tlv)
 501                 return;
 502
 503         lockdep_assert_held(&mvm->mutex);
 504
 505         /* there's no point in fw dump if the bus is dead */
 506         if (test_bit(STATUS_TRANS_DEAD, &mvm->trans->status)) {
 507                 IWL_ERR(mvm, "Skip fw error dump since bus is dead\n");
 508                 goto out;
 509         }
 510
 511         if (mvm->fw_dump_trig &&
 512             mvm->fw_dump_trig->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)
 513                 monitor_dump_only = true;
 514
 515         fw_error_dump = kzalloc(sizeof(*fw_error_dump), GFP_KERNEL);
 516         if (!fw_error_dump)
 517                 goto out;
 518
 519         /* SRAM - include stack CCM if driver knows the values for it */
 520         if (!mvm->cfg->dccm_offset || !mvm->cfg->dccm_len) {
 521                 const struct fw_img *img;
 522
 523                 img = &mvm->fw->img[mvm->cur_ucode];
 524                 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset;
 525                 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len;
 526         } else {
 527                 sram_ofs = mvm->cfg->dccm_offset;
 528                 sram_len = mvm->cfg->dccm_len;
 529         }
 530
 531         /* reading RXF/TXF sizes */
 532         if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
 533                 struct iwl_mvm_shared_mem_cfg *mem_cfg = &mvm->shared_mem_cfg;
 534
 535                 fifo_data_len = 0;
 536
 537                 /* Count RXF size */
 538                 for (i = 0; i < ARRAY_SIZE(mem_cfg->rxfifo_size); i++) {
 539                         if (!mem_cfg->rxfifo_size[i])
 540                                 continue;
 541
 542                         /* Add header info */
 543                         fifo_data_len += mem_cfg->rxfifo_size[i] +
 544                                          sizeof(*dump_data) +
 545                                          sizeof(struct iwl_fw_error_dump_fifo);
 546                 }
 547
 548                 for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++) {
 549                         if (!mem_cfg->txfifo_size[i])
 550                                 continue;
 551
 552                         /* Add header info */
 553                         fifo_data_len += mem_cfg->txfifo_size[i] +
 554                                          sizeof(*dump_data) +
 555                                          sizeof(struct iwl_fw_error_dump_fifo);
 556                 }
 557
 558                 if (fw_has_capa(&mvm->fw->ucode_capa,
 559                                 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
 560                         for (i = 0;
 561                              i < ARRAY_SIZE(mem_cfg->internal_txfifo_size);
 562                              i++) {
 563                                 if (!mem_cfg->internal_txfifo_size[i])
 564                                         continue;
 565
 566                                 /* Add header info */
 567                                 fifo_data_len +=
 568                                         mem_cfg->internal_txfifo_size[i] +
 569                                         sizeof(*dump_data) +
 570                                         sizeof(struct iwl_fw_error_dump_fifo);
 571                         }
 572                 }
 573
 574                 /* Make room for PRPH registers */
 575                 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
 576                         /* The range includes both boundaries */
 577                         int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
 578                                 iwl_prph_dump_addr[i].start + 4;
 579
 580                         prph_len += sizeof(*dump_data) +
 581                                 sizeof(struct iwl_fw_error_dump_prph) +
 582                                 num_bytes_in_chunk;
 583                 }
 584
 585                 if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 586                         radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
 587         }
 588
 589         file_len = sizeof(*dump_file) +
 590                    sizeof(*dump_data) * 2 +
 591                    fifo_data_len +
 592                    prph_len +
 593                    radio_len +
 594                    sizeof(*dump_info);
 595
 596         /* Make room for the SMEM, if it exists */
 597         if (smem_len)
 598                 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + smem_len;
 599
 600         /* Make room for the secondary SRAM, if it exists */
 601         if (sram2_len)
 602                 file_len += sizeof(*dump_data) + sizeof(*dump_mem) + sram2_len;
 603
 604         /* Make room for MEM segments */
 605         for (i = 0; i < ARRAY_SIZE(mvm->fw->dbg_mem_tlv); i++) {
 606                 if (fw_dbg_mem[i])
 607                         file_len += sizeof(*dump_data) + sizeof(*dump_mem) +
 608                                 le32_to_cpu(fw_dbg_mem[i]->len);
 609         }
 610
 611         /* Make room for fw's virtual image pages, if it exists */
 612         if (mvm->fw->img[mvm->cur_ucode].paging_mem_size &&
 613             mvm->fw_paging_db[0].fw_paging_block)
 614                 file_len += mvm->num_of_paging_blk *
 615                         (sizeof(*dump_data) +
 616                          sizeof(struct iwl_fw_error_dump_paging) +
 617                          PAGING_BLOCK_SIZE);
 618
 619         /* If we only want a monitor dump, reset the file length */
 620         if (monitor_dump_only) {
 621                 file_len = sizeof(*dump_file) + sizeof(*dump_data) +
 622                            sizeof(*dump_info);
 623         }
 624
 625         /*
 626          * In 8000 HW family B-step include the ICCM (which resides separately)
 627          */
 628         if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
 629             CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP)
 630                 file_len += sizeof(*dump_data) + sizeof(*dump_mem) +
 631                             IWL8260_ICCM_LEN;
 632
 633         if (mvm->fw_dump_desc)
 634                 file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
 635                             mvm->fw_dump_desc->len;
 636
 637         if (!mvm->fw->dbg_dynamic_mem)
 638                 file_len += sram_len + sizeof(*dump_mem);
 639
 640         dump_file = vzalloc(file_len);
 641         if (!dump_file) {
 642                 kfree(fw_error_dump);
 643                 goto out;
 644         }
 645
 646         fw_error_dump->op_mode_ptr = dump_file;
 647
 648         dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
 649         dump_data = (void *)dump_file->data;
 650
 651         dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
 652         dump_data->len = cpu_to_le32(sizeof(*dump_info));
 653         dump_info = (void *)dump_data->data;
 654         dump_info->device_family =
 655                 mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000 ?
 656                         cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_7) :
 657                         cpu_to_le32(IWL_FW_ERROR_DUMP_FAMILY_8);
 658         dump_info->hw_step = cpu_to_le32(CSR_HW_REV_STEP(mvm->trans->hw_rev));
 659         memcpy(dump_info->fw_human_readable, mvm->fw->human_readable,
 660                sizeof(dump_info->fw_human_readable));
 661         strncpy(dump_info->dev_human_readable, mvm->cfg->name,
 662                 sizeof(dump_info->dev_human_readable));
 663         strncpy(dump_info->bus_human_readable, mvm->dev->bus->name,
 664                 sizeof(dump_info->bus_human_readable));
 665
 666         dump_data = iwl_fw_error_next_data(dump_data);
 667         /* We only dump the FIFOs if the FW is in error state */
 668         if (test_bit(STATUS_FW_ERROR, &mvm->trans->status)) {
 669                 iwl_mvm_dump_fifos(mvm, &dump_data);
 670                 if (radio_len)
 671                         iwl_mvm_read_radio_reg(mvm, &dump_data);
 672         }
 673
 674         if (mvm->fw_dump_desc) {
 675                 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
 676                 dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
 677                                              mvm->fw_dump_desc->len);
 678                 dump_trig = (void *)dump_data->data;
 679                 memcpy(dump_trig, &mvm->fw_dump_desc->trig_desc,
 680                        sizeof(*dump_trig) + mvm->fw_dump_desc->len);
 681
 682                 dump_data = iwl_fw_error_next_data(dump_data);
 683         }
 684
 685         /* In case we only want monitor dump, skip to dump trasport data */
 686         if (monitor_dump_only)
 687                 goto dump_trans_data;
 688
 689         if (!mvm->fw->dbg_dynamic_mem) {
 690                 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
 691                 dump_data->len = cpu_to_le32(sram_len + sizeof(*dump_mem));
 692                 dump_mem = (void *)dump_data->data;
 693                 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
 694                 dump_mem->offset = cpu_to_le32(sram_ofs);
 695                 iwl_trans_read_mem_bytes(mvm->trans, sram_ofs, dump_mem->data,
 696                                          sram_len);
 697                 dump_data = iwl_fw_error_next_data(dump_data);
 698         }
 699
 700         for (i = 0; i < ARRAY_SIZE(mvm->fw->dbg_mem_tlv); i++) {
 701                 if (fw_dbg_mem[i]) {
 702                         u32 len = le32_to_cpu(fw_dbg_mem[i]->len);
 703                         u32 ofs = le32_to_cpu(fw_dbg_mem[i]->ofs);
 704
 705                         dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
 706                         dump_data->len = cpu_to_le32(len +
 707                                         sizeof(*dump_mem));
 708                         dump_mem = (void *)dump_data->data;
 709                         dump_mem->type = fw_dbg_mem[i]->data_type;
 710                         dump_mem->offset = cpu_to_le32(ofs);
 711                         iwl_trans_read_mem_bytes(mvm->trans, ofs,
 712                                                  dump_mem->data,
 713                                                  len);
 714                         dump_data = iwl_fw_error_next_data(dump_data);
 715                 }
 716         }
 717
 718         if (smem_len) {
 719                 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
 720                 dump_data->len = cpu_to_le32(smem_len + sizeof(*dump_mem));
 721                 dump_mem = (void *)dump_data->data;
 722                 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SMEM);
 723                 dump_mem->offset = cpu_to_le32(mvm->cfg->smem_offset);
 724                 iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->smem_offset,
 725                                          dump_mem->data, smem_len);
 726                 dump_data = iwl_fw_error_next_data(dump_data);
 727         }
 728
 729         if (sram2_len) {
 730                 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
 731                 dump_data->len = cpu_to_le32(sram2_len + sizeof(*dump_mem));
 732                 dump_mem = (void *)dump_data->data;
 733                 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
 734                 dump_mem->offset = cpu_to_le32(mvm->cfg->dccm2_offset);
 735                 iwl_trans_read_mem_bytes(mvm->trans, mvm->cfg->dccm2_offset,
 736                                          dump_mem->data, sram2_len);
 737                 dump_data = iwl_fw_error_next_data(dump_data);
 738         }
 739
 740         if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
 741             CSR_HW_REV_STEP(mvm->trans->hw_rev) == SILICON_B_STEP) {
 742                 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
 743                 dump_data->len = cpu_to_le32(IWL8260_ICCM_LEN +
 744                                              sizeof(*dump_mem));
 745                 dump_mem = (void *)dump_data->data;
 746                 dump_mem->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_SRAM);
 747                 dump_mem->offset = cpu_to_le32(IWL8260_ICCM_OFFSET);
 748                 iwl_trans_read_mem_bytes(mvm->trans, IWL8260_ICCM_OFFSET,
 749                                          dump_mem->data, IWL8260_ICCM_LEN);
 750                 dump_data = iwl_fw_error_next_data(dump_data);
 751         }
 752
 753         /* Dump fw's virtual image */
 754         if (mvm->fw->img[mvm->cur_ucode].paging_mem_size &&
 755             mvm->fw_paging_db[0].fw_paging_block) {
 756                 for (i = 1; i < mvm->num_of_paging_blk + 1; i++) {
 757                         struct iwl_fw_error_dump_paging *paging;
 758                         struct page *pages =
 759                                 mvm->fw_paging_db[i].fw_paging_block;
 760
 761                         dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
 762                         dump_data->len = cpu_to_le32(sizeof(*paging) +
 763                                                      PAGING_BLOCK_SIZE);
 764                         paging = (void *)dump_data->data;
 765                         paging->index = cpu_to_le32(i);
 766                         memcpy(paging->data, page_address(pages),
 767                                PAGING_BLOCK_SIZE);
 768                         dump_data = iwl_fw_error_next_data(dump_data);
 769                 }
 770         }
 771
 772         if (prph_len)
 773                 iwl_dump_prph(mvm->trans, &dump_data);
 774
 775 dump_trans_data:
 776         fw_error_dump->trans_ptr = iwl_trans_dump_data(mvm->trans,
 777                                                        mvm->fw_dump_trig);
 778         fw_error_dump->op_mode_len = file_len;
 779         if (fw_error_dump->trans_ptr)
 780                 file_len += fw_error_dump->trans_ptr->len;
 781         dump_file->file_len = cpu_to_le32(file_len);
 782
 783         dev_coredumpm(mvm->trans->dev, THIS_MODULE, fw_error_dump, 0,
 784                       GFP_KERNEL, iwl_mvm_read_coredump, iwl_mvm_free_coredump);
 785
 786 out:
 787         iwl_mvm_free_fw_dump_desc(mvm);
 788         mvm->fw_dump_trig = NULL;
 789         clear_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status);
 790 }
 791
 792 const struct iwl_mvm_dump_desc iwl_mvm_dump_desc_assert = {
 793         .trig_desc = {
 794                 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT),
 795         },
 796 };
 797
 798 int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
 799                                 const struct iwl_mvm_dump_desc *desc,
 800                                 const struct iwl_fw_dbg_trigger_tlv *trigger)
 801 {
 802         unsigned int delay = 0;
 803
 804         if (trigger)
 805                 delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
 806
 807         if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
 808                 return -EBUSY;
 809
 810         if (WARN_ON(mvm->fw_dump_desc))
 811                 iwl_mvm_free_fw_dump_desc(mvm);
 812
 813         IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
 814                  le32_to_cpu(desc->trig_desc.type));
 815
 816         mvm->fw_dump_desc = desc;
 817         mvm->fw_dump_trig = trigger;
 818
 819         queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay);
 820
 821         return 0;
 822 }
 823
 824 int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
 825                            const char *str, size_t len,
 826                            const struct iwl_fw_dbg_trigger_tlv *trigger)
 827 {
 828         struct iwl_mvm_dump_desc *desc;
 829
 830         desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
 831         if (!desc)
 832                 return -ENOMEM;
 833
 834         desc->len = len;
 835         desc->trig_desc.type = cpu_to_le32(trig);
 836         memcpy(desc->trig_desc.data, str, len);
 837
 838         return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
 839 }
 840
 841 int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
 842                                 struct iwl_fw_dbg_trigger_tlv *trigger,
 843                                 const char *fmt, ...)
 844 {
 845         u16 occurrences = le16_to_cpu(trigger->occurrences);
 846         int ret, len = 0;
 847         char buf[64];
 848
 849         if (!occurrences)
 850                 return 0;
 851
 852         if (fmt) {
 853                 va_list ap;
 854
 855                 buf[sizeof(buf) - 1] = '\0';
 856
 857                 va_start(ap, fmt);
 858                 vsnprintf(buf, sizeof(buf), fmt, ap);
 859                 va_end(ap);
 860
 861                 /* check for truncation */
 862                 if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
 863                         buf[sizeof(buf) - 1] = '\0';
 864
 865                 len = strlen(buf) + 1;
 866         }
 867
 868         ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
 869                                      trigger);
 870
 871         if (ret)
 872                 return ret;
 873
 874         trigger->occurrences = cpu_to_le16(occurrences - 1);
 875         return 0;
 876 }
 877
 878 static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
 879 {
 880         if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 881                 iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
 882         else
 883                 iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
 884 }
 885
 886 int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
 887 {
 888         u8 *ptr;
 889         int ret;
 890         int i;
 891
 892         if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
 893                       "Invalid configuration %d\n", conf_id))
 894                 return -EINVAL;
 895
 896         /* EARLY START - firmware's configuration is hard coded */
 897         if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
 898              !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
 899             conf_id == FW_DBG_START_FROM_ALIVE) {
 900                 iwl_mvm_restart_early_start(mvm);
 901                 return 0;
 902         }
 903
 904         if (!mvm->fw->dbg_conf_tlv[conf_id])
 905                 return -EINVAL;
 906
 907         if (mvm->fw_dbg_conf != FW_DBG_INVALID)
 908                 IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
 909                          mvm->fw_dbg_conf);
 910
 911         /* Send all HCMDs for configuring the FW debug */
 912         ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
 913         for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
 914                 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
 915
 916                 ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
 917                                            le16_to_cpu(cmd->len), cmd->data);
 918                 if (ret)
 919                         return ret;
 920
 921                 ptr += sizeof(*cmd);
 922                 ptr += le16_to_cpu(cmd->len);
 923         }
 924
 925         mvm->fw_dbg_conf = conf_id;
 926         return ret;
 927 }