drivers/net/wireless/ath/ath9k/ar9003_eeprom.h

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef AR9003_EEPROM_H
  18 #define AR9003_EEPROM_H
  19
  20 #include <linux/types.h>
  21
  22 #define AR9300_EEP_VER               0xD000
  23 #define AR9300_EEP_VER_MINOR_MASK    0xFFF
  24 #define AR9300_EEP_MINOR_VER_1       0x1
  25 #define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1
  26
  27 /* 16-bit offset location start of calibration struct */
  28 #define AR9300_EEP_START_LOC         256
  29 #define AR9300_NUM_5G_CAL_PIERS      8
  30 #define AR9300_NUM_2G_CAL_PIERS      3
  31 #define AR9300_NUM_5G_20_TARGET_POWERS  8
  32 #define AR9300_NUM_5G_40_TARGET_POWERS  8
  33 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
  34 #define AR9300_NUM_2G_20_TARGET_POWERS  3
  35 #define AR9300_NUM_2G_40_TARGET_POWERS  3
  36 /* #define AR9300_NUM_CTLS              21 */
  37 #define AR9300_NUM_CTLS_5G           9
  38 #define AR9300_NUM_CTLS_2G           12
  39 #define AR9300_NUM_BAND_EDGES_5G     8
  40 #define AR9300_NUM_BAND_EDGES_2G     4
  41 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
  42 #define AR9300_EEPMISC_WOW           0x02
  43 #define AR9300_CUSTOMER_DATA_SIZE    20
  44
  45 #define AR9300_MAX_CHAINS            3
  46 #define AR9300_ANT_16S               25
  47 #define AR9300_FUTURE_MODAL_SZ       6
  48
  49 #define AR9300_PAPRD_RATE_MASK          0x01ffffff
  50 #define AR9300_PAPRD_SCALE_1            0x0e000000
  51 #define AR9300_PAPRD_SCALE_1_S          25
  52 #define AR9300_PAPRD_SCALE_2            0x70000000
  53 #define AR9300_PAPRD_SCALE_2_S          28
  54
  55 /* Delta from which to start power to pdadc table */
  56 /* This offset is used in both open loop and closed loop power control
  57  * schemes. In open loop power control, it is not really needed, but for
  58  * the "sake of consistency" it was kept. For certain AP designs, this
  59  * value is overwritten by the value in the flag "pwrTableOffset" just
  60  * before writing the pdadc vs pwr into the chip registers.
  61  */
  62 #define AR9300_PWR_TABLE_OFFSET  0
  63
  64 /* byte addressable */
  65 #define AR9300_EEPROM_SIZE (16*1024)
  66
  67 #define AR9300_BASE_ADDR_4K 0xfff
  68 #define AR9300_BASE_ADDR 0x3ff
  69 #define AR9300_BASE_ADDR_512 0x1ff
  70
  71 #define AR9300_OTP_BASE                 (AR_SREV_9340(ah) ? 0x30000 : 0x14000)
  72 #define AR9300_OTP_STATUS               (AR_SREV_9340(ah) ? 0x30018 : 0x15f18)
  73 #define AR9300_OTP_STATUS_TYPE          0x7
  74 #define AR9300_OTP_STATUS_VALID         0x4
  75 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
  76 #define AR9300_OTP_STATUS_SM_BUSY       0x1
  77 #define AR9300_OTP_READ_DATA            (AR_SREV_9340(ah) ? 0x3001c : 0x15f1c)
  78
  79 enum targetPowerHTRates {
  80         HT_TARGET_RATE_0_8_16,
  81         HT_TARGET_RATE_1_3_9_11_17_19,
  82         HT_TARGET_RATE_4,
  83         HT_TARGET_RATE_5,
  84         HT_TARGET_RATE_6,
  85         HT_TARGET_RATE_7,
  86         HT_TARGET_RATE_12,
  87         HT_TARGET_RATE_13,
  88         HT_TARGET_RATE_14,
  89         HT_TARGET_RATE_15,
  90         HT_TARGET_RATE_20,
  91         HT_TARGET_RATE_21,
  92         HT_TARGET_RATE_22,
  93         HT_TARGET_RATE_23
  94 };
  95
  96 enum targetPowerLegacyRates {
  97         LEGACY_TARGET_RATE_6_24,
  98         LEGACY_TARGET_RATE_36,
  99         LEGACY_TARGET_RATE_48,
 100         LEGACY_TARGET_RATE_54
 101 };
 102
 103 enum targetPowerCckRates {
 104         LEGACY_TARGET_RATE_1L_5L,
 105         LEGACY_TARGET_RATE_5S,
 106         LEGACY_TARGET_RATE_11L,
 107         LEGACY_TARGET_RATE_11S
 108 };
 109
 110 enum ar9300_Rates {
 111         ALL_TARGET_LEGACY_6_24,
 112         ALL_TARGET_LEGACY_36,
 113         ALL_TARGET_LEGACY_48,
 114         ALL_TARGET_LEGACY_54,
 115         ALL_TARGET_LEGACY_1L_5L,
 116         ALL_TARGET_LEGACY_5S,
 117         ALL_TARGET_LEGACY_11L,
 118         ALL_TARGET_LEGACY_11S,
 119         ALL_TARGET_HT20_0_8_16,
 120         ALL_TARGET_HT20_1_3_9_11_17_19,
 121         ALL_TARGET_HT20_4,
 122         ALL_TARGET_HT20_5,
 123         ALL_TARGET_HT20_6,
 124         ALL_TARGET_HT20_7,
 125         ALL_TARGET_HT20_12,
 126         ALL_TARGET_HT20_13,
 127         ALL_TARGET_HT20_14,
 128         ALL_TARGET_HT20_15,
 129         ALL_TARGET_HT20_20,
 130         ALL_TARGET_HT20_21,
 131         ALL_TARGET_HT20_22,
 132         ALL_TARGET_HT20_23,
 133         ALL_TARGET_HT40_0_8_16,
 134         ALL_TARGET_HT40_1_3_9_11_17_19,
 135         ALL_TARGET_HT40_4,
 136         ALL_TARGET_HT40_5,
 137         ALL_TARGET_HT40_6,
 138         ALL_TARGET_HT40_7,
 139         ALL_TARGET_HT40_12,
 140         ALL_TARGET_HT40_13,
 141         ALL_TARGET_HT40_14,
 142         ALL_TARGET_HT40_15,
 143         ALL_TARGET_HT40_20,
 144         ALL_TARGET_HT40_21,
 145         ALL_TARGET_HT40_22,
 146         ALL_TARGET_HT40_23,
 147         ar9300RateSize,
 148 };
 149
 150
 151 struct eepFlags {
 152         u8 opFlags;
 153         u8 eepMisc;
 154 } __packed;
 155
 156 enum CompressAlgorithm {
 157         _CompressNone = 0,
 158         _CompressLzma,
 159         _CompressPairs,
 160         _CompressBlock,
 161         _Compress4,
 162         _Compress5,
 163         _Compress6,
 164         _Compress7,
 165 };
 166
 167 struct ar9300_base_eep_hdr {
 168         __le16 regDmn[2];
 169         /* 4 bits tx and 4 bits rx */
 170         u8 txrxMask;
 171         struct eepFlags opCapFlags;
 172         u8 rfSilent;
 173         u8 blueToothOptions;
 174         u8 deviceCap;
 175         /* takes lower byte in eeprom location */
 176         u8 deviceType;
 177         /* offset in dB to be added to beginning
 178          * of pdadc table in calibration
 179          */
 180         int8_t pwrTableOffset;
 181         u8 params_for_tuning_caps[2];
 182         /*
 183          * bit0 - enable tx temp comp
 184          * bit1 - enable tx volt comp
 185          * bit2 - enable fastClock - default to 1
 186          * bit3 - enable doubling - default to 1
 187          * bit4 - enable internal regulator - default to 1
 188          */
 189         u8 featureEnable;
 190         /* misc flags: bit0 - turn down drivestrength */
 191         u8 miscConfiguration;
 192         u8 eepromWriteEnableGpio;
 193         u8 wlanDisableGpio;
 194         u8 wlanLedGpio;
 195         u8 rxBandSelectGpio;
 196         u8 txrxgain;
 197         /* SW controlled internal regulator fields */
 198         __le32 swreg;
 199 } __packed;
 200
 201 struct ar9300_modal_eep_header {
 202         /* 4 idle, t1, t2, b (4 bits per setting) */
 203         __le32 antCtrlCommon;
 204         /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 205         __le32 antCtrlCommon2;
 206         /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
 207         __le16 antCtrlChain[AR9300_MAX_CHAINS];
 208         /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 209         u8 xatten1DB[AR9300_MAX_CHAINS];
 210         /* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
 211         u8 xatten1Margin[AR9300_MAX_CHAINS];
 212         int8_t tempSlope;
 213         int8_t voltSlope;
 214         /* spur channels in usual fbin coding format */
 215         u8 spurChans[AR_EEPROM_MODAL_SPURS];
 216         /* 3  Check if the register is per chain */
 217         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
 218         u8 reserved[11];
 219         int8_t quick_drop;
 220         u8 xpaBiasLvl;
 221         u8 txFrameToDataStart;
 222         u8 txFrameToPaOn;
 223         u8 txClip;
 224         int8_t antennaGain;
 225         u8 switchSettling;
 226         int8_t adcDesiredSize;
 227         u8 txEndToXpaOff;
 228         u8 txEndToRxOn;
 229         u8 txFrameToXpaOn;
 230         u8 thresh62;
 231         __le32 papdRateMaskHt20;
 232         __le32 papdRateMaskHt40;
 233         __le16 switchcomspdt;
 234         u8 xlna_bias_strength;
 235         u8 futureModal[7];
 236 } __packed;
 237
 238 struct ar9300_cal_data_per_freq_op_loop {
 239         int8_t refPower;
 240         /* pdadc voltage at power measurement */
 241         u8 voltMeas;
 242         /* pcdac used for power measurement   */
 243         u8 tempMeas;
 244         /* range is -60 to -127 create a mapping equation 1db resolution */
 245         int8_t rxNoisefloorCal;
 246         /*range is same as noisefloor */
 247         int8_t rxNoisefloorPower;
 248         /* temp measured when noisefloor cal was performed */
 249         u8 rxTempMeas;
 250 } __packed;
 251
 252 struct cal_tgt_pow_legacy {
 253         u8 tPow2x[4];
 254 } __packed;
 255
 256 struct cal_tgt_pow_ht {
 257         u8 tPow2x[14];
 258 } __packed;
 259
 260 struct cal_ctl_data_2g {
 261         u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
 262 } __packed;
 263
 264 struct cal_ctl_data_5g {
 265         u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
 266 } __packed;
 267
 268 struct ar9300_BaseExtension_1 {
 269         u8 ant_div_control;
 270         u8 future[3];
 271         u8 tempslopextension[8];
 272         int8_t quick_drop_low;
 273         int8_t quick_drop_high;
 274 } __packed;
 275
 276 struct ar9300_BaseExtension_2 {
 277         int8_t    tempSlopeLow;
 278         int8_t    tempSlopeHigh;
 279         u8   xatten1DBLow[AR9300_MAX_CHAINS];
 280         u8   xatten1MarginLow[AR9300_MAX_CHAINS];
 281         u8   xatten1DBHigh[AR9300_MAX_CHAINS];
 282         u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
 283 } __packed;
 284
 285 struct ar9300_eeprom {
 286         u8 eepromVersion;
 287         u8 templateVersion;
 288         u8 macAddr[6];
 289         u8 custData[AR9300_CUSTOMER_DATA_SIZE];
 290
 291         struct ar9300_base_eep_hdr baseEepHeader;
 292
 293         struct ar9300_modal_eep_header modalHeader2G;
 294         struct ar9300_BaseExtension_1 base_ext1;
 295         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
 296         struct ar9300_cal_data_per_freq_op_loop
 297          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
 298         u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
 299         u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
 300         u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
 301         u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
 302         struct cal_tgt_pow_legacy
 303          calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
 304         struct cal_tgt_pow_legacy
 305          calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
 306         struct cal_tgt_pow_ht
 307          calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
 308         struct cal_tgt_pow_ht
 309          calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
 310         u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
 311         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
 312         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
 313         struct ar9300_modal_eep_header modalHeader5G;
 314         struct ar9300_BaseExtension_2 base_ext2;
 315         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
 316         struct ar9300_cal_data_per_freq_op_loop
 317          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
 318         u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
 319         u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
 320         u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
 321         struct cal_tgt_pow_legacy
 322          calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
 323         struct cal_tgt_pow_ht
 324          calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
 325         struct cal_tgt_pow_ht
 326          calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
 327         u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
 328         u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
 329         struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
 330 } __packed;
 331
 332 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
 333 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
 334
 335 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
 336
 337 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
 338                                            struct ath9k_channel *chan);
 339
 340 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
 341
 342 #endif