1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 ************************************************************************/
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
74 #include <linux/tcp.h>
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
80 #include <asm/div64.h>
85 #include "s2io-regs.h"
87 #define DRV_VERSION "2.0.26.2"
89 /* S2io Driver name & version. */
90 static char s2io_driver_name[] = "Neterion";
91 static char s2io_driver_version[] = DRV_VERSION;
93 static int rxd_size[2] = {32,48};
94 static int rxd_count[2] = {127,85};
96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
123 struct mac_info *mac_control;
125 mac_control = &sp->mac_control;
126 if (rxb_size <= rxd_count[sp->rxd_mode])
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
133 static inline int is_s2io_card_up(const struct s2io_nic * sp)
135 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
138 /* Ethtool related variables and Macros. */
139 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
140 "Register test\t(offline)",
141 "Eeprom test\t(offline)",
142 "Link test\t(online)",
143 "RLDRAM test\t(offline)",
144 "BIST Test\t(offline)"
147 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
149 {"tmac_data_octets"},
153 {"tmac_pause_ctrl_frms"},
157 {"tmac_any_err_frms"},
158 {"tmac_ttl_less_fb_octets"},
159 {"tmac_vld_ip_octets"},
167 {"rmac_data_octets"},
168 {"rmac_fcs_err_frms"},
170 {"rmac_vld_mcst_frms"},
171 {"rmac_vld_bcst_frms"},
172 {"rmac_in_rng_len_err_frms"},
173 {"rmac_out_rng_len_err_frms"},
175 {"rmac_pause_ctrl_frms"},
176 {"rmac_unsup_ctrl_frms"},
178 {"rmac_accepted_ucst_frms"},
179 {"rmac_accepted_nucst_frms"},
180 {"rmac_discarded_frms"},
181 {"rmac_drop_events"},
182 {"rmac_ttl_less_fb_octets"},
184 {"rmac_usized_frms"},
185 {"rmac_osized_frms"},
187 {"rmac_jabber_frms"},
188 {"rmac_ttl_64_frms"},
189 {"rmac_ttl_65_127_frms"},
190 {"rmac_ttl_128_255_frms"},
191 {"rmac_ttl_256_511_frms"},
192 {"rmac_ttl_512_1023_frms"},
193 {"rmac_ttl_1024_1518_frms"},
201 {"rmac_err_drp_udp"},
202 {"rmac_xgmii_err_sym"},
220 {"rmac_xgmii_data_err_cnt"},
221 {"rmac_xgmii_ctrl_err_cnt"},
222 {"rmac_accepted_ip"},
226 {"new_rd_req_rtry_cnt"},
228 {"wr_rtry_rd_ack_cnt"},
231 {"new_wr_req_rtry_cnt"},
234 {"rd_rtry_wr_ack_cnt"},
244 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
245 {"rmac_ttl_1519_4095_frms"},
246 {"rmac_ttl_4096_8191_frms"},
247 {"rmac_ttl_8192_max_frms"},
248 {"rmac_ttl_gt_max_frms"},
249 {"rmac_osized_alt_frms"},
250 {"rmac_jabber_alt_frms"},
251 {"rmac_gt_max_alt_frms"},
253 {"rmac_len_discard"},
254 {"rmac_fcs_discard"},
257 {"rmac_red_discard"},
258 {"rmac_rts_discard"},
259 {"rmac_ingm_full_discard"},
263 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
264 {"\n DRIVER STATISTICS"},
265 {"single_bit_ecc_errs"},
266 {"double_bit_ecc_errs"},
279 ("alarm_transceiver_temp_high"),
280 ("alarm_transceiver_temp_low"),
281 ("alarm_laser_bias_current_high"),
282 ("alarm_laser_bias_current_low"),
283 ("alarm_laser_output_power_high"),
284 ("alarm_laser_output_power_low"),
285 ("warn_transceiver_temp_high"),
286 ("warn_transceiver_temp_low"),
287 ("warn_laser_bias_current_high"),
288 ("warn_laser_bias_current_low"),
289 ("warn_laser_output_power_high"),
290 ("warn_laser_output_power_low"),
291 ("lro_aggregated_pkts"),
292 ("lro_flush_both_count"),
293 ("lro_out_of_sequence_pkts"),
294 ("lro_flush_due_to_max_pkts"),
295 ("lro_avg_aggr_pkts"),
296 ("mem_alloc_fail_cnt"),
297 ("pci_map_fail_cnt"),
298 ("watchdog_timer_cnt"),
305 ("tx_tcode_buf_abort_cnt"),
306 ("tx_tcode_desc_abort_cnt"),
307 ("tx_tcode_parity_err_cnt"),
308 ("tx_tcode_link_loss_cnt"),
309 ("tx_tcode_list_proc_err_cnt"),
310 ("rx_tcode_parity_err_cnt"),
311 ("rx_tcode_abort_cnt"),
312 ("rx_tcode_parity_abort_cnt"),
313 ("rx_tcode_rda_fail_cnt"),
314 ("rx_tcode_unkn_prot_cnt"),
315 ("rx_tcode_fcs_err_cnt"),
316 ("rx_tcode_buf_size_err_cnt"),
317 ("rx_tcode_rxd_corrupt_cnt"),
318 ("rx_tcode_unkn_err_cnt"),
326 {"mac_tmac_err_cnt"},
327 {"mac_rmac_err_cnt"},
328 {"xgxs_txgxs_err_cnt"},
329 {"xgxs_rxgxs_err_cnt"},
331 {"prc_pcix_err_cnt"},
338 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
339 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
341 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
343 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
344 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
346 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
347 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
349 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
350 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
352 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
353 init_timer(&timer); \
354 timer.function = handle; \
355 timer.data = (unsigned long) arg; \
356 mod_timer(&timer, (jiffies + exp)) \
359 static void s2io_vlan_rx_register(struct net_device *dev,
360 struct vlan_group *grp)
362 struct s2io_nic *nic = dev->priv;
365 spin_lock_irqsave(&nic->tx_lock, flags);
367 spin_unlock_irqrestore(&nic->tx_lock, flags);
370 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
371 static int vlan_strip_flag;
374 * Constants to be programmed into the Xena's registers, to configure
379 static const u64 herc_act_dtx_cfg[] = {
381 0x8000051536750000ULL, 0x80000515367500E0ULL,
383 0x8000051536750004ULL, 0x80000515367500E4ULL,
385 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
387 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
389 0x801205150D440000ULL, 0x801205150D4400E0ULL,
391 0x801205150D440004ULL, 0x801205150D4400E4ULL,
393 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
395 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
400 static const u64 xena_dtx_cfg[] = {
402 0x8000051500000000ULL, 0x80000515000000E0ULL,
404 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
406 0x8001051500000000ULL, 0x80010515000000E0ULL,
408 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
410 0x8002051500000000ULL, 0x80020515000000E0ULL,
412 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
417 * Constants for Fixing the MacAddress problem seen mostly on
420 static const u64 fix_mac[] = {
421 0x0060000000000000ULL, 0x0060600000000000ULL,
422 0x0040600000000000ULL, 0x0000600000000000ULL,
423 0x0020600000000000ULL, 0x0060600000000000ULL,
424 0x0020600000000000ULL, 0x0060600000000000ULL,
425 0x0020600000000000ULL, 0x0060600000000000ULL,
426 0x0020600000000000ULL, 0x0060600000000000ULL,
427 0x0020600000000000ULL, 0x0060600000000000ULL,
428 0x0020600000000000ULL, 0x0060600000000000ULL,
429 0x0020600000000000ULL, 0x0060600000000000ULL,
430 0x0020600000000000ULL, 0x0060600000000000ULL,
431 0x0020600000000000ULL, 0x0060600000000000ULL,
432 0x0020600000000000ULL, 0x0060600000000000ULL,
433 0x0020600000000000ULL, 0x0000600000000000ULL,
434 0x0040600000000000ULL, 0x0060600000000000ULL,
438 MODULE_LICENSE("GPL");
439 MODULE_VERSION(DRV_VERSION);
442 /* Module Loadable parameters. */
443 S2IO_PARM_INT(tx_fifo_num, 1);
444 S2IO_PARM_INT(rx_ring_num, 1);
447 S2IO_PARM_INT(rx_ring_mode, 1);
448 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
449 S2IO_PARM_INT(rmac_pause_time, 0x100);
450 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
451 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
452 S2IO_PARM_INT(shared_splits, 0);
453 S2IO_PARM_INT(tmac_util_period, 5);
454 S2IO_PARM_INT(rmac_util_period, 5);
455 S2IO_PARM_INT(bimodal, 0);
456 S2IO_PARM_INT(l3l4hdr_size, 128);
457 /* Frequency of Rx desc syncs expressed as power of 2 */
458 S2IO_PARM_INT(rxsync_frequency, 3);
459 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
460 S2IO_PARM_INT(intr_type, 2);
461 /* Large receive offload feature */
462 S2IO_PARM_INT(lro, 0);
463 /* Max pkts to be aggregated by LRO at one time. If not specified,
464 * aggregation happens until we hit max IP pkt size(64K)
466 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
467 S2IO_PARM_INT(indicate_max_pkts, 0);
469 S2IO_PARM_INT(napi, 1);
470 S2IO_PARM_INT(ufo, 0);
471 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
473 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
474 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
475 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
476 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
477 static unsigned int rts_frm_len[MAX_RX_RINGS] =
478 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
480 module_param_array(tx_fifo_len, uint, NULL, 0);
481 module_param_array(rx_ring_sz, uint, NULL, 0);
482 module_param_array(rts_frm_len, uint, NULL, 0);
486 * This table lists all the devices that this driver supports.
488 static struct pci_device_id s2io_tbl[] __devinitdata = {
489 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
490 PCI_ANY_ID, PCI_ANY_ID},
491 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
492 PCI_ANY_ID, PCI_ANY_ID},
493 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
494 PCI_ANY_ID, PCI_ANY_ID},
495 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
496 PCI_ANY_ID, PCI_ANY_ID},
500 MODULE_DEVICE_TABLE(pci, s2io_tbl);
502 static struct pci_error_handlers s2io_err_handler = {
503 .error_detected = s2io_io_error_detected,
504 .slot_reset = s2io_io_slot_reset,
505 .resume = s2io_io_resume,
508 static struct pci_driver s2io_driver = {
510 .id_table = s2io_tbl,
511 .probe = s2io_init_nic,
512 .remove = __devexit_p(s2io_rem_nic),
513 .err_handler = &s2io_err_handler,
516 /* A simplifier macro used both by init and free shared_mem Fns(). */
517 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
520 * init_shared_mem - Allocation and Initialization of Memory
521 * @nic: Device private variable.
522 * Description: The function allocates all the memory areas shared
523 * between the NIC and the driver. This includes Tx descriptors,
524 * Rx descriptors and the statistics block.
527 static int init_shared_mem(struct s2io_nic *nic)
530 void *tmp_v_addr, *tmp_v_addr_next;
531 dma_addr_t tmp_p_addr, tmp_p_addr_next;
532 struct RxD_block *pre_rxd_blk = NULL;
534 int lst_size, lst_per_page;
535 struct net_device *dev = nic->dev;
539 struct mac_info *mac_control;
540 struct config_param *config;
541 unsigned long long mem_allocated = 0;
543 mac_control = &nic->mac_control;
544 config = &nic->config;
547 /* Allocation and initialization of TXDLs in FIOFs */
549 for (i = 0; i < config->tx_fifo_num; i++) {
550 size += config->tx_cfg[i].fifo_len;
552 if (size > MAX_AVAILABLE_TXDS) {
553 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
554 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
558 lst_size = (sizeof(struct TxD) * config->max_txds);
559 lst_per_page = PAGE_SIZE / lst_size;
561 for (i = 0; i < config->tx_fifo_num; i++) {
562 int fifo_len = config->tx_cfg[i].fifo_len;
563 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
564 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
566 if (!mac_control->fifos[i].list_info) {
568 "Malloc failed for list_info\n");
571 mem_allocated += list_holder_size;
572 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
574 for (i = 0; i < config->tx_fifo_num; i++) {
575 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
577 mac_control->fifos[i].tx_curr_put_info.offset = 0;
578 mac_control->fifos[i].tx_curr_put_info.fifo_len =
579 config->tx_cfg[i].fifo_len - 1;
580 mac_control->fifos[i].tx_curr_get_info.offset = 0;
581 mac_control->fifos[i].tx_curr_get_info.fifo_len =
582 config->tx_cfg[i].fifo_len - 1;
583 mac_control->fifos[i].fifo_no = i;
584 mac_control->fifos[i].nic = nic;
585 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
587 for (j = 0; j < page_num; j++) {
591 tmp_v = pci_alloc_consistent(nic->pdev,
595 "pci_alloc_consistent ");
596 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
599 /* If we got a zero DMA address(can happen on
600 * certain platforms like PPC), reallocate.
601 * Store virtual address of page we don't want,
605 mac_control->zerodma_virt_addr = tmp_v;
607 "%s: Zero DMA address for TxDL. ", dev->name);
609 "Virtual address %p\n", tmp_v);
610 tmp_v = pci_alloc_consistent(nic->pdev,
614 "pci_alloc_consistent ");
615 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
618 mem_allocated += PAGE_SIZE;
620 while (k < lst_per_page) {
621 int l = (j * lst_per_page) + k;
622 if (l == config->tx_cfg[i].fifo_len)
624 mac_control->fifos[i].list_info[l].list_virt_addr =
625 tmp_v + (k * lst_size);
626 mac_control->fifos[i].list_info[l].list_phy_addr =
627 tmp_p + (k * lst_size);
633 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
634 if (!nic->ufo_in_band_v)
636 mem_allocated += (size * sizeof(u64));
638 /* Allocation and initialization of RXDs in Rings */
640 for (i = 0; i < config->rx_ring_num; i++) {
641 if (config->rx_cfg[i].num_rxd %
642 (rxd_count[nic->rxd_mode] + 1)) {
643 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
644 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
646 DBG_PRINT(ERR_DBG, "RxDs per Block");
649 size += config->rx_cfg[i].num_rxd;
650 mac_control->rings[i].block_count =
651 config->rx_cfg[i].num_rxd /
652 (rxd_count[nic->rxd_mode] + 1 );
653 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
654 mac_control->rings[i].block_count;
656 if (nic->rxd_mode == RXD_MODE_1)
657 size = (size * (sizeof(struct RxD1)));
659 size = (size * (sizeof(struct RxD3)));
661 for (i = 0; i < config->rx_ring_num; i++) {
662 mac_control->rings[i].rx_curr_get_info.block_index = 0;
663 mac_control->rings[i].rx_curr_get_info.offset = 0;
664 mac_control->rings[i].rx_curr_get_info.ring_len =
665 config->rx_cfg[i].num_rxd - 1;
666 mac_control->rings[i].rx_curr_put_info.block_index = 0;
667 mac_control->rings[i].rx_curr_put_info.offset = 0;
668 mac_control->rings[i].rx_curr_put_info.ring_len =
669 config->rx_cfg[i].num_rxd - 1;
670 mac_control->rings[i].nic = nic;
671 mac_control->rings[i].ring_no = i;
673 blk_cnt = config->rx_cfg[i].num_rxd /
674 (rxd_count[nic->rxd_mode] + 1);
675 /* Allocating all the Rx blocks */
676 for (j = 0; j < blk_cnt; j++) {
677 struct rx_block_info *rx_blocks;
680 rx_blocks = &mac_control->rings[i].rx_blocks[j];
681 size = SIZE_OF_BLOCK; //size is always page size
682 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
684 if (tmp_v_addr == NULL) {
686 * In case of failure, free_shared_mem()
687 * is called, which should free any
688 * memory that was alloced till the
691 rx_blocks->block_virt_addr = tmp_v_addr;
694 mem_allocated += size;
695 memset(tmp_v_addr, 0, size);
696 rx_blocks->block_virt_addr = tmp_v_addr;
697 rx_blocks->block_dma_addr = tmp_p_addr;
698 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
699 rxd_count[nic->rxd_mode],
701 if (!rx_blocks->rxds)
704 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
705 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
706 rx_blocks->rxds[l].virt_addr =
707 rx_blocks->block_virt_addr +
708 (rxd_size[nic->rxd_mode] * l);
709 rx_blocks->rxds[l].dma_addr =
710 rx_blocks->block_dma_addr +
711 (rxd_size[nic->rxd_mode] * l);
714 /* Interlinking all Rx Blocks */
715 for (j = 0; j < blk_cnt; j++) {
717 mac_control->rings[i].rx_blocks[j].block_virt_addr;
719 mac_control->rings[i].rx_blocks[(j + 1) %
720 blk_cnt].block_virt_addr;
722 mac_control->rings[i].rx_blocks[j].block_dma_addr;
724 mac_control->rings[i].rx_blocks[(j + 1) %
725 blk_cnt].block_dma_addr;
727 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
728 pre_rxd_blk->reserved_2_pNext_RxD_block =
729 (unsigned long) tmp_v_addr_next;
730 pre_rxd_blk->pNext_RxD_Blk_physical =
731 (u64) tmp_p_addr_next;
734 if (nic->rxd_mode == RXD_MODE_3B) {
736 * Allocation of Storages for buffer addresses in 2BUFF mode
737 * and the buffers as well.
739 for (i = 0; i < config->rx_ring_num; i++) {
740 blk_cnt = config->rx_cfg[i].num_rxd /
741 (rxd_count[nic->rxd_mode]+ 1);
742 mac_control->rings[i].ba =
743 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
745 if (!mac_control->rings[i].ba)
747 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
748 for (j = 0; j < blk_cnt; j++) {
750 mac_control->rings[i].ba[j] =
751 kmalloc((sizeof(struct buffAdd) *
752 (rxd_count[nic->rxd_mode] + 1)),
754 if (!mac_control->rings[i].ba[j])
756 mem_allocated += (sizeof(struct buffAdd) * \
757 (rxd_count[nic->rxd_mode] + 1));
758 while (k != rxd_count[nic->rxd_mode]) {
759 ba = &mac_control->rings[i].ba[j][k];
761 ba->ba_0_org = (void *) kmalloc
762 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
766 (BUF0_LEN + ALIGN_SIZE);
767 tmp = (unsigned long)ba->ba_0_org;
769 tmp &= ~((unsigned long) ALIGN_SIZE);
770 ba->ba_0 = (void *) tmp;
772 ba->ba_1_org = (void *) kmalloc
773 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
777 += (BUF1_LEN + ALIGN_SIZE);
778 tmp = (unsigned long) ba->ba_1_org;
780 tmp &= ~((unsigned long) ALIGN_SIZE);
781 ba->ba_1 = (void *) tmp;
788 /* Allocation and initialization of Statistics block */
789 size = sizeof(struct stat_block);
790 mac_control->stats_mem = pci_alloc_consistent
791 (nic->pdev, size, &mac_control->stats_mem_phy);
793 if (!mac_control->stats_mem) {
795 * In case of failure, free_shared_mem() is called, which
796 * should free any memory that was alloced till the
801 mem_allocated += size;
802 mac_control->stats_mem_sz = size;
804 tmp_v_addr = mac_control->stats_mem;
805 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
806 memset(tmp_v_addr, 0, size);
807 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
808 (unsigned long long) tmp_p_addr);
809 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
814 * free_shared_mem - Free the allocated Memory
815 * @nic: Device private variable.
816 * Description: This function is to free all memory locations allocated by
817 * the init_shared_mem() function and return it to the kernel.
820 static void free_shared_mem(struct s2io_nic *nic)
822 int i, j, blk_cnt, size;
825 dma_addr_t tmp_p_addr;
826 struct mac_info *mac_control;
827 struct config_param *config;
828 int lst_size, lst_per_page;
829 struct net_device *dev;
837 mac_control = &nic->mac_control;
838 config = &nic->config;
840 lst_size = (sizeof(struct TxD) * config->max_txds);
841 lst_per_page = PAGE_SIZE / lst_size;
843 for (i = 0; i < config->tx_fifo_num; i++) {
844 ufo_size += config->tx_cfg[i].fifo_len;
845 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
847 for (j = 0; j < page_num; j++) {
848 int mem_blks = (j * lst_per_page);
849 if (!mac_control->fifos[i].list_info)
851 if (!mac_control->fifos[i].list_info[mem_blks].
854 pci_free_consistent(nic->pdev, PAGE_SIZE,
855 mac_control->fifos[i].
858 mac_control->fifos[i].
861 nic->mac_control.stats_info->sw_stat.mem_freed
864 /* If we got a zero DMA address during allocation,
867 if (mac_control->zerodma_virt_addr) {
868 pci_free_consistent(nic->pdev, PAGE_SIZE,
869 mac_control->zerodma_virt_addr,
872 "%s: Freeing TxDL with zero DMA addr. ",
874 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
875 mac_control->zerodma_virt_addr);
876 nic->mac_control.stats_info->sw_stat.mem_freed
879 kfree(mac_control->fifos[i].list_info);
880 nic->mac_control.stats_info->sw_stat.mem_freed +=
881 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
884 size = SIZE_OF_BLOCK;
885 for (i = 0; i < config->rx_ring_num; i++) {
886 blk_cnt = mac_control->rings[i].block_count;
887 for (j = 0; j < blk_cnt; j++) {
888 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
890 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
892 if (tmp_v_addr == NULL)
894 pci_free_consistent(nic->pdev, size,
895 tmp_v_addr, tmp_p_addr);
896 nic->mac_control.stats_info->sw_stat.mem_freed += size;
897 kfree(mac_control->rings[i].rx_blocks[j].rxds);
898 nic->mac_control.stats_info->sw_stat.mem_freed +=
899 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
903 if (nic->rxd_mode == RXD_MODE_3B) {
904 /* Freeing buffer storage addresses in 2BUFF mode. */
905 for (i = 0; i < config->rx_ring_num; i++) {
906 blk_cnt = config->rx_cfg[i].num_rxd /
907 (rxd_count[nic->rxd_mode] + 1);
908 for (j = 0; j < blk_cnt; j++) {
910 if (!mac_control->rings[i].ba[j])
912 while (k != rxd_count[nic->rxd_mode]) {
914 &mac_control->rings[i].ba[j][k];
916 nic->mac_control.stats_info->sw_stat.\
917 mem_freed += (BUF0_LEN + ALIGN_SIZE);
919 nic->mac_control.stats_info->sw_stat.\
920 mem_freed += (BUF1_LEN + ALIGN_SIZE);
923 kfree(mac_control->rings[i].ba[j]);
924 nic->mac_control.stats_info->sw_stat.mem_freed +=
925 (sizeof(struct buffAdd) *
926 (rxd_count[nic->rxd_mode] + 1));
928 kfree(mac_control->rings[i].ba);
929 nic->mac_control.stats_info->sw_stat.mem_freed +=
930 (sizeof(struct buffAdd *) * blk_cnt);
934 if (mac_control->stats_mem) {
935 pci_free_consistent(nic->pdev,
936 mac_control->stats_mem_sz,
937 mac_control->stats_mem,
938 mac_control->stats_mem_phy);
939 nic->mac_control.stats_info->sw_stat.mem_freed +=
940 mac_control->stats_mem_sz;
942 if (nic->ufo_in_band_v) {
943 kfree(nic->ufo_in_band_v);
944 nic->mac_control.stats_info->sw_stat.mem_freed
945 += (ufo_size * sizeof(u64));
950 * s2io_verify_pci_mode -
953 static int s2io_verify_pci_mode(struct s2io_nic *nic)
955 struct XENA_dev_config __iomem *bar0 = nic->bar0;
956 register u64 val64 = 0;
959 val64 = readq(&bar0->pci_mode);
960 mode = (u8)GET_PCI_MODE(val64);
962 if ( val64 & PCI_MODE_UNKNOWN_MODE)
963 return -1; /* Unknown PCI mode */
967 #define NEC_VENID 0x1033
968 #define NEC_DEVID 0x0125
969 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
971 struct pci_dev *tdev = NULL;
972 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
973 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
974 if (tdev->bus == s2io_pdev->bus->parent)
982 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
984 * s2io_print_pci_mode -
986 static int s2io_print_pci_mode(struct s2io_nic *nic)
988 struct XENA_dev_config __iomem *bar0 = nic->bar0;
989 register u64 val64 = 0;
991 struct config_param *config = &nic->config;
993 val64 = readq(&bar0->pci_mode);
994 mode = (u8)GET_PCI_MODE(val64);
996 if ( val64 & PCI_MODE_UNKNOWN_MODE)
997 return -1; /* Unknown PCI mode */
999 config->bus_speed = bus_speed[mode];
1001 if (s2io_on_nec_bridge(nic->pdev)) {
1002 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1007 if (val64 & PCI_MODE_32_BITS) {
1008 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1010 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1014 case PCI_MODE_PCI_33:
1015 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1017 case PCI_MODE_PCI_66:
1018 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1020 case PCI_MODE_PCIX_M1_66:
1021 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1023 case PCI_MODE_PCIX_M1_100:
1024 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1026 case PCI_MODE_PCIX_M1_133:
1027 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1029 case PCI_MODE_PCIX_M2_66:
1030 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1032 case PCI_MODE_PCIX_M2_100:
1033 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1035 case PCI_MODE_PCIX_M2_133:
1036 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1039 return -1; /* Unsupported bus speed */
1046 * init_nic - Initialization of hardware
1047 * @nic: device peivate variable
1048 * Description: The function sequentially configures every block
1049 * of the H/W from their reset values.
1050 * Return Value: SUCCESS on success and
1051 * '-1' on failure (endian settings incorrect).
1054 static int init_nic(struct s2io_nic *nic)
1056 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1057 struct net_device *dev = nic->dev;
1058 register u64 val64 = 0;
1062 struct mac_info *mac_control;
1063 struct config_param *config;
1065 unsigned long long mem_share;
1068 mac_control = &nic->mac_control;
1069 config = &nic->config;
1071 /* to set the swapper controle on the card */
1072 if(s2io_set_swapper(nic)) {
1073 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1078 * Herc requires EOI to be removed from reset before XGXS, so..
1080 if (nic->device_type & XFRAME_II_DEVICE) {
1081 val64 = 0xA500000000ULL;
1082 writeq(val64, &bar0->sw_reset);
1084 val64 = readq(&bar0->sw_reset);
1087 /* Remove XGXS from reset state */
1089 writeq(val64, &bar0->sw_reset);
1091 val64 = readq(&bar0->sw_reset);
1093 /* Enable Receiving broadcasts */
1094 add = &bar0->mac_cfg;
1095 val64 = readq(&bar0->mac_cfg);
1096 val64 |= MAC_RMAC_BCAST_ENABLE;
1097 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1098 writel((u32) val64, add);
1099 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1100 writel((u32) (val64 >> 32), (add + 4));
1102 /* Read registers in all blocks */
1103 val64 = readq(&bar0->mac_int_mask);
1104 val64 = readq(&bar0->mc_int_mask);
1105 val64 = readq(&bar0->xgxs_int_mask);
1109 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1111 if (nic->device_type & XFRAME_II_DEVICE) {
1112 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1113 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1114 &bar0->dtx_control, UF);
1116 msleep(1); /* Necessary!! */
1120 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1121 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1122 &bar0->dtx_control, UF);
1123 val64 = readq(&bar0->dtx_control);
1128 /* Tx DMA Initialization */
1130 writeq(val64, &bar0->tx_fifo_partition_0);
1131 writeq(val64, &bar0->tx_fifo_partition_1);
1132 writeq(val64, &bar0->tx_fifo_partition_2);
1133 writeq(val64, &bar0->tx_fifo_partition_3);
1136 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1138 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1139 13) | vBIT(config->tx_cfg[i].fifo_priority,
1142 if (i == (config->tx_fifo_num - 1)) {
1149 writeq(val64, &bar0->tx_fifo_partition_0);
1153 writeq(val64, &bar0->tx_fifo_partition_1);
1157 writeq(val64, &bar0->tx_fifo_partition_2);
1161 writeq(val64, &bar0->tx_fifo_partition_3);
1167 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1168 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1170 if ((nic->device_type == XFRAME_I_DEVICE) &&
1171 (nic->pdev->revision < 4))
1172 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1174 val64 = readq(&bar0->tx_fifo_partition_0);
1175 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1176 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1179 * Initialization of Tx_PA_CONFIG register to ignore packet
1180 * integrity checking.
1182 val64 = readq(&bar0->tx_pa_cfg);
1183 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1184 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1185 writeq(val64, &bar0->tx_pa_cfg);
1187 /* Rx DMA intialization. */
1189 for (i = 0; i < config->rx_ring_num; i++) {
1191 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1194 writeq(val64, &bar0->rx_queue_priority);
1197 * Allocating equal share of memory to all the
1201 if (nic->device_type & XFRAME_II_DEVICE)
1206 for (i = 0; i < config->rx_ring_num; i++) {
1209 mem_share = (mem_size / config->rx_ring_num +
1210 mem_size % config->rx_ring_num);
1211 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1214 mem_share = (mem_size / config->rx_ring_num);
1215 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1218 mem_share = (mem_size / config->rx_ring_num);
1219 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1222 mem_share = (mem_size / config->rx_ring_num);
1223 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1226 mem_share = (mem_size / config->rx_ring_num);
1227 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1230 mem_share = (mem_size / config->rx_ring_num);
1231 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1234 mem_share = (mem_size / config->rx_ring_num);
1235 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1238 mem_share = (mem_size / config->rx_ring_num);
1239 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1243 writeq(val64, &bar0->rx_queue_cfg);
1246 * Filling Tx round robin registers
1247 * as per the number of FIFOs
1249 switch (config->tx_fifo_num) {
1251 val64 = 0x0000000000000000ULL;
1252 writeq(val64, &bar0->tx_w_round_robin_0);
1253 writeq(val64, &bar0->tx_w_round_robin_1);
1254 writeq(val64, &bar0->tx_w_round_robin_2);
1255 writeq(val64, &bar0->tx_w_round_robin_3);
1256 writeq(val64, &bar0->tx_w_round_robin_4);
1259 val64 = 0x0000010000010000ULL;
1260 writeq(val64, &bar0->tx_w_round_robin_0);
1261 val64 = 0x0100000100000100ULL;
1262 writeq(val64, &bar0->tx_w_round_robin_1);
1263 val64 = 0x0001000001000001ULL;
1264 writeq(val64, &bar0->tx_w_round_robin_2);
1265 val64 = 0x0000010000010000ULL;
1266 writeq(val64, &bar0->tx_w_round_robin_3);
1267 val64 = 0x0100000000000000ULL;
1268 writeq(val64, &bar0->tx_w_round_robin_4);
1271 val64 = 0x0001000102000001ULL;
1272 writeq(val64, &bar0->tx_w_round_robin_0);
1273 val64 = 0x0001020000010001ULL;
1274 writeq(val64, &bar0->tx_w_round_robin_1);
1275 val64 = 0x0200000100010200ULL;
1276 writeq(val64, &bar0->tx_w_round_robin_2);
1277 val64 = 0x0001000102000001ULL;
1278 writeq(val64, &bar0->tx_w_round_robin_3);
1279 val64 = 0x0001020000000000ULL;
1280 writeq(val64, &bar0->tx_w_round_robin_4);
1283 val64 = 0x0001020300010200ULL;
1284 writeq(val64, &bar0->tx_w_round_robin_0);
1285 val64 = 0x0100000102030001ULL;
1286 writeq(val64, &bar0->tx_w_round_robin_1);
1287 val64 = 0x0200010000010203ULL;
1288 writeq(val64, &bar0->tx_w_round_robin_2);
1289 val64 = 0x0001020001000001ULL;
1290 writeq(val64, &bar0->tx_w_round_robin_3);
1291 val64 = 0x0203000100000000ULL;
1292 writeq(val64, &bar0->tx_w_round_robin_4);
1295 val64 = 0x0001000203000102ULL;
1296 writeq(val64, &bar0->tx_w_round_robin_0);
1297 val64 = 0x0001020001030004ULL;
1298 writeq(val64, &bar0->tx_w_round_robin_1);
1299 val64 = 0x0001000203000102ULL;
1300 writeq(val64, &bar0->tx_w_round_robin_2);
1301 val64 = 0x0001020001030004ULL;
1302 writeq(val64, &bar0->tx_w_round_robin_3);
1303 val64 = 0x0001000000000000ULL;
1304 writeq(val64, &bar0->tx_w_round_robin_4);
1307 val64 = 0x0001020304000102ULL;
1308 writeq(val64, &bar0->tx_w_round_robin_0);
1309 val64 = 0x0304050001020001ULL;
1310 writeq(val64, &bar0->tx_w_round_robin_1);
1311 val64 = 0x0203000100000102ULL;
1312 writeq(val64, &bar0->tx_w_round_robin_2);
1313 val64 = 0x0304000102030405ULL;
1314 writeq(val64, &bar0->tx_w_round_robin_3);
1315 val64 = 0x0001000200000000ULL;
1316 writeq(val64, &bar0->tx_w_round_robin_4);
1319 val64 = 0x0001020001020300ULL;
1320 writeq(val64, &bar0->tx_w_round_robin_0);
1321 val64 = 0x0102030400010203ULL;
1322 writeq(val64, &bar0->tx_w_round_robin_1);
1323 val64 = 0x0405060001020001ULL;
1324 writeq(val64, &bar0->tx_w_round_robin_2);
1325 val64 = 0x0304050000010200ULL;
1326 writeq(val64, &bar0->tx_w_round_robin_3);
1327 val64 = 0x0102030000000000ULL;
1328 writeq(val64, &bar0->tx_w_round_robin_4);
1331 val64 = 0x0001020300040105ULL;
1332 writeq(val64, &bar0->tx_w_round_robin_0);
1333 val64 = 0x0200030106000204ULL;
1334 writeq(val64, &bar0->tx_w_round_robin_1);
1335 val64 = 0x0103000502010007ULL;
1336 writeq(val64, &bar0->tx_w_round_robin_2);
1337 val64 = 0x0304010002060500ULL;
1338 writeq(val64, &bar0->tx_w_round_robin_3);
1339 val64 = 0x0103020400000000ULL;
1340 writeq(val64, &bar0->tx_w_round_robin_4);
1344 /* Enable all configured Tx FIFO partitions */
1345 val64 = readq(&bar0->tx_fifo_partition_0);
1346 val64 |= (TX_FIFO_PARTITION_EN);
1347 writeq(val64, &bar0->tx_fifo_partition_0);
1349 /* Filling the Rx round robin registers as per the
1350 * number of Rings and steering based on QoS.
1352 switch (config->rx_ring_num) {
1354 val64 = 0x8080808080808080ULL;
1355 writeq(val64, &bar0->rts_qos_steering);
1358 val64 = 0x0000010000010000ULL;
1359 writeq(val64, &bar0->rx_w_round_robin_0);
1360 val64 = 0x0100000100000100ULL;
1361 writeq(val64, &bar0->rx_w_round_robin_1);
1362 val64 = 0x0001000001000001ULL;
1363 writeq(val64, &bar0->rx_w_round_robin_2);
1364 val64 = 0x0000010000010000ULL;
1365 writeq(val64, &bar0->rx_w_round_robin_3);
1366 val64 = 0x0100000000000000ULL;
1367 writeq(val64, &bar0->rx_w_round_robin_4);
1369 val64 = 0x8080808040404040ULL;
1370 writeq(val64, &bar0->rts_qos_steering);
1373 val64 = 0x0001000102000001ULL;
1374 writeq(val64, &bar0->rx_w_round_robin_0);
1375 val64 = 0x0001020000010001ULL;
1376 writeq(val64, &bar0->rx_w_round_robin_1);
1377 val64 = 0x0200000100010200ULL;
1378 writeq(val64, &bar0->rx_w_round_robin_2);
1379 val64 = 0x0001000102000001ULL;
1380 writeq(val64, &bar0->rx_w_round_robin_3);
1381 val64 = 0x0001020000000000ULL;
1382 writeq(val64, &bar0->rx_w_round_robin_4);
1384 val64 = 0x8080804040402020ULL;
1385 writeq(val64, &bar0->rts_qos_steering);
1388 val64 = 0x0001020300010200ULL;
1389 writeq(val64, &bar0->rx_w_round_robin_0);
1390 val64 = 0x0100000102030001ULL;
1391 writeq(val64, &bar0->rx_w_round_robin_1);
1392 val64 = 0x0200010000010203ULL;
1393 writeq(val64, &bar0->rx_w_round_robin_2);
1394 val64 = 0x0001020001000001ULL;
1395 writeq(val64, &bar0->rx_w_round_robin_3);
1396 val64 = 0x0203000100000000ULL;
1397 writeq(val64, &bar0->rx_w_round_robin_4);
1399 val64 = 0x8080404020201010ULL;
1400 writeq(val64, &bar0->rts_qos_steering);
1403 val64 = 0x0001000203000102ULL;
1404 writeq(val64, &bar0->rx_w_round_robin_0);
1405 val64 = 0x0001020001030004ULL;
1406 writeq(val64, &bar0->rx_w_round_robin_1);
1407 val64 = 0x0001000203000102ULL;
1408 writeq(val64, &bar0->rx_w_round_robin_2);
1409 val64 = 0x0001020001030004ULL;
1410 writeq(val64, &bar0->rx_w_round_robin_3);
1411 val64 = 0x0001000000000000ULL;
1412 writeq(val64, &bar0->rx_w_round_robin_4);
1414 val64 = 0x8080404020201008ULL;
1415 writeq(val64, &bar0->rts_qos_steering);
1418 val64 = 0x0001020304000102ULL;
1419 writeq(val64, &bar0->rx_w_round_robin_0);
1420 val64 = 0x0304050001020001ULL;
1421 writeq(val64, &bar0->rx_w_round_robin_1);
1422 val64 = 0x0203000100000102ULL;
1423 writeq(val64, &bar0->rx_w_round_robin_2);
1424 val64 = 0x0304000102030405ULL;
1425 writeq(val64, &bar0->rx_w_round_robin_3);
1426 val64 = 0x0001000200000000ULL;
1427 writeq(val64, &bar0->rx_w_round_robin_4);
1429 val64 = 0x8080404020100804ULL;
1430 writeq(val64, &bar0->rts_qos_steering);
1433 val64 = 0x0001020001020300ULL;
1434 writeq(val64, &bar0->rx_w_round_robin_0);
1435 val64 = 0x0102030400010203ULL;
1436 writeq(val64, &bar0->rx_w_round_robin_1);
1437 val64 = 0x0405060001020001ULL;
1438 writeq(val64, &bar0->rx_w_round_robin_2);
1439 val64 = 0x0304050000010200ULL;
1440 writeq(val64, &bar0->rx_w_round_robin_3);
1441 val64 = 0x0102030000000000ULL;
1442 writeq(val64, &bar0->rx_w_round_robin_4);
1444 val64 = 0x8080402010080402ULL;
1445 writeq(val64, &bar0->rts_qos_steering);
1448 val64 = 0x0001020300040105ULL;
1449 writeq(val64, &bar0->rx_w_round_robin_0);
1450 val64 = 0x0200030106000204ULL;
1451 writeq(val64, &bar0->rx_w_round_robin_1);
1452 val64 = 0x0103000502010007ULL;
1453 writeq(val64, &bar0->rx_w_round_robin_2);
1454 val64 = 0x0304010002060500ULL;
1455 writeq(val64, &bar0->rx_w_round_robin_3);
1456 val64 = 0x0103020400000000ULL;
1457 writeq(val64, &bar0->rx_w_round_robin_4);
1459 val64 = 0x8040201008040201ULL;
1460 writeq(val64, &bar0->rts_qos_steering);
1466 for (i = 0; i < 8; i++)
1467 writeq(val64, &bar0->rts_frm_len_n[i]);
1469 /* Set the default rts frame length for the rings configured */
1470 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1471 for (i = 0 ; i < config->rx_ring_num ; i++)
1472 writeq(val64, &bar0->rts_frm_len_n[i]);
1474 /* Set the frame length for the configured rings
1475 * desired by the user
1477 for (i = 0; i < config->rx_ring_num; i++) {
1478 /* If rts_frm_len[i] == 0 then it is assumed that user not
1479 * specified frame length steering.
1480 * If the user provides the frame length then program
1481 * the rts_frm_len register for those values or else
1482 * leave it as it is.
1484 if (rts_frm_len[i] != 0) {
1485 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1486 &bar0->rts_frm_len_n[i]);
1490 /* Disable differentiated services steering logic */
1491 for (i = 0; i < 64; i++) {
1492 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1493 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1495 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1500 /* Program statistics memory */
1501 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1503 if (nic->device_type == XFRAME_II_DEVICE) {
1504 val64 = STAT_BC(0x320);
1505 writeq(val64, &bar0->stat_byte_cnt);
1509 * Initializing the sampling rate for the device to calculate the
1510 * bandwidth utilization.
1512 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1513 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1514 writeq(val64, &bar0->mac_link_util);
1518 * Initializing the Transmit and Receive Traffic Interrupt
1522 * TTI Initialization. Default Tx timer gets us about
1523 * 250 interrupts per sec. Continuous interrupts are enabled
1526 if (nic->device_type == XFRAME_II_DEVICE) {
1527 int count = (nic->config.bus_speed * 125)/2;
1528 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1531 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1533 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1534 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1535 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1536 if (use_continuous_tx_intrs)
1537 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1538 writeq(val64, &bar0->tti_data1_mem);
1540 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1541 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1542 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1543 writeq(val64, &bar0->tti_data2_mem);
1545 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1546 writeq(val64, &bar0->tti_command_mem);
1549 * Once the operation completes, the Strobe bit of the command
1550 * register will be reset. We poll for this particular condition
1551 * We wait for a maximum of 500ms for the operation to complete,
1552 * if it's not complete by then we return error.
1556 val64 = readq(&bar0->tti_command_mem);
1557 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1561 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1569 if (nic->config.bimodal) {
1571 for (k = 0; k < config->rx_ring_num; k++) {
1572 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1573 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1574 writeq(val64, &bar0->tti_command_mem);
1577 * Once the operation completes, the Strobe bit of the command
1578 * register will be reset. We poll for this particular condition
1579 * We wait for a maximum of 500ms for the operation to complete,
1580 * if it's not complete by then we return error.
1584 val64 = readq(&bar0->tti_command_mem);
1585 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1590 "%s: TTI init Failed\n",
1600 /* RTI Initialization */
1601 if (nic->device_type == XFRAME_II_DEVICE) {
1603 * Programmed to generate Apprx 500 Intrs per
1606 int count = (nic->config.bus_speed * 125)/4;
1607 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1609 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1611 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1612 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1613 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1615 writeq(val64, &bar0->rti_data1_mem);
1617 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1618 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1619 if (nic->config.intr_type == MSI_X)
1620 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1621 RTI_DATA2_MEM_RX_UFC_D(0x40));
1623 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1624 RTI_DATA2_MEM_RX_UFC_D(0x80));
1625 writeq(val64, &bar0->rti_data2_mem);
1627 for (i = 0; i < config->rx_ring_num; i++) {
1628 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1629 | RTI_CMD_MEM_OFFSET(i);
1630 writeq(val64, &bar0->rti_command_mem);
1633 * Once the operation completes, the Strobe bit of the
1634 * command register will be reset. We poll for this
1635 * particular condition. We wait for a maximum of 500ms
1636 * for the operation to complete, if it's not complete
1637 * by then we return error.
1641 val64 = readq(&bar0->rti_command_mem);
1642 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1646 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1657 * Initializing proper values as Pause threshold into all
1658 * the 8 Queues on Rx side.
1660 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1661 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1663 /* Disable RMAC PAD STRIPPING */
1664 add = &bar0->mac_cfg;
1665 val64 = readq(&bar0->mac_cfg);
1666 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1667 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1668 writel((u32) (val64), add);
1669 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1670 writel((u32) (val64 >> 32), (add + 4));
1671 val64 = readq(&bar0->mac_cfg);
1673 /* Enable FCS stripping by adapter */
1674 add = &bar0->mac_cfg;
1675 val64 = readq(&bar0->mac_cfg);
1676 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1677 if (nic->device_type == XFRAME_II_DEVICE)
1678 writeq(val64, &bar0->mac_cfg);
1680 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1681 writel((u32) (val64), add);
1682 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1683 writel((u32) (val64 >> 32), (add + 4));
1687 * Set the time value to be inserted in the pause frame
1688 * generated by xena.
1690 val64 = readq(&bar0->rmac_pause_cfg);
1691 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1692 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1693 writeq(val64, &bar0->rmac_pause_cfg);
1696 * Set the Threshold Limit for Generating the pause frame
1697 * If the amount of data in any Queue exceeds ratio of
1698 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1699 * pause frame is generated
1702 for (i = 0; i < 4; i++) {
1704 (((u64) 0xFF00 | nic->mac_control.
1705 mc_pause_threshold_q0q3)
1708 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1711 for (i = 0; i < 4; i++) {
1713 (((u64) 0xFF00 | nic->mac_control.
1714 mc_pause_threshold_q4q7)
1717 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1720 * TxDMA will stop Read request if the number of read split has
1721 * exceeded the limit pointed by shared_splits
1723 val64 = readq(&bar0->pic_control);
1724 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1725 writeq(val64, &bar0->pic_control);
1727 if (nic->config.bus_speed == 266) {
1728 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1729 writeq(0x0, &bar0->read_retry_delay);
1730 writeq(0x0, &bar0->write_retry_delay);
1734 * Programming the Herc to split every write transaction
1735 * that does not start on an ADB to reduce disconnects.
1737 if (nic->device_type == XFRAME_II_DEVICE) {
1738 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1739 MISC_LINK_STABILITY_PRD(3);
1740 writeq(val64, &bar0->misc_control);
1741 val64 = readq(&bar0->pic_control2);
1742 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1743 writeq(val64, &bar0->pic_control2);
1745 if (strstr(nic->product_name, "CX4")) {
1746 val64 = TMAC_AVG_IPG(0x17);
1747 writeq(val64, &bar0->tmac_avg_ipg);
1752 #define LINK_UP_DOWN_INTERRUPT 1
1753 #define MAC_RMAC_ERR_TIMER 2
1755 static int s2io_link_fault_indication(struct s2io_nic *nic)
1757 if (nic->config.intr_type != INTA)
1758 return MAC_RMAC_ERR_TIMER;
1759 if (nic->device_type == XFRAME_II_DEVICE)
1760 return LINK_UP_DOWN_INTERRUPT;
1762 return MAC_RMAC_ERR_TIMER;
1766 * do_s2io_write_bits - update alarm bits in alarm register
1767 * @value: alarm bits
1768 * @flag: interrupt status
1769 * @addr: address value
1770 * Description: update alarm bits in alarm register
1774 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1778 temp64 = readq(addr);
1780 if(flag == ENABLE_INTRS)
1781 temp64 &= ~((u64) value);
1783 temp64 |= ((u64) value);
1784 writeq(temp64, addr);
1787 void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1789 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1790 register u64 gen_int_mask = 0;
1792 if (mask & TX_DMA_INTR) {
1794 gen_int_mask |= TXDMA_INT_M;
1796 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1797 TXDMA_PCC_INT | TXDMA_TTI_INT |
1798 TXDMA_LSO_INT | TXDMA_TPA_INT |
1799 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1801 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1802 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1803 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1804 &bar0->pfc_err_mask);
1806 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1807 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1808 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1810 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1811 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1812 PCC_N_SERR | PCC_6_COF_OV_ERR |
1813 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1814 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1815 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1817 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1818 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1820 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1821 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1822 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1823 flag, &bar0->lso_err_mask);
1825 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1826 flag, &bar0->tpa_err_mask);
1828 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1832 if (mask & TX_MAC_INTR) {
1833 gen_int_mask |= TXMAC_INT_M;
1834 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1835 &bar0->mac_int_mask);
1836 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1837 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1838 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1839 flag, &bar0->mac_tmac_err_mask);
1842 if (mask & TX_XGXS_INTR) {
1843 gen_int_mask |= TXXGXS_INT_M;
1844 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1845 &bar0->xgxs_int_mask);
1846 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1847 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1848 flag, &bar0->xgxs_txgxs_err_mask);
1851 if (mask & RX_DMA_INTR) {
1852 gen_int_mask |= RXDMA_INT_M;
1853 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1854 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1855 flag, &bar0->rxdma_int_mask);
1856 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1857 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1858 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1859 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1860 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1861 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1862 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1863 &bar0->prc_pcix_err_mask);
1864 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1865 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1866 &bar0->rpa_err_mask);
1867 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1868 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1869 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1870 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1871 flag, &bar0->rda_err_mask);
1872 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1873 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1874 flag, &bar0->rti_err_mask);
1877 if (mask & RX_MAC_INTR) {
1878 gen_int_mask |= RXMAC_INT_M;
1879 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1880 &bar0->mac_int_mask);
1881 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1882 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1883 RMAC_DOUBLE_ECC_ERR |
1884 RMAC_LINK_STATE_CHANGE_INT,
1885 flag, &bar0->mac_rmac_err_mask);
1888 if (mask & RX_XGXS_INTR)
1890 gen_int_mask |= RXXGXS_INT_M;
1891 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1892 &bar0->xgxs_int_mask);
1893 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1894 &bar0->xgxs_rxgxs_err_mask);
1897 if (mask & MC_INTR) {
1898 gen_int_mask |= MC_INT_M;
1899 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1900 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1901 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1902 &bar0->mc_err_mask);
1904 nic->general_int_mask = gen_int_mask;
1906 /* Remove this line when alarm interrupts are enabled */
1907 nic->general_int_mask = 0;
1910 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1911 * @nic: device private variable,
1912 * @mask: A mask indicating which Intr block must be modified and,
1913 * @flag: A flag indicating whether to enable or disable the Intrs.
1914 * Description: This function will either disable or enable the interrupts
1915 * depending on the flag argument. The mask argument can be used to
1916 * enable/disable any Intr block.
1917 * Return Value: NONE.
1920 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1922 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1923 register u64 temp64 = 0, intr_mask = 0;
1925 intr_mask = nic->general_int_mask;
1927 /* Top level interrupt classification */
1928 /* PIC Interrupts */
1929 if (mask & TX_PIC_INTR) {
1930 /* Enable PIC Intrs in the general intr mask register */
1931 intr_mask |= TXPIC_INT_M;
1932 if (flag == ENABLE_INTRS) {
1934 * If Hercules adapter enable GPIO otherwise
1935 * disable all PCIX, Flash, MDIO, IIC and GPIO
1936 * interrupts for now.
1939 if (s2io_link_fault_indication(nic) ==
1940 LINK_UP_DOWN_INTERRUPT ) {
1941 do_s2io_write_bits(PIC_INT_GPIO, flag,
1942 &bar0->pic_int_mask);
1943 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1944 &bar0->gpio_int_mask);
1946 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1947 } else if (flag == DISABLE_INTRS) {
1949 * Disable PIC Intrs in the general
1950 * intr mask register
1952 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1956 /* Tx traffic interrupts */
1957 if (mask & TX_TRAFFIC_INTR) {
1958 intr_mask |= TXTRAFFIC_INT_M;
1959 if (flag == ENABLE_INTRS) {
1961 * Enable all the Tx side interrupts
1962 * writing 0 Enables all 64 TX interrupt levels
1964 writeq(0x0, &bar0->tx_traffic_mask);
1965 } else if (flag == DISABLE_INTRS) {
1967 * Disable Tx Traffic Intrs in the general intr mask
1970 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1974 /* Rx traffic interrupts */
1975 if (mask & RX_TRAFFIC_INTR) {
1976 intr_mask |= RXTRAFFIC_INT_M;
1977 if (flag == ENABLE_INTRS) {
1978 /* writing 0 Enables all 8 RX interrupt levels */
1979 writeq(0x0, &bar0->rx_traffic_mask);
1980 } else if (flag == DISABLE_INTRS) {
1982 * Disable Rx Traffic Intrs in the general intr mask
1985 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1989 temp64 = readq(&bar0->general_int_mask);
1990 if (flag == ENABLE_INTRS)
1991 temp64 &= ~((u64) intr_mask);
1993 temp64 = DISABLE_ALL_INTRS;
1994 writeq(temp64, &bar0->general_int_mask);
1996 nic->general_int_mask = readq(&bar0->general_int_mask);
2000 * verify_pcc_quiescent- Checks for PCC quiescent state
2001 * Return: 1 If PCC is quiescence
2002 * 0 If PCC is not quiescence
2004 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2007 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2008 u64 val64 = readq(&bar0->adapter_status);
2010 herc = (sp->device_type == XFRAME_II_DEVICE);
2012 if (flag == FALSE) {
2013 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2014 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2017 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2021 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2022 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2023 ADAPTER_STATUS_RMAC_PCC_IDLE))
2026 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2027 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2035 * verify_xena_quiescence - Checks whether the H/W is ready
2036 * Description: Returns whether the H/W is ready to go or not. Depending
2037 * on whether adapter enable bit was written or not the comparison
2038 * differs and the calling function passes the input argument flag to
2040 * Return: 1 If xena is quiescence
2041 * 0 If Xena is not quiescence
2044 static int verify_xena_quiescence(struct s2io_nic *sp)
2047 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2048 u64 val64 = readq(&bar0->adapter_status);
2049 mode = s2io_verify_pci_mode(sp);
2051 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2052 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2055 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2056 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2059 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2060 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2063 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2064 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2067 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2068 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2071 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2072 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2075 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2076 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2079 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2080 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2085 * In PCI 33 mode, the P_PLL is not used, and therefore,
2086 * the the P_PLL_LOCK bit in the adapter_status register will
2089 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2090 sp->device_type == XFRAME_II_DEVICE && mode !=
2092 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2095 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2096 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2097 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2104 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2105 * @sp: Pointer to device specifc structure
2107 * New procedure to clear mac address reading problems on Alpha platforms
2111 static void fix_mac_address(struct s2io_nic * sp)
2113 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2117 while (fix_mac[i] != END_SIGN) {
2118 writeq(fix_mac[i++], &bar0->gpio_control);
2120 val64 = readq(&bar0->gpio_control);
2125 * start_nic - Turns the device on
2126 * @nic : device private variable.
2128 * This function actually turns the device on. Before this function is
2129 * called,all Registers are configured from their reset states
2130 * and shared memory is allocated but the NIC is still quiescent. On
2131 * calling this function, the device interrupts are cleared and the NIC is
2132 * literally switched on by writing into the adapter control register.
2134 * SUCCESS on success and -1 on failure.
2137 static int start_nic(struct s2io_nic *nic)
2139 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2140 struct net_device *dev = nic->dev;
2141 register u64 val64 = 0;
2143 struct mac_info *mac_control;
2144 struct config_param *config;
2146 mac_control = &nic->mac_control;
2147 config = &nic->config;
2149 /* PRC Initialization and configuration */
2150 for (i = 0; i < config->rx_ring_num; i++) {
2151 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2152 &bar0->prc_rxd0_n[i]);
2154 val64 = readq(&bar0->prc_ctrl_n[i]);
2155 if (nic->config.bimodal)
2156 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2157 if (nic->rxd_mode == RXD_MODE_1)
2158 val64 |= PRC_CTRL_RC_ENABLED;
2160 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2161 if (nic->device_type == XFRAME_II_DEVICE)
2162 val64 |= PRC_CTRL_GROUP_READS;
2163 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2164 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2165 writeq(val64, &bar0->prc_ctrl_n[i]);
2168 if (nic->rxd_mode == RXD_MODE_3B) {
2169 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2170 val64 = readq(&bar0->rx_pa_cfg);
2171 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2172 writeq(val64, &bar0->rx_pa_cfg);
2175 if (vlan_tag_strip == 0) {
2176 val64 = readq(&bar0->rx_pa_cfg);
2177 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2178 writeq(val64, &bar0->rx_pa_cfg);
2179 vlan_strip_flag = 0;
2183 * Enabling MC-RLDRAM. After enabling the device, we timeout
2184 * for around 100ms, which is approximately the time required
2185 * for the device to be ready for operation.
2187 val64 = readq(&bar0->mc_rldram_mrs);
2188 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2189 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2190 val64 = readq(&bar0->mc_rldram_mrs);
2192 msleep(100); /* Delay by around 100 ms. */
2194 /* Enabling ECC Protection. */
2195 val64 = readq(&bar0->adapter_control);
2196 val64 &= ~ADAPTER_ECC_EN;
2197 writeq(val64, &bar0->adapter_control);
2200 * Verify if the device is ready to be enabled, if so enable
2203 val64 = readq(&bar0->adapter_status);
2204 if (!verify_xena_quiescence(nic)) {
2205 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2206 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2207 (unsigned long long) val64);
2212 * With some switches, link might be already up at this point.
2213 * Because of this weird behavior, when we enable laser,
2214 * we may not get link. We need to handle this. We cannot
2215 * figure out which switch is misbehaving. So we are forced to
2216 * make a global change.
2219 /* Enabling Laser. */
2220 val64 = readq(&bar0->adapter_control);
2221 val64 |= ADAPTER_EOI_TX_ON;
2222 writeq(val64, &bar0->adapter_control);
2224 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2226 * Dont see link state interrupts initally on some switches,
2227 * so directly scheduling the link state task here.
2229 schedule_work(&nic->set_link_task);
2231 /* SXE-002: Initialize link and activity LED */
2232 subid = nic->pdev->subsystem_device;
2233 if (((subid & 0xFF) >= 0x07) &&
2234 (nic->device_type == XFRAME_I_DEVICE)) {
2235 val64 = readq(&bar0->gpio_control);
2236 val64 |= 0x0000800000000000ULL;
2237 writeq(val64, &bar0->gpio_control);
2238 val64 = 0x0411040400000000ULL;
2239 writeq(val64, (void __iomem *)bar0 + 0x2700);
2245 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2247 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2248 TxD *txdlp, int get_off)
2250 struct s2io_nic *nic = fifo_data->nic;
2251 struct sk_buff *skb;
2256 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2257 pci_unmap_single(nic->pdev, (dma_addr_t)
2258 txds->Buffer_Pointer, sizeof(u64),
2263 skb = (struct sk_buff *) ((unsigned long)
2264 txds->Host_Control);
2266 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2269 pci_unmap_single(nic->pdev, (dma_addr_t)
2270 txds->Buffer_Pointer,
2271 skb->len - skb->data_len,
2273 frg_cnt = skb_shinfo(skb)->nr_frags;
2276 for (j = 0; j < frg_cnt; j++, txds++) {
2277 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2278 if (!txds->Buffer_Pointer)
2280 pci_unmap_page(nic->pdev, (dma_addr_t)
2281 txds->Buffer_Pointer,
2282 frag->size, PCI_DMA_TODEVICE);
2285 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2290 * free_tx_buffers - Free all queued Tx buffers
2291 * @nic : device private variable.
2293 * Free all queued Tx buffers.
2294 * Return Value: void
2297 static void free_tx_buffers(struct s2io_nic *nic)
2299 struct net_device *dev = nic->dev;
2300 struct sk_buff *skb;
2303 struct mac_info *mac_control;
2304 struct config_param *config;
2307 mac_control = &nic->mac_control;
2308 config = &nic->config;
2310 for (i = 0; i < config->tx_fifo_num; i++) {
2311 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2312 txdp = (struct TxD *) \
2313 mac_control->fifos[i].list_info[j].list_virt_addr;
2314 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2316 nic->mac_control.stats_info->sw_stat.mem_freed
2323 "%s:forcibly freeing %d skbs on FIFO%d\n",
2325 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2326 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2331 * stop_nic - To stop the nic
2332 * @nic ; device private variable.
2334 * This function does exactly the opposite of what the start_nic()
2335 * function does. This function is called to stop the device.
2340 static void stop_nic(struct s2io_nic *nic)
2342 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2343 register u64 val64 = 0;
2345 struct mac_info *mac_control;
2346 struct config_param *config;
2348 mac_control = &nic->mac_control;
2349 config = &nic->config;
2351 /* Disable all interrupts */
2352 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2353 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2354 interruptible |= TX_PIC_INTR;
2355 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2357 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2358 val64 = readq(&bar0->adapter_control);
2359 val64 &= ~(ADAPTER_CNTL_EN);
2360 writeq(val64, &bar0->adapter_control);
2364 * fill_rx_buffers - Allocates the Rx side skbs
2365 * @nic: device private variable
2366 * @ring_no: ring number
2368 * The function allocates Rx side skbs and puts the physical
2369 * address of these buffers into the RxD buffer pointers, so that the NIC
2370 * can DMA the received frame into these locations.
2371 * The NIC supports 3 receive modes, viz
2373 * 2. three buffer and
2374 * 3. Five buffer modes.
2375 * Each mode defines how many fragments the received frame will be split
2376 * up into by the NIC. The frame is split into L3 header, L4 Header,
2377 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2378 * is split into 3 fragments. As of now only single buffer mode is
2381 * SUCCESS on success or an appropriate -ve value on failure.
2384 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2386 struct net_device *dev = nic->dev;
2387 struct sk_buff *skb;
2389 int off, off1, size, block_no, block_no1;
2392 struct mac_info *mac_control;
2393 struct config_param *config;
2396 unsigned long flags;
2397 struct RxD_t *first_rxdp = NULL;
2398 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2401 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
2403 mac_control = &nic->mac_control;
2404 config = &nic->config;
2405 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2406 atomic_read(&nic->rx_bufs_left[ring_no]);
2408 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2409 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2410 while (alloc_tab < alloc_cnt) {
2411 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2413 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2415 rxdp = mac_control->rings[ring_no].
2416 rx_blocks[block_no].rxds[off].virt_addr;
2418 if ((block_no == block_no1) && (off == off1) &&
2419 (rxdp->Host_Control)) {
2420 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2422 DBG_PRINT(INTR_DBG, " info equated\n");
2425 if (off && (off == rxd_count[nic->rxd_mode])) {
2426 mac_control->rings[ring_no].rx_curr_put_info.
2428 if (mac_control->rings[ring_no].rx_curr_put_info.
2429 block_index == mac_control->rings[ring_no].
2431 mac_control->rings[ring_no].rx_curr_put_info.
2433 block_no = mac_control->rings[ring_no].
2434 rx_curr_put_info.block_index;
2435 if (off == rxd_count[nic->rxd_mode])
2437 mac_control->rings[ring_no].rx_curr_put_info.
2439 rxdp = mac_control->rings[ring_no].
2440 rx_blocks[block_no].block_virt_addr;
2441 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2445 spin_lock_irqsave(&nic->put_lock, flags);
2446 mac_control->rings[ring_no].put_pos =
2447 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2448 spin_unlock_irqrestore(&nic->put_lock, flags);
2450 mac_control->rings[ring_no].put_pos =
2451 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2453 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2454 ((nic->rxd_mode == RXD_MODE_3B) &&
2455 (rxdp->Control_2 & BIT(0)))) {
2456 mac_control->rings[ring_no].rx_curr_put_info.
2460 /* calculate size of skb based on ring mode */
2461 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2462 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2463 if (nic->rxd_mode == RXD_MODE_1)
2464 size += NET_IP_ALIGN;
2466 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2469 skb = dev_alloc_skb(size);
2471 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2472 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2475 first_rxdp->Control_1 |= RXD_OWN_XENA;
2477 nic->mac_control.stats_info->sw_stat. \
2478 mem_alloc_fail_cnt++;
2481 nic->mac_control.stats_info->sw_stat.mem_allocated
2483 if (nic->rxd_mode == RXD_MODE_1) {
2484 /* 1 buffer mode - normal operation mode */
2485 rxdp1 = (struct RxD1*)rxdp;
2486 memset(rxdp, 0, sizeof(struct RxD1));
2487 skb_reserve(skb, NET_IP_ALIGN);
2488 rxdp1->Buffer0_ptr = pci_map_single
2489 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2490 PCI_DMA_FROMDEVICE);
2491 if( (rxdp1->Buffer0_ptr == 0) ||
2492 (rxdp1->Buffer0_ptr ==
2494 goto pci_map_failed;
2497 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2499 } else if (nic->rxd_mode == RXD_MODE_3B) {
2502 * 2 buffer mode provides 128
2503 * byte aligned receive buffers.
2506 rxdp3 = (struct RxD3*)rxdp;
2507 /* save buffer pointers to avoid frequent dma mapping */
2508 Buffer0_ptr = rxdp3->Buffer0_ptr;
2509 Buffer1_ptr = rxdp3->Buffer1_ptr;
2510 memset(rxdp, 0, sizeof(struct RxD3));
2511 /* restore the buffer pointers for dma sync*/
2512 rxdp3->Buffer0_ptr = Buffer0_ptr;
2513 rxdp3->Buffer1_ptr = Buffer1_ptr;
2515 ba = &mac_control->rings[ring_no].ba[block_no][off];
2516 skb_reserve(skb, BUF0_LEN);
2517 tmp = (u64)(unsigned long) skb->data;
2520 skb->data = (void *) (unsigned long)tmp;
2521 skb_reset_tail_pointer(skb);
2523 if (!(rxdp3->Buffer0_ptr))
2524 rxdp3->Buffer0_ptr =
2525 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2526 PCI_DMA_FROMDEVICE);
2528 pci_dma_sync_single_for_device(nic->pdev,
2529 (dma_addr_t) rxdp3->Buffer0_ptr,
2530 BUF0_LEN, PCI_DMA_FROMDEVICE);
2531 if( (rxdp3->Buffer0_ptr == 0) ||
2532 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2533 goto pci_map_failed;
2535 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2536 if (nic->rxd_mode == RXD_MODE_3B) {
2537 /* Two buffer mode */
2540 * Buffer2 will have L3/L4 header plus
2543 rxdp3->Buffer2_ptr = pci_map_single
2544 (nic->pdev, skb->data, dev->mtu + 4,
2545 PCI_DMA_FROMDEVICE);
2547 if( (rxdp3->Buffer2_ptr == 0) ||
2548 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2549 goto pci_map_failed;
2551 rxdp3->Buffer1_ptr =
2552 pci_map_single(nic->pdev,
2554 PCI_DMA_FROMDEVICE);
2555 if( (rxdp3->Buffer1_ptr == 0) ||
2556 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2559 (dma_addr_t)rxdp3->Buffer2_ptr,
2561 PCI_DMA_FROMDEVICE);
2562 goto pci_map_failed;
2564 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2565 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2568 rxdp->Control_2 |= BIT(0);
2570 rxdp->Host_Control = (unsigned long) (skb);
2571 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2572 rxdp->Control_1 |= RXD_OWN_XENA;
2574 if (off == (rxd_count[nic->rxd_mode] + 1))
2576 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2578 rxdp->Control_2 |= SET_RXD_MARKER;
2579 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2582 first_rxdp->Control_1 |= RXD_OWN_XENA;
2586 atomic_inc(&nic->rx_bufs_left[ring_no]);
2591 /* Transfer ownership of first descriptor to adapter just before
2592 * exiting. Before that, use memory barrier so that ownership
2593 * and other fields are seen by adapter correctly.
2597 first_rxdp->Control_1 |= RXD_OWN_XENA;
2602 stats->pci_map_fail_cnt++;
2603 stats->mem_freed += skb->truesize;
2604 dev_kfree_skb_irq(skb);
2608 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2610 struct net_device *dev = sp->dev;
2612 struct sk_buff *skb;
2614 struct mac_info *mac_control;
2619 mac_control = &sp->mac_control;
2620 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2621 rxdp = mac_control->rings[ring_no].
2622 rx_blocks[blk].rxds[j].virt_addr;
2623 skb = (struct sk_buff *)
2624 ((unsigned long) rxdp->Host_Control);
2628 if (sp->rxd_mode == RXD_MODE_1) {
2629 rxdp1 = (struct RxD1*)rxdp;
2630 pci_unmap_single(sp->pdev, (dma_addr_t)
2633 HEADER_ETHERNET_II_802_3_SIZE
2634 + HEADER_802_2_SIZE +
2636 PCI_DMA_FROMDEVICE);
2637 memset(rxdp, 0, sizeof(struct RxD1));
2638 } else if(sp->rxd_mode == RXD_MODE_3B) {
2639 rxdp3 = (struct RxD3*)rxdp;
2640 ba = &mac_control->rings[ring_no].
2642 pci_unmap_single(sp->pdev, (dma_addr_t)
2645 PCI_DMA_FROMDEVICE);
2646 pci_unmap_single(sp->pdev, (dma_addr_t)
2649 PCI_DMA_FROMDEVICE);
2650 pci_unmap_single(sp->pdev, (dma_addr_t)
2653 PCI_DMA_FROMDEVICE);
2654 memset(rxdp, 0, sizeof(struct RxD3));
2656 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2658 atomic_dec(&sp->rx_bufs_left[ring_no]);
2663 * free_rx_buffers - Frees all Rx buffers
2664 * @sp: device private variable.
2666 * This function will free all Rx buffers allocated by host.
2671 static void free_rx_buffers(struct s2io_nic *sp)
2673 struct net_device *dev = sp->dev;
2674 int i, blk = 0, buf_cnt = 0;
2675 struct mac_info *mac_control;
2676 struct config_param *config;
2678 mac_control = &sp->mac_control;
2679 config = &sp->config;
2681 for (i = 0; i < config->rx_ring_num; i++) {
2682 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2683 free_rxd_blk(sp,i,blk);
2685 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2686 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2687 mac_control->rings[i].rx_curr_put_info.offset = 0;
2688 mac_control->rings[i].rx_curr_get_info.offset = 0;
2689 atomic_set(&sp->rx_bufs_left[i], 0);
2690 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2691 dev->name, buf_cnt, i);
2696 * s2io_poll - Rx interrupt handler for NAPI support
2697 * @napi : pointer to the napi structure.
2698 * @budget : The number of packets that were budgeted to be processed
2699 * during one pass through the 'Poll" function.
2701 * Comes into picture only if NAPI support has been incorporated. It does
2702 * the same thing that rx_intr_handler does, but not in a interrupt context
2703 * also It will process only a given number of packets.
2705 * 0 on success and 1 if there are No Rx packets to be processed.
2708 static int s2io_poll(struct napi_struct *napi, int budget)
2710 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2711 struct net_device *dev = nic->dev;
2712 int pkt_cnt = 0, org_pkts_to_process;
2713 struct mac_info *mac_control;
2714 struct config_param *config;
2715 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2718 if (!is_s2io_card_up(nic))
2721 mac_control = &nic->mac_control;
2722 config = &nic->config;
2724 nic->pkts_to_process = budget;
2725 org_pkts_to_process = nic->pkts_to_process;
2727 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2728 readl(&bar0->rx_traffic_int);
2730 for (i = 0; i < config->rx_ring_num; i++) {
2731 rx_intr_handler(&mac_control->rings[i]);
2732 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2733 if (!nic->pkts_to_process) {
2734 /* Quota for the current iteration has been met */
2739 netif_rx_complete(dev, napi);
2741 for (i = 0; i < config->rx_ring_num; i++) {
2742 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2743 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2744 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2748 /* Re enable the Rx interrupts. */
2749 writeq(0x0, &bar0->rx_traffic_mask);
2750 readl(&bar0->rx_traffic_mask);
2754 for (i = 0; i < config->rx_ring_num; i++) {
2755 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2756 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2757 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2764 #ifdef CONFIG_NET_POLL_CONTROLLER
2766 * s2io_netpoll - netpoll event handler entry point
2767 * @dev : pointer to the device structure.
2769 * This function will be called by upper layer to check for events on the
2770 * interface in situations where interrupts are disabled. It is used for
2771 * specific in-kernel networking tasks, such as remote consoles and kernel
2772 * debugging over the network (example netdump in RedHat).
2774 static void s2io_netpoll(struct net_device *dev)
2776 struct s2io_nic *nic = dev->priv;
2777 struct mac_info *mac_control;
2778 struct config_param *config;
2779 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2780 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2783 if (pci_channel_offline(nic->pdev))
2786 disable_irq(dev->irq);
2788 mac_control = &nic->mac_control;
2789 config = &nic->config;
2791 writeq(val64, &bar0->rx_traffic_int);
2792 writeq(val64, &bar0->tx_traffic_int);
2794 /* we need to free up the transmitted skbufs or else netpoll will
2795 * run out of skbs and will fail and eventually netpoll application such
2796 * as netdump will fail.
2798 for (i = 0; i < config->tx_fifo_num; i++)
2799 tx_intr_handler(&mac_control->fifos[i]);
2801 /* check for received packet and indicate up to network */
2802 for (i = 0; i < config->rx_ring_num; i++)
2803 rx_intr_handler(&mac_control->rings[i]);
2805 for (i = 0; i < config->rx_ring_num; i++) {
2806 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2807 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2808 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2812 enable_irq(dev->irq);
2818 * rx_intr_handler - Rx interrupt handler
2819 * @nic: device private variable.
2821 * If the interrupt is because of a received frame or if the
2822 * receive ring contains fresh as yet un-processed frames,this function is
2823 * called. It picks out the RxD at which place the last Rx processing had
2824 * stopped and sends the skb to the OSM's Rx handler and then increments
2829 static void rx_intr_handler(struct ring_info *ring_data)
2831 struct s2io_nic *nic = ring_data->nic;
2832 struct net_device *dev = (struct net_device *) nic->dev;
2833 int get_block, put_block, put_offset;
2834 struct rx_curr_get_info get_info, put_info;
2836 struct sk_buff *skb;
2842 spin_lock(&nic->rx_lock);
2844 get_info = ring_data->rx_curr_get_info;
2845 get_block = get_info.block_index;
2846 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2847 put_block = put_info.block_index;
2848 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2850 spin_lock(&nic->put_lock);
2851 put_offset = ring_data->put_pos;
2852 spin_unlock(&nic->put_lock);
2854 put_offset = ring_data->put_pos;
2856 while (RXD_IS_UP2DT(rxdp)) {
2858 * If your are next to put index then it's
2859 * FIFO full condition
2861 if ((get_block == put_block) &&
2862 (get_info.offset + 1) == put_info.offset) {
2863 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2866 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2868 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2870 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2871 spin_unlock(&nic->rx_lock);
2874 if (nic->rxd_mode == RXD_MODE_1) {
2875 rxdp1 = (struct RxD1*)rxdp;
2876 pci_unmap_single(nic->pdev, (dma_addr_t)
2879 HEADER_ETHERNET_II_802_3_SIZE +
2882 PCI_DMA_FROMDEVICE);
2883 } else if (nic->rxd_mode == RXD_MODE_3B) {
2884 rxdp3 = (struct RxD3*)rxdp;
2885 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2887 BUF0_LEN, PCI_DMA_FROMDEVICE);
2888 pci_unmap_single(nic->pdev, (dma_addr_t)
2891 PCI_DMA_FROMDEVICE);
2893 prefetch(skb->data);
2894 rx_osm_handler(ring_data, rxdp);
2896 ring_data->rx_curr_get_info.offset = get_info.offset;
2897 rxdp = ring_data->rx_blocks[get_block].
2898 rxds[get_info.offset].virt_addr;
2899 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2900 get_info.offset = 0;
2901 ring_data->rx_curr_get_info.offset = get_info.offset;
2903 if (get_block == ring_data->block_count)
2905 ring_data->rx_curr_get_info.block_index = get_block;
2906 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2909 nic->pkts_to_process -= 1;
2910 if ((napi) && (!nic->pkts_to_process))
2913 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2917 /* Clear all LRO sessions before exiting */
2918 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2919 struct lro *lro = &nic->lro0_n[i];
2921 update_L3L4_header(nic, lro);
2922 queue_rx_frame(lro->parent);
2923 clear_lro_session(lro);
2928 spin_unlock(&nic->rx_lock);
2932 * tx_intr_handler - Transmit interrupt handler
2933 * @nic : device private variable
2935 * If an interrupt was raised to indicate DMA complete of the
2936 * Tx packet, this function is called. It identifies the last TxD
2937 * whose buffer was freed and frees all skbs whose data have already
2938 * DMA'ed into the NICs internal memory.
2943 static void tx_intr_handler(struct fifo_info *fifo_data)
2945 struct s2io_nic *nic = fifo_data->nic;
2946 struct net_device *dev = (struct net_device *) nic->dev;
2947 struct tx_curr_get_info get_info, put_info;
2948 struct sk_buff *skb;
2952 get_info = fifo_data->tx_curr_get_info;
2953 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2954 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2956 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2957 (get_info.offset != put_info.offset) &&
2958 (txdlp->Host_Control)) {
2959 /* Check for TxD errors */
2960 if (txdlp->Control_1 & TXD_T_CODE) {
2961 unsigned long long err;
2962 err = txdlp->Control_1 & TXD_T_CODE;
2964 nic->mac_control.stats_info->sw_stat.
2968 /* update t_code statistics */
2969 err_mask = err >> 48;
2972 nic->mac_control.stats_info->sw_stat.
2977 nic->mac_control.stats_info->sw_stat.
2978 tx_desc_abort_cnt++;
2982 nic->mac_control.stats_info->sw_stat.
2983 tx_parity_err_cnt++;
2987 nic->mac_control.stats_info->sw_stat.
2992 nic->mac_control.stats_info->sw_stat.
2993 tx_list_proc_err_cnt++;
2998 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3000 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3002 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3006 /* Updating the statistics block */
3007 nic->stats.tx_bytes += skb->len;
3008 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3009 dev_kfree_skb_irq(skb);
3012 if (get_info.offset == get_info.fifo_len + 1)
3013 get_info.offset = 0;
3014 txdlp = (struct TxD *) fifo_data->list_info
3015 [get_info.offset].list_virt_addr;
3016 fifo_data->tx_curr_get_info.offset =
3020 spin_lock(&nic->tx_lock);
3021 if (netif_queue_stopped(dev))
3022 netif_wake_queue(dev);
3023 spin_unlock(&nic->tx_lock);
3027 * s2io_mdio_write - Function to write in to MDIO registers
3028 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3029 * @addr : address value
3030 * @value : data value
3031 * @dev : pointer to net_device structure
3033 * This function is used to write values to the MDIO registers
3036 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3039 struct s2io_nic *sp = dev->priv;
3040 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3042 //address transaction
3043 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3044 | MDIO_MMD_DEV_ADDR(mmd_type)
3045 | MDIO_MMS_PRT_ADDR(0x0);
3046 writeq(val64, &bar0->mdio_control);
3047 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3048 writeq(val64, &bar0->mdio_control);
3053 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3054 | MDIO_MMD_DEV_ADDR(mmd_type)
3055 | MDIO_MMS_PRT_ADDR(0x0)
3056 | MDIO_MDIO_DATA(value)
3057 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3058 writeq(val64, &bar0->mdio_control);
3059 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3060 writeq(val64, &bar0->mdio_control);
3064 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3065 | MDIO_MMD_DEV_ADDR(mmd_type)
3066 | MDIO_MMS_PRT_ADDR(0x0)
3067 | MDIO_OP(MDIO_OP_READ_TRANS);
3068 writeq(val64, &bar0->mdio_control);
3069 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3070 writeq(val64, &bar0->mdio_control);
3076 * s2io_mdio_read - Function to write in to MDIO registers
3077 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3078 * @addr : address value
3079 * @dev : pointer to net_device structure
3081 * This function is used to read values to the MDIO registers
3084 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3088 struct s2io_nic *sp = dev->priv;
3089 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3091 /* address transaction */
3092 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3093 | MDIO_MMD_DEV_ADDR(mmd_type)
3094 | MDIO_MMS_PRT_ADDR(0x0);
3095 writeq(val64, &bar0->mdio_control);
3096 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3097 writeq(val64, &bar0->mdio_control);
3100 /* Data transaction */
3102 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3103 | MDIO_MMD_DEV_ADDR(mmd_type)
3104 | MDIO_MMS_PRT_ADDR(0x0)
3105 | MDIO_OP(MDIO_OP_READ_TRANS);
3106 writeq(val64, &bar0->mdio_control);
3107 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3108 writeq(val64, &bar0->mdio_control);
3111 /* Read the value from regs */
3112 rval64 = readq(&bar0->mdio_control);
3113 rval64 = rval64 & 0xFFFF0000;
3114 rval64 = rval64 >> 16;
3118 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3119 * @counter : couter value to be updated
3120 * @flag : flag to indicate the status
3121 * @type : counter type
3123 * This function is to check the status of the xpak counters value
3127 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3132 for(i = 0; i <index; i++)
3137 *counter = *counter + 1;
3138 val64 = *regs_stat & mask;
3139 val64 = val64 >> (index * 0x2);
3146 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3147 "service. Excessive temperatures may "
3148 "result in premature transceiver "
3152 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3153 "service Excessive bias currents may "
3154 "indicate imminent laser diode "
3158 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3159 "service Excessive laser output "
3160 "power may saturate far-end "
3164 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3169 val64 = val64 << (index * 0x2);
3170 *regs_stat = (*regs_stat & (~mask)) | (val64);
3173 *regs_stat = *regs_stat & (~mask);
3178 * s2io_updt_xpak_counter - Function to update the xpak counters
3179 * @dev : pointer to net_device struct
3181 * This function is to upate the status of the xpak counters value
3184 static void s2io_updt_xpak_counter(struct net_device *dev)
3192 struct s2io_nic *sp = dev->priv;
3193 struct stat_block *stat_info = sp->mac_control.stats_info;
3195 /* Check the communication with the MDIO slave */
3198 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3199 if((val64 == 0xFFFF) || (val64 == 0x0000))
3201 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3202 "Returned %llx\n", (unsigned long long)val64);
3206 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3209 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3210 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3211 (unsigned long long)val64);
3215 /* Loading the DOM register to MDIO register */
3217 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3218 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3220 /* Reading the Alarm flags */
3223 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3225 flag = CHECKBIT(val64, 0x7);
3227 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3228 &stat_info->xpak_stat.xpak_regs_stat,
3231 if(CHECKBIT(val64, 0x6))
3232 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3234 flag = CHECKBIT(val64, 0x3);
3236 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3237 &stat_info->xpak_stat.xpak_regs_stat,
3240 if(CHECKBIT(val64, 0x2))
3241 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3243 flag = CHECKBIT(val64, 0x1);
3245 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3246 &stat_info->xpak_stat.xpak_regs_stat,
3249 if(CHECKBIT(val64, 0x0))
3250 stat_info->xpak_stat.alarm_laser_output_power_low++;
3252 /* Reading the Warning flags */
3255 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3257 if(CHECKBIT(val64, 0x7))
3258 stat_info->xpak_stat.warn_transceiver_temp_high++;
3260 if(CHECKBIT(val64, 0x6))
3261 stat_info->xpak_stat.warn_transceiver_temp_low++;
3263 if(CHECKBIT(val64, 0x3))
3264 stat_info->xpak_stat.warn_laser_bias_current_high++;
3266 if(CHECKBIT(val64, 0x2))
3267 stat_info->xpak_stat.warn_laser_bias_current_low++;
3269 if(CHECKBIT(val64, 0x1))
3270 stat_info->xpak_stat.warn_laser_output_power_high++;
3272 if(CHECKBIT(val64, 0x0))
3273 stat_info->xpak_stat.warn_laser_output_power_low++;
3277 * wait_for_cmd_complete - waits for a command to complete.
3278 * @sp : private member of the device structure, which is a pointer to the
3279 * s2io_nic structure.
3280 * Description: Function that waits for a command to Write into RMAC
3281 * ADDR DATA registers to be completed and returns either success or
3282 * error depending on whether the command was complete or not.
3284 * SUCCESS on success and FAILURE on failure.
3287 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3290 int ret = FAILURE, cnt = 0, delay = 1;
3293 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3297 val64 = readq(addr);
3298 if (bit_state == S2IO_BIT_RESET) {
3299 if (!(val64 & busy_bit)) {
3304 if (!(val64 & busy_bit)) {
3321 * check_pci_device_id - Checks if the device id is supported
3323 * Description: Function to check if the pci device id is supported by driver.
3324 * Return value: Actual device id if supported else PCI_ANY_ID
3326 static u16 check_pci_device_id(u16 id)
3329 case PCI_DEVICE_ID_HERC_WIN:
3330 case PCI_DEVICE_ID_HERC_UNI:
3331 return XFRAME_II_DEVICE;
3332 case PCI_DEVICE_ID_S2IO_UNI:
3333 case PCI_DEVICE_ID_S2IO_WIN:
3334 return XFRAME_I_DEVICE;
3341 * s2io_reset - Resets the card.
3342 * @sp : private member of the device structure.
3343 * Description: Function to Reset the card. This function then also
3344 * restores the previously saved PCI configuration space registers as
3345 * the card reset also resets the configuration space.
3350 static void s2io_reset(struct s2io_nic * sp)
3352 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3357 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3358 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3360 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3361 __FUNCTION__, sp->dev->name);
3363 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3364 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3366 val64 = SW_RESET_ALL;
3367 writeq(val64, &bar0->sw_reset);
3368 if (strstr(sp->product_name, "CX4")) {
3372 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3374 /* Restore the PCI state saved during initialization. */
3375 pci_restore_state(sp->pdev);
3376 pci_read_config_word(sp->pdev, 0x2, &val16);
3377 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3382 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3383 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3386 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3390 /* Set swapper to enable I/O register access */
3391 s2io_set_swapper(sp);
3393 /* Restore the MSIX table entries from local variables */
3394 restore_xmsi_data(sp);
3396 /* Clear certain PCI/PCI-X fields after reset */
3397 if (sp->device_type == XFRAME_II_DEVICE) {
3398 /* Clear "detected parity error" bit */
3399 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3401 /* Clearing PCIX Ecc status register */
3402 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3404 /* Clearing PCI_STATUS error reflected here */
3405 writeq(BIT(62), &bar0->txpic_int_reg);
3408 /* Reset device statistics maintained by OS */
3409 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3411 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3412 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3413 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3414 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3415 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3416 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3417 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3418 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3419 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3420 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3421 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3422 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3423 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3424 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3425 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3426 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3427 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3428 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3429 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3431 /* SXE-002: Configure link and activity LED to turn it off */
3432 subid = sp->pdev->subsystem_device;
3433 if (((subid & 0xFF) >= 0x07) &&
3434 (sp->device_type == XFRAME_I_DEVICE)) {
3435 val64 = readq(&bar0->gpio_control);
3436 val64 |= 0x0000800000000000ULL;
3437 writeq(val64, &bar0->gpio_control);
3438 val64 = 0x0411040400000000ULL;
3439 writeq(val64, (void __iomem *)bar0 + 0x2700);
3443 * Clear spurious ECC interrupts that would have occured on
3444 * XFRAME II cards after reset.
3446 if (sp->device_type == XFRAME_II_DEVICE) {
3447 val64 = readq(&bar0->pcc_err_reg);
3448 writeq(val64, &bar0->pcc_err_reg);
3451 /* restore the previously assigned mac address */
3452 s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3454 sp->device_enabled_once = FALSE;
3458 * s2io_set_swapper - to set the swapper controle on the card
3459 * @sp : private member of the device structure,
3460 * pointer to the s2io_nic structure.
3461 * Description: Function to set the swapper control on the card
3462 * correctly depending on the 'endianness' of the system.
3464 * SUCCESS on success and FAILURE on failure.
3467 static int s2io_set_swapper(struct s2io_nic * sp)
3469 struct net_device *dev = sp->dev;
3470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3471 u64 val64, valt, valr;
3474 * Set proper endian settings and verify the same by reading
3475 * the PIF Feed-back register.
3478 val64 = readq(&bar0->pif_rd_swapper_fb);
3479 if (val64 != 0x0123456789ABCDEFULL) {
3481 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3482 0x8100008181000081ULL, /* FE=1, SE=0 */
3483 0x4200004242000042ULL, /* FE=0, SE=1 */
3484 0}; /* FE=0, SE=0 */
3487 writeq(value[i], &bar0->swapper_ctrl);
3488 val64 = readq(&bar0->pif_rd_swapper_fb);
3489 if (val64 == 0x0123456789ABCDEFULL)
3494 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3496 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3497 (unsigned long long) val64);
3502 valr = readq(&bar0->swapper_ctrl);
3505 valt = 0x0123456789ABCDEFULL;
3506 writeq(valt, &bar0->xmsi_address);
3507 val64 = readq(&bar0->xmsi_address);
3511 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3512 0x0081810000818100ULL, /* FE=1, SE=0 */
3513 0x0042420000424200ULL, /* FE=0, SE=1 */
3514 0}; /* FE=0, SE=0 */
3517 writeq((value[i] | valr), &bar0->swapper_ctrl);
3518 writeq(valt, &bar0->xmsi_address);
3519 val64 = readq(&bar0->xmsi_address);
3525 unsigned long long x = val64;
3526 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3527 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3531 val64 = readq(&bar0->swapper_ctrl);
3532 val64 &= 0xFFFF000000000000ULL;
3536 * The device by default set to a big endian format, so a
3537 * big endian driver need not set anything.
3539 val64 |= (SWAPPER_CTRL_TXP_FE |
3540 SWAPPER_CTRL_TXP_SE |
3541 SWAPPER_CTRL_TXD_R_FE |
3542 SWAPPER_CTRL_TXD_W_FE |
3543 SWAPPER_CTRL_TXF_R_FE |
3544 SWAPPER_CTRL_RXD_R_FE |
3545 SWAPPER_CTRL_RXD_W_FE |
3546 SWAPPER_CTRL_RXF_W_FE |
3547 SWAPPER_CTRL_XMSI_FE |
3548 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3549 if (sp->config.intr_type == INTA)
3550 val64 |= SWAPPER_CTRL_XMSI_SE;
3551 writeq(val64, &bar0->swapper_ctrl);
3554 * Initially we enable all bits to make it accessible by the
3555 * driver, then we selectively enable only those bits that
3558 val64 |= (SWAPPER_CTRL_TXP_FE |
3559 SWAPPER_CTRL_TXP_SE |
3560 SWAPPER_CTRL_TXD_R_FE |
3561 SWAPPER_CTRL_TXD_R_SE |
3562 SWAPPER_CTRL_TXD_W_FE |
3563 SWAPPER_CTRL_TXD_W_SE |
3564 SWAPPER_CTRL_TXF_R_FE |
3565 SWAPPER_CTRL_RXD_R_FE |
3566 SWAPPER_CTRL_RXD_R_SE |
3567 SWAPPER_CTRL_RXD_W_FE |
3568 SWAPPER_CTRL_RXD_W_SE |
3569 SWAPPER_CTRL_RXF_W_FE |
3570 SWAPPER_CTRL_XMSI_FE |
3571 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3572 if (sp->config.intr_type == INTA)
3573 val64 |= SWAPPER_CTRL_XMSI_SE;
3574 writeq(val64, &bar0->swapper_ctrl);
3576 val64 = readq(&bar0->swapper_ctrl);
3579 * Verifying if endian settings are accurate by reading a
3580 * feedback register.
3582 val64 = readq(&bar0->pif_rd_swapper_fb);
3583 if (val64 != 0x0123456789ABCDEFULL) {
3584 /* Endian settings are incorrect, calls for another dekko. */
3585 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3587 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3588 (unsigned long long) val64);
3595 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3597 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3599 int ret = 0, cnt = 0;
3602 val64 = readq(&bar0->xmsi_access);
3603 if (!(val64 & BIT(15)))
3609 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3616 static void restore_xmsi_data(struct s2io_nic *nic)
3618 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3622 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3623 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3624 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3625 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3626 writeq(val64, &bar0->xmsi_access);
3627 if (wait_for_msix_trans(nic, i)) {
3628 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3634 static void store_xmsi_data(struct s2io_nic *nic)
3636 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3637 u64 val64, addr, data;
3640 /* Store and display */
3641 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3642 val64 = (BIT(15) | vBIT(i, 26, 6));
3643 writeq(val64, &bar0->xmsi_access);
3644 if (wait_for_msix_trans(nic, i)) {
3645 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3648 addr = readq(&bar0->xmsi_address);
3649 data = readq(&bar0->xmsi_data);
3651 nic->msix_info[i].addr = addr;
3652 nic->msix_info[i].data = data;
3657 static int s2io_enable_msi_x(struct s2io_nic *nic)
3659 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3661 u16 msi_control; /* Temp variable */
3662 int ret, i, j, msix_indx = 1;
3664 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3666 if (nic->entries == NULL) {
3667 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3669 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3672 nic->mac_control.stats_info->sw_stat.mem_allocated
3673 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3674 memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3677 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3679 if (nic->s2io_entries == NULL) {
3680 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3682 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3683 kfree(nic->entries);
3684 nic->mac_control.stats_info->sw_stat.mem_freed
3685 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3688 nic->mac_control.stats_info->sw_stat.mem_allocated
3689 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3690 memset(nic->s2io_entries, 0,
3691 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3693 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3694 nic->entries[i].entry = i;
3695 nic->s2io_entries[i].entry = i;
3696 nic->s2io_entries[i].arg = NULL;
3697 nic->s2io_entries[i].in_use = 0;
3700 tx_mat = readq(&bar0->tx_mat0_n[0]);
3701 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3702 tx_mat |= TX_MAT_SET(i, msix_indx);
3703 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3704 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3705 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3707 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3709 if (!nic->config.bimodal) {
3710 rx_mat = readq(&bar0->rx_mat);
3711 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3712 rx_mat |= RX_MAT_SET(j, msix_indx);
3713 nic->s2io_entries[msix_indx].arg
3714 = &nic->mac_control.rings[j];
3715 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3716 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3718 writeq(rx_mat, &bar0->rx_mat);
3720 tx_mat = readq(&bar0->tx_mat0_n[7]);
3721 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3722 tx_mat |= TX_MAT_SET(i, msix_indx);
3723 nic->s2io_entries[msix_indx].arg
3724 = &nic->mac_control.rings[j];
3725 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3726 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3728 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3731 nic->avail_msix_vectors = 0;
3732 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3733 /* We fail init if error or we get less vectors than min required */
3734 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3735 nic->avail_msix_vectors = ret;
3736 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3739 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3740 kfree(nic->entries);
3741 nic->mac_control.stats_info->sw_stat.mem_freed
3742 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3743 kfree(nic->s2io_entries);
3744 nic->mac_control.stats_info->sw_stat.mem_freed
3745 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3746 nic->entries = NULL;
3747 nic->s2io_entries = NULL;
3748 nic->avail_msix_vectors = 0;
3751 if (!nic->avail_msix_vectors)
3752 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3755 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3756 * in the herc NIC. (Temp change, needs to be removed later)
3758 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3759 msi_control |= 0x1; /* Enable MSI */
3760 pci_write_config_word(nic->pdev, 0x42, msi_control);
3765 /* Handle software interrupt used during MSI(X) test */
3766 static irqreturn_t __devinit s2io_test_intr(int irq, void *dev_id)
3768 struct s2io_nic *sp = dev_id;
3770 sp->msi_detected = 1;
3771 wake_up(&sp->msi_wait);
3776 /* Test interrupt path by forcing a a software IRQ */
3777 static int __devinit s2io_test_msi(struct s2io_nic *sp)
3779 struct pci_dev *pdev = sp->pdev;
3780 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3784 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3787 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3788 sp->dev->name, pci_name(pdev), pdev->irq);
3792 init_waitqueue_head (&sp->msi_wait);
3793 sp->msi_detected = 0;
3795 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3796 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3797 val64 |= SCHED_INT_CTRL_TIMER_EN;
3798 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3799 writeq(val64, &bar0->scheduled_int_ctrl);
3801 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3803 if (!sp->msi_detected) {
3804 /* MSI(X) test failed, go back to INTx mode */
3805 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated"
3806 "using MSI(X) during test\n", sp->dev->name,
3812 free_irq(sp->entries[1].vector, sp);
3814 writeq(saved64, &bar0->scheduled_int_ctrl);
3818 /* ********************************************************* *
3819 * Functions defined below concern the OS part of the driver *
3820 * ********************************************************* */
3823 * s2io_open - open entry point of the driver
3824 * @dev : pointer to the device structure.
3826 * This function is the open entry point of the driver. It mainly calls a
3827 * function to allocate Rx buffers and inserts them into the buffer
3828 * descriptors and then enables the Rx part of the NIC.
3830 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3834 static int s2io_open(struct net_device *dev)
3836 struct s2io_nic *sp = dev->priv;
3840 * Make sure you have link off by default every time
3841 * Nic is initialized
3843 netif_carrier_off(dev);
3844 sp->last_link_state = 0;
3846 napi_enable(&sp->napi);
3848 if (sp->config.intr_type == MSI_X) {
3849 int ret = s2io_enable_msi_x(sp);
3854 ret = s2io_test_msi(sp);
3856 /* rollback MSI-X, will re-enable during add_isr() */
3858 sp->mac_control.stats_info->sw_stat.mem_freed +=
3859 (MAX_REQUESTED_MSI_X *
3860 sizeof(struct msix_entry));
3861 kfree(sp->s2io_entries);
3862 sp->mac_control.stats_info->sw_stat.mem_freed +=
3863 (MAX_REQUESTED_MSI_X *
3864 sizeof(struct s2io_msix_entry));
3866 sp->s2io_entries = NULL;
3868 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3869 msi_control &= 0xFFFE; /* Disable MSI */
3870 pci_write_config_word(sp->pdev, 0x42, msi_control);
3872 pci_disable_msix(sp->pdev);
3878 "%s: MSI-X requested but failed to enable\n",
3880 sp->config.intr_type = INTA;
3884 /* NAPI doesn't work well with MSI(X) */
3885 if (sp->config.intr_type != INTA) {
3887 sp->config.napi = 0;
3890 /* Initialize H/W and enable interrupts */
3891 err = s2io_card_up(sp);
3893 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3895 goto hw_init_failed;
3898 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3899 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3902 goto hw_init_failed;
3905 netif_start_queue(dev);
3909 napi_disable(&sp->napi);
3910 if (sp->config.intr_type == MSI_X) {
3913 sp->mac_control.stats_info->sw_stat.mem_freed
3914 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3916 if (sp->s2io_entries) {
3917 kfree(sp->s2io_entries);
3918 sp->mac_control.stats_info->sw_stat.mem_freed
3919 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3926 * s2io_close -close entry point of the driver
3927 * @dev : device pointer.
3929 * This is the stop entry point of the driver. It needs to undo exactly
3930 * whatever was done by the open entry point,thus it's usually referred to
3931 * as the close function.Among other things this function mainly stops the
3932 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3934 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3938 static int s2io_close(struct net_device *dev)
3940 struct s2io_nic *sp = dev->priv;
3942 netif_stop_queue(dev);
3943 napi_disable(&sp->napi);
3944 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3951 * s2io_xmit - Tx entry point of te driver
3952 * @skb : the socket buffer containing the Tx data.
3953 * @dev : device pointer.
3955 * This function is the Tx entry point of the driver. S2IO NIC supports
3956 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3957 * NOTE: when device cant queue the pkt,just the trans_start variable will
3960 * 0 on success & 1 on failure.
3963 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3965 struct s2io_nic *sp = dev->priv;
3966 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3969 struct TxFIFO_element __iomem *tx_fifo;
3970 unsigned long flags;
3972 int vlan_priority = 0;
3973 struct mac_info *mac_control;
3974 struct config_param *config;
3976 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
3978 mac_control = &sp->mac_control;
3979 config = &sp->config;
3981 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3983 if (unlikely(skb->len <= 0)) {
3984 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3985 dev_kfree_skb_any(skb);
3989 spin_lock_irqsave(&sp->tx_lock, flags);
3990 if (!is_s2io_card_up(sp)) {
3991 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3993 spin_unlock_irqrestore(&sp->tx_lock, flags);
3999 /* Get Fifo number to Transmit based on vlan priority */
4000 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4001 vlan_tag = vlan_tx_tag_get(skb);
4002 vlan_priority = vlan_tag >> 13;
4003 queue = config->fifo_mapping[vlan_priority];
4006 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
4007 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
4008 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
4011 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
4012 /* Avoid "put" pointer going beyond "get" pointer */
4013 if (txdp->Host_Control ||
4014 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4015 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4016 netif_stop_queue(dev);
4018 spin_unlock_irqrestore(&sp->tx_lock, flags);
4022 offload_type = s2io_offload_type(skb);
4023 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4024 txdp->Control_1 |= TXD_TCP_LSO_EN;
4025 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4027 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4029 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4032 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4033 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4034 txdp->Control_2 |= config->tx_intr_type;
4036 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4037 txdp->Control_2 |= TXD_VLAN_ENABLE;
4038 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4041 frg_len = skb->len - skb->data_len;
4042 if (offload_type == SKB_GSO_UDP) {
4045 ufo_size = s2io_udp_mss(skb);
4047 txdp->Control_1 |= TXD_UFO_EN;
4048 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4049 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4051 sp->ufo_in_band_v[put_off] =
4052 (u64)skb_shinfo(skb)->ip6_frag_id;
4054 sp->ufo_in_band_v[put_off] =
4055 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4057 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4058 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4060 sizeof(u64), PCI_DMA_TODEVICE);
4061 if((txdp->Buffer_Pointer == 0) ||
4062 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4063 goto pci_map_failed;
4067 txdp->Buffer_Pointer = pci_map_single
4068 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4069 if((txdp->Buffer_Pointer == 0) ||
4070 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4071 goto pci_map_failed;
4073 txdp->Host_Control = (unsigned long) skb;
4074 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4075 if (offload_type == SKB_GSO_UDP)
4076 txdp->Control_1 |= TXD_UFO_EN;
4078 frg_cnt = skb_shinfo(skb)->nr_frags;
4079 /* For fragmented SKB. */
4080 for (i = 0; i < frg_cnt; i++) {
4081 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4082 /* A '0' length fragment will be ignored */
4086 txdp->Buffer_Pointer = (u64) pci_map_page
4087 (sp->pdev, frag->page, frag->page_offset,
4088 frag->size, PCI_DMA_TODEVICE);
4089 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4090 if (offload_type == SKB_GSO_UDP)
4091 txdp->Control_1 |= TXD_UFO_EN;
4093 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4095 if (offload_type == SKB_GSO_UDP)
4096 frg_cnt++; /* as Txd0 was used for inband header */
4098 tx_fifo = mac_control->tx_FIFO_start[queue];
4099 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4100 writeq(val64, &tx_fifo->TxDL_Pointer);
4102 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4105 val64 |= TX_FIFO_SPECIAL_FUNC;
4107 writeq(val64, &tx_fifo->List_Control);
4112 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4114 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4116 /* Avoid "put" pointer going beyond "get" pointer */
4117 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4118 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4120 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4122 netif_stop_queue(dev);
4124 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4125 dev->trans_start = jiffies;
4126 spin_unlock_irqrestore(&sp->tx_lock, flags);
4130 stats->pci_map_fail_cnt++;
4131 netif_stop_queue(dev);
4132 stats->mem_freed += skb->truesize;
4134 spin_unlock_irqrestore(&sp->tx_lock, flags);
4139 s2io_alarm_handle(unsigned long data)
4141 struct s2io_nic *sp = (struct s2io_nic *)data;
4142 struct net_device *dev = sp->dev;
4144 s2io_handle_errors(dev);
4145 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4148 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4150 int rxb_size, level;
4153 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4154 level = rx_buffer_level(sp, rxb_size, rng_n);
4156 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4158 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4159 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4160 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4161 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4163 clear_bit(0, (&sp->tasklet_status));
4166 clear_bit(0, (&sp->tasklet_status));
4167 } else if (level == LOW)
4168 tasklet_schedule(&sp->task);
4170 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4171 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4172 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4177 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4179 struct ring_info *ring = (struct ring_info *)dev_id;
4180 struct s2io_nic *sp = ring->nic;
4182 if (!is_s2io_card_up(sp))
4185 rx_intr_handler(ring);
4186 s2io_chk_rx_buffers(sp, ring->ring_no);
4191 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4193 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4194 struct s2io_nic *sp = fifo->nic;
4196 if (!is_s2io_card_up(sp))
4199 tx_intr_handler(fifo);
4202 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4204 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4207 val64 = readq(&bar0->pic_int_status);
4208 if (val64 & PIC_INT_GPIO) {
4209 val64 = readq(&bar0->gpio_int_reg);
4210 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4211 (val64 & GPIO_INT_REG_LINK_UP)) {
4213 * This is unstable state so clear both up/down
4214 * interrupt and adapter to re-evaluate the link state.
4216 val64 |= GPIO_INT_REG_LINK_DOWN;
4217 val64 |= GPIO_INT_REG_LINK_UP;
4218 writeq(val64, &bar0->gpio_int_reg);
4219 val64 = readq(&bar0->gpio_int_mask);
4220 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4221 GPIO_INT_MASK_LINK_DOWN);
4222 writeq(val64, &bar0->gpio_int_mask);
4224 else if (val64 & GPIO_INT_REG_LINK_UP) {
4225 val64 = readq(&bar0->adapter_status);
4226 /* Enable Adapter */
4227 val64 = readq(&bar0->adapter_control);
4228 val64 |= ADAPTER_CNTL_EN;
4229 writeq(val64, &bar0->adapter_control);
4230 val64 |= ADAPTER_LED_ON;
4231 writeq(val64, &bar0->adapter_control);
4232 if (!sp->device_enabled_once)
4233 sp->device_enabled_once = 1;
4235 s2io_link(sp, LINK_UP);
4237 * unmask link down interrupt and mask link-up
4240 val64 = readq(&bar0->gpio_int_mask);
4241 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4242 val64 |= GPIO_INT_MASK_LINK_UP;
4243 writeq(val64, &bar0->gpio_int_mask);
4245 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4246 val64 = readq(&bar0->adapter_status);
4247 s2io_link(sp, LINK_DOWN);
4248 /* Link is down so unmaks link up interrupt */
4249 val64 = readq(&bar0->gpio_int_mask);
4250 val64 &= ~GPIO_INT_MASK_LINK_UP;
4251 val64 |= GPIO_INT_MASK_LINK_DOWN;
4252 writeq(val64, &bar0->gpio_int_mask);
4255 val64 = readq(&bar0->adapter_control);
4256 val64 = val64 &(~ADAPTER_LED_ON);
4257 writeq(val64, &bar0->adapter_control);
4260 val64 = readq(&bar0->gpio_int_mask);
4264 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4265 * @value: alarm bits
4266 * @addr: address value
4267 * @cnt: counter variable
4268 * Description: Check for alarm and increment the counter
4270 * 1 - if alarm bit set
4271 * 0 - if alarm bit is not set
4273 int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4274 unsigned long long *cnt)
4277 val64 = readq(addr);
4278 if ( val64 & value ) {
4279 writeq(val64, addr);
4288 * s2io_handle_errors - Xframe error indication handler
4289 * @nic: device private variable
4290 * Description: Handle alarms such as loss of link, single or
4291 * double ECC errors, critical and serious errors.
4295 static void s2io_handle_errors(void * dev_id)
4297 struct net_device *dev = (struct net_device *) dev_id;
4298 struct s2io_nic *sp = dev->priv;
4299 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4300 u64 temp64 = 0,val64=0;
4303 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4304 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4306 if (!is_s2io_card_up(sp))
4309 if (pci_channel_offline(sp->pdev))
4312 memset(&sw_stat->ring_full_cnt, 0,
4313 sizeof(sw_stat->ring_full_cnt));
4315 /* Handling the XPAK counters update */
4316 if(stats->xpak_timer_count < 72000) {
4317 /* waiting for an hour */
4318 stats->xpak_timer_count++;
4320 s2io_updt_xpak_counter(dev);
4321 /* reset the count to zero */
4322 stats->xpak_timer_count = 0;
4325 /* Handling link status change error Intr */
4326 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4327 val64 = readq(&bar0->mac_rmac_err_reg);
4328 writeq(val64, &bar0->mac_rmac_err_reg);
4329 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4330 schedule_work(&sp->set_link_task);
4333 /* In case of a serious error, the device will be Reset. */
4334 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4335 &sw_stat->serious_err_cnt))
4338 /* Check for data parity error */
4339 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4340 &sw_stat->parity_err_cnt))
4343 /* Check for ring full counter */
4344 if (sp->device_type == XFRAME_II_DEVICE) {
4345 val64 = readq(&bar0->ring_bump_counter1);
4346 for (i=0; i<4; i++) {
4347 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4348 temp64 >>= 64 - ((i+1)*16);
4349 sw_stat->ring_full_cnt[i] += temp64;
4352 val64 = readq(&bar0->ring_bump_counter2);
4353 for (i=0; i<4; i++) {
4354 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4355 temp64 >>= 64 - ((i+1)*16);
4356 sw_stat->ring_full_cnt[i+4] += temp64;
4360 val64 = readq(&bar0->txdma_int_status);
4361 /*check for pfc_err*/
4362 if (val64 & TXDMA_PFC_INT) {
4363 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4364 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4365 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4366 &sw_stat->pfc_err_cnt))
4368 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4369 &sw_stat->pfc_err_cnt);
4372 /*check for tda_err*/
4373 if (val64 & TXDMA_TDA_INT) {
4374 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4375 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4376 &sw_stat->tda_err_cnt))
4378 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4379 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4381 /*check for pcc_err*/
4382 if (val64 & TXDMA_PCC_INT) {
4383 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4384 | PCC_N_SERR | PCC_6_COF_OV_ERR
4385 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4386 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4387 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4388 &sw_stat->pcc_err_cnt))
4390 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4391 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4394 /*check for tti_err*/
4395 if (val64 & TXDMA_TTI_INT) {
4396 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4397 &sw_stat->tti_err_cnt))
4399 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4400 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4403 /*check for lso_err*/
4404 if (val64 & TXDMA_LSO_INT) {
4405 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4406 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4407 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4409 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4410 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4413 /*check for tpa_err*/
4414 if (val64 & TXDMA_TPA_INT) {
4415 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4416 &sw_stat->tpa_err_cnt))
4418 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4419 &sw_stat->tpa_err_cnt);
4422 /*check for sm_err*/
4423 if (val64 & TXDMA_SM_INT) {
4424 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4425 &sw_stat->sm_err_cnt))
4429 val64 = readq(&bar0->mac_int_status);
4430 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4431 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4432 &bar0->mac_tmac_err_reg,
4433 &sw_stat->mac_tmac_err_cnt))
4435 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4436 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4437 &bar0->mac_tmac_err_reg,
4438 &sw_stat->mac_tmac_err_cnt);
4441 val64 = readq(&bar0->xgxs_int_status);
4442 if (val64 & XGXS_INT_STATUS_TXGXS) {
4443 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4444 &bar0->xgxs_txgxs_err_reg,
4445 &sw_stat->xgxs_txgxs_err_cnt))
4447 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4448 &bar0->xgxs_txgxs_err_reg,
4449 &sw_stat->xgxs_txgxs_err_cnt);
4452 val64 = readq(&bar0->rxdma_int_status);
4453 if (val64 & RXDMA_INT_RC_INT_M) {
4454 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4455 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4456 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4458 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4459 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4460 &sw_stat->rc_err_cnt);
4461 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4462 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4463 &sw_stat->prc_pcix_err_cnt))
4465 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4466 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4467 &sw_stat->prc_pcix_err_cnt);
4470 if (val64 & RXDMA_INT_RPA_INT_M) {
4471 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4472 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4474 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4475 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4478 if (val64 & RXDMA_INT_RDA_INT_M) {
4479 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4480 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4481 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4482 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4484 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4485 | RDA_MISC_ERR | RDA_PCIX_ERR,
4486 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4489 if (val64 & RXDMA_INT_RTI_INT_M) {
4490 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4491 &sw_stat->rti_err_cnt))
4493 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4494 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4497 val64 = readq(&bar0->mac_int_status);
4498 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4499 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4500 &bar0->mac_rmac_err_reg,
4501 &sw_stat->mac_rmac_err_cnt))
4503 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4504 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4505 &sw_stat->mac_rmac_err_cnt);
4508 val64 = readq(&bar0->xgxs_int_status);
4509 if (val64 & XGXS_INT_STATUS_RXGXS) {
4510 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4511 &bar0->xgxs_rxgxs_err_reg,
4512 &sw_stat->xgxs_rxgxs_err_cnt))
4516 val64 = readq(&bar0->mc_int_status);
4517 if(val64 & MC_INT_STATUS_MC_INT) {
4518 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4519 &sw_stat->mc_err_cnt))
4522 /* Handling Ecc errors */
4523 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4524 writeq(val64, &bar0->mc_err_reg);
4525 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4526 sw_stat->double_ecc_errs++;
4527 if (sp->device_type != XFRAME_II_DEVICE) {
4529 * Reset XframeI only if critical error
4532 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4533 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4537 sw_stat->single_ecc_errs++;
4543 netif_stop_queue(dev);
4544 schedule_work(&sp->rst_timer_task);
4545 sw_stat->soft_reset_cnt++;
4550 * s2io_isr - ISR handler of the device .
4551 * @irq: the irq of the device.
4552 * @dev_id: a void pointer to the dev structure of the NIC.
4553 * Description: This function is the ISR handler of the device. It
4554 * identifies the reason for the interrupt and calls the relevant
4555 * service routines. As a contongency measure, this ISR allocates the
4556 * recv buffers, if their numbers are below the panic value which is
4557 * presently set to 25% of the original number of rcv buffers allocated.
4559 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4560 * IRQ_NONE: will be returned if interrupt is not from our device
4562 static irqreturn_t s2io_isr(int irq, void *dev_id)
4564 struct net_device *dev = (struct net_device *) dev_id;
4565 struct s2io_nic *sp = dev->priv;
4566 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4569 struct mac_info *mac_control;
4570 struct config_param *config;
4572 /* Pretend we handled any irq's from a disconnected card */
4573 if (pci_channel_offline(sp->pdev))
4576 if (!is_s2io_card_up(sp))
4579 mac_control = &sp->mac_control;
4580 config = &sp->config;
4583 * Identify the cause for interrupt and call the appropriate
4584 * interrupt handler. Causes for the interrupt could be;
4589 reason = readq(&bar0->general_int_status);
4591 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4592 /* Nothing much can be done. Get out */
4596 if (reason & (GEN_INTR_RXTRAFFIC |
4597 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4599 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4602 if (reason & GEN_INTR_RXTRAFFIC) {
4603 if (likely(netif_rx_schedule_prep(dev,
4605 __netif_rx_schedule(dev, &sp->napi);
4606 writeq(S2IO_MINUS_ONE,
4607 &bar0->rx_traffic_mask);
4609 writeq(S2IO_MINUS_ONE,
4610 &bar0->rx_traffic_int);
4614 * rx_traffic_int reg is an R1 register, writing all 1's
4615 * will ensure that the actual interrupt causing bit
4616 * get's cleared and hence a read can be avoided.
4618 if (reason & GEN_INTR_RXTRAFFIC)
4619 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4621 for (i = 0; i < config->rx_ring_num; i++)
4622 rx_intr_handler(&mac_control->rings[i]);
4626 * tx_traffic_int reg is an R1 register, writing all 1's
4627 * will ensure that the actual interrupt causing bit get's
4628 * cleared and hence a read can be avoided.
4630 if (reason & GEN_INTR_TXTRAFFIC)
4631 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4633 for (i = 0; i < config->tx_fifo_num; i++)
4634 tx_intr_handler(&mac_control->fifos[i]);
4636 if (reason & GEN_INTR_TXPIC)
4637 s2io_txpic_intr_handle(sp);
4640 * Reallocate the buffers from the interrupt handler itself.
4642 if (!config->napi) {
4643 for (i = 0; i < config->rx_ring_num; i++)
4644 s2io_chk_rx_buffers(sp, i);
4646 writeq(sp->general_int_mask, &bar0->general_int_mask);
4647 readl(&bar0->general_int_status);
4653 /* The interrupt was not raised by us */
4663 static void s2io_updt_stats(struct s2io_nic *sp)
4665 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4669 if (is_s2io_card_up(sp)) {
4670 /* Apprx 30us on a 133 MHz bus */
4671 val64 = SET_UPDT_CLICKS(10) |
4672 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4673 writeq(val64, &bar0->stat_cfg);
4676 val64 = readq(&bar0->stat_cfg);
4677 if (!(val64 & BIT(0)))
4681 break; /* Updt failed */
4687 * s2io_get_stats - Updates the device statistics structure.
4688 * @dev : pointer to the device structure.
4690 * This function updates the device statistics structure in the s2io_nic
4691 * structure and returns a pointer to the same.
4693 * pointer to the updated net_device_stats structure.
4696 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4698 struct s2io_nic *sp = dev->priv;
4699 struct mac_info *mac_control;
4700 struct config_param *config;
4703 mac_control = &sp->mac_control;
4704 config = &sp->config;
4706 /* Configure Stats for immediate updt */
4707 s2io_updt_stats(sp);
4709 sp->stats.tx_packets =
4710 le32_to_cpu(mac_control->stats_info->tmac_frms);
4711 sp->stats.tx_errors =
4712 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4713 sp->stats.rx_errors =
4714 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4715 sp->stats.multicast =
4716 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4717 sp->stats.rx_length_errors =
4718 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4720 return (&sp->stats);
4724 * s2io_set_multicast - entry point for multicast address enable/disable.
4725 * @dev : pointer to the device structure
4727 * This function is a driver entry point which gets called by the kernel
4728 * whenever multicast addresses must be enabled/disabled. This also gets
4729 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4730 * determine, if multicast address must be enabled or if promiscuous mode
4731 * is to be disabled etc.
4736 static void s2io_set_multicast(struct net_device *dev)
4739 struct dev_mc_list *mclist;
4740 struct s2io_nic *sp = dev->priv;
4741 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4742 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4744 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4747 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4748 /* Enable all Multicast addresses */
4749 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4750 &bar0->rmac_addr_data0_mem);
4751 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4752 &bar0->rmac_addr_data1_mem);
4753 val64 = RMAC_ADDR_CMD_MEM_WE |
4754 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4755 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4756 writeq(val64, &bar0->rmac_addr_cmd_mem);
4757 /* Wait till command completes */
4758 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4759 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4763 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4764 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4765 /* Disable all Multicast addresses */
4766 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4767 &bar0->rmac_addr_data0_mem);
4768 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4769 &bar0->rmac_addr_data1_mem);
4770 val64 = RMAC_ADDR_CMD_MEM_WE |
4771 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4772 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4773 writeq(val64, &bar0->rmac_addr_cmd_mem);
4774 /* Wait till command completes */
4775 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4776 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4780 sp->all_multi_pos = 0;
4783 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4784 /* Put the NIC into promiscuous mode */
4785 add = &bar0->mac_cfg;
4786 val64 = readq(&bar0->mac_cfg);
4787 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4789 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4790 writel((u32) val64, add);
4791 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4792 writel((u32) (val64 >> 32), (add + 4));
4794 if (vlan_tag_strip != 1) {
4795 val64 = readq(&bar0->rx_pa_cfg);
4796 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4797 writeq(val64, &bar0->rx_pa_cfg);
4798 vlan_strip_flag = 0;
4801 val64 = readq(&bar0->mac_cfg);
4802 sp->promisc_flg = 1;
4803 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4805 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4806 /* Remove the NIC from promiscuous mode */
4807 add = &bar0->mac_cfg;
4808 val64 = readq(&bar0->mac_cfg);
4809 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4811 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4812 writel((u32) val64, add);
4813 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4814 writel((u32) (val64 >> 32), (add + 4));
4816 if (vlan_tag_strip != 0) {
4817 val64 = readq(&bar0->rx_pa_cfg);
4818 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4819 writeq(val64, &bar0->rx_pa_cfg);
4820 vlan_strip_flag = 1;
4823 val64 = readq(&bar0->mac_cfg);
4824 sp->promisc_flg = 0;
4825 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4829 /* Update individual M_CAST address list */
4830 if ((!sp->m_cast_flg) && dev->mc_count) {
4832 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4833 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4835 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4836 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4840 prev_cnt = sp->mc_addr_count;
4841 sp->mc_addr_count = dev->mc_count;
4843 /* Clear out the previous list of Mc in the H/W. */
4844 for (i = 0; i < prev_cnt; i++) {
4845 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4846 &bar0->rmac_addr_data0_mem);
4847 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4848 &bar0->rmac_addr_data1_mem);
4849 val64 = RMAC_ADDR_CMD_MEM_WE |
4850 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4851 RMAC_ADDR_CMD_MEM_OFFSET
4852 (MAC_MC_ADDR_START_OFFSET + i);
4853 writeq(val64, &bar0->rmac_addr_cmd_mem);
4855 /* Wait for command completes */
4856 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4857 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4859 DBG_PRINT(ERR_DBG, "%s: Adding ",
4861 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4866 /* Create the new Rx filter list and update the same in H/W. */
4867 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4868 i++, mclist = mclist->next) {
4869 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4872 for (j = 0; j < ETH_ALEN; j++) {
4873 mac_addr |= mclist->dmi_addr[j];
4877 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4878 &bar0->rmac_addr_data0_mem);
4879 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4880 &bar0->rmac_addr_data1_mem);
4881 val64 = RMAC_ADDR_CMD_MEM_WE |
4882 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4883 RMAC_ADDR_CMD_MEM_OFFSET
4884 (i + MAC_MC_ADDR_START_OFFSET);
4885 writeq(val64, &bar0->rmac_addr_cmd_mem);
4887 /* Wait for command completes */
4888 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4889 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4891 DBG_PRINT(ERR_DBG, "%s: Adding ",
4893 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4901 * s2io_set_mac_addr - Programs the Xframe mac address
4902 * @dev : pointer to the device structure.
4903 * @addr: a uchar pointer to the new mac address which is to be set.
4904 * Description : This procedure will program the Xframe to receive
4905 * frames with new Mac Address
4906 * Return value: SUCCESS on success and an appropriate (-)ve integer
4907 * as defined in errno.h file on failure.
4910 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4912 struct s2io_nic *sp = dev->priv;
4913 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4914 register u64 val64, mac_addr = 0;
4916 u64 old_mac_addr = 0;
4919 * Set the new MAC address as the new unicast filter and reflect this
4920 * change on the device address registered with the OS. It will be
4923 for (i = 0; i < ETH_ALEN; i++) {
4925 mac_addr |= addr[i];
4927 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4933 /* Update the internal structure with this new mac address */
4934 if(mac_addr != old_mac_addr) {
4935 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4936 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4937 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4938 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4939 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4940 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4941 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
4944 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4945 &bar0->rmac_addr_data0_mem);
4948 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4949 RMAC_ADDR_CMD_MEM_OFFSET(0);
4950 writeq(val64, &bar0->rmac_addr_cmd_mem);
4951 /* Wait till command completes */
4952 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4953 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
4954 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4962 * s2io_ethtool_sset - Sets different link parameters.
4963 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4964 * @info: pointer to the structure with parameters given by ethtool to set
4967 * The function sets different link parameters provided by the user onto
4973 static int s2io_ethtool_sset(struct net_device *dev,
4974 struct ethtool_cmd *info)
4976 struct s2io_nic *sp = dev->priv;
4977 if ((info->autoneg == AUTONEG_ENABLE) ||
4978 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4981 s2io_close(sp->dev);
4989 * s2io_ethtol_gset - Return link specific information.
4990 * @sp : private member of the device structure, pointer to the
4991 * s2io_nic structure.
4992 * @info : pointer to the structure with parameters given by ethtool
4993 * to return link information.
4995 * Returns link specific information like speed, duplex etc.. to ethtool.
4997 * return 0 on success.
5000 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5002 struct s2io_nic *sp = dev->priv;
5003 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5004 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5005 info->port = PORT_FIBRE;
5006 /* info->transceiver?? TODO */
5008 if (netif_carrier_ok(sp->dev)) {
5009 info->speed = 10000;
5010 info->duplex = DUPLEX_FULL;
5016 info->autoneg = AUTONEG_DISABLE;
5021 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5022 * @sp : private member of the device structure, which is a pointer to the
5023 * s2io_nic structure.
5024 * @info : pointer to the structure with parameters given by ethtool to
5025 * return driver information.
5027 * Returns driver specefic information like name, version etc.. to ethtool.
5032 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5033 struct ethtool_drvinfo *info)
5035 struct s2io_nic *sp = dev->priv;
5037 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5038 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5039 strncpy(info->fw_version, "", sizeof(info->fw_version));
5040 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5041 info->regdump_len = XENA_REG_SPACE;
5042 info->eedump_len = XENA_EEPROM_SPACE;
5046 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5047 * @sp: private member of the device structure, which is a pointer to the
5048 * s2io_nic structure.
5049 * @regs : pointer to the structure with parameters given by ethtool for
5050 * dumping the registers.
5051 * @reg_space: The input argumnet into which all the registers are dumped.
5053 * Dumps the entire register space of xFrame NIC into the user given
5059 static void s2io_ethtool_gregs(struct net_device *dev,
5060 struct ethtool_regs *regs, void *space)
5064 u8 *reg_space = (u8 *) space;
5065 struct s2io_nic *sp = dev->priv;
5067 regs->len = XENA_REG_SPACE;
5068 regs->version = sp->pdev->subsystem_device;
5070 for (i = 0; i < regs->len; i += 8) {
5071 reg = readq(sp->bar0 + i);
5072 memcpy((reg_space + i), ®, 8);
5077 * s2io_phy_id - timer function that alternates adapter LED.
5078 * @data : address of the private member of the device structure, which
5079 * is a pointer to the s2io_nic structure, provided as an u32.
5080 * Description: This is actually the timer function that alternates the
5081 * adapter LED bit of the adapter control bit to set/reset every time on
5082 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5083 * once every second.
5085 static void s2io_phy_id(unsigned long data)
5087 struct s2io_nic *sp = (struct s2io_nic *) data;
5088 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5092 subid = sp->pdev->subsystem_device;
5093 if ((sp->device_type == XFRAME_II_DEVICE) ||
5094 ((subid & 0xFF) >= 0x07)) {
5095 val64 = readq(&bar0->gpio_control);
5096 val64 ^= GPIO_CTRL_GPIO_0;
5097 writeq(val64, &bar0->gpio_control);
5099 val64 = readq(&bar0->adapter_control);
5100 val64 ^= ADAPTER_LED_ON;
5101 writeq(val64, &bar0->adapter_control);
5104 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5108 * s2io_ethtool_idnic - To physically identify the nic on the system.
5109 * @sp : private member of the device structure, which is a pointer to the
5110 * s2io_nic structure.
5111 * @id : pointer to the structure with identification parameters given by
5113 * Description: Used to physically identify the NIC on the system.
5114 * The Link LED will blink for a time specified by the user for
5116 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5117 * identification is possible only if it's link is up.
5119 * int , returns 0 on success
5122 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5124 u64 val64 = 0, last_gpio_ctrl_val;
5125 struct s2io_nic *sp = dev->priv;
5126 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5129 subid = sp->pdev->subsystem_device;
5130 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5131 if ((sp->device_type == XFRAME_I_DEVICE) &&
5132 ((subid & 0xFF) < 0x07)) {
5133 val64 = readq(&bar0->adapter_control);
5134 if (!(val64 & ADAPTER_CNTL_EN)) {
5136 "Adapter Link down, cannot blink LED\n");
5140 if (sp->id_timer.function == NULL) {
5141 init_timer(&sp->id_timer);
5142 sp->id_timer.function = s2io_phy_id;
5143 sp->id_timer.data = (unsigned long) sp;
5145 mod_timer(&sp->id_timer, jiffies);
5147 msleep_interruptible(data * HZ);
5149 msleep_interruptible(MAX_FLICKER_TIME);
5150 del_timer_sync(&sp->id_timer);
5152 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5153 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5154 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5160 static void s2io_ethtool_gringparam(struct net_device *dev,
5161 struct ethtool_ringparam *ering)
5163 struct s2io_nic *sp = dev->priv;
5164 int i,tx_desc_count=0,rx_desc_count=0;
5166 if (sp->rxd_mode == RXD_MODE_1)
5167 ering->rx_max_pending = MAX_RX_DESC_1;
5168 else if (sp->rxd_mode == RXD_MODE_3B)
5169 ering->rx_max_pending = MAX_RX_DESC_2;
5171 ering->tx_max_pending = MAX_TX_DESC;
5172 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5173 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5175 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5176 ering->tx_pending = tx_desc_count;
5178 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5179 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5181 ering->rx_pending = rx_desc_count;
5183 ering->rx_mini_max_pending = 0;
5184 ering->rx_mini_pending = 0;
5185 if(sp->rxd_mode == RXD_MODE_1)
5186 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5187 else if (sp->rxd_mode == RXD_MODE_3B)
5188 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5189 ering->rx_jumbo_pending = rx_desc_count;
5193 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5194 * @sp : private member of the device structure, which is a pointer to the
5195 * s2io_nic structure.
5196 * @ep : pointer to the structure with pause parameters given by ethtool.
5198 * Returns the Pause frame generation and reception capability of the NIC.
5202 static void s2io_ethtool_getpause_data(struct net_device *dev,
5203 struct ethtool_pauseparam *ep)
5206 struct s2io_nic *sp = dev->priv;
5207 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5209 val64 = readq(&bar0->rmac_pause_cfg);
5210 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5211 ep->tx_pause = TRUE;
5212 if (val64 & RMAC_PAUSE_RX_ENABLE)
5213 ep->rx_pause = TRUE;
5214 ep->autoneg = FALSE;
5218 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5219 * @sp : private member of the device structure, which is a pointer to the
5220 * s2io_nic structure.
5221 * @ep : pointer to the structure with pause parameters given by ethtool.
5223 * It can be used to set or reset Pause frame generation or reception
5224 * support of the NIC.
5226 * int, returns 0 on Success
5229 static int s2io_ethtool_setpause_data(struct net_device *dev,
5230 struct ethtool_pauseparam *ep)
5233 struct s2io_nic *sp = dev->priv;
5234 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5236 val64 = readq(&bar0->rmac_pause_cfg);
5238 val64 |= RMAC_PAUSE_GEN_ENABLE;
5240 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5242 val64 |= RMAC_PAUSE_RX_ENABLE;
5244 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5245 writeq(val64, &bar0->rmac_pause_cfg);
5250 * read_eeprom - reads 4 bytes of data from user given offset.
5251 * @sp : private member of the device structure, which is a pointer to the
5252 * s2io_nic structure.
5253 * @off : offset at which the data must be written
5254 * @data : Its an output parameter where the data read at the given
5257 * Will read 4 bytes of data from the user given offset and return the
5259 * NOTE: Will allow to read only part of the EEPROM visible through the
5262 * -1 on failure and 0 on success.
5265 #define S2IO_DEV_ID 5
5266 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5271 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5273 if (sp->device_type == XFRAME_I_DEVICE) {
5274 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5275 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5276 I2C_CONTROL_CNTL_START;
5277 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5279 while (exit_cnt < 5) {
5280 val64 = readq(&bar0->i2c_control);
5281 if (I2C_CONTROL_CNTL_END(val64)) {
5282 *data = I2C_CONTROL_GET_DATA(val64);
5291 if (sp->device_type == XFRAME_II_DEVICE) {
5292 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5293 SPI_CONTROL_BYTECNT(0x3) |
5294 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5295 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5296 val64 |= SPI_CONTROL_REQ;
5297 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5298 while (exit_cnt < 5) {
5299 val64 = readq(&bar0->spi_control);
5300 if (val64 & SPI_CONTROL_NACK) {
5303 } else if (val64 & SPI_CONTROL_DONE) {
5304 *data = readq(&bar0->spi_data);
5317 * write_eeprom - actually writes the relevant part of the data value.
5318 * @sp : private member of the device structure, which is a pointer to the
5319 * s2io_nic structure.
5320 * @off : offset at which the data must be written
5321 * @data : The data that is to be written
5322 * @cnt : Number of bytes of the data that are actually to be written into
5323 * the Eeprom. (max of 3)
5325 * Actually writes the relevant part of the data value into the Eeprom
5326 * through the I2C bus.
5328 * 0 on success, -1 on failure.
5331 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5333 int exit_cnt = 0, ret = -1;
5335 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5337 if (sp->device_type == XFRAME_I_DEVICE) {
5338 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5339 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5340 I2C_CONTROL_CNTL_START;
5341 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5343 while (exit_cnt < 5) {
5344 val64 = readq(&bar0->i2c_control);
5345 if (I2C_CONTROL_CNTL_END(val64)) {
5346 if (!(val64 & I2C_CONTROL_NACK))
5355 if (sp->device_type == XFRAME_II_DEVICE) {
5356 int write_cnt = (cnt == 8) ? 0 : cnt;
5357 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5359 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5360 SPI_CONTROL_BYTECNT(write_cnt) |
5361 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5362 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5363 val64 |= SPI_CONTROL_REQ;
5364 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5365 while (exit_cnt < 5) {
5366 val64 = readq(&bar0->spi_control);
5367 if (val64 & SPI_CONTROL_NACK) {
5370 } else if (val64 & SPI_CONTROL_DONE) {
5380 static void s2io_vpd_read(struct s2io_nic *nic)
5384 int i=0, cnt, fail = 0;
5385 int vpd_addr = 0x80;
5387 if (nic->device_type == XFRAME_II_DEVICE) {
5388 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5392 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5395 strcpy(nic->serial_num, "NOT AVAILABLE");
5397 vpd_data = kmalloc(256, GFP_KERNEL);
5399 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5402 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5404 for (i = 0; i < 256; i +=4 ) {
5405 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5406 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5407 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5408 for (cnt = 0; cnt <5; cnt++) {
5410 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5415 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5419 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5420 (u32 *)&vpd_data[i]);
5424 /* read serial number of adapter */
5425 for (cnt = 0; cnt < 256; cnt++) {
5426 if ((vpd_data[cnt] == 'S') &&
5427 (vpd_data[cnt+1] == 'N') &&
5428 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5429 memset(nic->serial_num, 0, VPD_STRING_LEN);
5430 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5437 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5438 memset(nic->product_name, 0, vpd_data[1]);
5439 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5442 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5446 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5447 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5448 * @eeprom : pointer to the user level structure provided by ethtool,
5449 * containing all relevant information.
5450 * @data_buf : user defined value to be written into Eeprom.
5451 * Description: Reads the values stored in the Eeprom at given offset
5452 * for a given length. Stores these values int the input argument data
5453 * buffer 'data_buf' and returns these to the caller (ethtool.)
5458 static int s2io_ethtool_geeprom(struct net_device *dev,
5459 struct ethtool_eeprom *eeprom, u8 * data_buf)
5463 struct s2io_nic *sp = dev->priv;
5465 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5467 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5468 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5470 for (i = 0; i < eeprom->len; i += 4) {
5471 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5472 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5476 memcpy((data_buf + i), &valid, 4);
5482 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5483 * @sp : private member of the device structure, which is a pointer to the
5484 * s2io_nic structure.
5485 * @eeprom : pointer to the user level structure provided by ethtool,
5486 * containing all relevant information.
5487 * @data_buf ; user defined value to be written into Eeprom.
5489 * Tries to write the user provided value in the Eeprom, at the offset
5490 * given by the user.
5492 * 0 on success, -EFAULT on failure.
5495 static int s2io_ethtool_seeprom(struct net_device *dev,
5496 struct ethtool_eeprom *eeprom,
5499 int len = eeprom->len, cnt = 0;
5500 u64 valid = 0, data;
5501 struct s2io_nic *sp = dev->priv;
5503 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5505 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5506 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5512 data = (u32) data_buf[cnt] & 0x000000FF;
5514 valid = (u32) (data << 24);
5518 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5520 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5522 "write into the specified offset\n");
5533 * s2io_register_test - reads and writes into all clock domains.
5534 * @sp : private member of the device structure, which is a pointer to the
5535 * s2io_nic structure.
5536 * @data : variable that returns the result of each of the test conducted b
5539 * Read and write into all clock domains. The NIC has 3 clock domains,
5540 * see that registers in all the three regions are accessible.
5545 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5547 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5548 u64 val64 = 0, exp_val;
5551 val64 = readq(&bar0->pif_rd_swapper_fb);
5552 if (val64 != 0x123456789abcdefULL) {
5554 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5557 val64 = readq(&bar0->rmac_pause_cfg);
5558 if (val64 != 0xc000ffff00000000ULL) {
5560 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5563 val64 = readq(&bar0->rx_queue_cfg);
5564 if (sp->device_type == XFRAME_II_DEVICE)
5565 exp_val = 0x0404040404040404ULL;
5567 exp_val = 0x0808080808080808ULL;
5568 if (val64 != exp_val) {
5570 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5573 val64 = readq(&bar0->xgxs_efifo_cfg);
5574 if (val64 != 0x000000001923141EULL) {
5576 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5579 val64 = 0x5A5A5A5A5A5A5A5AULL;
5580 writeq(val64, &bar0->xmsi_data);
5581 val64 = readq(&bar0->xmsi_data);
5582 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5584 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5587 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5588 writeq(val64, &bar0->xmsi_data);
5589 val64 = readq(&bar0->xmsi_data);
5590 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5592 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5600 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5601 * @sp : private member of the device structure, which is a pointer to the
5602 * s2io_nic structure.
5603 * @data:variable that returns the result of each of the test conducted by
5606 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5612 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5615 u64 ret_data, org_4F0, org_7F0;
5616 u8 saved_4F0 = 0, saved_7F0 = 0;
5617 struct net_device *dev = sp->dev;
5619 /* Test Write Error at offset 0 */
5620 /* Note that SPI interface allows write access to all areas
5621 * of EEPROM. Hence doing all negative testing only for Xframe I.
5623 if (sp->device_type == XFRAME_I_DEVICE)
5624 if (!write_eeprom(sp, 0, 0, 3))
5627 /* Save current values at offsets 0x4F0 and 0x7F0 */
5628 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5630 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5633 /* Test Write at offset 4f0 */
5634 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5636 if (read_eeprom(sp, 0x4F0, &ret_data))
5639 if (ret_data != 0x012345) {
5640 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5641 "Data written %llx Data read %llx\n",
5642 dev->name, (unsigned long long)0x12345,
5643 (unsigned long long)ret_data);
5647 /* Reset the EEPROM data go FFFF */
5648 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5650 /* Test Write Request Error at offset 0x7c */
5651 if (sp->device_type == XFRAME_I_DEVICE)
5652 if (!write_eeprom(sp, 0x07C, 0, 3))
5655 /* Test Write Request at offset 0x7f0 */
5656 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5658 if (read_eeprom(sp, 0x7F0, &ret_data))
5661 if (ret_data != 0x012345) {
5662 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5663 "Data written %llx Data read %llx\n",
5664 dev->name, (unsigned long long)0x12345,
5665 (unsigned long long)ret_data);
5669 /* Reset the EEPROM data go FFFF */
5670 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5672 if (sp->device_type == XFRAME_I_DEVICE) {
5673 /* Test Write Error at offset 0x80 */
5674 if (!write_eeprom(sp, 0x080, 0, 3))
5677 /* Test Write Error at offset 0xfc */
5678 if (!write_eeprom(sp, 0x0FC, 0, 3))
5681 /* Test Write Error at offset 0x100 */
5682 if (!write_eeprom(sp, 0x100, 0, 3))
5685 /* Test Write Error at offset 4ec */
5686 if (!write_eeprom(sp, 0x4EC, 0, 3))
5690 /* Restore values at offsets 0x4F0 and 0x7F0 */
5692 write_eeprom(sp, 0x4F0, org_4F0, 3);
5694 write_eeprom(sp, 0x7F0, org_7F0, 3);
5701 * s2io_bist_test - invokes the MemBist test of the card .
5702 * @sp : private member of the device structure, which is a pointer to the
5703 * s2io_nic structure.
5704 * @data:variable that returns the result of each of the test conducted by
5707 * This invokes the MemBist test of the card. We give around
5708 * 2 secs time for the Test to complete. If it's still not complete
5709 * within this peiod, we consider that the test failed.
5711 * 0 on success and -1 on failure.
5714 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5717 int cnt = 0, ret = -1;
5719 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5720 bist |= PCI_BIST_START;
5721 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5724 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5725 if (!(bist & PCI_BIST_START)) {
5726 *data = (bist & PCI_BIST_CODE_MASK);
5738 * s2io-link_test - verifies the link state of the nic
5739 * @sp ; private member of the device structure, which is a pointer to the
5740 * s2io_nic structure.
5741 * @data: variable that returns the result of each of the test conducted by
5744 * The function verifies the link state of the NIC and updates the input
5745 * argument 'data' appropriately.
5750 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5752 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5755 val64 = readq(&bar0->adapter_status);
5756 if(!(LINK_IS_UP(val64)))
5765 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5766 * @sp - private member of the device structure, which is a pointer to the
5767 * s2io_nic structure.
5768 * @data - variable that returns the result of each of the test
5769 * conducted by the driver.
5771 * This is one of the offline test that tests the read and write
5772 * access to the RldRam chip on the NIC.
5777 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5779 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5781 int cnt, iteration = 0, test_fail = 0;
5783 val64 = readq(&bar0->adapter_control);
5784 val64 &= ~ADAPTER_ECC_EN;
5785 writeq(val64, &bar0->adapter_control);
5787 val64 = readq(&bar0->mc_rldram_test_ctrl);
5788 val64 |= MC_RLDRAM_TEST_MODE;
5789 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5791 val64 = readq(&bar0->mc_rldram_mrs);
5792 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5793 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5795 val64 |= MC_RLDRAM_MRS_ENABLE;
5796 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5798 while (iteration < 2) {
5799 val64 = 0x55555555aaaa0000ULL;
5800 if (iteration == 1) {
5801 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5803 writeq(val64, &bar0->mc_rldram_test_d0);
5805 val64 = 0xaaaa5a5555550000ULL;
5806 if (iteration == 1) {
5807 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5809 writeq(val64, &bar0->mc_rldram_test_d1);
5811 val64 = 0x55aaaaaaaa5a0000ULL;
5812 if (iteration == 1) {
5813 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5815 writeq(val64, &bar0->mc_rldram_test_d2);
5817 val64 = (u64) (0x0000003ffffe0100ULL);
5818 writeq(val64, &bar0->mc_rldram_test_add);
5820 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5822 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5824 for (cnt = 0; cnt < 5; cnt++) {
5825 val64 = readq(&bar0->mc_rldram_test_ctrl);
5826 if (val64 & MC_RLDRAM_TEST_DONE)
5834 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5835 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5837 for (cnt = 0; cnt < 5; cnt++) {
5838 val64 = readq(&bar0->mc_rldram_test_ctrl);
5839 if (val64 & MC_RLDRAM_TEST_DONE)
5847 val64 = readq(&bar0->mc_rldram_test_ctrl);
5848 if (!(val64 & MC_RLDRAM_TEST_PASS))
5856 /* Bring the adapter out of test mode */
5857 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5863 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5864 * @sp : private member of the device structure, which is a pointer to the
5865 * s2io_nic structure.
5866 * @ethtest : pointer to a ethtool command specific structure that will be
5867 * returned to the user.
5868 * @data : variable that returns the result of each of the test
5869 * conducted by the driver.
5871 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5872 * the health of the card.
5877 static void s2io_ethtool_test(struct net_device *dev,
5878 struct ethtool_test *ethtest,
5881 struct s2io_nic *sp = dev->priv;
5882 int orig_state = netif_running(sp->dev);
5884 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5885 /* Offline Tests. */
5887 s2io_close(sp->dev);
5889 if (s2io_register_test(sp, &data[0]))
5890 ethtest->flags |= ETH_TEST_FL_FAILED;
5894 if (s2io_rldram_test(sp, &data[3]))
5895 ethtest->flags |= ETH_TEST_FL_FAILED;
5899 if (s2io_eeprom_test(sp, &data[1]))
5900 ethtest->flags |= ETH_TEST_FL_FAILED;
5902 if (s2io_bist_test(sp, &data[4]))
5903 ethtest->flags |= ETH_TEST_FL_FAILED;
5913 "%s: is not up, cannot run test\n",
5922 if (s2io_link_test(sp, &data[2]))
5923 ethtest->flags |= ETH_TEST_FL_FAILED;
5932 static void s2io_get_ethtool_stats(struct net_device *dev,
5933 struct ethtool_stats *estats,
5937 struct s2io_nic *sp = dev->priv;
5938 struct stat_block *stat_info = sp->mac_control.stats_info;
5940 s2io_updt_stats(sp);
5942 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5943 le32_to_cpu(stat_info->tmac_frms);
5945 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5946 le32_to_cpu(stat_info->tmac_data_octets);
5947 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5949 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5950 le32_to_cpu(stat_info->tmac_mcst_frms);
5952 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5953 le32_to_cpu(stat_info->tmac_bcst_frms);
5954 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5956 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5957 le32_to_cpu(stat_info->tmac_ttl_octets);
5959 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5960 le32_to_cpu(stat_info->tmac_ucst_frms);
5962 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5963 le32_to_cpu(stat_info->tmac_nucst_frms);
5965 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5966 le32_to_cpu(stat_info->tmac_any_err_frms);
5967 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5968 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5970 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5971 le32_to_cpu(stat_info->tmac_vld_ip);
5973 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5974 le32_to_cpu(stat_info->tmac_drop_ip);
5976 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5977 le32_to_cpu(stat_info->tmac_icmp);
5979 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5980 le32_to_cpu(stat_info->tmac_rst_tcp);
5981 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5982 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5983 le32_to_cpu(stat_info->tmac_udp);
5985 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5986 le32_to_cpu(stat_info->rmac_vld_frms);
5988 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5989 le32_to_cpu(stat_info->rmac_data_octets);
5990 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5991 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5993 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5994 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5996 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5997 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5998 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5999 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6000 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6001 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6002 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6004 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6005 le32_to_cpu(stat_info->rmac_ttl_octets);
6007 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6008 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6010 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6011 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6013 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6014 le32_to_cpu(stat_info->rmac_discarded_frms);
6016 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6017 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6018 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6019 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6021 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6022 le32_to_cpu(stat_info->rmac_usized_frms);
6024 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6025 le32_to_cpu(stat_info->rmac_osized_frms);
6027 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6028 le32_to_cpu(stat_info->rmac_frag_frms);
6030 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6031 le32_to_cpu(stat_info->rmac_jabber_frms);
6032 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6033 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6034 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6035 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6036 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6037 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6039 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6040 le32_to_cpu(stat_info->rmac_ip);
6041 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6042 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6044 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6045 le32_to_cpu(stat_info->rmac_drop_ip);
6047 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6048 le32_to_cpu(stat_info->rmac_icmp);
6049 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6051 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6052 le32_to_cpu(stat_info->rmac_udp);
6054 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6055 le32_to_cpu(stat_info->rmac_err_drp_udp);
6056 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6057 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6058 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6059 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6060 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6061 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6062 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6063 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6064 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6065 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6066 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6067 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6068 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6069 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6070 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6071 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6072 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6074 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6075 le32_to_cpu(stat_info->rmac_pause_cnt);
6076 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6077 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6079 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6080 le32_to_cpu(stat_info->rmac_accepted_ip);
6081 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6082 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6083 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6084 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6085 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6086 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6087 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6088 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6089 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6090 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6091 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6092 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6093 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6094 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6095 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6096 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6097 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6098 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6099 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6101 /* Enhanced statistics exist only for Hercules */
6102 if(sp->device_type == XFRAME_II_DEVICE) {
6104 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6106 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6108 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6109 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6110 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6111 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6112 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6113 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6114 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6115 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6116 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6117 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6118 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6119 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6120 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6121 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6125 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6126 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6127 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6128 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6129 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6130 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6131 for (k = 0; k < MAX_RX_RINGS; k++)
6132 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6133 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6134 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6135 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6136 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6137 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6138 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6139 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6140 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6141 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6142 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6143 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6144 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6145 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6146 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6147 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6148 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6149 if (stat_info->sw_stat.num_aggregations) {
6150 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6153 * Since 64-bit divide does not work on all platforms,
6154 * do repeated subtraction.
6156 while (tmp >= stat_info->sw_stat.num_aggregations) {
6157 tmp -= stat_info->sw_stat.num_aggregations;
6160 tmp_stats[i++] = count;
6164 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6165 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6166 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6167 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6168 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6169 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6170 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6171 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6172 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6174 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6175 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6176 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6177 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6178 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6180 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6181 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6182 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6183 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6184 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6185 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6186 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6187 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6188 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6189 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6190 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6191 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6192 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6193 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6194 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6195 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6196 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6197 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6198 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6199 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6200 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6201 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6202 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6203 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6204 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6205 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6208 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6210 return (XENA_REG_SPACE);
6214 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6216 struct s2io_nic *sp = dev->priv;
6218 return (sp->rx_csum);
6221 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6223 struct s2io_nic *sp = dev->priv;
6233 static int s2io_get_eeprom_len(struct net_device *dev)
6235 return (XENA_EEPROM_SPACE);
6238 static int s2io_get_sset_count(struct net_device *dev, int sset)
6240 struct s2io_nic *sp = dev->priv;
6244 return S2IO_TEST_LEN;
6246 switch(sp->device_type) {
6247 case XFRAME_I_DEVICE:
6248 return XFRAME_I_STAT_LEN;
6249 case XFRAME_II_DEVICE:
6250 return XFRAME_II_STAT_LEN;
6259 static void s2io_ethtool_get_strings(struct net_device *dev,
6260 u32 stringset, u8 * data)
6263 struct s2io_nic *sp = dev->priv;
6265 switch (stringset) {
6267 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6270 stat_size = sizeof(ethtool_xena_stats_keys);
6271 memcpy(data, ðtool_xena_stats_keys,stat_size);
6272 if(sp->device_type == XFRAME_II_DEVICE) {
6273 memcpy(data + stat_size,
6274 ðtool_enhanced_stats_keys,
6275 sizeof(ethtool_enhanced_stats_keys));
6276 stat_size += sizeof(ethtool_enhanced_stats_keys);
6279 memcpy(data + stat_size, ðtool_driver_stats_keys,
6280 sizeof(ethtool_driver_stats_keys));
6284 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6287 dev->features |= NETIF_F_IP_CSUM;
6289 dev->features &= ~NETIF_F_IP_CSUM;
6294 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6296 return (dev->features & NETIF_F_TSO) != 0;
6298 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6301 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6303 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6308 static const struct ethtool_ops netdev_ethtool_ops = {
6309 .get_settings = s2io_ethtool_gset,
6310 .set_settings = s2io_ethtool_sset,
6311 .get_drvinfo = s2io_ethtool_gdrvinfo,
6312 .get_regs_len = s2io_ethtool_get_regs_len,
6313 .get_regs = s2io_ethtool_gregs,
6314 .get_link = ethtool_op_get_link,
6315 .get_eeprom_len = s2io_get_eeprom_len,
6316 .get_eeprom = s2io_ethtool_geeprom,
6317 .set_eeprom = s2io_ethtool_seeprom,
6318 .get_ringparam = s2io_ethtool_gringparam,
6319 .get_pauseparam = s2io_ethtool_getpause_data,
6320 .set_pauseparam = s2io_ethtool_setpause_data,
6321 .get_rx_csum = s2io_ethtool_get_rx_csum,
6322 .set_rx_csum = s2io_ethtool_set_rx_csum,
6323 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6324 .set_sg = ethtool_op_set_sg,
6325 .get_tso = s2io_ethtool_op_get_tso,
6326 .set_tso = s2io_ethtool_op_set_tso,
6327 .set_ufo = ethtool_op_set_ufo,
6328 .self_test = s2io_ethtool_test,
6329 .get_strings = s2io_ethtool_get_strings,
6330 .phys_id = s2io_ethtool_idnic,
6331 .get_ethtool_stats = s2io_get_ethtool_stats,
6332 .get_sset_count = s2io_get_sset_count,
6336 * s2io_ioctl - Entry point for the Ioctl
6337 * @dev : Device pointer.
6338 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6339 * a proprietary structure used to pass information to the driver.
6340 * @cmd : This is used to distinguish between the different commands that
6341 * can be passed to the IOCTL functions.
6343 * Currently there are no special functionality supported in IOCTL, hence
6344 * function always return EOPNOTSUPPORTED
6347 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6353 * s2io_change_mtu - entry point to change MTU size for the device.
6354 * @dev : device pointer.
6355 * @new_mtu : the new MTU size for the device.
6356 * Description: A driver entry point to change MTU size for the device.
6357 * Before changing the MTU the device must be stopped.
6359 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6363 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6365 struct s2io_nic *sp = dev->priv;
6367 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6368 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6374 if (netif_running(dev)) {
6376 netif_stop_queue(dev);
6377 if (s2io_card_up(sp)) {
6378 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6381 if (netif_queue_stopped(dev))
6382 netif_wake_queue(dev);
6383 } else { /* Device is down */
6384 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6385 u64 val64 = new_mtu;
6387 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6394 * s2io_tasklet - Bottom half of the ISR.
6395 * @dev_adr : address of the device structure in dma_addr_t format.
6397 * This is the tasklet or the bottom half of the ISR. This is
6398 * an extension of the ISR which is scheduled by the scheduler to be run
6399 * when the load on the CPU is low. All low priority tasks of the ISR can
6400 * be pushed into the tasklet. For now the tasklet is used only to
6401 * replenish the Rx buffers in the Rx buffer descriptors.
6406 static void s2io_tasklet(unsigned long dev_addr)
6408 struct net_device *dev = (struct net_device *) dev_addr;
6409 struct s2io_nic *sp = dev->priv;
6411 struct mac_info *mac_control;
6412 struct config_param *config;
6414 mac_control = &sp->mac_control;
6415 config = &sp->config;
6417 if (!TASKLET_IN_USE) {
6418 for (i = 0; i < config->rx_ring_num; i++) {
6419 ret = fill_rx_buffers(sp, i);
6420 if (ret == -ENOMEM) {
6421 DBG_PRINT(INFO_DBG, "%s: Out of ",
6423 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6425 } else if (ret == -EFILL) {
6427 "%s: Rx Ring %d is full\n",
6432 clear_bit(0, (&sp->tasklet_status));
6437 * s2io_set_link - Set the LInk status
6438 * @data: long pointer to device private structue
6439 * Description: Sets the link status for the adapter
6442 static void s2io_set_link(struct work_struct *work)
6444 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6445 struct net_device *dev = nic->dev;
6446 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6452 if (!netif_running(dev))
6455 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6456 /* The card is being reset, no point doing anything */
6460 subid = nic->pdev->subsystem_device;
6461 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6463 * Allow a small delay for the NICs self initiated
6464 * cleanup to complete.
6469 val64 = readq(&bar0->adapter_status);
6470 if (LINK_IS_UP(val64)) {
6471 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6472 if (verify_xena_quiescence(nic)) {
6473 val64 = readq(&bar0->adapter_control);
6474 val64 |= ADAPTER_CNTL_EN;
6475 writeq(val64, &bar0->adapter_control);
6476 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6477 nic->device_type, subid)) {
6478 val64 = readq(&bar0->gpio_control);
6479 val64 |= GPIO_CTRL_GPIO_0;
6480 writeq(val64, &bar0->gpio_control);
6481 val64 = readq(&bar0->gpio_control);
6483 val64 |= ADAPTER_LED_ON;
6484 writeq(val64, &bar0->adapter_control);
6486 nic->device_enabled_once = TRUE;
6488 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6489 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6490 netif_stop_queue(dev);
6493 val64 = readq(&bar0->adapter_control);
6494 val64 |= ADAPTER_LED_ON;
6495 writeq(val64, &bar0->adapter_control);
6496 s2io_link(nic, LINK_UP);
6498 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6500 val64 = readq(&bar0->gpio_control);
6501 val64 &= ~GPIO_CTRL_GPIO_0;
6502 writeq(val64, &bar0->gpio_control);
6503 val64 = readq(&bar0->gpio_control);
6506 val64 = readq(&bar0->adapter_control);
6507 val64 = val64 &(~ADAPTER_LED_ON);
6508 writeq(val64, &bar0->adapter_control);
6509 s2io_link(nic, LINK_DOWN);
6511 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6517 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6519 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6520 u64 *temp2, int size)
6522 struct net_device *dev = sp->dev;
6523 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6525 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6526 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6529 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6531 * As Rx frame are not going to be processed,
6532 * using same mapped address for the Rxd
6535 rxdp1->Buffer0_ptr = *temp0;
6537 *skb = dev_alloc_skb(size);
6539 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6540 DBG_PRINT(INFO_DBG, "memory to allocate ");
6541 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6542 sp->mac_control.stats_info->sw_stat. \
6543 mem_alloc_fail_cnt++;
6546 sp->mac_control.stats_info->sw_stat.mem_allocated
6547 += (*skb)->truesize;
6548 /* storing the mapped addr in a temp variable
6549 * such it will be used for next rxd whose
6550 * Host Control is NULL
6552 rxdp1->Buffer0_ptr = *temp0 =
6553 pci_map_single( sp->pdev, (*skb)->data,
6554 size - NET_IP_ALIGN,
6555 PCI_DMA_FROMDEVICE);
6556 if( (rxdp1->Buffer0_ptr == 0) ||
6557 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6558 goto memalloc_failed;
6560 rxdp->Host_Control = (unsigned long) (*skb);
6562 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6563 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6564 /* Two buffer Mode */
6566 rxdp3->Buffer2_ptr = *temp2;
6567 rxdp3->Buffer0_ptr = *temp0;
6568 rxdp3->Buffer1_ptr = *temp1;
6570 *skb = dev_alloc_skb(size);
6572 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6573 DBG_PRINT(INFO_DBG, "memory to allocate ");
6574 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6575 sp->mac_control.stats_info->sw_stat. \
6576 mem_alloc_fail_cnt++;
6579 sp->mac_control.stats_info->sw_stat.mem_allocated
6580 += (*skb)->truesize;
6581 rxdp3->Buffer2_ptr = *temp2 =
6582 pci_map_single(sp->pdev, (*skb)->data,
6584 PCI_DMA_FROMDEVICE);
6585 if( (rxdp3->Buffer2_ptr == 0) ||
6586 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6587 goto memalloc_failed;
6589 rxdp3->Buffer0_ptr = *temp0 =
6590 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6591 PCI_DMA_FROMDEVICE);
6592 if( (rxdp3->Buffer0_ptr == 0) ||
6593 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6594 pci_unmap_single (sp->pdev,
6595 (dma_addr_t)rxdp3->Buffer2_ptr,
6596 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6597 goto memalloc_failed;
6599 rxdp->Host_Control = (unsigned long) (*skb);
6601 /* Buffer-1 will be dummy buffer not used */
6602 rxdp3->Buffer1_ptr = *temp1 =
6603 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6604 PCI_DMA_FROMDEVICE);
6605 if( (rxdp3->Buffer1_ptr == 0) ||
6606 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6607 pci_unmap_single (sp->pdev,
6608 (dma_addr_t)rxdp3->Buffer0_ptr,
6609 BUF0_LEN, PCI_DMA_FROMDEVICE);
6610 pci_unmap_single (sp->pdev,
6611 (dma_addr_t)rxdp3->Buffer2_ptr,
6612 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6613 goto memalloc_failed;
6619 stats->pci_map_fail_cnt++;
6620 stats->mem_freed += (*skb)->truesize;
6621 dev_kfree_skb(*skb);
6625 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6628 struct net_device *dev = sp->dev;
6629 if (sp->rxd_mode == RXD_MODE_1) {
6630 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6631 } else if (sp->rxd_mode == RXD_MODE_3B) {
6632 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6633 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6634 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6638 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6640 int i, j, k, blk_cnt = 0, size;
6641 struct mac_info * mac_control = &sp->mac_control;
6642 struct config_param *config = &sp->config;
6643 struct net_device *dev = sp->dev;
6644 struct RxD_t *rxdp = NULL;
6645 struct sk_buff *skb = NULL;
6646 struct buffAdd *ba = NULL;
6647 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6649 /* Calculate the size based on ring mode */
6650 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6651 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6652 if (sp->rxd_mode == RXD_MODE_1)
6653 size += NET_IP_ALIGN;
6654 else if (sp->rxd_mode == RXD_MODE_3B)
6655 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6657 for (i = 0; i < config->rx_ring_num; i++) {
6658 blk_cnt = config->rx_cfg[i].num_rxd /
6659 (rxd_count[sp->rxd_mode] +1);
6661 for (j = 0; j < blk_cnt; j++) {
6662 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6663 rxdp = mac_control->rings[i].
6664 rx_blocks[j].rxds[k].virt_addr;
6665 if(sp->rxd_mode == RXD_MODE_3B)
6666 ba = &mac_control->rings[i].ba[j][k];
6667 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6668 &skb,(u64 *)&temp0_64,
6675 set_rxd_buffer_size(sp, rxdp, size);
6677 /* flip the Ownership bit to Hardware */
6678 rxdp->Control_1 |= RXD_OWN_XENA;
6686 static int s2io_add_isr(struct s2io_nic * sp)
6689 struct net_device *dev = sp->dev;
6692 if (sp->config.intr_type == MSI_X)
6693 ret = s2io_enable_msi_x(sp);
6695 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6696 sp->config.intr_type = INTA;
6699 /* Store the values of the MSIX table in the struct s2io_nic structure */
6700 store_xmsi_data(sp);
6702 /* After proper initialization of H/W, register ISR */
6703 if (sp->config.intr_type == MSI_X) {
6704 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6706 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6707 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6708 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6710 err = request_irq(sp->entries[i].vector,
6711 s2io_msix_fifo_handle, 0, sp->desc[i],
6712 sp->s2io_entries[i].arg);
6713 /* If either data or addr is zero print it */
6714 if(!(sp->msix_info[i].addr &&
6715 sp->msix_info[i].data)) {
6716 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6717 "Data:0x%lx\n",sp->desc[i],
6718 (unsigned long long)
6719 sp->msix_info[i].addr,
6721 ntohl(sp->msix_info[i].data));
6726 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6728 err = request_irq(sp->entries[i].vector,
6729 s2io_msix_ring_handle, 0, sp->desc[i],
6730 sp->s2io_entries[i].arg);
6731 /* If either data or addr is zero print it */
6732 if(!(sp->msix_info[i].addr &&
6733 sp->msix_info[i].data)) {
6734 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6735 "Data:0x%lx\n",sp->desc[i],
6736 (unsigned long long)
6737 sp->msix_info[i].addr,
6739 ntohl(sp->msix_info[i].data));
6745 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6746 "failed\n", dev->name, i);
6747 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6750 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6752 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6753 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
6755 if (sp->config.intr_type == INTA) {
6756 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6759 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6766 static void s2io_rem_isr(struct s2io_nic * sp)
6768 struct net_device *dev = sp->dev;
6769 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6771 if (sp->config.intr_type == MSI_X) {
6775 for (i=1; (sp->s2io_entries[i].in_use ==
6776 MSIX_REGISTERED_SUCCESS); i++) {
6777 int vector = sp->entries[i].vector;
6778 void *arg = sp->s2io_entries[i].arg;
6780 synchronize_irq(vector);
6781 free_irq(vector, arg);
6786 (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
6787 kfree(sp->s2io_entries);
6789 (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
6791 sp->s2io_entries = NULL;
6793 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6794 msi_control &= 0xFFFE; /* Disable MSI */
6795 pci_write_config_word(sp->pdev, 0x42, msi_control);
6797 pci_disable_msix(sp->pdev);
6799 synchronize_irq(sp->pdev->irq);
6800 free_irq(sp->pdev->irq, dev);
6804 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
6807 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6808 unsigned long flags;
6809 register u64 val64 = 0;
6811 del_timer_sync(&sp->alarm_timer);
6812 /* If s2io_set_link task is executing, wait till it completes. */
6813 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
6816 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
6818 /* disable Tx and Rx traffic on the NIC */
6825 tasklet_kill(&sp->task);
6827 /* Check if the device is Quiescent and then Reset the NIC */
6829 /* As per the HW requirement we need to replenish the
6830 * receive buffer to avoid the ring bump. Since there is
6831 * no intention of processing the Rx frame at this pointwe are
6832 * just settting the ownership bit of rxd in Each Rx
6833 * ring to HW and set the appropriate buffer size
6834 * based on the ring mode
6836 rxd_owner_bit_reset(sp);
6838 val64 = readq(&bar0->adapter_status);
6839 if (verify_xena_quiescence(sp)) {
6840 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6848 "s2io_close:Device not Quiescent ");
6849 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6850 (unsigned long long) val64);
6857 spin_lock_irqsave(&sp->tx_lock, flags);
6858 /* Free all Tx buffers */
6859 free_tx_buffers(sp);
6860 spin_unlock_irqrestore(&sp->tx_lock, flags);
6862 /* Free all Rx buffers */
6863 spin_lock_irqsave(&sp->rx_lock, flags);
6864 free_rx_buffers(sp);
6865 spin_unlock_irqrestore(&sp->rx_lock, flags);
6867 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
6870 static void s2io_card_down(struct s2io_nic * sp)
6872 do_s2io_card_down(sp, 1);
6875 static int s2io_card_up(struct s2io_nic * sp)
6878 struct mac_info *mac_control;
6879 struct config_param *config;
6880 struct net_device *dev = (struct net_device *) sp->dev;
6883 /* Initialize the H/W I/O registers */
6884 if (init_nic(sp) != 0) {
6885 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6892 * Initializing the Rx buffers. For now we are considering only 1
6893 * Rx ring and initializing buffers into 30 Rx blocks
6895 mac_control = &sp->mac_control;
6896 config = &sp->config;
6898 for (i = 0; i < config->rx_ring_num; i++) {
6899 if ((ret = fill_rx_buffers(sp, i))) {
6900 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6903 free_rx_buffers(sp);
6906 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6907 atomic_read(&sp->rx_bufs_left[i]));
6909 /* Maintain the state prior to the open */
6910 if (sp->promisc_flg)
6911 sp->promisc_flg = 0;
6912 if (sp->m_cast_flg) {
6914 sp->all_multi_pos= 0;
6917 /* Setting its receive mode */
6918 s2io_set_multicast(dev);
6921 /* Initialize max aggregatable pkts per session based on MTU */
6922 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6923 /* Check if we can use(if specified) user provided value */
6924 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6925 sp->lro_max_aggr_per_sess = lro_max_pkts;
6928 /* Enable Rx Traffic and interrupts on the NIC */
6929 if (start_nic(sp)) {
6930 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6932 free_rx_buffers(sp);
6936 /* Add interrupt service routine */
6937 if (s2io_add_isr(sp) != 0) {
6938 if (sp->config.intr_type == MSI_X)
6941 free_rx_buffers(sp);
6945 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6947 /* Enable tasklet for the device */
6948 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6950 /* Enable select interrupts */
6951 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
6952 if (sp->config.intr_type != INTA)
6953 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6955 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6956 interruptible |= TX_PIC_INTR;
6957 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6960 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
6965 * s2io_restart_nic - Resets the NIC.
6966 * @data : long pointer to the device private structure
6968 * This function is scheduled to be run by the s2io_tx_watchdog
6969 * function after 0.5 secs to reset the NIC. The idea is to reduce
6970 * the run time of the watch dog routine which is run holding a
6974 static void s2io_restart_nic(struct work_struct *work)
6976 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
6977 struct net_device *dev = sp->dev;
6981 if (!netif_running(dev))
6985 if (s2io_card_up(sp)) {
6986 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6989 netif_wake_queue(dev);
6990 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6997 * s2io_tx_watchdog - Watchdog for transmit side.
6998 * @dev : Pointer to net device structure
7000 * This function is triggered if the Tx Queue is stopped
7001 * for a pre-defined amount of time when the Interface is still up.
7002 * If the Interface is jammed in such a situation, the hardware is
7003 * reset (by s2io_close) and restarted again (by s2io_open) to
7004 * overcome any problem that might have been caused in the hardware.
7009 static void s2io_tx_watchdog(struct net_device *dev)
7011 struct s2io_nic *sp = dev->priv;
7013 if (netif_carrier_ok(dev)) {
7014 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7015 schedule_work(&sp->rst_timer_task);
7016 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7021 * rx_osm_handler - To perform some OS related operations on SKB.
7022 * @sp: private member of the device structure,pointer to s2io_nic structure.
7023 * @skb : the socket buffer pointer.
7024 * @len : length of the packet
7025 * @cksum : FCS checksum of the frame.
7026 * @ring_no : the ring from which this RxD was extracted.
7028 * This function is called by the Rx interrupt serivce routine to perform
7029 * some OS related operations on the SKB before passing it to the upper
7030 * layers. It mainly checks if the checksum is OK, if so adds it to the
7031 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7032 * to the upper layer. If the checksum is wrong, it increments the Rx
7033 * packet error count, frees the SKB and returns error.
7035 * SUCCESS on success and -1 on failure.
7037 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7039 struct s2io_nic *sp = ring_data->nic;
7040 struct net_device *dev = (struct net_device *) sp->dev;
7041 struct sk_buff *skb = (struct sk_buff *)
7042 ((unsigned long) rxdp->Host_Control);
7043 int ring_no = ring_data->ring_no;
7044 u16 l3_csum, l4_csum;
7045 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7052 /* Check for parity error */
7054 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7056 err_mask = err >> 48;
7059 sp->mac_control.stats_info->sw_stat.
7060 rx_parity_err_cnt++;
7064 sp->mac_control.stats_info->sw_stat.
7069 sp->mac_control.stats_info->sw_stat.
7070 rx_parity_abort_cnt++;
7074 sp->mac_control.stats_info->sw_stat.
7079 sp->mac_control.stats_info->sw_stat.
7084 sp->mac_control.stats_info->sw_stat.
7089 sp->mac_control.stats_info->sw_stat.
7090 rx_buf_size_err_cnt++;
7094 sp->mac_control.stats_info->sw_stat.
7095 rx_rxd_corrupt_cnt++;
7099 sp->mac_control.stats_info->sw_stat.
7104 * Drop the packet if bad transfer code. Exception being
7105 * 0x5, which could be due to unsupported IPv6 extension header.
7106 * In this case, we let stack handle the packet.
7107 * Note that in this case, since checksum will be incorrect,
7108 * stack will validate the same.
7110 if (err_mask != 0x5) {
7111 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7112 dev->name, err_mask);
7113 sp->stats.rx_crc_errors++;
7114 sp->mac_control.stats_info->sw_stat.mem_freed
7117 atomic_dec(&sp->rx_bufs_left[ring_no]);
7118 rxdp->Host_Control = 0;
7123 /* Updating statistics */
7124 sp->stats.rx_packets++;
7125 rxdp->Host_Control = 0;
7126 if (sp->rxd_mode == RXD_MODE_1) {
7127 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7129 sp->stats.rx_bytes += len;
7132 } else if (sp->rxd_mode == RXD_MODE_3B) {
7133 int get_block = ring_data->rx_curr_get_info.block_index;
7134 int get_off = ring_data->rx_curr_get_info.offset;
7135 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7136 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7137 unsigned char *buff = skb_push(skb, buf0_len);
7139 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7140 sp->stats.rx_bytes += buf0_len + buf2_len;
7141 memcpy(buff, ba->ba_0, buf0_len);
7142 skb_put(skb, buf2_len);
7145 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7146 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7148 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7149 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7150 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7152 * NIC verifies if the Checksum of the received
7153 * frame is Ok or not and accordingly returns
7154 * a flag in the RxD.
7156 skb->ip_summed = CHECKSUM_UNNECESSARY;
7162 ret = s2io_club_tcp_session(skb->data, &tcp,
7163 &tcp_len, &lro, rxdp, sp);
7165 case 3: /* Begin anew */
7168 case 1: /* Aggregate */
7170 lro_append_pkt(sp, lro,
7174 case 4: /* Flush session */
7176 lro_append_pkt(sp, lro,
7178 queue_rx_frame(lro->parent);
7179 clear_lro_session(lro);
7180 sp->mac_control.stats_info->
7181 sw_stat.flush_max_pkts++;
7184 case 2: /* Flush both */
7185 lro->parent->data_len =
7187 sp->mac_control.stats_info->
7188 sw_stat.sending_both++;
7189 queue_rx_frame(lro->parent);
7190 clear_lro_session(lro);
7192 case 0: /* sessions exceeded */
7193 case -1: /* non-TCP or not
7197 * First pkt in session not
7198 * L3/L4 aggregatable
7203 "%s: Samadhana!!\n",
7210 * Packet with erroneous checksum, let the
7211 * upper layers deal with it.
7213 skb->ip_summed = CHECKSUM_NONE;
7216 skb->ip_summed = CHECKSUM_NONE;
7218 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7220 skb->protocol = eth_type_trans(skb, dev);
7221 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7223 /* Queueing the vlan frame to the upper layer */
7225 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7226 RXD_GET_VLAN_TAG(rxdp->Control_2));
7228 vlan_hwaccel_rx(skb, sp->vlgrp,
7229 RXD_GET_VLAN_TAG(rxdp->Control_2));
7232 netif_receive_skb(skb);
7238 queue_rx_frame(skb);
7240 dev->last_rx = jiffies;
7242 atomic_dec(&sp->rx_bufs_left[ring_no]);
7247 * s2io_link - stops/starts the Tx queue.
7248 * @sp : private member of the device structure, which is a pointer to the
7249 * s2io_nic structure.
7250 * @link : inidicates whether link is UP/DOWN.
7252 * This function stops/starts the Tx queue depending on whether the link
7253 * status of the NIC is is down or up. This is called by the Alarm
7254 * interrupt handler whenever a link change interrupt comes up.
7259 static void s2io_link(struct s2io_nic * sp, int link)
7261 struct net_device *dev = (struct net_device *) sp->dev;
7263 if (link != sp->last_link_state) {
7264 if (link == LINK_DOWN) {
7265 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7266 netif_carrier_off(dev);
7267 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7268 sp->mac_control.stats_info->sw_stat.link_up_time =
7269 jiffies - sp->start_time;
7270 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7272 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7273 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7274 sp->mac_control.stats_info->sw_stat.link_down_time =
7275 jiffies - sp->start_time;
7276 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7277 netif_carrier_on(dev);
7280 sp->last_link_state = link;
7281 sp->start_time = jiffies;
7285 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7286 * @sp : private member of the device structure, which is a pointer to the
7287 * s2io_nic structure.
7289 * This function initializes a few of the PCI and PCI-X configuration registers
7290 * with recommended values.
7295 static void s2io_init_pci(struct s2io_nic * sp)
7297 u16 pci_cmd = 0, pcix_cmd = 0;
7299 /* Enable Data Parity Error Recovery in PCI-X command register. */
7300 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7302 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7304 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7307 /* Set the PErr Response bit in PCI command register. */
7308 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7309 pci_write_config_word(sp->pdev, PCI_COMMAND,
7310 (pci_cmd | PCI_COMMAND_PARITY));
7311 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7314 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7316 if ( tx_fifo_num > 8) {
7317 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7319 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7322 if ( rx_ring_num > 8) {
7323 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7325 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7328 if (*dev_intr_type != INTA)
7331 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7332 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7333 "Defaulting to INTA\n");
7334 *dev_intr_type = INTA;
7337 if ((*dev_intr_type == MSI_X) &&
7338 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7339 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7340 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7341 "Defaulting to INTA\n");
7342 *dev_intr_type = INTA;
7345 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7346 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7347 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7354 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7355 * or Traffic class respectively.
7356 * @nic: device peivate variable
7357 * Description: The function configures the receive steering to
7358 * desired receive ring.
7359 * Return Value: SUCCESS on success and
7360 * '-1' on failure (endian settings incorrect).
7362 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7364 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7365 register u64 val64 = 0;
7367 if (ds_codepoint > 63)
7370 val64 = RTS_DS_MEM_DATA(ring);
7371 writeq(val64, &bar0->rts_ds_mem_data);
7373 val64 = RTS_DS_MEM_CTRL_WE |
7374 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7375 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7377 writeq(val64, &bar0->rts_ds_mem_ctrl);
7379 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7380 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7385 * s2io_init_nic - Initialization of the adapter .
7386 * @pdev : structure containing the PCI related information of the device.
7387 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7389 * The function initializes an adapter identified by the pci_dec structure.
7390 * All OS related initialization including memory and device structure and
7391 * initlaization of the device private variable is done. Also the swapper
7392 * control register is initialized to enable read and write into the I/O
7393 * registers of the device.
7395 * returns 0 on success and negative on failure.
7398 static int __devinit
7399 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7401 struct s2io_nic *sp;
7402 struct net_device *dev;
7404 int dma_flag = FALSE;
7405 u32 mac_up, mac_down;
7406 u64 val64 = 0, tmp64 = 0;
7407 struct XENA_dev_config __iomem *bar0 = NULL;
7409 struct mac_info *mac_control;
7410 struct config_param *config;
7412 u8 dev_intr_type = intr_type;
7413 DECLARE_MAC_BUF(mac);
7415 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7418 if ((ret = pci_enable_device(pdev))) {
7420 "s2io_init_nic: pci_enable_device failed\n");
7424 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7425 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7427 if (pci_set_consistent_dma_mask
7428 (pdev, DMA_64BIT_MASK)) {
7430 "Unable to obtain 64bit DMA for \
7431 consistent allocations\n");
7432 pci_disable_device(pdev);
7435 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7436 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7438 pci_disable_device(pdev);
7441 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7442 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7443 pci_disable_device(pdev);
7447 dev = alloc_etherdev(sizeof(struct s2io_nic));
7449 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7450 pci_disable_device(pdev);
7451 pci_release_regions(pdev);
7455 pci_set_master(pdev);
7456 pci_set_drvdata(pdev, dev);
7457 SET_NETDEV_DEV(dev, &pdev->dev);
7459 /* Private member variable initialized to s2io NIC structure */
7461 memset(sp, 0, sizeof(struct s2io_nic));
7464 sp->high_dma_flag = dma_flag;
7465 sp->device_enabled_once = FALSE;
7466 if (rx_ring_mode == 1)
7467 sp->rxd_mode = RXD_MODE_1;
7468 if (rx_ring_mode == 2)
7469 sp->rxd_mode = RXD_MODE_3B;
7471 sp->config.intr_type = dev_intr_type;
7473 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7474 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7475 sp->device_type = XFRAME_II_DEVICE;
7477 sp->device_type = XFRAME_I_DEVICE;
7481 /* Initialize some PCI/PCI-X fields of the NIC. */
7485 * Setting the device configuration parameters.
7486 * Most of these parameters can be specified by the user during
7487 * module insertion as they are module loadable parameters. If
7488 * these parameters are not not specified during load time, they
7489 * are initialized with default values.
7491 mac_control = &sp->mac_control;
7492 config = &sp->config;
7494 config->napi = napi;
7496 /* Tx side parameters. */
7497 config->tx_fifo_num = tx_fifo_num;
7498 for (i = 0; i < MAX_TX_FIFOS; i++) {
7499 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7500 config->tx_cfg[i].fifo_priority = i;
7503 /* mapping the QoS priority to the configured fifos */
7504 for (i = 0; i < MAX_TX_FIFOS; i++)
7505 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7507 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7508 for (i = 0; i < config->tx_fifo_num; i++) {
7509 config->tx_cfg[i].f_no_snoop =
7510 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7511 if (config->tx_cfg[i].fifo_len < 65) {
7512 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7516 /* + 2 because one Txd for skb->data and one Txd for UFO */
7517 config->max_txds = MAX_SKB_FRAGS + 2;
7519 /* Rx side parameters. */
7520 config->rx_ring_num = rx_ring_num;
7521 for (i = 0; i < MAX_RX_RINGS; i++) {
7522 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7523 (rxd_count[sp->rxd_mode] + 1);
7524 config->rx_cfg[i].ring_priority = i;
7527 for (i = 0; i < rx_ring_num; i++) {
7528 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7529 config->rx_cfg[i].f_no_snoop =
7530 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7533 /* Setting Mac Control parameters */
7534 mac_control->rmac_pause_time = rmac_pause_time;
7535 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7536 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7539 /* Initialize Ring buffer parameters. */
7540 for (i = 0; i < config->rx_ring_num; i++)
7541 atomic_set(&sp->rx_bufs_left[i], 0);
7543 /* initialize the shared memory used by the NIC and the host */
7544 if (init_shared_mem(sp)) {
7545 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7548 goto mem_alloc_failed;
7551 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7552 pci_resource_len(pdev, 0));
7554 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7557 goto bar0_remap_failed;
7560 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7561 pci_resource_len(pdev, 2));
7563 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7566 goto bar1_remap_failed;
7569 dev->irq = pdev->irq;
7570 dev->base_addr = (unsigned long) sp->bar0;
7572 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7573 for (j = 0; j < MAX_TX_FIFOS; j++) {
7574 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7575 (sp->bar1 + (j * 0x00020000));
7578 /* Driver entry points */
7579 dev->open = &s2io_open;
7580 dev->stop = &s2io_close;
7581 dev->hard_start_xmit = &s2io_xmit;
7582 dev->get_stats = &s2io_get_stats;
7583 dev->set_multicast_list = &s2io_set_multicast;
7584 dev->do_ioctl = &s2io_ioctl;
7585 dev->change_mtu = &s2io_change_mtu;
7586 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7587 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7588 dev->vlan_rx_register = s2io_vlan_rx_register;
7591 * will use eth_mac_addr() for dev->set_mac_address
7592 * mac address will be set every time dev->open() is called
7594 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
7596 #ifdef CONFIG_NET_POLL_CONTROLLER
7597 dev->poll_controller = s2io_netpoll;
7600 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7601 if (sp->high_dma_flag == TRUE)
7602 dev->features |= NETIF_F_HIGHDMA;
7603 dev->features |= NETIF_F_TSO;
7604 dev->features |= NETIF_F_TSO6;
7605 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7606 dev->features |= NETIF_F_UFO;
7607 dev->features |= NETIF_F_HW_CSUM;
7610 dev->tx_timeout = &s2io_tx_watchdog;
7611 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7612 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7613 INIT_WORK(&sp->set_link_task, s2io_set_link);
7615 pci_save_state(sp->pdev);
7617 /* Setting swapper control on the NIC, for proper reset operation */
7618 if (s2io_set_swapper(sp)) {
7619 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7622 goto set_swap_failed;
7625 /* Verify if the Herc works on the slot its placed into */
7626 if (sp->device_type & XFRAME_II_DEVICE) {
7627 mode = s2io_verify_pci_mode(sp);
7629 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7630 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7632 goto set_swap_failed;
7636 /* Not needed for Herc */
7637 if (sp->device_type & XFRAME_I_DEVICE) {
7639 * Fix for all "FFs" MAC address problems observed on
7642 fix_mac_address(sp);
7647 * MAC address initialization.
7648 * For now only one mac address will be read and used.
7651 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7652 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7653 writeq(val64, &bar0->rmac_addr_cmd_mem);
7654 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7655 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7656 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7657 mac_down = (u32) tmp64;
7658 mac_up = (u32) (tmp64 >> 32);
7660 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7661 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7662 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7663 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7664 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7665 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7667 /* Set the factory defined MAC address initially */
7668 dev->addr_len = ETH_ALEN;
7669 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7671 /* Store the values of the MSIX table in the s2io_nic structure */
7672 store_xmsi_data(sp);
7673 /* reset Nic and bring it to known state */
7677 * Initialize the tasklet status and link state flags
7678 * and the card state parameter
7680 sp->tasklet_status = 0;
7683 /* Initialize spinlocks */
7684 spin_lock_init(&sp->tx_lock);
7687 spin_lock_init(&sp->put_lock);
7688 spin_lock_init(&sp->rx_lock);
7691 * SXE-002: Configure link and activity LED to init state
7694 subid = sp->pdev->subsystem_device;
7695 if ((subid & 0xFF) >= 0x07) {
7696 val64 = readq(&bar0->gpio_control);
7697 val64 |= 0x0000800000000000ULL;
7698 writeq(val64, &bar0->gpio_control);
7699 val64 = 0x0411040400000000ULL;
7700 writeq(val64, (void __iomem *) bar0 + 0x2700);
7701 val64 = readq(&bar0->gpio_control);
7704 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7706 if (register_netdev(dev)) {
7707 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7709 goto register_failed;
7712 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7713 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7714 sp->product_name, pdev->revision);
7715 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7716 s2io_driver_version);
7717 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
7718 dev->name, print_mac(mac, dev->dev_addr));
7719 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7720 if (sp->device_type & XFRAME_II_DEVICE) {
7721 mode = s2io_print_pci_mode(sp);
7723 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7725 unregister_netdev(dev);
7726 goto set_swap_failed;
7729 switch(sp->rxd_mode) {
7731 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7735 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7741 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7742 switch(sp->config.intr_type) {
7744 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7747 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7751 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7754 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7755 " enabled\n", dev->name);
7756 /* Initialize device name */
7757 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7759 /* Initialize bimodal Interrupts */
7760 sp->config.bimodal = bimodal;
7761 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7762 sp->config.bimodal = 0;
7763 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7768 * Make Link state as off at this point, when the Link change
7769 * interrupt comes the state will be automatically changed to
7772 netif_carrier_off(dev);
7783 free_shared_mem(sp);
7784 pci_disable_device(pdev);
7785 pci_release_regions(pdev);
7786 pci_set_drvdata(pdev, NULL);
7793 * s2io_rem_nic - Free the PCI device
7794 * @pdev: structure containing the PCI related information of the device.
7795 * Description: This function is called by the Pci subsystem to release a
7796 * PCI device and free up all resource held up by the device. This could
7797 * be in response to a Hot plug event or when the driver is to be removed
7801 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7803 struct net_device *dev =
7804 (struct net_device *) pci_get_drvdata(pdev);
7805 struct s2io_nic *sp;
7808 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7812 flush_scheduled_work();
7815 unregister_netdev(dev);
7817 free_shared_mem(sp);
7820 pci_release_regions(pdev);
7821 pci_set_drvdata(pdev, NULL);
7823 pci_disable_device(pdev);
7827 * s2io_starter - Entry point for the driver
7828 * Description: This function is the entry point for the driver. It verifies
7829 * the module loadable parameters and initializes PCI configuration space.
7832 int __init s2io_starter(void)
7834 return pci_register_driver(&s2io_driver);
7838 * s2io_closer - Cleanup routine for the driver
7839 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7842 static __exit void s2io_closer(void)
7844 pci_unregister_driver(&s2io_driver);
7845 DBG_PRINT(INIT_DBG, "cleanup done\n");
7848 module_init(s2io_starter);
7849 module_exit(s2io_closer);
7851 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7852 struct tcphdr **tcp, struct RxD_t *rxdp)
7855 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7857 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7858 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7864 * By default the VLAN field in the MAC is stripped by the card, if this
7865 * feature is turned off in rx_pa_cfg register, then the ip_off field
7866 * has to be shifted by a further 2 bytes
7869 case 0: /* DIX type */
7870 case 4: /* DIX type with VLAN */
7871 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7873 /* LLC, SNAP etc are considered non-mergeable */
7878 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7879 ip_len = (u8)((*ip)->ihl);
7881 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7886 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7889 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7890 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7891 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7896 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7898 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7901 static void initiate_new_session(struct lro *lro, u8 *l2h,
7902 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7904 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7908 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7909 lro->tcp_ack = ntohl(tcp->ack_seq);
7911 lro->total_len = ntohs(ip->tot_len);
7914 * check if we saw TCP timestamp. Other consistency checks have
7915 * already been done.
7917 if (tcp->doff == 8) {
7919 ptr = (u32 *)(tcp+1);
7921 lro->cur_tsval = *(ptr+1);
7922 lro->cur_tsecr = *(ptr+2);
7927 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7929 struct iphdr *ip = lro->iph;
7930 struct tcphdr *tcp = lro->tcph;
7932 struct stat_block *statinfo = sp->mac_control.stats_info;
7933 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7935 /* Update L3 header */
7936 ip->tot_len = htons(lro->total_len);
7938 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7941 /* Update L4 header */
7942 tcp->ack_seq = lro->tcp_ack;
7943 tcp->window = lro->window;
7945 /* Update tsecr field if this session has timestamps enabled */
7947 u32 *ptr = (u32 *)(tcp + 1);
7948 *(ptr+2) = lro->cur_tsecr;
7951 /* Update counters required for calculation of
7952 * average no. of packets aggregated.
7954 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7955 statinfo->sw_stat.num_aggregations++;
7958 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7959 struct tcphdr *tcp, u32 l4_pyld)
7961 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7962 lro->total_len += l4_pyld;
7963 lro->frags_len += l4_pyld;
7964 lro->tcp_next_seq += l4_pyld;
7967 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7968 lro->tcp_ack = tcp->ack_seq;
7969 lro->window = tcp->window;
7973 /* Update tsecr and tsval from this packet */
7974 ptr = (u32 *) (tcp + 1);
7975 lro->cur_tsval = *(ptr + 1);
7976 lro->cur_tsecr = *(ptr + 2);
7980 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7981 struct tcphdr *tcp, u32 tcp_pyld_len)
7985 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7987 if (!tcp_pyld_len) {
7988 /* Runt frame or a pure ack */
7992 if (ip->ihl != 5) /* IP has options */
7995 /* If we see CE codepoint in IP header, packet is not mergeable */
7996 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7999 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8000 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8001 tcp->ece || tcp->cwr || !tcp->ack) {
8003 * Currently recognize only the ack control word and
8004 * any other control field being set would result in
8005 * flushing the LRO session
8011 * Allow only one TCP timestamp option. Don't aggregate if
8012 * any other options are detected.
8014 if (tcp->doff != 5 && tcp->doff != 8)
8017 if (tcp->doff == 8) {
8018 ptr = (u8 *)(tcp + 1);
8019 while (*ptr == TCPOPT_NOP)
8021 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8024 /* Ensure timestamp value increases monotonically */
8026 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
8029 /* timestamp echo reply should be non-zero */
8030 if (*((u32 *)(ptr+6)) == 0)
8038 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8039 struct RxD_t *rxdp, struct s2io_nic *sp)
8042 struct tcphdr *tcph;
8045 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8047 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8048 ip->saddr, ip->daddr);
8053 tcph = (struct tcphdr *)*tcp;
8054 *tcp_len = get_l4_pyld_length(ip, tcph);
8055 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8056 struct lro *l_lro = &sp->lro0_n[i];
8057 if (l_lro->in_use) {
8058 if (check_for_socket_match(l_lro, ip, tcph))
8060 /* Sock pair matched */
8063 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8064 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8065 "0x%x, actual 0x%x\n", __FUNCTION__,
8066 (*lro)->tcp_next_seq,
8069 sp->mac_control.stats_info->
8070 sw_stat.outof_sequence_pkts++;
8075 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8076 ret = 1; /* Aggregate */
8078 ret = 2; /* Flush both */
8084 /* Before searching for available LRO objects,
8085 * check if the pkt is L3/L4 aggregatable. If not
8086 * don't create new LRO session. Just send this
8089 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8093 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8094 struct lro *l_lro = &sp->lro0_n[i];
8095 if (!(l_lro->in_use)) {
8097 ret = 3; /* Begin anew */
8103 if (ret == 0) { /* sessions exceeded */
8104 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8112 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
8115 update_L3L4_header(sp, *lro);
8118 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8119 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8120 update_L3L4_header(sp, *lro);
8121 ret = 4; /* Flush the LRO */
8125 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8133 static void clear_lro_session(struct lro *lro)
8135 static u16 lro_struct_size = sizeof(struct lro);
8137 memset(lro, 0, lro_struct_size);
8140 static void queue_rx_frame(struct sk_buff *skb)
8142 struct net_device *dev = skb->dev;
8144 skb->protocol = eth_type_trans(skb, dev);
8146 netif_receive_skb(skb);
8151 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8152 struct sk_buff *skb,
8155 struct sk_buff *first = lro->parent;
8157 first->len += tcp_len;
8158 first->data_len = lro->frags_len;
8159 skb_pull(skb, (skb->len - tcp_len));
8160 if (skb_shinfo(first)->frag_list)
8161 lro->last_frag->next = skb;
8163 skb_shinfo(first)->frag_list = skb;
8164 first->truesize += skb->truesize;
8165 lro->last_frag = skb;
8166 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8171 * s2io_io_error_detected - called when PCI error is detected
8172 * @pdev: Pointer to PCI device
8173 * @state: The current pci connection state
8175 * This function is called after a PCI bus error affecting
8176 * this device has been detected.
8178 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8179 pci_channel_state_t state)
8181 struct net_device *netdev = pci_get_drvdata(pdev);
8182 struct s2io_nic *sp = netdev->priv;
8184 netif_device_detach(netdev);
8186 if (netif_running(netdev)) {
8187 /* Bring down the card, while avoiding PCI I/O */
8188 do_s2io_card_down(sp, 0);
8190 pci_disable_device(pdev);
8192 return PCI_ERS_RESULT_NEED_RESET;
8196 * s2io_io_slot_reset - called after the pci bus has been reset.
8197 * @pdev: Pointer to PCI device
8199 * Restart the card from scratch, as if from a cold-boot.
8200 * At this point, the card has exprienced a hard reset,
8201 * followed by fixups by BIOS, and has its config space
8202 * set up identically to what it was at cold boot.
8204 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8206 struct net_device *netdev = pci_get_drvdata(pdev);
8207 struct s2io_nic *sp = netdev->priv;
8209 if (pci_enable_device(pdev)) {
8210 printk(KERN_ERR "s2io: "
8211 "Cannot re-enable PCI device after reset.\n");
8212 return PCI_ERS_RESULT_DISCONNECT;
8215 pci_set_master(pdev);
8218 return PCI_ERS_RESULT_RECOVERED;
8222 * s2io_io_resume - called when traffic can start flowing again.
8223 * @pdev: Pointer to PCI device
8225 * This callback is called when the error recovery driver tells
8226 * us that its OK to resume normal operation.
8228 static void s2io_io_resume(struct pci_dev *pdev)
8230 struct net_device *netdev = pci_get_drvdata(pdev);
8231 struct s2io_nic *sp = netdev->priv;
8233 if (netif_running(netdev)) {
8234 if (s2io_card_up(sp)) {
8235 printk(KERN_ERR "s2io: "
8236 "Can't bring device back up after reset.\n");
8240 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8242 printk(KERN_ERR "s2io: "
8243 "Can't resetore mac addr after reset.\n");
8248 netif_device_attach(netdev);
8249 netif_wake_queue(netdev);
git.samba.org / sfrench / cifs-2.6.git / blob