1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
59 #include <linux/module.h>
60 #include <linux/types.h>
61 #include <linux/errno.h>
62 #include <linux/ioport.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/kernel.h>
66 #include <linux/netdevice.h>
67 #include <linux/etherdevice.h>
68 #include <linux/mdio.h>
69 #include <linux/skbuff.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/stddef.h>
73 #include <linux/ioctl.h>
74 #include <linux/timex.h>
75 #include <linux/ethtool.h>
76 #include <linux/workqueue.h>
77 #include <linux/if_vlan.h>
79 #include <linux/tcp.h>
80 #include <linux/uaccess.h>
82 #include <linux/slab.h>
85 #include <asm/system.h>
86 #include <asm/div64.h>
91 #include "s2io-regs.h"
93 #define DRV_VERSION "2.0.26.27"
95 /* S2io Driver name & version. */
96 static char s2io_driver_name[] = "Neterion";
97 static char s2io_driver_version[] = DRV_VERSION;
99 static int rxd_size[2] = {32, 48};
100 static int rxd_count[2] = {127, 85};
102 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
117 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
122 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
125 static inline int is_s2io_card_up(const struct s2io_nic *sp)
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
130 /* Ethtool related variables and Macros. */
131 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
139 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
141 {"tmac_data_octets"},
145 {"tmac_pause_ctrl_frms"},
149 {"tmac_any_err_frms"},
150 {"tmac_ttl_less_fb_octets"},
151 {"tmac_vld_ip_octets"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
165 {"rmac_out_rng_len_err_frms"},
167 {"rmac_pause_ctrl_frms"},
168 {"rmac_unsup_ctrl_frms"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
172 {"rmac_discarded_frms"},
173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
179 {"rmac_jabber_frms"},
180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
193 {"rmac_err_drp_udp"},
194 {"rmac_xgmii_err_sym"},
212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
214 {"rmac_accepted_ip"},
218 {"new_rd_req_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
223 {"new_wr_req_rtry_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
236 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
255 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
323 {"prc_pcix_err_cnt"},
330 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
334 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
337 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
340 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
341 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
343 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
349 /* copy mac addr to def_mac_addr array */
350 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
361 static void s2io_vlan_rx_register(struct net_device *dev,
362 struct vlan_group *grp)
365 struct s2io_nic *nic = netdev_priv(dev);
366 unsigned long flags[MAX_TX_FIFOS];
367 struct config_param *config = &nic->config;
368 struct mac_info *mac_control = &nic->mac_control;
370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
385 /* Unregister the vlan */
386 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
389 struct s2io_nic *nic = netdev_priv(dev);
390 unsigned long flags[MAX_TX_FIFOS];
391 struct config_param *config = &nic->config;
392 struct mac_info *mac_control = &nic->mac_control;
394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
411 * Constants to be programmed into the Xena's registers, to configure
416 static const u64 herc_act_dtx_cfg[] = {
418 0x8000051536750000ULL, 0x80000515367500E0ULL,
420 0x8000051536750004ULL, 0x80000515367500E4ULL,
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
437 static const u64 xena_dtx_cfg[] = {
439 0x8000051500000000ULL, 0x80000515000000E0ULL,
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
447 0x8002051500000000ULL, 0x80020515000000E0ULL,
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
454 * Constants for Fixing the MacAddress problem seen mostly on
457 static const u64 fix_mac[] = {
458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
475 MODULE_LICENSE("GPL");
476 MODULE_VERSION(DRV_VERSION);
479 /* Module Loadable parameters. */
480 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
481 S2IO_PARM_INT(rx_ring_num, 1);
482 S2IO_PARM_INT(multiq, 0);
483 S2IO_PARM_INT(rx_ring_mode, 1);
484 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485 S2IO_PARM_INT(rmac_pause_time, 0x100);
486 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488 S2IO_PARM_INT(shared_splits, 0);
489 S2IO_PARM_INT(tmac_util_period, 5);
490 S2IO_PARM_INT(rmac_util_period, 5);
491 S2IO_PARM_INT(l3l4hdr_size, 128);
492 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
494 /* Frequency of Rx desc syncs expressed as power of 2 */
495 S2IO_PARM_INT(rxsync_frequency, 3);
496 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
497 S2IO_PARM_INT(intr_type, 2);
498 /* Large receive offload feature */
499 static unsigned int lro_enable = 1;
500 module_param_named(lro, lro_enable, uint, 0);
502 /* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
505 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
506 S2IO_PARM_INT(indicate_max_pkts, 0);
508 S2IO_PARM_INT(napi, 1);
509 S2IO_PARM_INT(ufo, 0);
510 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
512 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
513 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
514 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
515 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
516 static unsigned int rts_frm_len[MAX_RX_RINGS] =
517 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
519 module_param_array(tx_fifo_len, uint, NULL, 0);
520 module_param_array(rx_ring_sz, uint, NULL, 0);
521 module_param_array(rts_frm_len, uint, NULL, 0);
525 * This table lists all the devices that this driver supports.
527 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
539 MODULE_DEVICE_TABLE(pci, s2io_tbl);
541 static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
547 static struct pci_driver s2io_driver = {
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
555 /* A simplifier macro used both by init and free shared_mem Fns(). */
556 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
558 /* netqueue manipulation helper functions */
559 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
561 if (!sp->config.multiq) {
564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
567 netif_tx_stop_all_queues(sp->dev);
570 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
572 if (!sp->config.multiq)
573 sp->mac_control.fifos[fifo_no].queue_state =
576 netif_tx_stop_all_queues(sp->dev);
579 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
581 if (!sp->config.multiq) {
584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
587 netif_tx_start_all_queues(sp->dev);
590 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
592 if (!sp->config.multiq)
593 sp->mac_control.fifos[fifo_no].queue_state =
596 netif_tx_start_all_queues(sp->dev);
599 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
601 if (!sp->config.multiq) {
604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
607 netif_tx_wake_all_queues(sp->dev);
610 static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
630 * Rx descriptors and the statistics block.
633 static int init_shared_mem(struct s2io_nic *nic)
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
638 struct RxD_block *pre_rxd_blk = NULL;
640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
646 unsigned long long mem_allocated = 0;
648 /* Allocation and initialization of TXDLs in FIFOs */
650 for (i = 0; i < config->tx_fifo_num; i++) {
651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
653 size += tx_cfg->fifo_len;
655 if (size > MAX_AVAILABLE_TXDS) {
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
663 for (i = 0; i < config->tx_fifo_num; i++) {
664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
666 size = tx_cfg->fifo_len;
668 * Legal values are from 2 to 8192
671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
678 lst_size = (sizeof(struct TxD) * config->max_txds);
679 lst_per_page = PAGE_SIZE / lst_size;
681 for (i = 0; i < config->tx_fifo_num; i++) {
682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
692 mem_allocated += list_holder_size;
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
709 for (j = 0; j < page_num; j++) {
713 tmp_v = pci_alloc_consistent(nic->pdev,
717 "pci_alloc_consistent failed for TxDL\n");
720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
726 mac_control->zerodma_virt_addr = tmp_v;
728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
731 tmp_v = pci_alloc_consistent(nic->pdev,
735 "pci_alloc_consistent failed for TxDL\n");
738 mem_allocated += PAGE_SIZE;
740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
742 if (l == tx_cfg->fifo_len)
744 fifo->list_info[l].list_virt_addr =
745 tmp_v + (k * lst_size);
746 fifo->list_info[l].list_phy_addr =
747 tmp_p + (k * lst_size);
753 for (i = 0; i < config->tx_fifo_num; i++) {
754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
761 mem_allocated += (size * sizeof(u64));
764 /* Allocation and initialization of RXDs in Rings */
766 for (i = 0; i < config->rx_ring_num; i++) {
767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
778 (rxd_count[nic->rxd_mode] + 1);
779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
781 if (nic->rxd_mode == RXD_MODE_1)
782 size = (size * (sizeof(struct RxD1)));
784 size = (size * (sizeof(struct RxD3)));
786 for (i = 0; i < config->rx_ring_num; i++) {
787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
799 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
800 /* Allocating all the Rx blocks */
801 for (j = 0; j < blk_cnt; j++) {
802 struct rx_block_info *rx_blocks;
805 rx_blocks = &ring->rx_blocks[j];
806 size = SIZE_OF_BLOCK; /* size is always page size */
807 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
809 if (tmp_v_addr == NULL) {
811 * In case of failure, free_shared_mem()
812 * is called, which should free any
813 * memory that was alloced till the
816 rx_blocks->block_virt_addr = tmp_v_addr;
819 mem_allocated += size;
820 memset(tmp_v_addr, 0, size);
822 size = sizeof(struct rxd_info) *
823 rxd_count[nic->rxd_mode];
824 rx_blocks->block_virt_addr = tmp_v_addr;
825 rx_blocks->block_dma_addr = tmp_p_addr;
826 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
827 if (!rx_blocks->rxds)
829 mem_allocated += size;
830 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
831 rx_blocks->rxds[l].virt_addr =
832 rx_blocks->block_virt_addr +
833 (rxd_size[nic->rxd_mode] * l);
834 rx_blocks->rxds[l].dma_addr =
835 rx_blocks->block_dma_addr +
836 (rxd_size[nic->rxd_mode] * l);
839 /* Interlinking all Rx Blocks */
840 for (j = 0; j < blk_cnt; j++) {
841 int next = (j + 1) % blk_cnt;
842 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
843 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
844 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
845 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
847 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
848 pre_rxd_blk->reserved_2_pNext_RxD_block =
849 (unsigned long)tmp_v_addr_next;
850 pre_rxd_blk->pNext_RxD_Blk_physical =
851 (u64)tmp_p_addr_next;
854 if (nic->rxd_mode == RXD_MODE_3B) {
856 * Allocation of Storages for buffer addresses in 2BUFF mode
857 * and the buffers as well.
859 for (i = 0; i < config->rx_ring_num; i++) {
860 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
861 struct ring_info *ring = &mac_control->rings[i];
863 blk_cnt = rx_cfg->num_rxd /
864 (rxd_count[nic->rxd_mode] + 1);
865 size = sizeof(struct buffAdd *) * blk_cnt;
866 ring->ba = kmalloc(size, GFP_KERNEL);
869 mem_allocated += size;
870 for (j = 0; j < blk_cnt; j++) {
873 size = sizeof(struct buffAdd) *
874 (rxd_count[nic->rxd_mode] + 1);
875 ring->ba[j] = kmalloc(size, GFP_KERNEL);
878 mem_allocated += size;
879 while (k != rxd_count[nic->rxd_mode]) {
880 ba = &ring->ba[j][k];
881 size = BUF0_LEN + ALIGN_SIZE;
882 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
885 mem_allocated += size;
886 tmp = (unsigned long)ba->ba_0_org;
888 tmp &= ~((unsigned long)ALIGN_SIZE);
889 ba->ba_0 = (void *)tmp;
891 size = BUF1_LEN + ALIGN_SIZE;
892 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
895 mem_allocated += size;
896 tmp = (unsigned long)ba->ba_1_org;
898 tmp &= ~((unsigned long)ALIGN_SIZE);
899 ba->ba_1 = (void *)tmp;
906 /* Allocation and initialization of Statistics block */
907 size = sizeof(struct stat_block);
908 mac_control->stats_mem =
909 pci_alloc_consistent(nic->pdev, size,
910 &mac_control->stats_mem_phy);
912 if (!mac_control->stats_mem) {
914 * In case of failure, free_shared_mem() is called, which
915 * should free any memory that was alloced till the
920 mem_allocated += size;
921 mac_control->stats_mem_sz = size;
923 tmp_v_addr = mac_control->stats_mem;
924 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
925 memset(tmp_v_addr, 0, size);
926 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
927 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
928 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
933 * free_shared_mem - Free the allocated Memory
934 * @nic: Device private variable.
935 * Description: This function is to free all memory locations allocated by
936 * the init_shared_mem() function and return it to the kernel.
939 static void free_shared_mem(struct s2io_nic *nic)
941 int i, j, blk_cnt, size;
943 dma_addr_t tmp_p_addr;
944 int lst_size, lst_per_page;
945 struct net_device *dev;
947 struct config_param *config;
948 struct mac_info *mac_control;
949 struct stat_block *stats;
950 struct swStat *swstats;
957 config = &nic->config;
958 mac_control = &nic->mac_control;
959 stats = mac_control->stats_info;
960 swstats = &stats->sw_stat;
962 lst_size = sizeof(struct TxD) * config->max_txds;
963 lst_per_page = PAGE_SIZE / lst_size;
965 for (i = 0; i < config->tx_fifo_num; i++) {
966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
972 struct list_info_hold *fli;
974 if (!fifo->list_info)
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
983 swstats->mem_freed += PAGE_SIZE;
985 /* If we got a zero DMA address during allocation,
988 if (mac_control->zerodma_virt_addr) {
989 pci_free_consistent(nic->pdev, PAGE_SIZE,
990 mac_control->zerodma_virt_addr,
993 "%s: Freeing TxDL with zero DMA address. "
994 "Virtual address %p\n",
995 dev->name, mac_control->zerodma_virt_addr);
996 swstats->mem_freed += PAGE_SIZE;
998 kfree(fifo->list_info);
999 swstats->mem_freed += tx_cfg->fifo_len *
1000 sizeof(struct list_info_hold);
1003 size = SIZE_OF_BLOCK;
1004 for (i = 0; i < config->rx_ring_num; i++) {
1005 struct ring_info *ring = &mac_control->rings[i];
1007 blk_cnt = ring->block_count;
1008 for (j = 0; j < blk_cnt; j++) {
1009 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1010 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1011 if (tmp_v_addr == NULL)
1013 pci_free_consistent(nic->pdev, size,
1014 tmp_v_addr, tmp_p_addr);
1015 swstats->mem_freed += size;
1016 kfree(ring->rx_blocks[j].rxds);
1017 swstats->mem_freed += sizeof(struct rxd_info) *
1018 rxd_count[nic->rxd_mode];
1022 if (nic->rxd_mode == RXD_MODE_3B) {
1023 /* Freeing buffer storage addresses in 2BUFF mode. */
1024 for (i = 0; i < config->rx_ring_num; i++) {
1025 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1026 struct ring_info *ring = &mac_control->rings[i];
1028 blk_cnt = rx_cfg->num_rxd /
1029 (rxd_count[nic->rxd_mode] + 1);
1030 for (j = 0; j < blk_cnt; j++) {
1034 while (k != rxd_count[nic->rxd_mode]) {
1035 struct buffAdd *ba = &ring->ba[j][k];
1036 kfree(ba->ba_0_org);
1037 swstats->mem_freed +=
1038 BUF0_LEN + ALIGN_SIZE;
1039 kfree(ba->ba_1_org);
1040 swstats->mem_freed +=
1041 BUF1_LEN + ALIGN_SIZE;
1045 swstats->mem_freed += sizeof(struct buffAdd) *
1046 (rxd_count[nic->rxd_mode] + 1);
1049 swstats->mem_freed += sizeof(struct buffAdd *) *
1054 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1055 struct fifo_info *fifo = &mac_control->fifos[i];
1056 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1058 if (fifo->ufo_in_band_v) {
1059 swstats->mem_freed += tx_cfg->fifo_len *
1061 kfree(fifo->ufo_in_band_v);
1065 if (mac_control->stats_mem) {
1066 swstats->mem_freed += mac_control->stats_mem_sz;
1067 pci_free_consistent(nic->pdev,
1068 mac_control->stats_mem_sz,
1069 mac_control->stats_mem,
1070 mac_control->stats_mem_phy);
1075 * s2io_verify_pci_mode -
1078 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1080 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1081 register u64 val64 = 0;
1084 val64 = readq(&bar0->pci_mode);
1085 mode = (u8)GET_PCI_MODE(val64);
1087 if (val64 & PCI_MODE_UNKNOWN_MODE)
1088 return -1; /* Unknown PCI mode */
1092 #define NEC_VENID 0x1033
1093 #define NEC_DEVID 0x0125
1094 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1096 struct pci_dev *tdev = NULL;
1097 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1098 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1099 if (tdev->bus == s2io_pdev->bus->parent) {
1108 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1110 * s2io_print_pci_mode -
1112 static int s2io_print_pci_mode(struct s2io_nic *nic)
1114 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1115 register u64 val64 = 0;
1117 struct config_param *config = &nic->config;
1118 const char *pcimode;
1120 val64 = readq(&bar0->pci_mode);
1121 mode = (u8)GET_PCI_MODE(val64);
1123 if (val64 & PCI_MODE_UNKNOWN_MODE)
1124 return -1; /* Unknown PCI mode */
1126 config->bus_speed = bus_speed[mode];
1128 if (s2io_on_nec_bridge(nic->pdev)) {
1129 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1135 case PCI_MODE_PCI_33:
1136 pcimode = "33MHz PCI bus";
1138 case PCI_MODE_PCI_66:
1139 pcimode = "66MHz PCI bus";
1141 case PCI_MODE_PCIX_M1_66:
1142 pcimode = "66MHz PCIX(M1) bus";
1144 case PCI_MODE_PCIX_M1_100:
1145 pcimode = "100MHz PCIX(M1) bus";
1147 case PCI_MODE_PCIX_M1_133:
1148 pcimode = "133MHz PCIX(M1) bus";
1150 case PCI_MODE_PCIX_M2_66:
1151 pcimode = "133MHz PCIX(M2) bus";
1153 case PCI_MODE_PCIX_M2_100:
1154 pcimode = "200MHz PCIX(M2) bus";
1156 case PCI_MODE_PCIX_M2_133:
1157 pcimode = "266MHz PCIX(M2) bus";
1160 pcimode = "unsupported bus!";
1164 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1165 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1171 * init_tti - Initialization transmit traffic interrupt scheme
1172 * @nic: device private variable
1173 * @link: link status (UP/DOWN) used to enable/disable continuous
1174 * transmit interrupts
1175 * Description: The function configures transmit traffic interrupts
1176 * Return Value: SUCCESS on success and
1180 static int init_tti(struct s2io_nic *nic, int link)
1182 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1183 register u64 val64 = 0;
1185 struct config_param *config = &nic->config;
1187 for (i = 0; i < config->tx_fifo_num; i++) {
1189 * TTI Initialization. Default Tx timer gets us about
1190 * 250 interrupts per sec. Continuous interrupts are enabled
1193 if (nic->device_type == XFRAME_II_DEVICE) {
1194 int count = (nic->config.bus_speed * 125)/2;
1195 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1197 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1199 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1200 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1201 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1202 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1204 if (use_continuous_tx_intrs && (link == LINK_UP))
1205 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1206 writeq(val64, &bar0->tti_data1_mem);
1208 if (nic->config.intr_type == MSI_X) {
1209 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1210 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1211 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1212 TTI_DATA2_MEM_TX_UFC_D(0x300);
1214 if ((nic->config.tx_steering_type ==
1215 TX_DEFAULT_STEERING) &&
1216 (config->tx_fifo_num > 1) &&
1217 (i >= nic->udp_fifo_idx) &&
1218 (i < (nic->udp_fifo_idx +
1219 nic->total_udp_fifos)))
1220 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1221 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1222 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1223 TTI_DATA2_MEM_TX_UFC_D(0x120);
1225 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1226 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1227 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1228 TTI_DATA2_MEM_TX_UFC_D(0x80);
1231 writeq(val64, &bar0->tti_data2_mem);
1233 val64 = TTI_CMD_MEM_WE |
1234 TTI_CMD_MEM_STROBE_NEW_CMD |
1235 TTI_CMD_MEM_OFFSET(i);
1236 writeq(val64, &bar0->tti_command_mem);
1238 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1239 TTI_CMD_MEM_STROBE_NEW_CMD,
1240 S2IO_BIT_RESET) != SUCCESS)
1248 * init_nic - Initialization of hardware
1249 * @nic: device private variable
1250 * Description: The function sequentially configures every block
1251 * of the H/W from their reset values.
1252 * Return Value: SUCCESS on success and
1253 * '-1' on failure (endian settings incorrect).
1256 static int init_nic(struct s2io_nic *nic)
1258 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1259 struct net_device *dev = nic->dev;
1260 register u64 val64 = 0;
1265 unsigned long long mem_share;
1267 struct config_param *config = &nic->config;
1268 struct mac_info *mac_control = &nic->mac_control;
1270 /* to set the swapper controle on the card */
1271 if (s2io_set_swapper(nic)) {
1272 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1277 * Herc requires EOI to be removed from reset before XGXS, so..
1279 if (nic->device_type & XFRAME_II_DEVICE) {
1280 val64 = 0xA500000000ULL;
1281 writeq(val64, &bar0->sw_reset);
1283 val64 = readq(&bar0->sw_reset);
1286 /* Remove XGXS from reset state */
1288 writeq(val64, &bar0->sw_reset);
1290 val64 = readq(&bar0->sw_reset);
1292 /* Ensure that it's safe to access registers by checking
1293 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1295 if (nic->device_type == XFRAME_II_DEVICE) {
1296 for (i = 0; i < 50; i++) {
1297 val64 = readq(&bar0->adapter_status);
1298 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1306 /* Enable Receiving broadcasts */
1307 add = &bar0->mac_cfg;
1308 val64 = readq(&bar0->mac_cfg);
1309 val64 |= MAC_RMAC_BCAST_ENABLE;
1310 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1311 writel((u32)val64, add);
1312 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1313 writel((u32) (val64 >> 32), (add + 4));
1315 /* Read registers in all blocks */
1316 val64 = readq(&bar0->mac_int_mask);
1317 val64 = readq(&bar0->mc_int_mask);
1318 val64 = readq(&bar0->xgxs_int_mask);
1322 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1324 if (nic->device_type & XFRAME_II_DEVICE) {
1325 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1326 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1327 &bar0->dtx_control, UF);
1329 msleep(1); /* Necessary!! */
1333 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1334 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1335 &bar0->dtx_control, UF);
1336 val64 = readq(&bar0->dtx_control);
1341 /* Tx DMA Initialization */
1343 writeq(val64, &bar0->tx_fifo_partition_0);
1344 writeq(val64, &bar0->tx_fifo_partition_1);
1345 writeq(val64, &bar0->tx_fifo_partition_2);
1346 writeq(val64, &bar0->tx_fifo_partition_3);
1348 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1349 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1351 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1352 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1354 if (i == (config->tx_fifo_num - 1)) {
1361 writeq(val64, &bar0->tx_fifo_partition_0);
1366 writeq(val64, &bar0->tx_fifo_partition_1);
1371 writeq(val64, &bar0->tx_fifo_partition_2);
1376 writeq(val64, &bar0->tx_fifo_partition_3);
1387 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1388 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1390 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1391 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1393 val64 = readq(&bar0->tx_fifo_partition_0);
1394 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1395 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1398 * Initialization of Tx_PA_CONFIG register to ignore packet
1399 * integrity checking.
1401 val64 = readq(&bar0->tx_pa_cfg);
1402 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1403 TX_PA_CFG_IGNORE_SNAP_OUI |
1404 TX_PA_CFG_IGNORE_LLC_CTRL |
1405 TX_PA_CFG_IGNORE_L2_ERR;
1406 writeq(val64, &bar0->tx_pa_cfg);
1408 /* Rx DMA intialization. */
1410 for (i = 0; i < config->rx_ring_num; i++) {
1411 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1413 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1415 writeq(val64, &bar0->rx_queue_priority);
1418 * Allocating equal share of memory to all the
1422 if (nic->device_type & XFRAME_II_DEVICE)
1427 for (i = 0; i < config->rx_ring_num; i++) {
1430 mem_share = (mem_size / config->rx_ring_num +
1431 mem_size % config->rx_ring_num);
1432 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1435 mem_share = (mem_size / config->rx_ring_num);
1436 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1439 mem_share = (mem_size / config->rx_ring_num);
1440 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1443 mem_share = (mem_size / config->rx_ring_num);
1444 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1447 mem_share = (mem_size / config->rx_ring_num);
1448 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1451 mem_share = (mem_size / config->rx_ring_num);
1452 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1455 mem_share = (mem_size / config->rx_ring_num);
1456 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1459 mem_share = (mem_size / config->rx_ring_num);
1460 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1464 writeq(val64, &bar0->rx_queue_cfg);
1467 * Filling Tx round robin registers
1468 * as per the number of FIFOs for equal scheduling priority
1470 switch (config->tx_fifo_num) {
1473 writeq(val64, &bar0->tx_w_round_robin_0);
1474 writeq(val64, &bar0->tx_w_round_robin_1);
1475 writeq(val64, &bar0->tx_w_round_robin_2);
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 writeq(val64, &bar0->tx_w_round_robin_4);
1480 val64 = 0x0001000100010001ULL;
1481 writeq(val64, &bar0->tx_w_round_robin_0);
1482 writeq(val64, &bar0->tx_w_round_robin_1);
1483 writeq(val64, &bar0->tx_w_round_robin_2);
1484 writeq(val64, &bar0->tx_w_round_robin_3);
1485 val64 = 0x0001000100000000ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_4);
1489 val64 = 0x0001020001020001ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_0);
1491 val64 = 0x0200010200010200ULL;
1492 writeq(val64, &bar0->tx_w_round_robin_1);
1493 val64 = 0x0102000102000102ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_2);
1495 val64 = 0x0001020001020001ULL;
1496 writeq(val64, &bar0->tx_w_round_robin_3);
1497 val64 = 0x0200010200000000ULL;
1498 writeq(val64, &bar0->tx_w_round_robin_4);
1501 val64 = 0x0001020300010203ULL;
1502 writeq(val64, &bar0->tx_w_round_robin_0);
1503 writeq(val64, &bar0->tx_w_round_robin_1);
1504 writeq(val64, &bar0->tx_w_round_robin_2);
1505 writeq(val64, &bar0->tx_w_round_robin_3);
1506 val64 = 0x0001020300000000ULL;
1507 writeq(val64, &bar0->tx_w_round_robin_4);
1510 val64 = 0x0001020304000102ULL;
1511 writeq(val64, &bar0->tx_w_round_robin_0);
1512 val64 = 0x0304000102030400ULL;
1513 writeq(val64, &bar0->tx_w_round_robin_1);
1514 val64 = 0x0102030400010203ULL;
1515 writeq(val64, &bar0->tx_w_round_robin_2);
1516 val64 = 0x0400010203040001ULL;
1517 writeq(val64, &bar0->tx_w_round_robin_3);
1518 val64 = 0x0203040000000000ULL;
1519 writeq(val64, &bar0->tx_w_round_robin_4);
1522 val64 = 0x0001020304050001ULL;
1523 writeq(val64, &bar0->tx_w_round_robin_0);
1524 val64 = 0x0203040500010203ULL;
1525 writeq(val64, &bar0->tx_w_round_robin_1);
1526 val64 = 0x0405000102030405ULL;
1527 writeq(val64, &bar0->tx_w_round_robin_2);
1528 val64 = 0x0001020304050001ULL;
1529 writeq(val64, &bar0->tx_w_round_robin_3);
1530 val64 = 0x0203040500000000ULL;
1531 writeq(val64, &bar0->tx_w_round_robin_4);
1534 val64 = 0x0001020304050600ULL;
1535 writeq(val64, &bar0->tx_w_round_robin_0);
1536 val64 = 0x0102030405060001ULL;
1537 writeq(val64, &bar0->tx_w_round_robin_1);
1538 val64 = 0x0203040506000102ULL;
1539 writeq(val64, &bar0->tx_w_round_robin_2);
1540 val64 = 0x0304050600010203ULL;
1541 writeq(val64, &bar0->tx_w_round_robin_3);
1542 val64 = 0x0405060000000000ULL;
1543 writeq(val64, &bar0->tx_w_round_robin_4);
1546 val64 = 0x0001020304050607ULL;
1547 writeq(val64, &bar0->tx_w_round_robin_0);
1548 writeq(val64, &bar0->tx_w_round_robin_1);
1549 writeq(val64, &bar0->tx_w_round_robin_2);
1550 writeq(val64, &bar0->tx_w_round_robin_3);
1551 val64 = 0x0001020300000000ULL;
1552 writeq(val64, &bar0->tx_w_round_robin_4);
1556 /* Enable all configured Tx FIFO partitions */
1557 val64 = readq(&bar0->tx_fifo_partition_0);
1558 val64 |= (TX_FIFO_PARTITION_EN);
1559 writeq(val64, &bar0->tx_fifo_partition_0);
1561 /* Filling the Rx round robin registers as per the
1562 * number of Rings and steering based on QoS with
1565 switch (config->rx_ring_num) {
1568 writeq(val64, &bar0->rx_w_round_robin_0);
1569 writeq(val64, &bar0->rx_w_round_robin_1);
1570 writeq(val64, &bar0->rx_w_round_robin_2);
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 writeq(val64, &bar0->rx_w_round_robin_4);
1574 val64 = 0x8080808080808080ULL;
1575 writeq(val64, &bar0->rts_qos_steering);
1578 val64 = 0x0001000100010001ULL;
1579 writeq(val64, &bar0->rx_w_round_robin_0);
1580 writeq(val64, &bar0->rx_w_round_robin_1);
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1582 writeq(val64, &bar0->rx_w_round_robin_3);
1583 val64 = 0x0001000100000000ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_4);
1586 val64 = 0x8080808040404040ULL;
1587 writeq(val64, &bar0->rts_qos_steering);
1590 val64 = 0x0001020001020001ULL;
1591 writeq(val64, &bar0->rx_w_round_robin_0);
1592 val64 = 0x0200010200010200ULL;
1593 writeq(val64, &bar0->rx_w_round_robin_1);
1594 val64 = 0x0102000102000102ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_2);
1596 val64 = 0x0001020001020001ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_3);
1598 val64 = 0x0200010200000000ULL;
1599 writeq(val64, &bar0->rx_w_round_robin_4);
1601 val64 = 0x8080804040402020ULL;
1602 writeq(val64, &bar0->rts_qos_steering);
1605 val64 = 0x0001020300010203ULL;
1606 writeq(val64, &bar0->rx_w_round_robin_0);
1607 writeq(val64, &bar0->rx_w_round_robin_1);
1608 writeq(val64, &bar0->rx_w_round_robin_2);
1609 writeq(val64, &bar0->rx_w_round_robin_3);
1610 val64 = 0x0001020300000000ULL;
1611 writeq(val64, &bar0->rx_w_round_robin_4);
1613 val64 = 0x8080404020201010ULL;
1614 writeq(val64, &bar0->rts_qos_steering);
1617 val64 = 0x0001020304000102ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_0);
1619 val64 = 0x0304000102030400ULL;
1620 writeq(val64, &bar0->rx_w_round_robin_1);
1621 val64 = 0x0102030400010203ULL;
1622 writeq(val64, &bar0->rx_w_round_robin_2);
1623 val64 = 0x0400010203040001ULL;
1624 writeq(val64, &bar0->rx_w_round_robin_3);
1625 val64 = 0x0203040000000000ULL;
1626 writeq(val64, &bar0->rx_w_round_robin_4);
1628 val64 = 0x8080404020201008ULL;
1629 writeq(val64, &bar0->rts_qos_steering);
1632 val64 = 0x0001020304050001ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_0);
1634 val64 = 0x0203040500010203ULL;
1635 writeq(val64, &bar0->rx_w_round_robin_1);
1636 val64 = 0x0405000102030405ULL;
1637 writeq(val64, &bar0->rx_w_round_robin_2);
1638 val64 = 0x0001020304050001ULL;
1639 writeq(val64, &bar0->rx_w_round_robin_3);
1640 val64 = 0x0203040500000000ULL;
1641 writeq(val64, &bar0->rx_w_round_robin_4);
1643 val64 = 0x8080404020100804ULL;
1644 writeq(val64, &bar0->rts_qos_steering);
1647 val64 = 0x0001020304050600ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_0);
1649 val64 = 0x0102030405060001ULL;
1650 writeq(val64, &bar0->rx_w_round_robin_1);
1651 val64 = 0x0203040506000102ULL;
1652 writeq(val64, &bar0->rx_w_round_robin_2);
1653 val64 = 0x0304050600010203ULL;
1654 writeq(val64, &bar0->rx_w_round_robin_3);
1655 val64 = 0x0405060000000000ULL;
1656 writeq(val64, &bar0->rx_w_round_robin_4);
1658 val64 = 0x8080402010080402ULL;
1659 writeq(val64, &bar0->rts_qos_steering);
1662 val64 = 0x0001020304050607ULL;
1663 writeq(val64, &bar0->rx_w_round_robin_0);
1664 writeq(val64, &bar0->rx_w_round_robin_1);
1665 writeq(val64, &bar0->rx_w_round_robin_2);
1666 writeq(val64, &bar0->rx_w_round_robin_3);
1667 val64 = 0x0001020300000000ULL;
1668 writeq(val64, &bar0->rx_w_round_robin_4);
1670 val64 = 0x8040201008040201ULL;
1671 writeq(val64, &bar0->rts_qos_steering);
1677 for (i = 0; i < 8; i++)
1678 writeq(val64, &bar0->rts_frm_len_n[i]);
1680 /* Set the default rts frame length for the rings configured */
1681 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1682 for (i = 0 ; i < config->rx_ring_num ; i++)
1683 writeq(val64, &bar0->rts_frm_len_n[i]);
1685 /* Set the frame length for the configured rings
1686 * desired by the user
1688 for (i = 0; i < config->rx_ring_num; i++) {
1689 /* If rts_frm_len[i] == 0 then it is assumed that user not
1690 * specified frame length steering.
1691 * If the user provides the frame length then program
1692 * the rts_frm_len register for those values or else
1693 * leave it as it is.
1695 if (rts_frm_len[i] != 0) {
1696 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1697 &bar0->rts_frm_len_n[i]);
1701 /* Disable differentiated services steering logic */
1702 for (i = 0; i < 64; i++) {
1703 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1705 "%s: rts_ds_steer failed on codepoint %d\n",
1711 /* Program statistics memory */
1712 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1714 if (nic->device_type == XFRAME_II_DEVICE) {
1715 val64 = STAT_BC(0x320);
1716 writeq(val64, &bar0->stat_byte_cnt);
1720 * Initializing the sampling rate for the device to calculate the
1721 * bandwidth utilization.
1723 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1724 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1725 writeq(val64, &bar0->mac_link_util);
1728 * Initializing the Transmit and Receive Traffic Interrupt
1732 /* Initialize TTI */
1733 if (SUCCESS != init_tti(nic, nic->last_link_state))
1736 /* RTI Initialization */
1737 if (nic->device_type == XFRAME_II_DEVICE) {
1739 * Programmed to generate Apprx 500 Intrs per
1742 int count = (nic->config.bus_speed * 125)/4;
1743 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1746 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1747 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1748 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1749 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1751 writeq(val64, &bar0->rti_data1_mem);
1753 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1754 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1755 if (nic->config.intr_type == MSI_X)
1756 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1757 RTI_DATA2_MEM_RX_UFC_D(0x40));
1759 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1760 RTI_DATA2_MEM_RX_UFC_D(0x80));
1761 writeq(val64, &bar0->rti_data2_mem);
1763 for (i = 0; i < config->rx_ring_num; i++) {
1764 val64 = RTI_CMD_MEM_WE |
1765 RTI_CMD_MEM_STROBE_NEW_CMD |
1766 RTI_CMD_MEM_OFFSET(i);
1767 writeq(val64, &bar0->rti_command_mem);
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1783 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1793 * Initializing proper values as Pause threshold into all
1794 * the 8 Queues on Rx side.
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1799 /* Disable RMAC PAD STRIPPING */
1800 add = &bar0->mac_cfg;
1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1823 * Set the time value to be inserted in the pause frame
1824 * generated by xena.
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1838 for (i = 0; i < 4; i++) {
1839 val64 |= (((u64)0xFF00 |
1840 nic->mac_control.mc_pause_threshold_q0q3)
1843 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1846 for (i = 0; i < 4; i++) {
1847 val64 |= (((u64)0xFF00 |
1848 nic->mac_control.mc_pause_threshold_q4q7)
1851 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1854 * TxDMA will stop Read request if the number of read split has
1855 * exceeded the limit pointed by shared_splits
1857 val64 = readq(&bar0->pic_control);
1858 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1859 writeq(val64, &bar0->pic_control);
1861 if (nic->config.bus_speed == 266) {
1862 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1863 writeq(0x0, &bar0->read_retry_delay);
1864 writeq(0x0, &bar0->write_retry_delay);
1868 * Programming the Herc to split every write transaction
1869 * that does not start on an ADB to reduce disconnects.
1871 if (nic->device_type == XFRAME_II_DEVICE) {
1872 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1873 MISC_LINK_STABILITY_PRD(3);
1874 writeq(val64, &bar0->misc_control);
1875 val64 = readq(&bar0->pic_control2);
1876 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1877 writeq(val64, &bar0->pic_control2);
1879 if (strstr(nic->product_name, "CX4")) {
1880 val64 = TMAC_AVG_IPG(0x17);
1881 writeq(val64, &bar0->tmac_avg_ipg);
1886 #define LINK_UP_DOWN_INTERRUPT 1
1887 #define MAC_RMAC_ERR_TIMER 2
1889 static int s2io_link_fault_indication(struct s2io_nic *nic)
1891 if (nic->device_type == XFRAME_II_DEVICE)
1892 return LINK_UP_DOWN_INTERRUPT;
1894 return MAC_RMAC_ERR_TIMER;
1898 * do_s2io_write_bits - update alarm bits in alarm register
1899 * @value: alarm bits
1900 * @flag: interrupt status
1901 * @addr: address value
1902 * Description: update alarm bits in alarm register
1906 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1910 temp64 = readq(addr);
1912 if (flag == ENABLE_INTRS)
1913 temp64 &= ~((u64)value);
1915 temp64 |= ((u64)value);
1916 writeq(temp64, addr);
1919 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1921 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1922 register u64 gen_int_mask = 0;
1925 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1926 if (mask & TX_DMA_INTR) {
1927 gen_int_mask |= TXDMA_INT_M;
1929 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1930 TXDMA_PCC_INT | TXDMA_TTI_INT |
1931 TXDMA_LSO_INT | TXDMA_TPA_INT |
1932 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1934 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1935 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1936 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1937 &bar0->pfc_err_mask);
1939 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1940 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1941 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1943 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1944 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1945 PCC_N_SERR | PCC_6_COF_OV_ERR |
1946 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1947 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1949 flag, &bar0->pcc_err_mask);
1951 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1952 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1954 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1955 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1956 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1957 flag, &bar0->lso_err_mask);
1959 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1960 flag, &bar0->tpa_err_mask);
1962 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1965 if (mask & TX_MAC_INTR) {
1966 gen_int_mask |= TXMAC_INT_M;
1967 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1968 &bar0->mac_int_mask);
1969 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1970 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1971 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1972 flag, &bar0->mac_tmac_err_mask);
1975 if (mask & TX_XGXS_INTR) {
1976 gen_int_mask |= TXXGXS_INT_M;
1977 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1978 &bar0->xgxs_int_mask);
1979 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1980 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1981 flag, &bar0->xgxs_txgxs_err_mask);
1984 if (mask & RX_DMA_INTR) {
1985 gen_int_mask |= RXDMA_INT_M;
1986 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1987 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1988 flag, &bar0->rxdma_int_mask);
1989 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1990 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1991 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1992 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1993 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1994 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1995 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1996 &bar0->prc_pcix_err_mask);
1997 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1998 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1999 &bar0->rpa_err_mask);
2000 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2001 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2002 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2003 RDA_FRM_ECC_SG_ERR |
2004 RDA_MISC_ERR|RDA_PCIX_ERR,
2005 flag, &bar0->rda_err_mask);
2006 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2007 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2008 flag, &bar0->rti_err_mask);
2011 if (mask & RX_MAC_INTR) {
2012 gen_int_mask |= RXMAC_INT_M;
2013 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2014 &bar0->mac_int_mask);
2015 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2016 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2017 RMAC_DOUBLE_ECC_ERR);
2018 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2019 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2020 do_s2io_write_bits(interruptible,
2021 flag, &bar0->mac_rmac_err_mask);
2024 if (mask & RX_XGXS_INTR) {
2025 gen_int_mask |= RXXGXS_INT_M;
2026 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2027 &bar0->xgxs_int_mask);
2028 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2029 &bar0->xgxs_rxgxs_err_mask);
2032 if (mask & MC_INTR) {
2033 gen_int_mask |= MC_INT_M;
2034 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2035 flag, &bar0->mc_int_mask);
2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
2040 nic->general_int_mask = gen_int_mask;
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2047 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2048 * @nic: device private variable,
2049 * @mask: A mask indicating which Intr block must be modified and,
2050 * @flag: A flag indicating whether to enable or disable the Intrs.
2051 * Description: This function will either disable or enable the interrupts
2052 * depending on the flag argument. The mask argument can be used to
2053 * enable/disable any Intr block.
2054 * Return Value: NONE.
2057 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2059 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2060 register u64 temp64 = 0, intr_mask = 0;
2062 intr_mask = nic->general_int_mask;
2064 /* Top level interrupt classification */
2065 /* PIC Interrupts */
2066 if (mask & TX_PIC_INTR) {
2067 /* Enable PIC Intrs in the general intr mask register */
2068 intr_mask |= TXPIC_INT_M;
2069 if (flag == ENABLE_INTRS) {
2071 * If Hercules adapter enable GPIO otherwise
2072 * disable all PCIX, Flash, MDIO, IIC and GPIO
2073 * interrupts for now.
2076 if (s2io_link_fault_indication(nic) ==
2077 LINK_UP_DOWN_INTERRUPT) {
2078 do_s2io_write_bits(PIC_INT_GPIO, flag,
2079 &bar0->pic_int_mask);
2080 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2081 &bar0->gpio_int_mask);
2083 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2084 } else if (flag == DISABLE_INTRS) {
2086 * Disable PIC Intrs in the general
2087 * intr mask register
2089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2093 /* Tx traffic interrupts */
2094 if (mask & TX_TRAFFIC_INTR) {
2095 intr_mask |= TXTRAFFIC_INT_M;
2096 if (flag == ENABLE_INTRS) {
2098 * Enable all the Tx side interrupts
2099 * writing 0 Enables all 64 TX interrupt levels
2101 writeq(0x0, &bar0->tx_traffic_mask);
2102 } else if (flag == DISABLE_INTRS) {
2104 * Disable Tx Traffic Intrs in the general intr mask
2107 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2111 /* Rx traffic interrupts */
2112 if (mask & RX_TRAFFIC_INTR) {
2113 intr_mask |= RXTRAFFIC_INT_M;
2114 if (flag == ENABLE_INTRS) {
2115 /* writing 0 Enables all 8 RX interrupt levels */
2116 writeq(0x0, &bar0->rx_traffic_mask);
2117 } else if (flag == DISABLE_INTRS) {
2119 * Disable Rx Traffic Intrs in the general intr mask
2122 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2126 temp64 = readq(&bar0->general_int_mask);
2127 if (flag == ENABLE_INTRS)
2128 temp64 &= ~((u64)intr_mask);
2130 temp64 = DISABLE_ALL_INTRS;
2131 writeq(temp64, &bar0->general_int_mask);
2133 nic->general_int_mask = readq(&bar0->general_int_mask);
2137 * verify_pcc_quiescent- Checks for PCC quiescent state
2138 * Return: 1 If PCC is quiescence
2139 * 0 If PCC is not quiescence
2141 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2145 u64 val64 = readq(&bar0->adapter_status);
2147 herc = (sp->device_type == XFRAME_II_DEVICE);
2149 if (flag == false) {
2150 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2151 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2154 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2159 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2160 ADAPTER_STATUS_RMAC_PCC_IDLE))
2163 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2164 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2172 * verify_xena_quiescence - Checks whether the H/W is ready
2173 * Description: Returns whether the H/W is ready to go or not. Depending
2174 * on whether adapter enable bit was written or not the comparison
2175 * differs and the calling function passes the input argument flag to
2177 * Return: 1 If xena is quiescence
2178 * 0 If Xena is not quiescence
2181 static int verify_xena_quiescence(struct s2io_nic *sp)
2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2185 u64 val64 = readq(&bar0->adapter_status);
2186 mode = s2io_verify_pci_mode(sp);
2188 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2189 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2192 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2193 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2196 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2197 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2200 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2201 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2204 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2205 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2208 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2209 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2212 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2213 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2216 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2217 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2222 * In PCI 33 mode, the P_PLL is not used, and therefore,
2223 * the the P_PLL_LOCK bit in the adapter_status register will
2226 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2227 sp->device_type == XFRAME_II_DEVICE &&
2228 mode != PCI_MODE_PCI_33) {
2229 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2232 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2233 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2234 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2241 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2242 * @sp: Pointer to device specifc structure
2244 * New procedure to clear mac address reading problems on Alpha platforms
2248 static void fix_mac_address(struct s2io_nic *sp)
2250 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2254 while (fix_mac[i] != END_SIGN) {
2255 writeq(fix_mac[i++], &bar0->gpio_control);
2257 val64 = readq(&bar0->gpio_control);
2262 * start_nic - Turns the device on
2263 * @nic : device private variable.
2265 * This function actually turns the device on. Before this function is
2266 * called,all Registers are configured from their reset states
2267 * and shared memory is allocated but the NIC is still quiescent. On
2268 * calling this function, the device interrupts are cleared and the NIC is
2269 * literally switched on by writing into the adapter control register.
2271 * SUCCESS on success and -1 on failure.
2274 static int start_nic(struct s2io_nic *nic)
2276 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2277 struct net_device *dev = nic->dev;
2278 register u64 val64 = 0;
2280 struct config_param *config = &nic->config;
2281 struct mac_info *mac_control = &nic->mac_control;
2283 /* PRC Initialization and configuration */
2284 for (i = 0; i < config->rx_ring_num; i++) {
2285 struct ring_info *ring = &mac_control->rings[i];
2287 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2288 &bar0->prc_rxd0_n[i]);
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
2313 nic->vlan_strip_flag = 0;
2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2326 msleep(100); /* Delay by around 100 ms. */
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2334 * Verify if the device is ready to be enabled, if so enable
2337 val64 = readq(&bar0->adapter_status);
2338 if (!verify_xena_quiescence(nic)) {
2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2340 "Adapter status reads: 0x%llx\n",
2341 dev->name, (unsigned long long)val64);
2346 * With some switches, link might be already up at this point.
2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2363 schedule_work(&nic->set_link_task);
2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2381 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2382 struct TxD *txdlp, int get_off)
2384 struct s2io_nic *nic = fifo_data->nic;
2385 struct sk_buff *skb;
2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2391 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2392 sizeof(u64), PCI_DMA_TODEVICE);
2396 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2398 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2401 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2402 skb_headlen(skb), PCI_DMA_TODEVICE);
2403 frg_cnt = skb_shinfo(skb)->nr_frags;
2406 for (j = 0; j < frg_cnt; j++, txds++) {
2407 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2408 if (!txds->Buffer_Pointer)
2410 pci_unmap_page(nic->pdev,
2411 (dma_addr_t)txds->Buffer_Pointer,
2412 frag->size, PCI_DMA_TODEVICE);
2415 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2420 * free_tx_buffers - Free all queued Tx buffers
2421 * @nic : device private variable.
2423 * Free all queued Tx buffers.
2424 * Return Value: void
2427 static void free_tx_buffers(struct s2io_nic *nic)
2429 struct net_device *dev = nic->dev;
2430 struct sk_buff *skb;
2434 struct config_param *config = &nic->config;
2435 struct mac_info *mac_control = &nic->mac_control;
2436 struct stat_block *stats = mac_control->stats_info;
2437 struct swStat *swstats = &stats->sw_stat;
2439 for (i = 0; i < config->tx_fifo_num; i++) {
2440 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2441 struct fifo_info *fifo = &mac_control->fifos[i];
2442 unsigned long flags;
2444 spin_lock_irqsave(&fifo->tx_lock, flags);
2445 for (j = 0; j < tx_cfg->fifo_len; j++) {
2446 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2447 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2449 swstats->mem_freed += skb->truesize;
2455 "%s: forcibly freeing %d skbs on FIFO%d\n",
2457 fifo->tx_curr_get_info.offset = 0;
2458 fifo->tx_curr_put_info.offset = 0;
2459 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2464 * stop_nic - To stop the nic
2465 * @nic ; device private variable.
2467 * This function does exactly the opposite of what the start_nic()
2468 * function does. This function is called to stop the device.
2473 static void stop_nic(struct s2io_nic *nic)
2475 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2476 register u64 val64 = 0;
2479 /* Disable all interrupts */
2480 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2481 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2482 interruptible |= TX_PIC_INTR;
2483 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2486 val64 = readq(&bar0->adapter_control);
2487 val64 &= ~(ADAPTER_CNTL_EN);
2488 writeq(val64, &bar0->adapter_control);
2492 * fill_rx_buffers - Allocates the Rx side skbs
2493 * @ring_info: per ring structure
2494 * @from_card_up: If this is true, we will map the buffer to get
2495 * the dma address for buf0 and buf1 to give it to the card.
2496 * Else we will sync the already mapped buffer to give it to the card.
2498 * The function allocates Rx side skbs and puts the physical
2499 * address of these buffers into the RxD buffer pointers, so that the NIC
2500 * can DMA the received frame into these locations.
2501 * The NIC supports 3 receive modes, viz
2503 * 2. three buffer and
2504 * 3. Five buffer modes.
2505 * Each mode defines how many fragments the received frame will be split
2506 * up into by the NIC. The frame is split into L3 header, L4 Header,
2507 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2508 * is split into 3 fragments. As of now only single buffer mode is
2511 * SUCCESS on success or an appropriate -ve value on failure.
2513 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2516 struct sk_buff *skb;
2518 int off, size, block_no, block_no1;
2523 struct RxD_t *first_rxdp = NULL;
2524 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2528 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2530 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2532 block_no1 = ring->rx_curr_get_info.block_index;
2533 while (alloc_tab < alloc_cnt) {
2534 block_no = ring->rx_curr_put_info.block_index;
2536 off = ring->rx_curr_put_info.offset;
2538 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540 rxd_index = off + 1;
2542 rxd_index += (block_no * ring->rxd_count);
2544 if ((block_no == block_no1) &&
2545 (off == ring->rx_curr_get_info.offset) &&
2546 (rxdp->Host_Control)) {
2547 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2551 if (off && (off == ring->rxd_count)) {
2552 ring->rx_curr_put_info.block_index++;
2553 if (ring->rx_curr_put_info.block_index ==
2555 ring->rx_curr_put_info.block_index = 0;
2556 block_no = ring->rx_curr_put_info.block_index;
2558 ring->rx_curr_put_info.offset = off;
2559 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2560 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2561 ring->dev->name, rxdp);
2565 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2566 ((ring->rxd_mode == RXD_MODE_3B) &&
2567 (rxdp->Control_2 & s2BIT(0)))) {
2568 ring->rx_curr_put_info.offset = off;
2571 /* calculate size of skb based on ring mode */
2573 HEADER_ETHERNET_II_802_3_SIZE +
2574 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2575 if (ring->rxd_mode == RXD_MODE_1)
2576 size += NET_IP_ALIGN;
2578 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2581 skb = dev_alloc_skb(size);
2583 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2587 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 swstats->mem_alloc_fail_cnt++;
2593 swstats->mem_allocated += skb->truesize;
2595 if (ring->rxd_mode == RXD_MODE_1) {
2596 /* 1 buffer mode - normal operation mode */
2597 rxdp1 = (struct RxD1 *)rxdp;
2598 memset(rxdp, 0, sizeof(struct RxD1));
2599 skb_reserve(skb, NET_IP_ALIGN);
2600 rxdp1->Buffer0_ptr =
2601 pci_map_single(ring->pdev, skb->data,
2602 size - NET_IP_ALIGN,
2603 PCI_DMA_FROMDEVICE);
2604 if (pci_dma_mapping_error(nic->pdev,
2605 rxdp1->Buffer0_ptr))
2606 goto pci_map_failed;
2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2610 rxdp->Host_Control = (unsigned long)skb;
2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
2614 * 2 buffer mode provides 128
2615 * byte aligned receive buffers.
2618 rxdp3 = (struct RxD3 *)rxdp;
2619 /* save buffer pointers to avoid frequent dma mapping */
2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
2622 memset(rxdp, 0, sizeof(struct RxD3));
2623 /* restore the buffer pointers for dma sync*/
2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
2627 ba = &ring->ba[block_no][off];
2628 skb_reserve(skb, BUF0_LEN);
2629 tmp = (u64)(unsigned long)skb->data;
2632 skb->data = (void *) (unsigned long)tmp;
2633 skb_reset_tail_pointer(skb);
2636 rxdp3->Buffer0_ptr =
2637 pci_map_single(ring->pdev, ba->ba_0,
2639 PCI_DMA_FROMDEVICE);
2640 if (pci_dma_mapping_error(nic->pdev,
2641 rxdp3->Buffer0_ptr))
2642 goto pci_map_failed;
2644 pci_dma_sync_single_for_device(ring->pdev,
2645 (dma_addr_t)rxdp3->Buffer0_ptr,
2647 PCI_DMA_FROMDEVICE);
2649 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2650 if (ring->rxd_mode == RXD_MODE_3B) {
2651 /* Two buffer mode */
2654 * Buffer2 will have L3/L4 header plus
2657 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2660 PCI_DMA_FROMDEVICE);
2662 if (pci_dma_mapping_error(nic->pdev,
2663 rxdp3->Buffer2_ptr))
2664 goto pci_map_failed;
2667 rxdp3->Buffer1_ptr =
2668 pci_map_single(ring->pdev,
2671 PCI_DMA_FROMDEVICE);
2673 if (pci_dma_mapping_error(nic->pdev,
2674 rxdp3->Buffer1_ptr)) {
2675 pci_unmap_single(ring->pdev,
2676 (dma_addr_t)(unsigned long)
2679 PCI_DMA_FROMDEVICE);
2680 goto pci_map_failed;
2683 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2684 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2687 rxdp->Control_2 |= s2BIT(0);
2688 rxdp->Host_Control = (unsigned long) (skb);
2690 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2691 rxdp->Control_1 |= RXD_OWN_XENA;
2693 if (off == (ring->rxd_count + 1))
2695 ring->rx_curr_put_info.offset = off;
2697 rxdp->Control_2 |= SET_RXD_MARKER;
2698 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2701 first_rxdp->Control_1 |= RXD_OWN_XENA;
2705 ring->rx_bufs_left += 1;
2710 /* Transfer ownership of first descriptor to adapter just before
2711 * exiting. Before that, use memory barrier so that ownership
2712 * and other fields are seen by adapter correctly.
2716 first_rxdp->Control_1 |= RXD_OWN_XENA;
2722 swstats->pci_map_fail_cnt++;
2723 swstats->mem_freed += skb->truesize;
2724 dev_kfree_skb_irq(skb);
2728 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2730 struct net_device *dev = sp->dev;
2732 struct sk_buff *skb;
2737 struct mac_info *mac_control = &sp->mac_control;
2738 struct stat_block *stats = mac_control->stats_info;
2739 struct swStat *swstats = &stats->sw_stat;
2741 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2742 rxdp = mac_control->rings[ring_no].
2743 rx_blocks[blk].rxds[j].virt_addr;
2744 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2747 if (sp->rxd_mode == RXD_MODE_1) {
2748 rxdp1 = (struct RxD1 *)rxdp;
2749 pci_unmap_single(sp->pdev,
2750 (dma_addr_t)rxdp1->Buffer0_ptr,
2752 HEADER_ETHERNET_II_802_3_SIZE +
2753 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2754 PCI_DMA_FROMDEVICE);
2755 memset(rxdp, 0, sizeof(struct RxD1));
2756 } else if (sp->rxd_mode == RXD_MODE_3B) {
2757 rxdp3 = (struct RxD3 *)rxdp;
2758 ba = &mac_control->rings[ring_no].ba[blk][j];
2759 pci_unmap_single(sp->pdev,
2760 (dma_addr_t)rxdp3->Buffer0_ptr,
2762 PCI_DMA_FROMDEVICE);
2763 pci_unmap_single(sp->pdev,
2764 (dma_addr_t)rxdp3->Buffer1_ptr,
2766 PCI_DMA_FROMDEVICE);
2767 pci_unmap_single(sp->pdev,
2768 (dma_addr_t)rxdp3->Buffer2_ptr,
2770 PCI_DMA_FROMDEVICE);
2771 memset(rxdp, 0, sizeof(struct RxD3));
2773 swstats->mem_freed += skb->truesize;
2775 mac_control->rings[ring_no].rx_bufs_left -= 1;
2780 * free_rx_buffers - Frees all Rx buffers
2781 * @sp: device private variable.
2783 * This function will free all Rx buffers allocated by host.
2788 static void free_rx_buffers(struct s2io_nic *sp)
2790 struct net_device *dev = sp->dev;
2791 int i, blk = 0, buf_cnt = 0;
2792 struct config_param *config = &sp->config;
2793 struct mac_info *mac_control = &sp->mac_control;
2795 for (i = 0; i < config->rx_ring_num; i++) {
2796 struct ring_info *ring = &mac_control->rings[i];
2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2799 free_rxd_blk(sp, i, blk);
2801 ring->rx_curr_put_info.block_index = 0;
2802 ring->rx_curr_get_info.block_index = 0;
2803 ring->rx_curr_put_info.offset = 0;
2804 ring->rx_curr_get_info.offset = 0;
2805 ring->rx_bufs_left = 0;
2806 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2807 dev->name, buf_cnt, i);
2811 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2814 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2821 * s2io_poll - Rx interrupt handler for NAPI support
2822 * @napi : pointer to the napi structure.
2823 * @budget : The number of packets that were budgeted to be processed
2824 * during one pass through the 'Poll" function.
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2833 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
2837 int pkts_processed = 0;
2838 u8 __iomem *addr = NULL;
2840 struct s2io_nic *nic = netdev_priv(dev);
2841 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2842 int budget_org = budget;
2844 if (unlikely(!is_s2io_card_up(nic)))
2847 pkts_processed = rx_intr_handler(ring, budget);
2848 s2io_chk_rx_buffers(nic, ring);
2850 if (pkts_processed < budget_org) {
2851 napi_complete(napi);
2852 /*Re Enable MSI-Rx Vector*/
2853 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2854 addr += 7 - ring->ring_no;
2855 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2859 return pkts_processed;
2862 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2864 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2865 int pkts_processed = 0;
2866 int ring_pkts_processed, i;
2867 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2868 int budget_org = budget;
2869 struct config_param *config = &nic->config;
2870 struct mac_info *mac_control = &nic->mac_control;
2872 if (unlikely(!is_s2io_card_up(nic)))
2875 for (i = 0; i < config->rx_ring_num; i++) {
2876 struct ring_info *ring = &mac_control->rings[i];
2877 ring_pkts_processed = rx_intr_handler(ring, budget);
2878 s2io_chk_rx_buffers(nic, ring);
2879 pkts_processed += ring_pkts_processed;
2880 budget -= ring_pkts_processed;
2884 if (pkts_processed < budget_org) {
2885 napi_complete(napi);
2886 /* Re enable the Rx interrupts for the ring */
2887 writeq(0, &bar0->rx_traffic_mask);
2888 readl(&bar0->rx_traffic_mask);
2890 return pkts_processed;
2893 #ifdef CONFIG_NET_POLL_CONTROLLER
2895 * s2io_netpoll - netpoll event handler entry point
2896 * @dev : pointer to the device structure.
2898 * This function will be called by upper layer to check for events on the
2899 * interface in situations where interrupts are disabled. It is used for
2900 * specific in-kernel networking tasks, such as remote consoles and kernel
2901 * debugging over the network (example netdump in RedHat).
2903 static void s2io_netpoll(struct net_device *dev)
2905 struct s2io_nic *nic = netdev_priv(dev);
2906 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2907 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2909 struct config_param *config = &nic->config;
2910 struct mac_info *mac_control = &nic->mac_control;
2912 if (pci_channel_offline(nic->pdev))
2915 disable_irq(dev->irq);
2917 writeq(val64, &bar0->rx_traffic_int);
2918 writeq(val64, &bar0->tx_traffic_int);
2920 /* we need to free up the transmitted skbufs or else netpoll will
2921 * run out of skbs and will fail and eventually netpoll application such
2922 * as netdump will fail.
2924 for (i = 0; i < config->tx_fifo_num; i++)
2925 tx_intr_handler(&mac_control->fifos[i]);
2927 /* check for received packet and indicate up to network */
2928 for (i = 0; i < config->rx_ring_num; i++) {
2929 struct ring_info *ring = &mac_control->rings[i];
2931 rx_intr_handler(ring, 0);
2934 for (i = 0; i < config->rx_ring_num; i++) {
2935 struct ring_info *ring = &mac_control->rings[i];
2937 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2939 "%s: Out of memory in Rx Netpoll!!\n",
2944 enable_irq(dev->irq);
2949 * rx_intr_handler - Rx interrupt handler
2950 * @ring_info: per ring structure.
2951 * @budget: budget for napi processing.
2953 * If the interrupt is because of a received frame or if the
2954 * receive ring contains fresh as yet un-processed frames,this function is
2955 * called. It picks out the RxD at which place the last Rx processing had
2956 * stopped and sends the skb to the OSM's Rx handler and then increments
2959 * No. of napi packets processed.
2961 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2963 int get_block, put_block;
2964 struct rx_curr_get_info get_info, put_info;
2966 struct sk_buff *skb;
2967 int pkt_cnt = 0, napi_pkts = 0;
2972 get_info = ring_data->rx_curr_get_info;
2973 get_block = get_info.block_index;
2974 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2975 put_block = put_info.block_index;
2976 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2978 while (RXD_IS_UP2DT(rxdp)) {
2980 * If your are next to put index then it's
2981 * FIFO full condition
2983 if ((get_block == put_block) &&
2984 (get_info.offset + 1) == put_info.offset) {
2985 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2986 ring_data->dev->name);
2989 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2991 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2992 ring_data->dev->name);
2995 if (ring_data->rxd_mode == RXD_MODE_1) {
2996 rxdp1 = (struct RxD1 *)rxdp;
2997 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3000 HEADER_ETHERNET_II_802_3_SIZE +
3003 PCI_DMA_FROMDEVICE);
3004 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3005 rxdp3 = (struct RxD3 *)rxdp;
3006 pci_dma_sync_single_for_cpu(ring_data->pdev,
3007 (dma_addr_t)rxdp3->Buffer0_ptr,
3009 PCI_DMA_FROMDEVICE);
3010 pci_unmap_single(ring_data->pdev,
3011 (dma_addr_t)rxdp3->Buffer2_ptr,
3013 PCI_DMA_FROMDEVICE);
3015 prefetch(skb->data);
3016 rx_osm_handler(ring_data, rxdp);
3018 ring_data->rx_curr_get_info.offset = get_info.offset;
3019 rxdp = ring_data->rx_blocks[get_block].
3020 rxds[get_info.offset].virt_addr;
3021 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3022 get_info.offset = 0;
3023 ring_data->rx_curr_get_info.offset = get_info.offset;
3025 if (get_block == ring_data->block_count)
3027 ring_data->rx_curr_get_info.block_index = get_block;
3028 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3031 if (ring_data->nic->config.napi) {
3038 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3041 if (ring_data->lro) {
3042 /* Clear all LRO sessions before exiting */
3043 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3044 struct lro *lro = &ring_data->lro0_n[i];
3046 update_L3L4_header(ring_data->nic, lro);
3047 queue_rx_frame(lro->parent, lro->vlan_tag);
3048 clear_lro_session(lro);
3056 * tx_intr_handler - Transmit interrupt handler
3057 * @nic : device private variable
3059 * If an interrupt was raised to indicate DMA complete of the
3060 * Tx packet, this function is called. It identifies the last TxD
3061 * whose buffer was freed and frees all skbs whose data have already
3062 * DMA'ed into the NICs internal memory.
3067 static void tx_intr_handler(struct fifo_info *fifo_data)
3069 struct s2io_nic *nic = fifo_data->nic;
3070 struct tx_curr_get_info get_info, put_info;
3071 struct sk_buff *skb = NULL;
3074 unsigned long flags = 0;
3076 struct stat_block *stats = nic->mac_control.stats_info;
3077 struct swStat *swstats = &stats->sw_stat;
3079 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3082 get_info = fifo_data->tx_curr_get_info;
3083 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3084 txdlp = (struct TxD *)
3085 fifo_data->list_info[get_info.offset].list_virt_addr;
3086 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3087 (get_info.offset != put_info.offset) &&
3088 (txdlp->Host_Control)) {
3089 /* Check for TxD errors */
3090 if (txdlp->Control_1 & TXD_T_CODE) {
3091 unsigned long long err;
3092 err = txdlp->Control_1 & TXD_T_CODE;
3094 swstats->parity_err_cnt++;
3097 /* update t_code statistics */
3098 err_mask = err >> 48;
3101 swstats->tx_buf_abort_cnt++;
3105 swstats->tx_desc_abort_cnt++;
3109 swstats->tx_parity_err_cnt++;
3113 swstats->tx_link_loss_cnt++;
3117 swstats->tx_list_proc_err_cnt++;
3122 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3124 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3125 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3131 /* Updating the statistics block */
3132 swstats->mem_freed += skb->truesize;
3133 dev_kfree_skb_irq(skb);
3136 if (get_info.offset == get_info.fifo_len + 1)
3137 get_info.offset = 0;
3138 txdlp = (struct TxD *)
3139 fifo_data->list_info[get_info.offset].list_virt_addr;
3140 fifo_data->tx_curr_get_info.offset = get_info.offset;
3143 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3145 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3149 * s2io_mdio_write - Function to write in to MDIO registers
3150 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3151 * @addr : address value
3152 * @value : data value
3153 * @dev : pointer to net_device structure
3155 * This function is used to write values to the MDIO registers
3158 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3159 struct net_device *dev)
3162 struct s2io_nic *sp = netdev_priv(dev);
3163 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3165 /* address transaction */
3166 val64 = MDIO_MMD_INDX_ADDR(addr) |
3167 MDIO_MMD_DEV_ADDR(mmd_type) |
3168 MDIO_MMS_PRT_ADDR(0x0);
3169 writeq(val64, &bar0->mdio_control);
3170 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3171 writeq(val64, &bar0->mdio_control);
3174 /* Data transaction */
3175 val64 = MDIO_MMD_INDX_ADDR(addr) |
3176 MDIO_MMD_DEV_ADDR(mmd_type) |
3177 MDIO_MMS_PRT_ADDR(0x0) |
3178 MDIO_MDIO_DATA(value) |
3179 MDIO_OP(MDIO_OP_WRITE_TRANS);
3180 writeq(val64, &bar0->mdio_control);
3181 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3182 writeq(val64, &bar0->mdio_control);
3185 val64 = MDIO_MMD_INDX_ADDR(addr) |
3186 MDIO_MMD_DEV_ADDR(mmd_type) |
3187 MDIO_MMS_PRT_ADDR(0x0) |
3188 MDIO_OP(MDIO_OP_READ_TRANS);
3189 writeq(val64, &bar0->mdio_control);
3190 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3191 writeq(val64, &bar0->mdio_control);
3196 * s2io_mdio_read - Function to write in to MDIO registers
3197 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3198 * @addr : address value
3199 * @dev : pointer to net_device structure
3201 * This function is used to read values to the MDIO registers
3204 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3208 struct s2io_nic *sp = netdev_priv(dev);
3209 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3211 /* address transaction */
3212 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3213 | MDIO_MMD_DEV_ADDR(mmd_type)
3214 | MDIO_MMS_PRT_ADDR(0x0));
3215 writeq(val64, &bar0->mdio_control);
3216 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3217 writeq(val64, &bar0->mdio_control);
3220 /* Data transaction */
3221 val64 = MDIO_MMD_INDX_ADDR(addr) |
3222 MDIO_MMD_DEV_ADDR(mmd_type) |
3223 MDIO_MMS_PRT_ADDR(0x0) |
3224 MDIO_OP(MDIO_OP_READ_TRANS);
3225 writeq(val64, &bar0->mdio_control);
3226 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3227 writeq(val64, &bar0->mdio_control);
3230 /* Read the value from regs */
3231 rval64 = readq(&bar0->mdio_control);
3232 rval64 = rval64 & 0xFFFF0000;
3233 rval64 = rval64 >> 16;
3238 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3239 * @counter : counter value to be updated
3240 * @flag : flag to indicate the status
3241 * @type : counter type
3243 * This function is to check the status of the xpak counters value
3247 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3253 for (i = 0; i < index; i++)
3257 *counter = *counter + 1;
3258 val64 = *regs_stat & mask;
3259 val64 = val64 >> (index * 0x2);
3265 "Take Xframe NIC out of service.\n");
3267 "Excessive temperatures may result in premature transceiver failure.\n");
3271 "Take Xframe NIC out of service.\n");
3273 "Excessive bias currents may indicate imminent laser diode failure.\n");
3277 "Take Xframe NIC out of service.\n");
3279 "Excessive laser output power may saturate far-end receiver.\n");
3283 "Incorrect XPAK Alarm type\n");
3287 val64 = val64 << (index * 0x2);
3288 *regs_stat = (*regs_stat & (~mask)) | (val64);
3291 *regs_stat = *regs_stat & (~mask);
3296 * s2io_updt_xpak_counter - Function to update the xpak counters
3297 * @dev : pointer to net_device struct
3299 * This function is to upate the status of the xpak counters value
3302 static void s2io_updt_xpak_counter(struct net_device *dev)
3310 struct s2io_nic *sp = netdev_priv(dev);
3311 struct stat_block *stats = sp->mac_control.stats_info;
3312 struct xpakStat *xstats = &stats->xpak_stat;
3314 /* Check the communication with the MDIO slave */
3317 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3318 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3320 "ERR: MDIO slave access failed - Returned %llx\n",
3321 (unsigned long long)val64);
3325 /* Check for the expected value of control reg 1 */
3326 if (val64 != MDIO_CTRL1_SPEED10G) {
3327 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3328 "Returned: %llx- Expected: 0x%x\n",
3329 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3333 /* Loading the DOM register to MDIO register */
3335 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3336 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3338 /* Reading the Alarm flags */
3341 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3343 flag = CHECKBIT(val64, 0x7);
3345 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3346 &xstats->xpak_regs_stat,
3349 if (CHECKBIT(val64, 0x6))
3350 xstats->alarm_transceiver_temp_low++;
3352 flag = CHECKBIT(val64, 0x3);
3354 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3355 &xstats->xpak_regs_stat,
3358 if (CHECKBIT(val64, 0x2))
3359 xstats->alarm_laser_bias_current_low++;
3361 flag = CHECKBIT(val64, 0x1);
3363 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3364 &xstats->xpak_regs_stat,
3367 if (CHECKBIT(val64, 0x0))
3368 xstats->alarm_laser_output_power_low++;
3370 /* Reading the Warning flags */
3373 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3375 if (CHECKBIT(val64, 0x7))
3376 xstats->warn_transceiver_temp_high++;
3378 if (CHECKBIT(val64, 0x6))
3379 xstats->warn_transceiver_temp_low++;
3381 if (CHECKBIT(val64, 0x3))
3382 xstats->warn_laser_bias_current_high++;
3384 if (CHECKBIT(val64, 0x2))
3385 xstats->warn_laser_bias_current_low++;
3387 if (CHECKBIT(val64, 0x1))
3388 xstats->warn_laser_output_power_high++;
3390 if (CHECKBIT(val64, 0x0))
3391 xstats->warn_laser_output_power_low++;
3395 * wait_for_cmd_complete - waits for a command to complete.
3396 * @sp : private member of the device structure, which is a pointer to the
3397 * s2io_nic structure.
3398 * Description: Function that waits for a command to Write into RMAC
3399 * ADDR DATA registers to be completed and returns either success or
3400 * error depending on whether the command was complete or not.
3402 * SUCCESS on success and FAILURE on failure.
3405 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3408 int ret = FAILURE, cnt = 0, delay = 1;
3411 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3415 val64 = readq(addr);
3416 if (bit_state == S2IO_BIT_RESET) {
3417 if (!(val64 & busy_bit)) {
3422 if (val64 & busy_bit) {
3439 * check_pci_device_id - Checks if the device id is supported
3441 * Description: Function to check if the pci device id is supported by driver.
3442 * Return value: Actual device id if supported else PCI_ANY_ID
3444 static u16 check_pci_device_id(u16 id)
3447 case PCI_DEVICE_ID_HERC_WIN:
3448 case PCI_DEVICE_ID_HERC_UNI:
3449 return XFRAME_II_DEVICE;
3450 case PCI_DEVICE_ID_S2IO_UNI:
3451 case PCI_DEVICE_ID_S2IO_WIN:
3452 return XFRAME_I_DEVICE;
3459 * s2io_reset - Resets the card.
3460 * @sp : private member of the device structure.
3461 * Description: Function to Reset the card. This function then also
3462 * restores the previously saved PCI configuration space registers as
3463 * the card reset also resets the configuration space.
3468 static void s2io_reset(struct s2io_nic *sp)
3470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3475 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3476 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3477 struct stat_block *stats;
3478 struct swStat *swstats;
3480 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3481 __func__, pci_name(sp->pdev));
3483 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3484 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3486 val64 = SW_RESET_ALL;
3487 writeq(val64, &bar0->sw_reset);
3488 if (strstr(sp->product_name, "CX4"))
3491 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3493 /* Restore the PCI state saved during initialization. */
3494 pci_restore_state(sp->pdev);
3495 pci_save_state(sp->pdev);
3496 pci_read_config_word(sp->pdev, 0x2, &val16);
3497 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3502 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3503 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3505 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3509 /* Set swapper to enable I/O register access */
3510 s2io_set_swapper(sp);
3512 /* restore mac_addr entries */
3513 do_s2io_restore_unicast_mc(sp);
3515 /* Restore the MSIX table entries from local variables */
3516 restore_xmsi_data(sp);
3518 /* Clear certain PCI/PCI-X fields after reset */
3519 if (sp->device_type == XFRAME_II_DEVICE) {
3520 /* Clear "detected parity error" bit */
3521 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3523 /* Clearing PCIX Ecc status register */
3524 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3526 /* Clearing PCI_STATUS error reflected here */
3527 writeq(s2BIT(62), &bar0->txpic_int_reg);
3530 /* Reset device statistics maintained by OS */
3531 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3533 stats = sp->mac_control.stats_info;
3534 swstats = &stats->sw_stat;
3536 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3537 up_cnt = swstats->link_up_cnt;
3538 down_cnt = swstats->link_down_cnt;
3539 up_time = swstats->link_up_time;
3540 down_time = swstats->link_down_time;
3541 reset_cnt = swstats->soft_reset_cnt;
3542 mem_alloc_cnt = swstats->mem_allocated;
3543 mem_free_cnt = swstats->mem_freed;
3544 watchdog_cnt = swstats->watchdog_timer_cnt;
3546 memset(stats, 0, sizeof(struct stat_block));
3548 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3549 swstats->link_up_cnt = up_cnt;
3550 swstats->link_down_cnt = down_cnt;
3551 swstats->link_up_time = up_time;
3552 swstats->link_down_time = down_time;
3553 swstats->soft_reset_cnt = reset_cnt;
3554 swstats->mem_allocated = mem_alloc_cnt;
3555 swstats->mem_freed = mem_free_cnt;
3556 swstats->watchdog_timer_cnt = watchdog_cnt;
3558 /* SXE-002: Configure link and activity LED to turn it off */
3559 subid = sp->pdev->subsystem_device;
3560 if (((subid & 0xFF) >= 0x07) &&
3561 (sp->device_type == XFRAME_I_DEVICE)) {
3562 val64 = readq(&bar0->gpio_control);
3563 val64 |= 0x0000800000000000ULL;
3564 writeq(val64, &bar0->gpio_control);
3565 val64 = 0x0411040400000000ULL;
3566 writeq(val64, (void __iomem *)bar0 + 0x2700);
3570 * Clear spurious ECC interrupts that would have occured on
3571 * XFRAME II cards after reset.
3573 if (sp->device_type == XFRAME_II_DEVICE) {
3574 val64 = readq(&bar0->pcc_err_reg);
3575 writeq(val64, &bar0->pcc_err_reg);
3578 sp->device_enabled_once = false;
3582 * s2io_set_swapper - to set the swapper controle on the card
3583 * @sp : private member of the device structure,
3584 * pointer to the s2io_nic structure.
3585 * Description: Function to set the swapper control on the card
3586 * correctly depending on the 'endianness' of the system.
3588 * SUCCESS on success and FAILURE on failure.
3591 static int s2io_set_swapper(struct s2io_nic *sp)
3593 struct net_device *dev = sp->dev;
3594 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3595 u64 val64, valt, valr;
3598 * Set proper endian settings and verify the same by reading
3599 * the PIF Feed-back register.
3602 val64 = readq(&bar0->pif_rd_swapper_fb);
3603 if (val64 != 0x0123456789ABCDEFULL) {
3605 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3606 0x8100008181000081ULL, /* FE=1, SE=0 */
3607 0x4200004242000042ULL, /* FE=0, SE=1 */
3608 0}; /* FE=0, SE=0 */
3611 writeq(value[i], &bar0->swapper_ctrl);
3612 val64 = readq(&bar0->pif_rd_swapper_fb);
3613 if (val64 == 0x0123456789ABCDEFULL)
3618 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3619 "feedback read %llx\n",
3620 dev->name, (unsigned long long)val64);
3625 valr = readq(&bar0->swapper_ctrl);
3628 valt = 0x0123456789ABCDEFULL;
3629 writeq(valt, &bar0->xmsi_address);
3630 val64 = readq(&bar0->xmsi_address);
3632 if (val64 != valt) {
3634 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3635 0x0081810000818100ULL, /* FE=1, SE=0 */
3636 0x0042420000424200ULL, /* FE=0, SE=1 */
3637 0}; /* FE=0, SE=0 */
3640 writeq((value[i] | valr), &bar0->swapper_ctrl);
3641 writeq(valt, &bar0->xmsi_address);
3642 val64 = readq(&bar0->xmsi_address);
3648 unsigned long long x = val64;
3650 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3654 val64 = readq(&bar0->swapper_ctrl);
3655 val64 &= 0xFFFF000000000000ULL;
3659 * The device by default set to a big endian format, so a
3660 * big endian driver need not set anything.
3662 val64 |= (SWAPPER_CTRL_TXP_FE |
3663 SWAPPER_CTRL_TXP_SE |
3664 SWAPPER_CTRL_TXD_R_FE |
3665 SWAPPER_CTRL_TXD_W_FE |
3666 SWAPPER_CTRL_TXF_R_FE |
3667 SWAPPER_CTRL_RXD_R_FE |
3668 SWAPPER_CTRL_RXD_W_FE |
3669 SWAPPER_CTRL_RXF_W_FE |
3670 SWAPPER_CTRL_XMSI_FE |
3671 SWAPPER_CTRL_STATS_FE |
3672 SWAPPER_CTRL_STATS_SE);
3673 if (sp->config.intr_type == INTA)
3674 val64 |= SWAPPER_CTRL_XMSI_SE;
3675 writeq(val64, &bar0->swapper_ctrl);
3678 * Initially we enable all bits to make it accessible by the
3679 * driver, then we selectively enable only those bits that
3682 val64 |= (SWAPPER_CTRL_TXP_FE |
3683 SWAPPER_CTRL_TXP_SE |
3684 SWAPPER_CTRL_TXD_R_FE |
3685 SWAPPER_CTRL_TXD_R_SE |
3686 SWAPPER_CTRL_TXD_W_FE |
3687 SWAPPER_CTRL_TXD_W_SE |
3688 SWAPPER_CTRL_TXF_R_FE |
3689 SWAPPER_CTRL_RXD_R_FE |
3690 SWAPPER_CTRL_RXD_R_SE |
3691 SWAPPER_CTRL_RXD_W_FE |
3692 SWAPPER_CTRL_RXD_W_SE |
3693 SWAPPER_CTRL_RXF_W_FE |
3694 SWAPPER_CTRL_XMSI_FE |
3695 SWAPPER_CTRL_STATS_FE |
3696 SWAPPER_CTRL_STATS_SE);
3697 if (sp->config.intr_type == INTA)
3698 val64 |= SWAPPER_CTRL_XMSI_SE;
3699 writeq(val64, &bar0->swapper_ctrl);
3701 val64 = readq(&bar0->swapper_ctrl);
3704 * Verifying if endian settings are accurate by reading a
3705 * feedback register.
3707 val64 = readq(&bar0->pif_rd_swapper_fb);
3708 if (val64 != 0x0123456789ABCDEFULL) {
3709 /* Endian settings are incorrect, calls for another dekko. */
3711 "%s: Endian settings are wrong, feedback read %llx\n",
3712 dev->name, (unsigned long long)val64);
3719 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3721 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3723 int ret = 0, cnt = 0;
3726 val64 = readq(&bar0->xmsi_access);
3727 if (!(val64 & s2BIT(15)))
3733 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3740 static void restore_xmsi_data(struct s2io_nic *nic)
3742 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3746 if (nic->device_type == XFRAME_I_DEVICE)
3749 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3750 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3751 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3752 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3753 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3754 writeq(val64, &bar0->xmsi_access);
3755 if (wait_for_msix_trans(nic, msix_index)) {
3756 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3757 __func__, msix_index);
3763 static void store_xmsi_data(struct s2io_nic *nic)
3765 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3766 u64 val64, addr, data;
3769 if (nic->device_type == XFRAME_I_DEVICE)
3772 /* Store and display */
3773 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3774 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3775 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3776 writeq(val64, &bar0->xmsi_access);
3777 if (wait_for_msix_trans(nic, msix_index)) {
3778 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3779 __func__, msix_index);
3782 addr = readq(&bar0->xmsi_address);
3783 data = readq(&bar0->xmsi_data);
3785 nic->msix_info[i].addr = addr;
3786 nic->msix_info[i].data = data;
3791 static int s2io_enable_msi_x(struct s2io_nic *nic)
3793 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3795 u16 msi_control; /* Temp variable */
3796 int ret, i, j, msix_indx = 1;
3798 struct stat_block *stats = nic->mac_control.stats_info;
3799 struct swStat *swstats = &stats->sw_stat;
3801 size = nic->num_entries * sizeof(struct msix_entry);
3802 nic->entries = kzalloc(size, GFP_KERNEL);
3803 if (!nic->entries) {
3804 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3806 swstats->mem_alloc_fail_cnt++;
3809 swstats->mem_allocated += size;
3811 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3812 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3813 if (!nic->s2io_entries) {
3814 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3816 swstats->mem_alloc_fail_cnt++;
3817 kfree(nic->entries);
3819 += (nic->num_entries * sizeof(struct msix_entry));
3822 swstats->mem_allocated += size;
3824 nic->entries[0].entry = 0;
3825 nic->s2io_entries[0].entry = 0;
3826 nic->s2io_entries[0].in_use = MSIX_FLG;
3827 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3828 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3830 for (i = 1; i < nic->num_entries; i++) {
3831 nic->entries[i].entry = ((i - 1) * 8) + 1;
3832 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3833 nic->s2io_entries[i].arg = NULL;
3834 nic->s2io_entries[i].in_use = 0;
3837 rx_mat = readq(&bar0->rx_mat);
3838 for (j = 0; j < nic->config.rx_ring_num; j++) {
3839 rx_mat |= RX_MAT_SET(j, msix_indx);
3840 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3841 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3842 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3845 writeq(rx_mat, &bar0->rx_mat);
3846 readq(&bar0->rx_mat);
3848 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3849 /* We fail init if error or we get less vectors than min required */
3851 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3852 kfree(nic->entries);
3853 swstats->mem_freed += nic->num_entries *
3854 sizeof(struct msix_entry);
3855 kfree(nic->s2io_entries);
3856 swstats->mem_freed += nic->num_entries *
3857 sizeof(struct s2io_msix_entry);
3858 nic->entries = NULL;
3859 nic->s2io_entries = NULL;
3864 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3865 * in the herc NIC. (Temp change, needs to be removed later)
3867 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3868 msi_control |= 0x1; /* Enable MSI */
3869 pci_write_config_word(nic->pdev, 0x42, msi_control);
3874 /* Handle software interrupt used during MSI(X) test */
3875 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3877 struct s2io_nic *sp = dev_id;
3879 sp->msi_detected = 1;
3880 wake_up(&sp->msi_wait);
3885 /* Test interrupt path by forcing a a software IRQ */
3886 static int s2io_test_msi(struct s2io_nic *sp)
3888 struct pci_dev *pdev = sp->pdev;
3889 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3893 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3896 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3897 sp->dev->name, pci_name(pdev), pdev->irq);
3901 init_waitqueue_head(&sp->msi_wait);
3902 sp->msi_detected = 0;
3904 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3905 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3906 val64 |= SCHED_INT_CTRL_TIMER_EN;
3907 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3908 writeq(val64, &bar0->scheduled_int_ctrl);
3910 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3912 if (!sp->msi_detected) {
3913 /* MSI(X) test failed, go back to INTx mode */
3914 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3915 "using MSI(X) during test\n",
3916 sp->dev->name, pci_name(pdev));
3921 free_irq(sp->entries[1].vector, sp);
3923 writeq(saved64, &bar0->scheduled_int_ctrl);
3928 static void remove_msix_isr(struct s2io_nic *sp)
3933 for (i = 0; i < sp->num_entries; i++) {
3934 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3935 int vector = sp->entries[i].vector;
3936 void *arg = sp->s2io_entries[i].arg;
3937 free_irq(vector, arg);
3942 kfree(sp->s2io_entries);
3944 sp->s2io_entries = NULL;
3946 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3947 msi_control &= 0xFFFE; /* Disable MSI */
3948 pci_write_config_word(sp->pdev, 0x42, msi_control);
3950 pci_disable_msix(sp->pdev);
3953 static void remove_inta_isr(struct s2io_nic *sp)
3955 struct net_device *dev = sp->dev;
3957 free_irq(sp->pdev->irq, dev);
3960 /* ********************************************************* *
3961 * Functions defined below concern the OS part of the driver *
3962 * ********************************************************* */
3965 * s2io_open - open entry point of the driver
3966 * @dev : pointer to the device structure.
3968 * This function is the open entry point of the driver. It mainly calls a
3969 * function to allocate Rx buffers and inserts them into the buffer
3970 * descriptors and then enables the Rx part of the NIC.
3972 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3976 static int s2io_open(struct net_device *dev)
3978 struct s2io_nic *sp = netdev_priv(dev);
3979 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3983 * Make sure you have link off by default every time
3984 * Nic is initialized
3986 netif_carrier_off(dev);
3987 sp->last_link_state = 0;
3989 /* Initialize H/W and enable interrupts */
3990 err = s2io_card_up(sp);
3992 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3994 goto hw_init_failed;
3997 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3998 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4001 goto hw_init_failed;
4003 s2io_start_all_tx_queue(sp);
4007 if (sp->config.intr_type == MSI_X) {
4010 swstats->mem_freed += sp->num_entries *
4011 sizeof(struct msix_entry);
4013 if (sp->s2io_entries) {
4014 kfree(sp->s2io_entries);
4015 swstats->mem_freed += sp->num_entries *
4016 sizeof(struct s2io_msix_entry);
4023 * s2io_close -close entry point of the driver
4024 * @dev : device pointer.
4026 * This is the stop entry point of the driver. It needs to undo exactly
4027 * whatever was done by the open entry point,thus it's usually referred to
4028 * as the close function.Among other things this function mainly stops the
4029 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4031 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4035 static int s2io_close(struct net_device *dev)
4037 struct s2io_nic *sp = netdev_priv(dev);
4038 struct config_param *config = &sp->config;
4042 /* Return if the device is already closed *
4043 * Can happen when s2io_card_up failed in change_mtu *
4045 if (!is_s2io_card_up(sp))
4048 s2io_stop_all_tx_queue(sp);
4049 /* delete all populated mac entries */
4050 for (offset = 1; offset < config->max_mc_addr; offset++) {
4051 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4052 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4053 do_s2io_delete_unicast_mc(sp, tmp64);
4062 * s2io_xmit - Tx entry point of te driver
4063 * @skb : the socket buffer containing the Tx data.
4064 * @dev : device pointer.
4066 * This function is the Tx entry point of the driver. S2IO NIC supports
4067 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4068 * NOTE: when device cant queue the pkt,just the trans_start variable will
4071 * 0 on success & 1 on failure.
4074 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4076 struct s2io_nic *sp = netdev_priv(dev);
4077 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4080 struct TxFIFO_element __iomem *tx_fifo;
4081 unsigned long flags = 0;
4083 struct fifo_info *fifo = NULL;
4084 int do_spin_lock = 1;
4086 int enable_per_list_interrupt = 0;
4087 struct config_param *config = &sp->config;
4088 struct mac_info *mac_control = &sp->mac_control;
4089 struct stat_block *stats = mac_control->stats_info;
4090 struct swStat *swstats = &stats->sw_stat;
4092 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4094 if (unlikely(skb->len <= 0)) {
4095 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4096 dev_kfree_skb_any(skb);
4097 return NETDEV_TX_OK;
4100 if (!is_s2io_card_up(sp)) {
4101 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4104 return NETDEV_TX_OK;
4108 if (sp->vlgrp && vlan_tx_tag_present(skb))
4109 vlan_tag = vlan_tx_tag_get(skb);
4110 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4111 if (skb->protocol == htons(ETH_P_IP)) {
4116 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4117 th = (struct tcphdr *)(((unsigned char *)ip) +
4120 if (ip->protocol == IPPROTO_TCP) {
4121 queue_len = sp->total_tcp_fifos;
4122 queue = (ntohs(th->source) +
4124 sp->fifo_selector[queue_len - 1];
4125 if (queue >= queue_len)
4126 queue = queue_len - 1;
4127 } else if (ip->protocol == IPPROTO_UDP) {
4128 queue_len = sp->total_udp_fifos;
4129 queue = (ntohs(th->source) +
4131 sp->fifo_selector[queue_len - 1];
4132 if (queue >= queue_len)
4133 queue = queue_len - 1;
4134 queue += sp->udp_fifo_idx;
4135 if (skb->len > 1024)
4136 enable_per_list_interrupt = 1;
4141 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4142 /* get fifo number based on skb->priority value */
4143 queue = config->fifo_mapping
4144 [skb->priority & (MAX_TX_FIFOS - 1)];
4145 fifo = &mac_control->fifos[queue];
4148 spin_lock_irqsave(&fifo->tx_lock, flags);
4150 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4151 return NETDEV_TX_LOCKED;
4154 if (sp->config.multiq) {
4155 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4156 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4157 return NETDEV_TX_BUSY;
4159 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4160 if (netif_queue_stopped(dev)) {
4161 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4162 return NETDEV_TX_BUSY;
4166 put_off = (u16)fifo->tx_curr_put_info.offset;
4167 get_off = (u16)fifo->tx_curr_get_info.offset;
4168 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4170 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4171 /* Avoid "put" pointer going beyond "get" pointer */
4172 if (txdp->Host_Control ||
4173 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4174 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4175 s2io_stop_tx_queue(sp, fifo->fifo_no);
4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178 return NETDEV_TX_OK;
4181 offload_type = s2io_offload_type(skb);
4182 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4183 txdp->Control_1 |= TXD_TCP_LSO_EN;
4184 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4186 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4187 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4191 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4192 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4193 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4194 if (enable_per_list_interrupt)
4195 if (put_off & (queue_len >> 5))
4196 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4198 txdp->Control_2 |= TXD_VLAN_ENABLE;
4199 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4202 frg_len = skb_headlen(skb);
4203 if (offload_type == SKB_GSO_UDP) {
4206 ufo_size = s2io_udp_mss(skb);
4208 txdp->Control_1 |= TXD_UFO_EN;
4209 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4210 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4212 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4213 fifo->ufo_in_band_v[put_off] =
4214 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4216 fifo->ufo_in_band_v[put_off] =
4217 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4219 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4220 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4221 fifo->ufo_in_band_v,
4224 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4225 goto pci_map_failed;
4229 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4230 frg_len, PCI_DMA_TODEVICE);
4231 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4232 goto pci_map_failed;
4234 txdp->Host_Control = (unsigned long)skb;
4235 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4236 if (offload_type == SKB_GSO_UDP)
4237 txdp->Control_1 |= TXD_UFO_EN;
4239 frg_cnt = skb_shinfo(skb)->nr_frags;
4240 /* For fragmented SKB. */
4241 for (i = 0; i < frg_cnt; i++) {
4242 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4243 /* A '0' length fragment will be ignored */
4247 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4251 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4252 if (offload_type == SKB_GSO_UDP)
4253 txdp->Control_1 |= TXD_UFO_EN;
4255 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4257 if (offload_type == SKB_GSO_UDP)
4258 frg_cnt++; /* as Txd0 was used for inband header */
4260 tx_fifo = mac_control->tx_FIFO_start[queue];
4261 val64 = fifo->list_info[put_off].list_phy_addr;
4262 writeq(val64, &tx_fifo->TxDL_Pointer);
4264 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4267 val64 |= TX_FIFO_SPECIAL_FUNC;
4269 writeq(val64, &tx_fifo->List_Control);
4274 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4276 fifo->tx_curr_put_info.offset = put_off;
4278 /* Avoid "put" pointer going beyond "get" pointer */
4279 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4280 swstats->fifo_full_cnt++;
4282 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4284 s2io_stop_tx_queue(sp, fifo->fifo_no);
4286 swstats->mem_allocated += skb->truesize;
4287 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4289 if (sp->config.intr_type == MSI_X)
4290 tx_intr_handler(fifo);
4292 return NETDEV_TX_OK;
4295 swstats->pci_map_fail_cnt++;
4296 s2io_stop_tx_queue(sp, fifo->fifo_no);
4297 swstats->mem_freed += skb->truesize;
4299 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4300 return NETDEV_TX_OK;
4304 s2io_alarm_handle(unsigned long data)
4306 struct s2io_nic *sp = (struct s2io_nic *)data;
4307 struct net_device *dev = sp->dev;
4309 s2io_handle_errors(dev);
4310 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4313 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4315 struct ring_info *ring = (struct ring_info *)dev_id;
4316 struct s2io_nic *sp = ring->nic;
4317 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4319 if (unlikely(!is_s2io_card_up(sp)))
4322 if (sp->config.napi) {
4323 u8 __iomem *addr = NULL;
4326 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4327 addr += (7 - ring->ring_no);
4328 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4331 napi_schedule(&ring->napi);
4333 rx_intr_handler(ring, 0);
4334 s2io_chk_rx_buffers(sp, ring);
4340 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4343 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4344 struct s2io_nic *sp = fifos->nic;
4345 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4346 struct config_param *config = &sp->config;
4349 if (unlikely(!is_s2io_card_up(sp)))
4352 reason = readq(&bar0->general_int_status);
4353 if (unlikely(reason == S2IO_MINUS_ONE))
4354 /* Nothing much can be done. Get out */
4357 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4358 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4360 if (reason & GEN_INTR_TXPIC)
4361 s2io_txpic_intr_handle(sp);
4363 if (reason & GEN_INTR_TXTRAFFIC)
4364 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4366 for (i = 0; i < config->tx_fifo_num; i++)
4367 tx_intr_handler(&fifos[i]);
4369 writeq(sp->general_int_mask, &bar0->general_int_mask);
4370 readl(&bar0->general_int_status);
4373 /* The interrupt was not raised by us */
4377 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4379 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4382 val64 = readq(&bar0->pic_int_status);
4383 if (val64 & PIC_INT_GPIO) {
4384 val64 = readq(&bar0->gpio_int_reg);
4385 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4386 (val64 & GPIO_INT_REG_LINK_UP)) {
4388 * This is unstable state so clear both up/down
4389 * interrupt and adapter to re-evaluate the link state.
4391 val64 |= GPIO_INT_REG_LINK_DOWN;
4392 val64 |= GPIO_INT_REG_LINK_UP;
4393 writeq(val64, &bar0->gpio_int_reg);
4394 val64 = readq(&bar0->gpio_int_mask);
4395 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4396 GPIO_INT_MASK_LINK_DOWN);
4397 writeq(val64, &bar0->gpio_int_mask);
4398 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4399 val64 = readq(&bar0->adapter_status);
4400 /* Enable Adapter */
4401 val64 = readq(&bar0->adapter_control);
4402 val64 |= ADAPTER_CNTL_EN;
4403 writeq(val64, &bar0->adapter_control);
4404 val64 |= ADAPTER_LED_ON;
4405 writeq(val64, &bar0->adapter_control);
4406 if (!sp->device_enabled_once)
4407 sp->device_enabled_once = 1;
4409 s2io_link(sp, LINK_UP);
4411 * unmask link down interrupt and mask link-up
4414 val64 = readq(&bar0->gpio_int_mask);
4415 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4416 val64 |= GPIO_INT_MASK_LINK_UP;
4417 writeq(val64, &bar0->gpio_int_mask);
4419 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4420 val64 = readq(&bar0->adapter_status);
4421 s2io_link(sp, LINK_DOWN);
4422 /* Link is down so unmaks link up interrupt */
4423 val64 = readq(&bar0->gpio_int_mask);
4424 val64 &= ~GPIO_INT_MASK_LINK_UP;
4425 val64 |= GPIO_INT_MASK_LINK_DOWN;
4426 writeq(val64, &bar0->gpio_int_mask);
4429 val64 = readq(&bar0->adapter_control);
4430 val64 = val64 & (~ADAPTER_LED_ON);
4431 writeq(val64, &bar0->adapter_control);
4434 val64 = readq(&bar0->gpio_int_mask);
4438 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4439 * @value: alarm bits
4440 * @addr: address value
4441 * @cnt: counter variable
4442 * Description: Check for alarm and increment the counter
4444 * 1 - if alarm bit set
4445 * 0 - if alarm bit is not set
4447 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4448 unsigned long long *cnt)
4451 val64 = readq(addr);
4452 if (val64 & value) {
4453 writeq(val64, addr);
4462 * s2io_handle_errors - Xframe error indication handler
4463 * @nic: device private variable
4464 * Description: Handle alarms such as loss of link, single or
4465 * double ECC errors, critical and serious errors.
4469 static void s2io_handle_errors(void *dev_id)
4471 struct net_device *dev = (struct net_device *)dev_id;
4472 struct s2io_nic *sp = netdev_priv(dev);
4473 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4474 u64 temp64 = 0, val64 = 0;
4477 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4478 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4480 if (!is_s2io_card_up(sp))
4483 if (pci_channel_offline(sp->pdev))
4486 memset(&sw_stat->ring_full_cnt, 0,
4487 sizeof(sw_stat->ring_full_cnt));
4489 /* Handling the XPAK counters update */
4490 if (stats->xpak_timer_count < 72000) {
4491 /* waiting for an hour */
4492 stats->xpak_timer_count++;
4494 s2io_updt_xpak_counter(dev);
4495 /* reset the count to zero */
4496 stats->xpak_timer_count = 0;
4499 /* Handling link status change error Intr */
4500 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4501 val64 = readq(&bar0->mac_rmac_err_reg);
4502 writeq(val64, &bar0->mac_rmac_err_reg);
4503 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4504 schedule_work(&sp->set_link_task);
4507 /* In case of a serious error, the device will be Reset. */
4508 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4509 &sw_stat->serious_err_cnt))
4512 /* Check for data parity error */
4513 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4514 &sw_stat->parity_err_cnt))
4517 /* Check for ring full counter */
4518 if (sp->device_type == XFRAME_II_DEVICE) {
4519 val64 = readq(&bar0->ring_bump_counter1);
4520 for (i = 0; i < 4; i++) {
4521 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4522 temp64 >>= 64 - ((i+1)*16);
4523 sw_stat->ring_full_cnt[i] += temp64;
4526 val64 = readq(&bar0->ring_bump_counter2);
4527 for (i = 0; i < 4; i++) {
4528 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4529 temp64 >>= 64 - ((i+1)*16);
4530 sw_stat->ring_full_cnt[i+4] += temp64;
4534 val64 = readq(&bar0->txdma_int_status);
4535 /*check for pfc_err*/
4536 if (val64 & TXDMA_PFC_INT) {
4537 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4538 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4541 &sw_stat->pfc_err_cnt))
4543 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4545 &sw_stat->pfc_err_cnt);
4548 /*check for tda_err*/
4549 if (val64 & TXDMA_TDA_INT) {
4550 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4554 &sw_stat->tda_err_cnt))
4556 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4558 &sw_stat->tda_err_cnt);
4560 /*check for pcc_err*/
4561 if (val64 & TXDMA_PCC_INT) {
4562 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4563 PCC_N_SERR | PCC_6_COF_OV_ERR |
4564 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4565 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4568 &sw_stat->pcc_err_cnt))
4570 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4572 &sw_stat->pcc_err_cnt);
4575 /*check for tti_err*/
4576 if (val64 & TXDMA_TTI_INT) {
4577 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4579 &sw_stat->tti_err_cnt))
4581 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4583 &sw_stat->tti_err_cnt);
4586 /*check for lso_err*/
4587 if (val64 & TXDMA_LSO_INT) {
4588 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4589 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4591 &sw_stat->lso_err_cnt))
4593 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4595 &sw_stat->lso_err_cnt);
4598 /*check for tpa_err*/
4599 if (val64 & TXDMA_TPA_INT) {
4600 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4602 &sw_stat->tpa_err_cnt))
4604 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4606 &sw_stat->tpa_err_cnt);
4609 /*check for sm_err*/
4610 if (val64 & TXDMA_SM_INT) {
4611 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4613 &sw_stat->sm_err_cnt))
4617 val64 = readq(&bar0->mac_int_status);
4618 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4619 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4620 &bar0->mac_tmac_err_reg,
4621 &sw_stat->mac_tmac_err_cnt))
4623 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4624 TMAC_DESC_ECC_SG_ERR |
4625 TMAC_DESC_ECC_DB_ERR,
4626 &bar0->mac_tmac_err_reg,
4627 &sw_stat->mac_tmac_err_cnt);
4630 val64 = readq(&bar0->xgxs_int_status);
4631 if (val64 & XGXS_INT_STATUS_TXGXS) {
4632 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt))
4636 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt);
4641 val64 = readq(&bar0->rxdma_int_status);
4642 if (val64 & RXDMA_INT_RC_INT_M) {
4643 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4645 RC_PRCn_SM_ERR_ALARM |
4646 RC_FTC_SM_ERR_ALARM,
4648 &sw_stat->rc_err_cnt))
4650 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4652 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4653 &sw_stat->rc_err_cnt);
4654 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4657 &bar0->prc_pcix_err_reg,
4658 &sw_stat->prc_pcix_err_cnt))
4660 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4663 &bar0->prc_pcix_err_reg,
4664 &sw_stat->prc_pcix_err_cnt);
4667 if (val64 & RXDMA_INT_RPA_INT_M) {
4668 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4670 &sw_stat->rpa_err_cnt))
4672 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4674 &sw_stat->rpa_err_cnt);
4677 if (val64 & RXDMA_INT_RDA_INT_M) {
4678 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4679 RDA_FRM_ECC_DB_N_AERR |
4682 RDA_RXD_ECC_DB_SERR,
4684 &sw_stat->rda_err_cnt))
4686 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4687 RDA_FRM_ECC_SG_ERR |
4691 &sw_stat->rda_err_cnt);
4694 if (val64 & RXDMA_INT_RTI_INT_M) {
4695 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4697 &sw_stat->rti_err_cnt))
4699 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4701 &sw_stat->rti_err_cnt);
4704 val64 = readq(&bar0->mac_int_status);
4705 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4706 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4707 &bar0->mac_rmac_err_reg,
4708 &sw_stat->mac_rmac_err_cnt))
4710 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4711 RMAC_SINGLE_ECC_ERR |
4712 RMAC_DOUBLE_ECC_ERR,
4713 &bar0->mac_rmac_err_reg,
4714 &sw_stat->mac_rmac_err_cnt);
4717 val64 = readq(&bar0->xgxs_int_status);
4718 if (val64 & XGXS_INT_STATUS_RXGXS) {
4719 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4720 &bar0->xgxs_rxgxs_err_reg,
4721 &sw_stat->xgxs_rxgxs_err_cnt))
4725 val64 = readq(&bar0->mc_int_status);
4726 if (val64 & MC_INT_STATUS_MC_INT) {
4727 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4729 &sw_stat->mc_err_cnt))
4732 /* Handling Ecc errors */
4733 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4734 writeq(val64, &bar0->mc_err_reg);
4735 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4736 sw_stat->double_ecc_errs++;
4737 if (sp->device_type != XFRAME_II_DEVICE) {
4739 * Reset XframeI only if critical error
4742 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4743 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4747 sw_stat->single_ecc_errs++;
4753 s2io_stop_all_tx_queue(sp);
4754 schedule_work(&sp->rst_timer_task);
4755 sw_stat->soft_reset_cnt++;
4759 * s2io_isr - ISR handler of the device .
4760 * @irq: the irq of the device.
4761 * @dev_id: a void pointer to the dev structure of the NIC.
4762 * Description: This function is the ISR handler of the device. It
4763 * identifies the reason for the interrupt and calls the relevant
4764 * service routines. As a contongency measure, this ISR allocates the
4765 * recv buffers, if their numbers are below the panic value which is
4766 * presently set to 25% of the original number of rcv buffers allocated.
4768 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4769 * IRQ_NONE: will be returned if interrupt is not from our device
4771 static irqreturn_t s2io_isr(int irq, void *dev_id)
4773 struct net_device *dev = (struct net_device *)dev_id;
4774 struct s2io_nic *sp = netdev_priv(dev);
4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4778 struct mac_info *mac_control;
4779 struct config_param *config;
4781 /* Pretend we handled any irq's from a disconnected card */
4782 if (pci_channel_offline(sp->pdev))
4785 if (!is_s2io_card_up(sp))
4788 config = &sp->config;
4789 mac_control = &sp->mac_control;
4792 * Identify the cause for interrupt and call the appropriate
4793 * interrupt handler. Causes for the interrupt could be;
4798 reason = readq(&bar0->general_int_status);
4800 if (unlikely(reason == S2IO_MINUS_ONE))
4801 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4804 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4805 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4808 if (reason & GEN_INTR_RXTRAFFIC) {
4809 napi_schedule(&sp->napi);
4810 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4812 readl(&bar0->rx_traffic_int);
4816 * rx_traffic_int reg is an R1 register, writing all 1's
4817 * will ensure that the actual interrupt causing bit
4818 * get's cleared and hence a read can be avoided.
4820 if (reason & GEN_INTR_RXTRAFFIC)
4821 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4823 for (i = 0; i < config->rx_ring_num; i++) {
4824 struct ring_info *ring = &mac_control->rings[i];
4826 rx_intr_handler(ring, 0);
4831 * tx_traffic_int reg is an R1 register, writing all 1's
4832 * will ensure that the actual interrupt causing bit get's
4833 * cleared and hence a read can be avoided.
4835 if (reason & GEN_INTR_TXTRAFFIC)
4836 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4838 for (i = 0; i < config->tx_fifo_num; i++)
4839 tx_intr_handler(&mac_control->fifos[i]);
4841 if (reason & GEN_INTR_TXPIC)
4842 s2io_txpic_intr_handle(sp);
4845 * Reallocate the buffers from the interrupt handler itself.
4847 if (!config->napi) {
4848 for (i = 0; i < config->rx_ring_num; i++) {
4849 struct ring_info *ring = &mac_control->rings[i];
4851 s2io_chk_rx_buffers(sp, ring);
4854 writeq(sp->general_int_mask, &bar0->general_int_mask);
4855 readl(&bar0->general_int_status);
4859 } else if (!reason) {
4860 /* The interrupt was not raised by us */
4870 static void s2io_updt_stats(struct s2io_nic *sp)
4872 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4876 if (is_s2io_card_up(sp)) {
4877 /* Apprx 30us on a 133 MHz bus */
4878 val64 = SET_UPDT_CLICKS(10) |
4879 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4880 writeq(val64, &bar0->stat_cfg);
4883 val64 = readq(&bar0->stat_cfg);
4884 if (!(val64 & s2BIT(0)))
4888 break; /* Updt failed */
4894 * s2io_get_stats - Updates the device statistics structure.
4895 * @dev : pointer to the device structure.
4897 * This function updates the device statistics structure in the s2io_nic
4898 * structure and returns a pointer to the same.
4900 * pointer to the updated net_device_stats structure.
4902 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4904 struct s2io_nic *sp = netdev_priv(dev);
4905 struct mac_info *mac_control = &sp->mac_control;
4906 struct stat_block *stats = mac_control->stats_info;
4909 /* Configure Stats for immediate updt */
4910 s2io_updt_stats(sp);
4912 /* A device reset will cause the on-adapter statistics to be zero'ed.
4913 * This can be done while running by changing the MTU. To prevent the
4914 * system from having the stats zero'ed, the driver keeps a copy of the
4915 * last update to the system (which is also zero'ed on reset). This
4916 * enables the driver to accurately know the delta between the last
4917 * update and the current update.
4919 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4920 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4921 sp->stats.rx_packets += delta;
4922 dev->stats.rx_packets += delta;
4924 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4925 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4926 sp->stats.tx_packets += delta;
4927 dev->stats.tx_packets += delta;
4929 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4930 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4931 sp->stats.rx_bytes += delta;
4932 dev->stats.rx_bytes += delta;
4934 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4935 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4936 sp->stats.tx_bytes += delta;
4937 dev->stats.tx_bytes += delta;
4939 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4940 sp->stats.rx_errors += delta;
4941 dev->stats.rx_errors += delta;
4943 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4944 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4945 sp->stats.tx_errors += delta;
4946 dev->stats.tx_errors += delta;
4948 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4949 sp->stats.rx_dropped += delta;
4950 dev->stats.rx_dropped += delta;
4952 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4953 sp->stats.tx_dropped += delta;
4954 dev->stats.tx_dropped += delta;
4956 /* The adapter MAC interprets pause frames as multicast packets, but
4957 * does not pass them up. This erroneously increases the multicast
4958 * packet count and needs to be deducted when the multicast frame count
4961 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4962 le32_to_cpu(stats->rmac_vld_mcst_frms);
4963 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4964 delta -= sp->stats.multicast;
4965 sp->stats.multicast += delta;
4966 dev->stats.multicast += delta;
4968 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4969 le32_to_cpu(stats->rmac_usized_frms)) +
4970 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4971 sp->stats.rx_length_errors += delta;
4972 dev->stats.rx_length_errors += delta;
4974 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4975 sp->stats.rx_crc_errors += delta;
4976 dev->stats.rx_crc_errors += delta;
4982 * s2io_set_multicast - entry point for multicast address enable/disable.
4983 * @dev : pointer to the device structure
4985 * This function is a driver entry point which gets called by the kernel
4986 * whenever multicast addresses must be enabled/disabled. This also gets
4987 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4988 * determine, if multicast address must be enabled or if promiscuous mode
4989 * is to be disabled etc.
4994 static void s2io_set_multicast(struct net_device *dev)
4997 struct netdev_hw_addr *ha;
4998 struct s2io_nic *sp = netdev_priv(dev);
4999 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5000 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
5002 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
5004 struct config_param *config = &sp->config;
5006 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5007 /* Enable all Multicast addresses */
5008 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5009 &bar0->rmac_addr_data0_mem);
5010 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5011 &bar0->rmac_addr_data1_mem);
5012 val64 = RMAC_ADDR_CMD_MEM_WE |
5013 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5014 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
5015 writeq(val64, &bar0->rmac_addr_cmd_mem);
5016 /* Wait till command completes */
5017 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5018 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5022 sp->all_multi_pos = config->max_mc_addr - 1;
5023 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5024 /* Disable all Multicast addresses */
5025 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5026 &bar0->rmac_addr_data0_mem);
5027 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5028 &bar0->rmac_addr_data1_mem);
5029 val64 = RMAC_ADDR_CMD_MEM_WE |
5030 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5032 writeq(val64, &bar0->rmac_addr_cmd_mem);
5033 /* Wait till command completes */
5034 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5035 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5039 sp->all_multi_pos = 0;
5042 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5043 /* Put the NIC into promiscuous mode */
5044 add = &bar0->mac_cfg;
5045 val64 = readq(&bar0->mac_cfg);
5046 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5048 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5049 writel((u32)val64, add);
5050 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5051 writel((u32) (val64 >> 32), (add + 4));
5053 if (vlan_tag_strip != 1) {
5054 val64 = readq(&bar0->rx_pa_cfg);
5055 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5056 writeq(val64, &bar0->rx_pa_cfg);
5057 sp->vlan_strip_flag = 0;
5060 val64 = readq(&bar0->mac_cfg);
5061 sp->promisc_flg = 1;
5062 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5064 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5065 /* Remove the NIC from promiscuous mode */
5066 add = &bar0->mac_cfg;
5067 val64 = readq(&bar0->mac_cfg);
5068 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5070 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5071 writel((u32)val64, add);
5072 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5073 writel((u32) (val64 >> 32), (add + 4));
5075 if (vlan_tag_strip != 0) {
5076 val64 = readq(&bar0->rx_pa_cfg);
5077 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5078 writeq(val64, &bar0->rx_pa_cfg);
5079 sp->vlan_strip_flag = 1;
5082 val64 = readq(&bar0->mac_cfg);
5083 sp->promisc_flg = 0;
5084 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5087 /* Update individual M_CAST address list */
5088 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5089 if (netdev_mc_count(dev) >
5090 (config->max_mc_addr - config->max_mac_addr)) {
5092 "%s: No more Rx filters can be added - "
5093 "please enable ALL_MULTI instead\n",
5098 prev_cnt = sp->mc_addr_count;
5099 sp->mc_addr_count = netdev_mc_count(dev);
5101 /* Clear out the previous list of Mc in the H/W. */
5102 for (i = 0; i < prev_cnt; i++) {
5103 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5104 &bar0->rmac_addr_data0_mem);
5105 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5106 &bar0->rmac_addr_data1_mem);
5107 val64 = RMAC_ADDR_CMD_MEM_WE |
5108 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5109 RMAC_ADDR_CMD_MEM_OFFSET
5110 (config->mc_start_offset + i);
5111 writeq(val64, &bar0->rmac_addr_cmd_mem);
5113 /* Wait for command completes */
5114 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5115 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5118 "%s: Adding Multicasts failed\n",
5124 /* Create the new Rx filter list and update the same in H/W. */
5126 netdev_for_each_mc_addr(ha, dev) {
5128 for (j = 0; j < ETH_ALEN; j++) {
5129 mac_addr |= ha->addr[j];
5133 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5134 &bar0->rmac_addr_data0_mem);
5135 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5136 &bar0->rmac_addr_data1_mem);
5137 val64 = RMAC_ADDR_CMD_MEM_WE |
5138 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5139 RMAC_ADDR_CMD_MEM_OFFSET
5140 (i + config->mc_start_offset);
5141 writeq(val64, &bar0->rmac_addr_cmd_mem);
5143 /* Wait for command completes */
5144 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5145 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5148 "%s: Adding Multicasts failed\n",
5157 /* read from CAM unicast & multicast addresses and store it in
5158 * def_mac_addr structure
5160 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5164 struct config_param *config = &sp->config;
5166 /* store unicast & multicast mac addresses */
5167 for (offset = 0; offset < config->max_mc_addr; offset++) {
5168 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5169 /* if read fails disable the entry */
5170 if (mac_addr == FAILURE)
5171 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5172 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5176 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5177 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5180 struct config_param *config = &sp->config;
5181 /* restore unicast mac address */
5182 for (offset = 0; offset < config->max_mac_addr; offset++)
5183 do_s2io_prog_unicast(sp->dev,
5184 sp->def_mac_addr[offset].mac_addr);
5186 /* restore multicast mac address */
5187 for (offset = config->mc_start_offset;
5188 offset < config->max_mc_addr; offset++)
5189 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5192 /* add a multicast MAC address to CAM */
5193 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5197 struct config_param *config = &sp->config;
5199 for (i = 0; i < ETH_ALEN; i++) {
5201 mac_addr |= addr[i];
5203 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5206 /* check if the multicast mac already preset in CAM */
5207 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5209 tmp64 = do_s2io_read_unicast_mc(sp, i);
5210 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5213 if (tmp64 == mac_addr)
5216 if (i == config->max_mc_addr) {
5218 "CAM full no space left for multicast MAC\n");
5221 /* Update the internal structure with this new mac address */
5222 do_s2io_copy_mac_addr(sp, i, mac_addr);
5224 return do_s2io_add_mac(sp, mac_addr, i);
5227 /* add MAC address to CAM */
5228 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5231 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5233 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5234 &bar0->rmac_addr_data0_mem);
5236 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5237 RMAC_ADDR_CMD_MEM_OFFSET(off);
5238 writeq(val64, &bar0->rmac_addr_cmd_mem);
5240 /* Wait till command completes */
5241 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5242 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5244 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5249 /* deletes a specified unicast/multicast mac entry from CAM */
5250 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5253 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5254 struct config_param *config = &sp->config;
5257 offset < config->max_mc_addr; offset++) {
5258 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5259 if (tmp64 == addr) {
5260 /* disable the entry by writing 0xffffffffffffULL */
5261 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5263 /* store the new mac list from CAM */
5264 do_s2io_store_unicast_mc(sp);
5268 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5269 (unsigned long long)addr);
5273 /* read mac entries from CAM */
5274 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5276 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5277 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5280 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5281 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5282 writeq(val64, &bar0->rmac_addr_cmd_mem);
5284 /* Wait till command completes */
5285 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5286 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5288 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5291 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5297 * s2io_set_mac_addr driver entry point
5300 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5302 struct sockaddr *addr = p;
5304 if (!is_valid_ether_addr(addr->sa_data))
5307 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5309 /* store the MAC address in CAM */
5310 return do_s2io_prog_unicast(dev, dev->dev_addr);
5313 * do_s2io_prog_unicast - Programs the Xframe mac address
5314 * @dev : pointer to the device structure.
5315 * @addr: a uchar pointer to the new mac address which is to be set.
5316 * Description : This procedure will program the Xframe to receive
5317 * frames with new Mac Address
5318 * Return value: SUCCESS on success and an appropriate (-)ve integer
5319 * as defined in errno.h file on failure.
5322 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5324 struct s2io_nic *sp = netdev_priv(dev);
5325 register u64 mac_addr = 0, perm_addr = 0;
5328 struct config_param *config = &sp->config;
5331 * Set the new MAC address as the new unicast filter and reflect this
5332 * change on the device address registered with the OS. It will be
5335 for (i = 0; i < ETH_ALEN; i++) {
5337 mac_addr |= addr[i];
5339 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5342 /* check if the dev_addr is different than perm_addr */
5343 if (mac_addr == perm_addr)
5346 /* check if the mac already preset in CAM */
5347 for (i = 1; i < config->max_mac_addr; i++) {
5348 tmp64 = do_s2io_read_unicast_mc(sp, i);
5349 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5352 if (tmp64 == mac_addr) {
5354 "MAC addr:0x%llx already present in CAM\n",
5355 (unsigned long long)mac_addr);
5359 if (i == config->max_mac_addr) {
5360 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5363 /* Update the internal structure with this new mac address */
5364 do_s2io_copy_mac_addr(sp, i, mac_addr);
5366 return do_s2io_add_mac(sp, mac_addr, i);
5370 * s2io_ethtool_sset - Sets different link parameters.
5371 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5372 * @info: pointer to the structure with parameters given by ethtool to set
5375 * The function sets different link parameters provided by the user onto
5381 static int s2io_ethtool_sset(struct net_device *dev,
5382 struct ethtool_cmd *info)
5384 struct s2io_nic *sp = netdev_priv(dev);
5385 if ((info->autoneg == AUTONEG_ENABLE) ||
5386 (info->speed != SPEED_10000) ||
5387 (info->duplex != DUPLEX_FULL))
5390 s2io_close(sp->dev);
5398 * s2io_ethtol_gset - Return link specific information.
5399 * @sp : private member of the device structure, pointer to the
5400 * s2io_nic structure.
5401 * @info : pointer to the structure with parameters given by ethtool
5402 * to return link information.
5404 * Returns link specific information like speed, duplex etc.. to ethtool.
5406 * return 0 on success.
5409 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5411 struct s2io_nic *sp = netdev_priv(dev);
5412 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5413 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5414 info->port = PORT_FIBRE;
5416 /* info->transceiver */
5417 info->transceiver = XCVR_EXTERNAL;
5419 if (netif_carrier_ok(sp->dev)) {
5420 info->speed = 10000;
5421 info->duplex = DUPLEX_FULL;
5427 info->autoneg = AUTONEG_DISABLE;
5432 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5433 * @sp : private member of the device structure, which is a pointer to the
5434 * s2io_nic structure.
5435 * @info : pointer to the structure with parameters given by ethtool to
5436 * return driver information.
5438 * Returns driver specefic information like name, version etc.. to ethtool.
5443 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5444 struct ethtool_drvinfo *info)
5446 struct s2io_nic *sp = netdev_priv(dev);
5448 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5449 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5450 strncpy(info->fw_version, "", sizeof(info->fw_version));
5451 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5452 info->regdump_len = XENA_REG_SPACE;
5453 info->eedump_len = XENA_EEPROM_SPACE;
5457 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5458 * @sp: private member of the device structure, which is a pointer to the
5459 * s2io_nic structure.
5460 * @regs : pointer to the structure with parameters given by ethtool for
5461 * dumping the registers.
5462 * @reg_space: The input argumnet into which all the registers are dumped.
5464 * Dumps the entire register space of xFrame NIC into the user given
5470 static void s2io_ethtool_gregs(struct net_device *dev,
5471 struct ethtool_regs *regs, void *space)
5475 u8 *reg_space = (u8 *)space;
5476 struct s2io_nic *sp = netdev_priv(dev);
5478 regs->len = XENA_REG_SPACE;
5479 regs->version = sp->pdev->subsystem_device;
5481 for (i = 0; i < regs->len; i += 8) {
5482 reg = readq(sp->bar0 + i);
5483 memcpy((reg_space + i), ®, 8);
5488 * s2io_phy_id - timer function that alternates adapter LED.
5489 * @data : address of the private member of the device structure, which
5490 * is a pointer to the s2io_nic structure, provided as an u32.
5491 * Description: This is actually the timer function that alternates the
5492 * adapter LED bit of the adapter control bit to set/reset every time on
5493 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5494 * once every second.
5496 static void s2io_phy_id(unsigned long data)
5498 struct s2io_nic *sp = (struct s2io_nic *)data;
5499 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5503 subid = sp->pdev->subsystem_device;
5504 if ((sp->device_type == XFRAME_II_DEVICE) ||
5505 ((subid & 0xFF) >= 0x07)) {
5506 val64 = readq(&bar0->gpio_control);
5507 val64 ^= GPIO_CTRL_GPIO_0;
5508 writeq(val64, &bar0->gpio_control);
5510 val64 = readq(&bar0->adapter_control);
5511 val64 ^= ADAPTER_LED_ON;
5512 writeq(val64, &bar0->adapter_control);
5515 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5519 * s2io_ethtool_idnic - To physically identify the nic on the system.
5520 * @sp : private member of the device structure, which is a pointer to the
5521 * s2io_nic structure.
5522 * @id : pointer to the structure with identification parameters given by
5524 * Description: Used to physically identify the NIC on the system.
5525 * The Link LED will blink for a time specified by the user for
5527 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5528 * identification is possible only if it's link is up.
5530 * int , returns 0 on success
5533 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5535 u64 val64 = 0, last_gpio_ctrl_val;
5536 struct s2io_nic *sp = netdev_priv(dev);
5537 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5540 subid = sp->pdev->subsystem_device;
5541 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5542 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5543 val64 = readq(&bar0->adapter_control);
5544 if (!(val64 & ADAPTER_CNTL_EN)) {
5545 pr_err("Adapter Link down, cannot blink LED\n");
5549 if (sp->id_timer.function == NULL) {
5550 init_timer(&sp->id_timer);
5551 sp->id_timer.function = s2io_phy_id;
5552 sp->id_timer.data = (unsigned long)sp;
5554 mod_timer(&sp->id_timer, jiffies);
5556 msleep_interruptible(data * HZ);
5558 msleep_interruptible(MAX_FLICKER_TIME);
5559 del_timer_sync(&sp->id_timer);
5561 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5562 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5563 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5569 static void s2io_ethtool_gringparam(struct net_device *dev,
5570 struct ethtool_ringparam *ering)
5572 struct s2io_nic *sp = netdev_priv(dev);
5573 int i, tx_desc_count = 0, rx_desc_count = 0;
5575 if (sp->rxd_mode == RXD_MODE_1)
5576 ering->rx_max_pending = MAX_RX_DESC_1;
5577 else if (sp->rxd_mode == RXD_MODE_3B)
5578 ering->rx_max_pending = MAX_RX_DESC_2;
5580 ering->tx_max_pending = MAX_TX_DESC;
5581 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5582 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5584 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5585 ering->tx_pending = tx_desc_count;
5587 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5588 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5590 ering->rx_pending = rx_desc_count;
5592 ering->rx_mini_max_pending = 0;
5593 ering->rx_mini_pending = 0;
5594 if (sp->rxd_mode == RXD_MODE_1)
5595 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5596 else if (sp->rxd_mode == RXD_MODE_3B)
5597 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5598 ering->rx_jumbo_pending = rx_desc_count;
5602 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5603 * @sp : private member of the device structure, which is a pointer to the
5604 * s2io_nic structure.
5605 * @ep : pointer to the structure with pause parameters given by ethtool.
5607 * Returns the Pause frame generation and reception capability of the NIC.
5611 static void s2io_ethtool_getpause_data(struct net_device *dev,
5612 struct ethtool_pauseparam *ep)
5615 struct s2io_nic *sp = netdev_priv(dev);
5616 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5618 val64 = readq(&bar0->rmac_pause_cfg);
5619 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5620 ep->tx_pause = true;
5621 if (val64 & RMAC_PAUSE_RX_ENABLE)
5622 ep->rx_pause = true;
5623 ep->autoneg = false;
5627 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5628 * @sp : private member of the device structure, which is a pointer to the
5629 * s2io_nic structure.
5630 * @ep : pointer to the structure with pause parameters given by ethtool.
5632 * It can be used to set or reset Pause frame generation or reception
5633 * support of the NIC.
5635 * int, returns 0 on Success
5638 static int s2io_ethtool_setpause_data(struct net_device *dev,
5639 struct ethtool_pauseparam *ep)
5642 struct s2io_nic *sp = netdev_priv(dev);
5643 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5645 val64 = readq(&bar0->rmac_pause_cfg);
5647 val64 |= RMAC_PAUSE_GEN_ENABLE;
5649 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5651 val64 |= RMAC_PAUSE_RX_ENABLE;
5653 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5654 writeq(val64, &bar0->rmac_pause_cfg);
5659 * read_eeprom - reads 4 bytes of data from user given offset.
5660 * @sp : private member of the device structure, which is a pointer to the
5661 * s2io_nic structure.
5662 * @off : offset at which the data must be written
5663 * @data : Its an output parameter where the data read at the given
5666 * Will read 4 bytes of data from the user given offset and return the
5668 * NOTE: Will allow to read only part of the EEPROM visible through the
5671 * -1 on failure and 0 on success.
5674 #define S2IO_DEV_ID 5
5675 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5680 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5682 if (sp->device_type == XFRAME_I_DEVICE) {
5683 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5684 I2C_CONTROL_ADDR(off) |
5685 I2C_CONTROL_BYTE_CNT(0x3) |
5687 I2C_CONTROL_CNTL_START;
5688 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5690 while (exit_cnt < 5) {
5691 val64 = readq(&bar0->i2c_control);
5692 if (I2C_CONTROL_CNTL_END(val64)) {
5693 *data = I2C_CONTROL_GET_DATA(val64);
5702 if (sp->device_type == XFRAME_II_DEVICE) {
5703 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5704 SPI_CONTROL_BYTECNT(0x3) |
5705 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5706 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5707 val64 |= SPI_CONTROL_REQ;
5708 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5709 while (exit_cnt < 5) {
5710 val64 = readq(&bar0->spi_control);
5711 if (val64 & SPI_CONTROL_NACK) {
5714 } else if (val64 & SPI_CONTROL_DONE) {
5715 *data = readq(&bar0->spi_data);
5728 * write_eeprom - actually writes the relevant part of the data value.
5729 * @sp : private member of the device structure, which is a pointer to the
5730 * s2io_nic structure.
5731 * @off : offset at which the data must be written
5732 * @data : The data that is to be written
5733 * @cnt : Number of bytes of the data that are actually to be written into
5734 * the Eeprom. (max of 3)
5736 * Actually writes the relevant part of the data value into the Eeprom
5737 * through the I2C bus.
5739 * 0 on success, -1 on failure.
5742 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5744 int exit_cnt = 0, ret = -1;
5746 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5748 if (sp->device_type == XFRAME_I_DEVICE) {
5749 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5750 I2C_CONTROL_ADDR(off) |
5751 I2C_CONTROL_BYTE_CNT(cnt) |
5752 I2C_CONTROL_SET_DATA((u32)data) |
5753 I2C_CONTROL_CNTL_START;
5754 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5756 while (exit_cnt < 5) {
5757 val64 = readq(&bar0->i2c_control);
5758 if (I2C_CONTROL_CNTL_END(val64)) {
5759 if (!(val64 & I2C_CONTROL_NACK))
5768 if (sp->device_type == XFRAME_II_DEVICE) {
5769 int write_cnt = (cnt == 8) ? 0 : cnt;
5770 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5772 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5773 SPI_CONTROL_BYTECNT(write_cnt) |
5774 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5775 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5776 val64 |= SPI_CONTROL_REQ;
5777 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5778 while (exit_cnt < 5) {
5779 val64 = readq(&bar0->spi_control);
5780 if (val64 & SPI_CONTROL_NACK) {
5783 } else if (val64 & SPI_CONTROL_DONE) {
5793 static void s2io_vpd_read(struct s2io_nic *nic)
5797 int i = 0, cnt, len, fail = 0;
5798 int vpd_addr = 0x80;
5799 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5801 if (nic->device_type == XFRAME_II_DEVICE) {
5802 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5805 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5808 strcpy(nic->serial_num, "NOT AVAILABLE");
5810 vpd_data = kmalloc(256, GFP_KERNEL);
5812 swstats->mem_alloc_fail_cnt++;
5815 swstats->mem_allocated += 256;
5817 for (i = 0; i < 256; i += 4) {
5818 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5819 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5820 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5821 for (cnt = 0; cnt < 5; cnt++) {
5823 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5828 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5832 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5833 (u32 *)&vpd_data[i]);
5837 /* read serial number of adapter */
5838 for (cnt = 0; cnt < 252; cnt++) {
5839 if ((vpd_data[cnt] == 'S') &&
5840 (vpd_data[cnt+1] == 'N')) {
5841 len = vpd_data[cnt+2];
5842 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5843 memcpy(nic->serial_num,
5846 memset(nic->serial_num+len,
5848 VPD_STRING_LEN-len);
5855 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5857 memcpy(nic->product_name, &vpd_data[3], len);
5858 nic->product_name[len] = 0;
5861 swstats->mem_freed += 256;
5865 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5866 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5867 * @eeprom : pointer to the user level structure provided by ethtool,
5868 * containing all relevant information.
5869 * @data_buf : user defined value to be written into Eeprom.
5870 * Description: Reads the values stored in the Eeprom at given offset
5871 * for a given length. Stores these values int the input argument data
5872 * buffer 'data_buf' and returns these to the caller (ethtool.)
5877 static int s2io_ethtool_geeprom(struct net_device *dev,
5878 struct ethtool_eeprom *eeprom, u8 * data_buf)
5882 struct s2io_nic *sp = netdev_priv(dev);
5884 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5886 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5887 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5889 for (i = 0; i < eeprom->len; i += 4) {
5890 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5891 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5895 memcpy((data_buf + i), &valid, 4);
5901 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5902 * @sp : private member of the device structure, which is a pointer to the
5903 * s2io_nic structure.
5904 * @eeprom : pointer to the user level structure provided by ethtool,
5905 * containing all relevant information.
5906 * @data_buf ; user defined value to be written into Eeprom.
5908 * Tries to write the user provided value in the Eeprom, at the offset
5909 * given by the user.
5911 * 0 on success, -EFAULT on failure.
5914 static int s2io_ethtool_seeprom(struct net_device *dev,
5915 struct ethtool_eeprom *eeprom,
5918 int len = eeprom->len, cnt = 0;
5919 u64 valid = 0, data;
5920 struct s2io_nic *sp = netdev_priv(dev);
5922 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5924 "ETHTOOL_WRITE_EEPROM Err: "
5925 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5926 (sp->pdev->vendor | (sp->pdev->device << 16)),
5932 data = (u32)data_buf[cnt] & 0x000000FF;
5934 valid = (u32)(data << 24);
5938 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5940 "ETHTOOL_WRITE_EEPROM Err: "
5941 "Cannot write into the specified offset\n");
5952 * s2io_register_test - reads and writes into all clock domains.
5953 * @sp : private member of the device structure, which is a pointer to the
5954 * s2io_nic structure.
5955 * @data : variable that returns the result of each of the test conducted b
5958 * Read and write into all clock domains. The NIC has 3 clock domains,
5959 * see that registers in all the three regions are accessible.
5964 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5966 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5967 u64 val64 = 0, exp_val;
5970 val64 = readq(&bar0->pif_rd_swapper_fb);
5971 if (val64 != 0x123456789abcdefULL) {
5973 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5976 val64 = readq(&bar0->rmac_pause_cfg);
5977 if (val64 != 0xc000ffff00000000ULL) {
5979 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5982 val64 = readq(&bar0->rx_queue_cfg);
5983 if (sp->device_type == XFRAME_II_DEVICE)
5984 exp_val = 0x0404040404040404ULL;
5986 exp_val = 0x0808080808080808ULL;
5987 if (val64 != exp_val) {
5989 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5992 val64 = readq(&bar0->xgxs_efifo_cfg);
5993 if (val64 != 0x000000001923141EULL) {
5995 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5998 val64 = 0x5A5A5A5A5A5A5A5AULL;
5999 writeq(val64, &bar0->xmsi_data);
6000 val64 = readq(&bar0->xmsi_data);
6001 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
6003 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
6006 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6007 writeq(val64, &bar0->xmsi_data);
6008 val64 = readq(&bar0->xmsi_data);
6009 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6011 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
6019 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
6020 * @sp : private member of the device structure, which is a pointer to the
6021 * s2io_nic structure.
6022 * @data:variable that returns the result of each of the test conducted by
6025 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
6031 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
6034 u64 ret_data, org_4F0, org_7F0;
6035 u8 saved_4F0 = 0, saved_7F0 = 0;
6036 struct net_device *dev = sp->dev;
6038 /* Test Write Error at offset 0 */
6039 /* Note that SPI interface allows write access to all areas
6040 * of EEPROM. Hence doing all negative testing only for Xframe I.
6042 if (sp->device_type == XFRAME_I_DEVICE)
6043 if (!write_eeprom(sp, 0, 0, 3))
6046 /* Save current values at offsets 0x4F0 and 0x7F0 */
6047 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6049 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6052 /* Test Write at offset 4f0 */
6053 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6055 if (read_eeprom(sp, 0x4F0, &ret_data))
6058 if (ret_data != 0x012345) {
6059 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6060 "Data written %llx Data read %llx\n",
6061 dev->name, (unsigned long long)0x12345,
6062 (unsigned long long)ret_data);
6066 /* Reset the EEPROM data go FFFF */
6067 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6069 /* Test Write Request Error at offset 0x7c */
6070 if (sp->device_type == XFRAME_I_DEVICE)
6071 if (!write_eeprom(sp, 0x07C, 0, 3))
6074 /* Test Write Request at offset 0x7f0 */
6075 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6077 if (read_eeprom(sp, 0x7F0, &ret_data))
6080 if (ret_data != 0x012345) {
6081 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6082 "Data written %llx Data read %llx\n",
6083 dev->name, (unsigned long long)0x12345,
6084 (unsigned long long)ret_data);
6088 /* Reset the EEPROM data go FFFF */
6089 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6091 if (sp->device_type == XFRAME_I_DEVICE) {
6092 /* Test Write Error at offset 0x80 */
6093 if (!write_eeprom(sp, 0x080, 0, 3))
6096 /* Test Write Error at offset 0xfc */
6097 if (!write_eeprom(sp, 0x0FC, 0, 3))
6100 /* Test Write Error at offset 0x100 */
6101 if (!write_eeprom(sp, 0x100, 0, 3))
6104 /* Test Write Error at offset 4ec */
6105 if (!write_eeprom(sp, 0x4EC, 0, 3))
6109 /* Restore values at offsets 0x4F0 and 0x7F0 */
6111 write_eeprom(sp, 0x4F0, org_4F0, 3);
6113 write_eeprom(sp, 0x7F0, org_7F0, 3);
6120 * s2io_bist_test - invokes the MemBist test of the card .
6121 * @sp : private member of the device structure, which is a pointer to the
6122 * s2io_nic structure.
6123 * @data:variable that returns the result of each of the test conducted by
6126 * This invokes the MemBist test of the card. We give around
6127 * 2 secs time for the Test to complete. If it's still not complete
6128 * within this peiod, we consider that the test failed.
6130 * 0 on success and -1 on failure.
6133 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6136 int cnt = 0, ret = -1;
6138 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6139 bist |= PCI_BIST_START;
6140 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6143 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6144 if (!(bist & PCI_BIST_START)) {
6145 *data = (bist & PCI_BIST_CODE_MASK);
6157 * s2io-link_test - verifies the link state of the nic
6158 * @sp ; private member of the device structure, which is a pointer to the
6159 * s2io_nic structure.
6160 * @data: variable that returns the result of each of the test conducted by
6163 * The function verifies the link state of the NIC and updates the input
6164 * argument 'data' appropriately.
6169 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6171 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6174 val64 = readq(&bar0->adapter_status);
6175 if (!(LINK_IS_UP(val64)))
6184 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6185 * @sp - private member of the device structure, which is a pointer to the
6186 * s2io_nic structure.
6187 * @data - variable that returns the result of each of the test
6188 * conducted by the driver.
6190 * This is one of the offline test that tests the read and write
6191 * access to the RldRam chip on the NIC.
6196 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6198 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6200 int cnt, iteration = 0, test_fail = 0;
6202 val64 = readq(&bar0->adapter_control);
6203 val64 &= ~ADAPTER_ECC_EN;
6204 writeq(val64, &bar0->adapter_control);
6206 val64 = readq(&bar0->mc_rldram_test_ctrl);
6207 val64 |= MC_RLDRAM_TEST_MODE;
6208 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6210 val64 = readq(&bar0->mc_rldram_mrs);
6211 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6212 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6214 val64 |= MC_RLDRAM_MRS_ENABLE;
6215 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6217 while (iteration < 2) {
6218 val64 = 0x55555555aaaa0000ULL;
6220 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6221 writeq(val64, &bar0->mc_rldram_test_d0);
6223 val64 = 0xaaaa5a5555550000ULL;
6225 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6226 writeq(val64, &bar0->mc_rldram_test_d1);
6228 val64 = 0x55aaaaaaaa5a0000ULL;
6230 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6231 writeq(val64, &bar0->mc_rldram_test_d2);
6233 val64 = (u64) (0x0000003ffffe0100ULL);
6234 writeq(val64, &bar0->mc_rldram_test_add);
6236 val64 = MC_RLDRAM_TEST_MODE |
6237 MC_RLDRAM_TEST_WRITE |
6239 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6241 for (cnt = 0; cnt < 5; cnt++) {
6242 val64 = readq(&bar0->mc_rldram_test_ctrl);
6243 if (val64 & MC_RLDRAM_TEST_DONE)
6251 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6252 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6254 for (cnt = 0; cnt < 5; cnt++) {
6255 val64 = readq(&bar0->mc_rldram_test_ctrl);
6256 if (val64 & MC_RLDRAM_TEST_DONE)
6264 val64 = readq(&bar0->mc_rldram_test_ctrl);
6265 if (!(val64 & MC_RLDRAM_TEST_PASS))
6273 /* Bring the adapter out of test mode */
6274 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6280 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6281 * @sp : private member of the device structure, which is a pointer to the
6282 * s2io_nic structure.
6283 * @ethtest : pointer to a ethtool command specific structure that will be
6284 * returned to the user.
6285 * @data : variable that returns the result of each of the test
6286 * conducted by the driver.
6288 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6289 * the health of the card.
6294 static void s2io_ethtool_test(struct net_device *dev,
6295 struct ethtool_test *ethtest,
6298 struct s2io_nic *sp = netdev_priv(dev);
6299 int orig_state = netif_running(sp->dev);
6301 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6302 /* Offline Tests. */
6304 s2io_close(sp->dev);
6306 if (s2io_register_test(sp, &data[0]))
6307 ethtest->flags |= ETH_TEST_FL_FAILED;
6311 if (s2io_rldram_test(sp, &data[3]))
6312 ethtest->flags |= ETH_TEST_FL_FAILED;
6316 if (s2io_eeprom_test(sp, &data[1]))
6317 ethtest->flags |= ETH_TEST_FL_FAILED;
6319 if (s2io_bist_test(sp, &data[4]))
6320 ethtest->flags |= ETH_TEST_FL_FAILED;
6329 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6338 if (s2io_link_test(sp, &data[2]))
6339 ethtest->flags |= ETH_TEST_FL_FAILED;
6348 static void s2io_get_ethtool_stats(struct net_device *dev,
6349 struct ethtool_stats *estats,
6353 struct s2io_nic *sp = netdev_priv(dev);
6354 struct stat_block *stats = sp->mac_control.stats_info;
6355 struct swStat *swstats = &stats->sw_stat;
6356 struct xpakStat *xstats = &stats->xpak_stat;
6358 s2io_updt_stats(sp);
6360 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6361 le32_to_cpu(stats->tmac_frms);
6363 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6364 le32_to_cpu(stats->tmac_data_octets);
6365 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6367 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6368 le32_to_cpu(stats->tmac_mcst_frms);
6370 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6371 le32_to_cpu(stats->tmac_bcst_frms);
6372 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6374 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6375 le32_to_cpu(stats->tmac_ttl_octets);
6377 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6378 le32_to_cpu(stats->tmac_ucst_frms);
6380 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6381 le32_to_cpu(stats->tmac_nucst_frms);
6383 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6384 le32_to_cpu(stats->tmac_any_err_frms);
6385 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6386 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6388 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6389 le32_to_cpu(stats->tmac_vld_ip);
6391 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6392 le32_to_cpu(stats->tmac_drop_ip);
6394 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6395 le32_to_cpu(stats->tmac_icmp);
6397 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6398 le32_to_cpu(stats->tmac_rst_tcp);
6399 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6400 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6401 le32_to_cpu(stats->tmac_udp);
6403 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6404 le32_to_cpu(stats->rmac_vld_frms);
6406 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6407 le32_to_cpu(stats->rmac_data_octets);
6408 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6409 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6411 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6412 le32_to_cpu(stats->rmac_vld_mcst_frms);
6414 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6415 le32_to_cpu(stats->rmac_vld_bcst_frms);
6416 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6417 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6419 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6420 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6422 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6423 le32_to_cpu(stats->rmac_ttl_octets);
6425 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6426 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6428 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6429 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6431 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6432 le32_to_cpu(stats->rmac_discarded_frms);
6434 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6435 << 32 | le32_to_cpu(stats->rmac_drop_events);
6436 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6437 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6439 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6440 le32_to_cpu(stats->rmac_usized_frms);
6442 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6443 le32_to_cpu(stats->rmac_osized_frms);
6445 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6446 le32_to_cpu(stats->rmac_frag_frms);
6448 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6449 le32_to_cpu(stats->rmac_jabber_frms);
6450 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6451 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6452 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6453 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6454 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6455 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6457 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6458 le32_to_cpu(stats->rmac_ip);
6459 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6460 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6462 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6463 le32_to_cpu(stats->rmac_drop_ip);
6465 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6466 le32_to_cpu(stats->rmac_icmp);
6467 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6469 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6470 le32_to_cpu(stats->rmac_udp);
6472 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6473 le32_to_cpu(stats->rmac_err_drp_udp);
6474 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6475 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6476 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6477 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6478 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6479 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6480 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6481 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6482 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6483 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6484 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6485 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6486 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6487 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6488 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6489 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6490 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6492 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6493 le32_to_cpu(stats->rmac_pause_cnt);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6495 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6497 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6498 le32_to_cpu(stats->rmac_accepted_ip);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6500 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6511 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6512 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6513 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6514 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6515 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6516 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6517 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6519 /* Enhanced statistics exist only for Hercules */
6520 if (sp->device_type == XFRAME_II_DEVICE) {
6522 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6524 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6526 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6527 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6528 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6529 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6530 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6531 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6532 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6533 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6534 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6535 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6536 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6537 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6538 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6539 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6543 tmp_stats[i++] = swstats->single_ecc_errs;
6544 tmp_stats[i++] = swstats->double_ecc_errs;
6545 tmp_stats[i++] = swstats->parity_err_cnt;
6546 tmp_stats[i++] = swstats->serious_err_cnt;
6547 tmp_stats[i++] = swstats->soft_reset_cnt;
6548 tmp_stats[i++] = swstats->fifo_full_cnt;
6549 for (k = 0; k < MAX_RX_RINGS; k++)
6550 tmp_stats[i++] = swstats->ring_full_cnt[k];
6551 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6552 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6553 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6554 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6555 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6556 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6557 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6558 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6559 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6560 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6561 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6562 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6563 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6564 tmp_stats[i++] = swstats->sending_both;
6565 tmp_stats[i++] = swstats->outof_sequence_pkts;
6566 tmp_stats[i++] = swstats->flush_max_pkts;
6567 if (swstats->num_aggregations) {
6568 u64 tmp = swstats->sum_avg_pkts_aggregated;
6571 * Since 64-bit divide does not work on all platforms,
6572 * do repeated subtraction.
6574 while (tmp >= swstats->num_aggregations) {
6575 tmp -= swstats->num_aggregations;
6578 tmp_stats[i++] = count;
6581 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6582 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6583 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6584 tmp_stats[i++] = swstats->mem_allocated;
6585 tmp_stats[i++] = swstats->mem_freed;
6586 tmp_stats[i++] = swstats->link_up_cnt;
6587 tmp_stats[i++] = swstats->link_down_cnt;
6588 tmp_stats[i++] = swstats->link_up_time;
6589 tmp_stats[i++] = swstats->link_down_time;
6591 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6592 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6593 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6594 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6595 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6597 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6598 tmp_stats[i++] = swstats->rx_abort_cnt;
6599 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6600 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6601 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6602 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6603 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6604 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6605 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6606 tmp_stats[i++] = swstats->tda_err_cnt;
6607 tmp_stats[i++] = swstats->pfc_err_cnt;
6608 tmp_stats[i++] = swstats->pcc_err_cnt;
6609 tmp_stats[i++] = swstats->tti_err_cnt;
6610 tmp_stats[i++] = swstats->tpa_err_cnt;
6611 tmp_stats[i++] = swstats->sm_err_cnt;
6612 tmp_stats[i++] = swstats->lso_err_cnt;
6613 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6614 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6615 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6616 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6617 tmp_stats[i++] = swstats->rc_err_cnt;
6618 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6619 tmp_stats[i++] = swstats->rpa_err_cnt;
6620 tmp_stats[i++] = swstats->rda_err_cnt;
6621 tmp_stats[i++] = swstats->rti_err_cnt;
6622 tmp_stats[i++] = swstats->mc_err_cnt;
6625 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6627 return XENA_REG_SPACE;
6631 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6633 struct s2io_nic *sp = netdev_priv(dev);
6638 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6640 struct s2io_nic *sp = netdev_priv(dev);
6650 static int s2io_get_eeprom_len(struct net_device *dev)
6652 return XENA_EEPROM_SPACE;
6655 static int s2io_get_sset_count(struct net_device *dev, int sset)
6657 struct s2io_nic *sp = netdev_priv(dev);
6661 return S2IO_TEST_LEN;
6663 switch (sp->device_type) {
6664 case XFRAME_I_DEVICE:
6665 return XFRAME_I_STAT_LEN;
6666 case XFRAME_II_DEVICE:
6667 return XFRAME_II_STAT_LEN;
6676 static void s2io_ethtool_get_strings(struct net_device *dev,
6677 u32 stringset, u8 *data)
6680 struct s2io_nic *sp = netdev_priv(dev);
6682 switch (stringset) {
6684 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6687 stat_size = sizeof(ethtool_xena_stats_keys);
6688 memcpy(data, ðtool_xena_stats_keys, stat_size);
6689 if (sp->device_type == XFRAME_II_DEVICE) {
6690 memcpy(data + stat_size,
6691 ðtool_enhanced_stats_keys,
6692 sizeof(ethtool_enhanced_stats_keys));
6693 stat_size += sizeof(ethtool_enhanced_stats_keys);
6696 memcpy(data + stat_size, ðtool_driver_stats_keys,
6697 sizeof(ethtool_driver_stats_keys));
6701 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6704 dev->features |= NETIF_F_IP_CSUM;
6706 dev->features &= ~NETIF_F_IP_CSUM;
6711 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6713 return (dev->features & NETIF_F_TSO) != 0;
6716 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6719 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6721 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6726 static int s2io_ethtool_set_flags(struct net_device *dev, u32 data)
6728 struct s2io_nic *sp = netdev_priv(dev);
6732 if (data & ~ETH_FLAG_LRO)
6735 if (data & ETH_FLAG_LRO) {
6737 if (!(dev->features & NETIF_F_LRO)) {
6738 dev->features |= NETIF_F_LRO;
6743 } else if (dev->features & NETIF_F_LRO) {
6744 dev->features &= ~NETIF_F_LRO;
6748 if (changed && netif_running(dev)) {
6749 s2io_stop_all_tx_queue(sp);
6751 sp->lro = !!(dev->features & NETIF_F_LRO);
6752 rc = s2io_card_up(sp);
6756 s2io_start_all_tx_queue(sp);
6762 static const struct ethtool_ops netdev_ethtool_ops = {
6763 .get_settings = s2io_ethtool_gset,
6764 .set_settings = s2io_ethtool_sset,
6765 .get_drvinfo = s2io_ethtool_gdrvinfo,
6766 .get_regs_len = s2io_ethtool_get_regs_len,
6767 .get_regs = s2io_ethtool_gregs,
6768 .get_link = ethtool_op_get_link,
6769 .get_eeprom_len = s2io_get_eeprom_len,
6770 .get_eeprom = s2io_ethtool_geeprom,
6771 .set_eeprom = s2io_ethtool_seeprom,
6772 .get_ringparam = s2io_ethtool_gringparam,
6773 .get_pauseparam = s2io_ethtool_getpause_data,
6774 .set_pauseparam = s2io_ethtool_setpause_data,
6775 .get_rx_csum = s2io_ethtool_get_rx_csum,
6776 .set_rx_csum = s2io_ethtool_set_rx_csum,
6777 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6778 .set_flags = s2io_ethtool_set_flags,
6779 .get_flags = ethtool_op_get_flags,
6780 .set_sg = ethtool_op_set_sg,
6781 .get_tso = s2io_ethtool_op_get_tso,
6782 .set_tso = s2io_ethtool_op_set_tso,
6783 .set_ufo = ethtool_op_set_ufo,
6784 .self_test = s2io_ethtool_test,
6785 .get_strings = s2io_ethtool_get_strings,
6786 .phys_id = s2io_ethtool_idnic,
6787 .get_ethtool_stats = s2io_get_ethtool_stats,
6788 .get_sset_count = s2io_get_sset_count,
6792 * s2io_ioctl - Entry point for the Ioctl
6793 * @dev : Device pointer.
6794 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6795 * a proprietary structure used to pass information to the driver.
6796 * @cmd : This is used to distinguish between the different commands that
6797 * can be passed to the IOCTL functions.
6799 * Currently there are no special functionality supported in IOCTL, hence
6800 * function always return EOPNOTSUPPORTED
6803 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6809 * s2io_change_mtu - entry point to change MTU size for the device.
6810 * @dev : device pointer.
6811 * @new_mtu : the new MTU size for the device.
6812 * Description: A driver entry point to change MTU size for the device.
6813 * Before changing the MTU the device must be stopped.
6815 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6819 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6821 struct s2io_nic *sp = netdev_priv(dev);
6824 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6825 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6830 if (netif_running(dev)) {
6831 s2io_stop_all_tx_queue(sp);
6833 ret = s2io_card_up(sp);
6835 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6839 s2io_wake_all_tx_queue(sp);
6840 } else { /* Device is down */
6841 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6842 u64 val64 = new_mtu;
6844 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6851 * s2io_set_link - Set the LInk status
6852 * @data: long pointer to device private structue
6853 * Description: Sets the link status for the adapter
6856 static void s2io_set_link(struct work_struct *work)
6858 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6860 struct net_device *dev = nic->dev;
6861 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6867 if (!netif_running(dev))
6870 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6871 /* The card is being reset, no point doing anything */
6875 subid = nic->pdev->subsystem_device;
6876 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6878 * Allow a small delay for the NICs self initiated
6879 * cleanup to complete.
6884 val64 = readq(&bar0->adapter_status);
6885 if (LINK_IS_UP(val64)) {
6886 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6887 if (verify_xena_quiescence(nic)) {
6888 val64 = readq(&bar0->adapter_control);
6889 val64 |= ADAPTER_CNTL_EN;
6890 writeq(val64, &bar0->adapter_control);
6891 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6892 nic->device_type, subid)) {
6893 val64 = readq(&bar0->gpio_control);
6894 val64 |= GPIO_CTRL_GPIO_0;
6895 writeq(val64, &bar0->gpio_control);
6896 val64 = readq(&bar0->gpio_control);
6898 val64 |= ADAPTER_LED_ON;
6899 writeq(val64, &bar0->adapter_control);
6901 nic->device_enabled_once = true;
6904 "%s: Error: device is not Quiescent\n",
6906 s2io_stop_all_tx_queue(nic);
6909 val64 = readq(&bar0->adapter_control);
6910 val64 |= ADAPTER_LED_ON;
6911 writeq(val64, &bar0->adapter_control);
6912 s2io_link(nic, LINK_UP);
6914 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6916 val64 = readq(&bar0->gpio_control);
6917 val64 &= ~GPIO_CTRL_GPIO_0;
6918 writeq(val64, &bar0->gpio_control);
6919 val64 = readq(&bar0->gpio_control);
6922 val64 = readq(&bar0->adapter_control);
6923 val64 = val64 & (~ADAPTER_LED_ON);
6924 writeq(val64, &bar0->adapter_control);
6925 s2io_link(nic, LINK_DOWN);
6927 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6933 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6935 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6936 u64 *temp2, int size)
6938 struct net_device *dev = sp->dev;
6939 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6941 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6942 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6945 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6947 * As Rx frame are not going to be processed,
6948 * using same mapped address for the Rxd
6951 rxdp1->Buffer0_ptr = *temp0;
6953 *skb = dev_alloc_skb(size);
6956 "%s: Out of memory to allocate %s\n",
6957 dev->name, "1 buf mode SKBs");
6958 stats->mem_alloc_fail_cnt++;
6961 stats->mem_allocated += (*skb)->truesize;
6962 /* storing the mapped addr in a temp variable
6963 * such it will be used for next rxd whose
6964 * Host Control is NULL
6966 rxdp1->Buffer0_ptr = *temp0 =
6967 pci_map_single(sp->pdev, (*skb)->data,
6968 size - NET_IP_ALIGN,
6969 PCI_DMA_FROMDEVICE);
6970 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6971 goto memalloc_failed;
6972 rxdp->Host_Control = (unsigned long) (*skb);
6974 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6975 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6976 /* Two buffer Mode */
6978 rxdp3->Buffer2_ptr = *temp2;
6979 rxdp3->Buffer0_ptr = *temp0;
6980 rxdp3->Buffer1_ptr = *temp1;
6982 *skb = dev_alloc_skb(size);
6985 "%s: Out of memory to allocate %s\n",
6988 stats->mem_alloc_fail_cnt++;
6991 stats->mem_allocated += (*skb)->truesize;
6992 rxdp3->Buffer2_ptr = *temp2 =
6993 pci_map_single(sp->pdev, (*skb)->data,
6995 PCI_DMA_FROMDEVICE);
6996 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6997 goto memalloc_failed;
6998 rxdp3->Buffer0_ptr = *temp0 =
6999 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
7000 PCI_DMA_FROMDEVICE);
7001 if (pci_dma_mapping_error(sp->pdev,
7002 rxdp3->Buffer0_ptr)) {
7003 pci_unmap_single(sp->pdev,
7004 (dma_addr_t)rxdp3->Buffer2_ptr,
7006 PCI_DMA_FROMDEVICE);
7007 goto memalloc_failed;
7009 rxdp->Host_Control = (unsigned long) (*skb);
7011 /* Buffer-1 will be dummy buffer not used */
7012 rxdp3->Buffer1_ptr = *temp1 =
7013 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
7014 PCI_DMA_FROMDEVICE);
7015 if (pci_dma_mapping_error(sp->pdev,
7016 rxdp3->Buffer1_ptr)) {
7017 pci_unmap_single(sp->pdev,
7018 (dma_addr_t)rxdp3->Buffer0_ptr,
7019 BUF0_LEN, PCI_DMA_FROMDEVICE);
7020 pci_unmap_single(sp->pdev,
7021 (dma_addr_t)rxdp3->Buffer2_ptr,
7023 PCI_DMA_FROMDEVICE);
7024 goto memalloc_failed;
7031 stats->pci_map_fail_cnt++;
7032 stats->mem_freed += (*skb)->truesize;
7033 dev_kfree_skb(*skb);
7037 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7040 struct net_device *dev = sp->dev;
7041 if (sp->rxd_mode == RXD_MODE_1) {
7042 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
7043 } else if (sp->rxd_mode == RXD_MODE_3B) {
7044 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7045 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
7046 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
7050 static int rxd_owner_bit_reset(struct s2io_nic *sp)
7052 int i, j, k, blk_cnt = 0, size;
7053 struct config_param *config = &sp->config;
7054 struct mac_info *mac_control = &sp->mac_control;
7055 struct net_device *dev = sp->dev;
7056 struct RxD_t *rxdp = NULL;
7057 struct sk_buff *skb = NULL;
7058 struct buffAdd *ba = NULL;
7059 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7061 /* Calculate the size based on ring mode */
7062 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7063 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7064 if (sp->rxd_mode == RXD_MODE_1)
7065 size += NET_IP_ALIGN;
7066 else if (sp->rxd_mode == RXD_MODE_3B)
7067 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
7069 for (i = 0; i < config->rx_ring_num; i++) {
7070 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7071 struct ring_info *ring = &mac_control->rings[i];
7073 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
7075 for (j = 0; j < blk_cnt; j++) {
7076 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7077 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7078 if (sp->rxd_mode == RXD_MODE_3B)
7079 ba = &ring->ba[j][k];
7080 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7088 set_rxd_buffer_size(sp, rxdp, size);
7090 /* flip the Ownership bit to Hardware */
7091 rxdp->Control_1 |= RXD_OWN_XENA;
7099 static int s2io_add_isr(struct s2io_nic *sp)
7102 struct net_device *dev = sp->dev;
7105 if (sp->config.intr_type == MSI_X)
7106 ret = s2io_enable_msi_x(sp);
7108 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7109 sp->config.intr_type = INTA;
7113 * Store the values of the MSIX table in
7114 * the struct s2io_nic structure
7116 store_xmsi_data(sp);
7118 /* After proper initialization of H/W, register ISR */
7119 if (sp->config.intr_type == MSI_X) {
7120 int i, msix_rx_cnt = 0;
7122 for (i = 0; i < sp->num_entries; i++) {
7123 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7124 if (sp->s2io_entries[i].type ==
7126 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7128 err = request_irq(sp->entries[i].vector,
7129 s2io_msix_ring_handle,
7132 sp->s2io_entries[i].arg);
7133 } else if (sp->s2io_entries[i].type ==
7135 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7137 err = request_irq(sp->entries[i].vector,
7138 s2io_msix_fifo_handle,
7141 sp->s2io_entries[i].arg);
7144 /* if either data or addr is zero print it. */
7145 if (!(sp->msix_info[i].addr &&
7146 sp->msix_info[i].data)) {
7148 "%s @Addr:0x%llx Data:0x%llx\n",
7150 (unsigned long long)
7151 sp->msix_info[i].addr,
7152 (unsigned long long)
7153 ntohl(sp->msix_info[i].data));
7157 remove_msix_isr(sp);
7160 "%s:MSI-X-%d registration "
7161 "failed\n", dev->name, i);
7164 "%s: Defaulting to INTA\n",
7166 sp->config.intr_type = INTA;
7169 sp->s2io_entries[i].in_use =
7170 MSIX_REGISTERED_SUCCESS;
7174 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7176 "MSI-X-TX entries enabled through alarm vector\n");
7179 if (sp->config.intr_type == INTA) {
7180 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7183 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7191 static void s2io_rem_isr(struct s2io_nic *sp)
7193 if (sp->config.intr_type == MSI_X)
7194 remove_msix_isr(sp);
7196 remove_inta_isr(sp);
7199 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7203 register u64 val64 = 0;
7204 struct config_param *config;
7205 config = &sp->config;
7207 if (!is_s2io_card_up(sp))
7210 del_timer_sync(&sp->alarm_timer);
7211 /* If s2io_set_link task is executing, wait till it completes. */
7212 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7214 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7217 if (sp->config.napi) {
7219 if (config->intr_type == MSI_X) {
7220 for (; off < sp->config.rx_ring_num; off++)
7221 napi_disable(&sp->mac_control.rings[off].napi);
7224 napi_disable(&sp->napi);
7227 /* disable Tx and Rx traffic on the NIC */
7233 /* stop the tx queue, indicate link down */
7234 s2io_link(sp, LINK_DOWN);
7236 /* Check if the device is Quiescent and then Reset the NIC */
7238 /* As per the HW requirement we need to replenish the
7239 * receive buffer to avoid the ring bump. Since there is
7240 * no intention of processing the Rx frame at this pointwe are
7241 * just settting the ownership bit of rxd in Each Rx
7242 * ring to HW and set the appropriate buffer size
7243 * based on the ring mode
7245 rxd_owner_bit_reset(sp);
7247 val64 = readq(&bar0->adapter_status);
7248 if (verify_xena_quiescence(sp)) {
7249 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7256 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7257 "adapter status reads 0x%llx\n",
7258 (unsigned long long)val64);
7265 /* Free all Tx buffers */
7266 free_tx_buffers(sp);
7268 /* Free all Rx buffers */
7269 free_rx_buffers(sp);
7271 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7274 static void s2io_card_down(struct s2io_nic *sp)
7276 do_s2io_card_down(sp, 1);
7279 static int s2io_card_up(struct s2io_nic *sp)
7282 struct config_param *config;
7283 struct mac_info *mac_control;
7284 struct net_device *dev = (struct net_device *)sp->dev;
7287 /* Initialize the H/W I/O registers */
7290 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7298 * Initializing the Rx buffers. For now we are considering only 1
7299 * Rx ring and initializing buffers into 30 Rx blocks
7301 config = &sp->config;
7302 mac_control = &sp->mac_control;
7304 for (i = 0; i < config->rx_ring_num; i++) {
7305 struct ring_info *ring = &mac_control->rings[i];
7307 ring->mtu = dev->mtu;
7308 ring->lro = sp->lro;
7309 ret = fill_rx_buffers(sp, ring, 1);
7311 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7314 free_rx_buffers(sp);
7317 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7318 ring->rx_bufs_left);
7321 /* Initialise napi */
7323 if (config->intr_type == MSI_X) {
7324 for (i = 0; i < sp->config.rx_ring_num; i++)
7325 napi_enable(&sp->mac_control.rings[i].napi);
7327 napi_enable(&sp->napi);
7331 /* Maintain the state prior to the open */
7332 if (sp->promisc_flg)
7333 sp->promisc_flg = 0;
7334 if (sp->m_cast_flg) {
7336 sp->all_multi_pos = 0;
7339 /* Setting its receive mode */
7340 s2io_set_multicast(dev);
7343 /* Initialize max aggregatable pkts per session based on MTU */
7344 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7345 /* Check if we can use (if specified) user provided value */
7346 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7347 sp->lro_max_aggr_per_sess = lro_max_pkts;
7350 /* Enable Rx Traffic and interrupts on the NIC */
7351 if (start_nic(sp)) {
7352 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7354 free_rx_buffers(sp);
7358 /* Add interrupt service routine */
7359 if (s2io_add_isr(sp) != 0) {
7360 if (sp->config.intr_type == MSI_X)
7363 free_rx_buffers(sp);
7367 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7369 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7371 /* Enable select interrupts */
7372 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7373 if (sp->config.intr_type != INTA) {
7374 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7375 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7377 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7378 interruptible |= TX_PIC_INTR;
7379 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7386 * s2io_restart_nic - Resets the NIC.
7387 * @data : long pointer to the device private structure
7389 * This function is scheduled to be run by the s2io_tx_watchdog
7390 * function after 0.5 secs to reset the NIC. The idea is to reduce
7391 * the run time of the watch dog routine which is run holding a
7395 static void s2io_restart_nic(struct work_struct *work)
7397 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7398 struct net_device *dev = sp->dev;
7402 if (!netif_running(dev))
7406 if (s2io_card_up(sp)) {
7407 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7409 s2io_wake_all_tx_queue(sp);
7410 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7416 * s2io_tx_watchdog - Watchdog for transmit side.
7417 * @dev : Pointer to net device structure
7419 * This function is triggered if the Tx Queue is stopped
7420 * for a pre-defined amount of time when the Interface is still up.
7421 * If the Interface is jammed in such a situation, the hardware is
7422 * reset (by s2io_close) and restarted again (by s2io_open) to
7423 * overcome any problem that might have been caused in the hardware.
7428 static void s2io_tx_watchdog(struct net_device *dev)
7430 struct s2io_nic *sp = netdev_priv(dev);
7431 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7433 if (netif_carrier_ok(dev)) {
7434 swstats->watchdog_timer_cnt++;
7435 schedule_work(&sp->rst_timer_task);
7436 swstats->soft_reset_cnt++;
7441 * rx_osm_handler - To perform some OS related operations on SKB.
7442 * @sp: private member of the device structure,pointer to s2io_nic structure.
7443 * @skb : the socket buffer pointer.
7444 * @len : length of the packet
7445 * @cksum : FCS checksum of the frame.
7446 * @ring_no : the ring from which this RxD was extracted.
7448 * This function is called by the Rx interrupt serivce routine to perform
7449 * some OS related operations on the SKB before passing it to the upper
7450 * layers. It mainly checks if the checksum is OK, if so adds it to the
7451 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7452 * to the upper layer. If the checksum is wrong, it increments the Rx
7453 * packet error count, frees the SKB and returns error.
7455 * SUCCESS on success and -1 on failure.
7457 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7459 struct s2io_nic *sp = ring_data->nic;
7460 struct net_device *dev = (struct net_device *)ring_data->dev;
7461 struct sk_buff *skb = (struct sk_buff *)
7462 ((unsigned long)rxdp->Host_Control);
7463 int ring_no = ring_data->ring_no;
7464 u16 l3_csum, l4_csum;
7465 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7466 struct lro *uninitialized_var(lro);
7468 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7473 /* Check for parity error */
7475 swstats->parity_err_cnt++;
7477 err_mask = err >> 48;
7480 swstats->rx_parity_err_cnt++;
7484 swstats->rx_abort_cnt++;
7488 swstats->rx_parity_abort_cnt++;
7492 swstats->rx_rda_fail_cnt++;
7496 swstats->rx_unkn_prot_cnt++;
7500 swstats->rx_fcs_err_cnt++;
7504 swstats->rx_buf_size_err_cnt++;
7508 swstats->rx_rxd_corrupt_cnt++;
7512 swstats->rx_unkn_err_cnt++;
7516 * Drop the packet if bad transfer code. Exception being
7517 * 0x5, which could be due to unsupported IPv6 extension header.
7518 * In this case, we let stack handle the packet.
7519 * Note that in this case, since checksum will be incorrect,
7520 * stack will validate the same.
7522 if (err_mask != 0x5) {
7523 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7524 dev->name, err_mask);
7525 dev->stats.rx_crc_errors++;
7529 ring_data->rx_bufs_left -= 1;
7530 rxdp->Host_Control = 0;
7535 rxdp->Host_Control = 0;
7536 if (sp->rxd_mode == RXD_MODE_1) {
7537 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7540 } else if (sp->rxd_mode == RXD_MODE_3B) {
7541 int get_block = ring_data->rx_curr_get_info.block_index;
7542 int get_off = ring_data->rx_curr_get_info.offset;
7543 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7544 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7545 unsigned char *buff = skb_push(skb, buf0_len);
7547 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7548 memcpy(buff, ba->ba_0, buf0_len);
7549 skb_put(skb, buf2_len);
7552 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7553 ((!ring_data->lro) ||
7554 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7556 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7557 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7558 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7560 * NIC verifies if the Checksum of the received
7561 * frame is Ok or not and accordingly returns
7562 * a flag in the RxD.
7564 skb->ip_summed = CHECKSUM_UNNECESSARY;
7565 if (ring_data->lro) {
7570 ret = s2io_club_tcp_session(ring_data,
7575 case 3: /* Begin anew */
7578 case 1: /* Aggregate */
7579 lro_append_pkt(sp, lro, skb, tcp_len);
7581 case 4: /* Flush session */
7582 lro_append_pkt(sp, lro, skb, tcp_len);
7583 queue_rx_frame(lro->parent,
7585 clear_lro_session(lro);
7586 swstats->flush_max_pkts++;
7588 case 2: /* Flush both */
7589 lro->parent->data_len = lro->frags_len;
7590 swstats->sending_both++;
7591 queue_rx_frame(lro->parent,
7593 clear_lro_session(lro);
7595 case 0: /* sessions exceeded */
7596 case -1: /* non-TCP or not L2 aggregatable */
7598 * First pkt in session not
7599 * L3/L4 aggregatable
7604 "%s: Samadhana!!\n",
7611 * Packet with erroneous checksum, let the
7612 * upper layers deal with it.
7614 skb->ip_summed = CHECKSUM_NONE;
7617 skb->ip_summed = CHECKSUM_NONE;
7619 swstats->mem_freed += skb->truesize;
7621 skb_record_rx_queue(skb, ring_no);
7622 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7624 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7629 * s2io_link - stops/starts the Tx queue.
7630 * @sp : private member of the device structure, which is a pointer to the
7631 * s2io_nic structure.
7632 * @link : inidicates whether link is UP/DOWN.
7634 * This function stops/starts the Tx queue depending on whether the link
7635 * status of the NIC is is down or up. This is called by the Alarm
7636 * interrupt handler whenever a link change interrupt comes up.
7641 static void s2io_link(struct s2io_nic *sp, int link)
7643 struct net_device *dev = (struct net_device *)sp->dev;
7644 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7646 if (link != sp->last_link_state) {
7648 if (link == LINK_DOWN) {
7649 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7650 s2io_stop_all_tx_queue(sp);
7651 netif_carrier_off(dev);
7652 if (swstats->link_up_cnt)
7653 swstats->link_up_time =
7654 jiffies - sp->start_time;
7655 swstats->link_down_cnt++;
7657 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7658 if (swstats->link_down_cnt)
7659 swstats->link_down_time =
7660 jiffies - sp->start_time;
7661 swstats->link_up_cnt++;
7662 netif_carrier_on(dev);
7663 s2io_wake_all_tx_queue(sp);
7666 sp->last_link_state = link;
7667 sp->start_time = jiffies;
7671 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7672 * @sp : private member of the device structure, which is a pointer to the
7673 * s2io_nic structure.
7675 * This function initializes a few of the PCI and PCI-X configuration registers
7676 * with recommended values.
7681 static void s2io_init_pci(struct s2io_nic *sp)
7683 u16 pci_cmd = 0, pcix_cmd = 0;
7685 /* Enable Data Parity Error Recovery in PCI-X command register. */
7686 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7688 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7690 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7693 /* Set the PErr Response bit in PCI command register. */
7694 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7695 pci_write_config_word(sp->pdev, PCI_COMMAND,
7696 (pci_cmd | PCI_COMMAND_PARITY));
7697 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7700 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7703 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7704 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7705 "(%d) not supported\n", tx_fifo_num);
7707 if (tx_fifo_num < 1)
7710 tx_fifo_num = MAX_TX_FIFOS;
7712 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7716 *dev_multiq = multiq;
7718 if (tx_steering_type && (1 == tx_fifo_num)) {
7719 if (tx_steering_type != TX_DEFAULT_STEERING)
7721 "Tx steering is not supported with "
7722 "one fifo. Disabling Tx steering.\n");
7723 tx_steering_type = NO_STEERING;
7726 if ((tx_steering_type < NO_STEERING) ||
7727 (tx_steering_type > TX_DEFAULT_STEERING)) {
7729 "Requested transmit steering not supported\n");
7730 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7731 tx_steering_type = NO_STEERING;
7734 if (rx_ring_num > MAX_RX_RINGS) {
7736 "Requested number of rx rings not supported\n");
7737 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7739 rx_ring_num = MAX_RX_RINGS;
7742 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7743 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7744 "Defaulting to INTA\n");
7745 *dev_intr_type = INTA;
7748 if ((*dev_intr_type == MSI_X) &&
7749 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7750 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7751 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7752 "Defaulting to INTA\n");
7753 *dev_intr_type = INTA;
7756 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7757 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7758 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7765 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7766 * or Traffic class respectively.
7767 * @nic: device private variable
7768 * Description: The function configures the receive steering to
7769 * desired receive ring.
7770 * Return Value: SUCCESS on success and
7771 * '-1' on failure (endian settings incorrect).
7773 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7775 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7776 register u64 val64 = 0;
7778 if (ds_codepoint > 63)
7781 val64 = RTS_DS_MEM_DATA(ring);
7782 writeq(val64, &bar0->rts_ds_mem_data);
7784 val64 = RTS_DS_MEM_CTRL_WE |
7785 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7786 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7788 writeq(val64, &bar0->rts_ds_mem_ctrl);
7790 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7791 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7795 static const struct net_device_ops s2io_netdev_ops = {
7796 .ndo_open = s2io_open,
7797 .ndo_stop = s2io_close,
7798 .ndo_get_stats = s2io_get_stats,
7799 .ndo_start_xmit = s2io_xmit,
7800 .ndo_validate_addr = eth_validate_addr,
7801 .ndo_set_multicast_list = s2io_set_multicast,
7802 .ndo_do_ioctl = s2io_ioctl,
7803 .ndo_set_mac_address = s2io_set_mac_addr,
7804 .ndo_change_mtu = s2io_change_mtu,
7805 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7806 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7807 .ndo_tx_timeout = s2io_tx_watchdog,
7808 #ifdef CONFIG_NET_POLL_CONTROLLER
7809 .ndo_poll_controller = s2io_netpoll,
7814 * s2io_init_nic - Initialization of the adapter .
7815 * @pdev : structure containing the PCI related information of the device.
7816 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7818 * The function initializes an adapter identified by the pci_dec structure.
7819 * All OS related initialization including memory and device structure and
7820 * initlaization of the device private variable is done. Also the swapper
7821 * control register is initialized to enable read and write into the I/O
7822 * registers of the device.
7824 * returns 0 on success and negative on failure.
7827 static int __devinit
7828 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7830 struct s2io_nic *sp;
7831 struct net_device *dev;
7833 int dma_flag = false;
7834 u32 mac_up, mac_down;
7835 u64 val64 = 0, tmp64 = 0;
7836 struct XENA_dev_config __iomem *bar0 = NULL;
7838 struct config_param *config;
7839 struct mac_info *mac_control;
7841 u8 dev_intr_type = intr_type;
7844 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7848 ret = pci_enable_device(pdev);
7851 "%s: pci_enable_device failed\n", __func__);
7855 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7856 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7858 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7860 "Unable to obtain 64bit DMA "
7861 "for consistent allocations\n");
7862 pci_disable_device(pdev);
7865 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7866 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7868 pci_disable_device(pdev);
7871 ret = pci_request_regions(pdev, s2io_driver_name);
7873 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7875 pci_disable_device(pdev);
7879 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7881 dev = alloc_etherdev(sizeof(struct s2io_nic));
7883 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7884 pci_disable_device(pdev);
7885 pci_release_regions(pdev);
7889 pci_set_master(pdev);
7890 pci_set_drvdata(pdev, dev);
7891 SET_NETDEV_DEV(dev, &pdev->dev);
7893 /* Private member variable initialized to s2io NIC structure */
7894 sp = netdev_priv(dev);
7897 sp->high_dma_flag = dma_flag;
7898 sp->device_enabled_once = false;
7899 if (rx_ring_mode == 1)
7900 sp->rxd_mode = RXD_MODE_1;
7901 if (rx_ring_mode == 2)
7902 sp->rxd_mode = RXD_MODE_3B;
7904 sp->config.intr_type = dev_intr_type;
7906 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7907 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7908 sp->device_type = XFRAME_II_DEVICE;
7910 sp->device_type = XFRAME_I_DEVICE;
7912 sp->lro = lro_enable;
7914 /* Initialize some PCI/PCI-X fields of the NIC. */
7918 * Setting the device configuration parameters.
7919 * Most of these parameters can be specified by the user during
7920 * module insertion as they are module loadable parameters. If
7921 * these parameters are not not specified during load time, they
7922 * are initialized with default values.
7924 config = &sp->config;
7925 mac_control = &sp->mac_control;
7927 config->napi = napi;
7928 config->tx_steering_type = tx_steering_type;
7930 /* Tx side parameters. */
7931 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7932 config->tx_fifo_num = MAX_TX_FIFOS;
7934 config->tx_fifo_num = tx_fifo_num;
7936 /* Initialize the fifos used for tx steering */
7937 if (config->tx_fifo_num < 5) {
7938 if (config->tx_fifo_num == 1)
7939 sp->total_tcp_fifos = 1;
7941 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7942 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7943 sp->total_udp_fifos = 1;
7944 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7946 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7947 FIFO_OTHER_MAX_NUM);
7948 sp->udp_fifo_idx = sp->total_tcp_fifos;
7949 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7950 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7953 config->multiq = dev_multiq;
7954 for (i = 0; i < config->tx_fifo_num; i++) {
7955 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7957 tx_cfg->fifo_len = tx_fifo_len[i];
7958 tx_cfg->fifo_priority = i;
7961 /* mapping the QoS priority to the configured fifos */
7962 for (i = 0; i < MAX_TX_FIFOS; i++)
7963 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7965 /* map the hashing selector table to the configured fifos */
7966 for (i = 0; i < config->tx_fifo_num; i++)
7967 sp->fifo_selector[i] = fifo_selector[i];
7970 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7971 for (i = 0; i < config->tx_fifo_num; i++) {
7972 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7974 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7975 if (tx_cfg->fifo_len < 65) {
7976 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7980 /* + 2 because one Txd for skb->data and one Txd for UFO */
7981 config->max_txds = MAX_SKB_FRAGS + 2;
7983 /* Rx side parameters. */
7984 config->rx_ring_num = rx_ring_num;
7985 for (i = 0; i < config->rx_ring_num; i++) {
7986 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7987 struct ring_info *ring = &mac_control->rings[i];
7989 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7990 rx_cfg->ring_priority = i;
7991 ring->rx_bufs_left = 0;
7992 ring->rxd_mode = sp->rxd_mode;
7993 ring->rxd_count = rxd_count[sp->rxd_mode];
7994 ring->pdev = sp->pdev;
7995 ring->dev = sp->dev;
7998 for (i = 0; i < rx_ring_num; i++) {
7999 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
8001 rx_cfg->ring_org = RING_ORG_BUFF1;
8002 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
8005 /* Setting Mac Control parameters */
8006 mac_control->rmac_pause_time = rmac_pause_time;
8007 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
8008 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
8011 /* initialize the shared memory used by the NIC and the host */
8012 if (init_shared_mem(sp)) {
8013 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
8015 goto mem_alloc_failed;
8018 sp->bar0 = pci_ioremap_bar(pdev, 0);
8020 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
8023 goto bar0_remap_failed;
8026 sp->bar1 = pci_ioremap_bar(pdev, 2);
8028 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
8031 goto bar1_remap_failed;
8034 dev->irq = pdev->irq;
8035 dev->base_addr = (unsigned long)sp->bar0;
8037 /* Initializing the BAR1 address as the start of the FIFO pointer. */
8038 for (j = 0; j < MAX_TX_FIFOS; j++) {
8039 mac_control->tx_FIFO_start[j] =
8040 (struct TxFIFO_element __iomem *)
8041 (sp->bar1 + (j * 0x00020000));
8044 /* Driver entry points */
8045 dev->netdev_ops = &s2io_netdev_ops;
8046 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
8047 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8049 dev->features |= NETIF_F_LRO;
8050 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8051 if (sp->high_dma_flag == true)
8052 dev->features |= NETIF_F_HIGHDMA;
8053 dev->features |= NETIF_F_TSO;
8054 dev->features |= NETIF_F_TSO6;
8055 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
8056 dev->features |= NETIF_F_UFO;
8057 dev->features |= NETIF_F_HW_CSUM;
8059 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
8060 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8061 INIT_WORK(&sp->set_link_task, s2io_set_link);
8063 pci_save_state(sp->pdev);
8065 /* Setting swapper control on the NIC, for proper reset operation */
8066 if (s2io_set_swapper(sp)) {
8067 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
8070 goto set_swap_failed;
8073 /* Verify if the Herc works on the slot its placed into */
8074 if (sp->device_type & XFRAME_II_DEVICE) {
8075 mode = s2io_verify_pci_mode(sp);
8077 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8080 goto set_swap_failed;
8084 if (sp->config.intr_type == MSI_X) {
8085 sp->num_entries = config->rx_ring_num + 1;
8086 ret = s2io_enable_msi_x(sp);
8089 ret = s2io_test_msi(sp);
8090 /* rollback MSI-X, will re-enable during add_isr() */
8091 remove_msix_isr(sp);
8096 "MSI-X requested but failed to enable\n");
8097 sp->config.intr_type = INTA;
8101 if (config->intr_type == MSI_X) {
8102 for (i = 0; i < config->rx_ring_num ; i++) {
8103 struct ring_info *ring = &mac_control->rings[i];
8105 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8108 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8111 /* Not needed for Herc */
8112 if (sp->device_type & XFRAME_I_DEVICE) {
8114 * Fix for all "FFs" MAC address problems observed on
8117 fix_mac_address(sp);
8122 * MAC address initialization.
8123 * For now only one mac address will be read and used.
8126 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8127 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8128 writeq(val64, &bar0->rmac_addr_cmd_mem);
8129 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8130 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8132 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8133 mac_down = (u32)tmp64;
8134 mac_up = (u32) (tmp64 >> 32);
8136 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8137 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8138 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8139 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8140 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8141 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8143 /* Set the factory defined MAC address initially */
8144 dev->addr_len = ETH_ALEN;
8145 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8146 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8148 /* initialize number of multicast & unicast MAC entries variables */
8149 if (sp->device_type == XFRAME_I_DEVICE) {
8150 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8151 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8152 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8153 } else if (sp->device_type == XFRAME_II_DEVICE) {
8154 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8155 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8156 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8159 /* store mac addresses from CAM to s2io_nic structure */
8160 do_s2io_store_unicast_mc(sp);
8162 /* Configure MSIX vector for number of rings configured plus one */
8163 if ((sp->device_type == XFRAME_II_DEVICE) &&
8164 (config->intr_type == MSI_X))
8165 sp->num_entries = config->rx_ring_num + 1;
8167 /* Store the values of the MSIX table in the s2io_nic structure */
8168 store_xmsi_data(sp);
8169 /* reset Nic and bring it to known state */
8173 * Initialize link state flags
8174 * and the card state parameter
8178 /* Initialize spinlocks */
8179 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8180 struct fifo_info *fifo = &mac_control->fifos[i];
8182 spin_lock_init(&fifo->tx_lock);
8186 * SXE-002: Configure link and activity LED to init state
8189 subid = sp->pdev->subsystem_device;
8190 if ((subid & 0xFF) >= 0x07) {
8191 val64 = readq(&bar0->gpio_control);
8192 val64 |= 0x0000800000000000ULL;
8193 writeq(val64, &bar0->gpio_control);
8194 val64 = 0x0411040400000000ULL;
8195 writeq(val64, (void __iomem *)bar0 + 0x2700);
8196 val64 = readq(&bar0->gpio_control);
8199 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8201 if (register_netdev(dev)) {
8202 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8204 goto register_failed;
8207 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8208 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8209 sp->product_name, pdev->revision);
8210 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8211 s2io_driver_version);
8212 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8213 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8214 if (sp->device_type & XFRAME_II_DEVICE) {
8215 mode = s2io_print_pci_mode(sp);
8218 unregister_netdev(dev);
8219 goto set_swap_failed;
8222 switch (sp->rxd_mode) {
8224 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8228 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8233 switch (sp->config.napi) {
8235 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8238 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8242 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8243 sp->config.tx_fifo_num);
8245 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8246 sp->config.rx_ring_num);
8248 switch (sp->config.intr_type) {
8250 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8253 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8256 if (sp->config.multiq) {
8257 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8258 struct fifo_info *fifo = &mac_control->fifos[i];
8260 fifo->multiq = config->multiq;
8262 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8265 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8268 switch (sp->config.tx_steering_type) {
8270 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8273 case TX_PRIORITY_STEERING:
8275 "%s: Priority steering enabled for transmit\n",
8278 case TX_DEFAULT_STEERING:
8280 "%s: Default steering enabled for transmit\n",
8285 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8289 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8291 /* Initialize device name */
8292 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8295 sp->vlan_strip_flag = 1;
8297 sp->vlan_strip_flag = 0;
8300 * Make Link state as off at this point, when the Link change
8301 * interrupt comes the state will be automatically changed to
8304 netif_carrier_off(dev);
8315 free_shared_mem(sp);
8316 pci_disable_device(pdev);
8317 pci_release_regions(pdev);
8318 pci_set_drvdata(pdev, NULL);
8325 * s2io_rem_nic - Free the PCI device
8326 * @pdev: structure containing the PCI related information of the device.
8327 * Description: This function is called by the Pci subsystem to release a
8328 * PCI device and free up all resource held up by the device. This could
8329 * be in response to a Hot plug event or when the driver is to be removed
8333 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8335 struct net_device *dev =
8336 (struct net_device *)pci_get_drvdata(pdev);
8337 struct s2io_nic *sp;
8340 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8344 flush_scheduled_work();
8346 sp = netdev_priv(dev);
8347 unregister_netdev(dev);
8349 free_shared_mem(sp);
8352 pci_release_regions(pdev);
8353 pci_set_drvdata(pdev, NULL);
8355 pci_disable_device(pdev);
8359 * s2io_starter - Entry point for the driver
8360 * Description: This function is the entry point for the driver. It verifies
8361 * the module loadable parameters and initializes PCI configuration space.
8364 static int __init s2io_starter(void)
8366 return pci_register_driver(&s2io_driver);
8370 * s2io_closer - Cleanup routine for the driver
8371 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8374 static __exit void s2io_closer(void)
8376 pci_unregister_driver(&s2io_driver);
8377 DBG_PRINT(INIT_DBG, "cleanup done\n");
8380 module_init(s2io_starter);
8381 module_exit(s2io_closer);
8383 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8384 struct tcphdr **tcp, struct RxD_t *rxdp,
8385 struct s2io_nic *sp)
8388 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8390 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8392 "%s: Non-TCP frames not supported for LRO\n",
8397 /* Checking for DIX type or DIX type with VLAN */
8398 if ((l2_type == 0) || (l2_type == 4)) {
8399 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8401 * If vlan stripping is disabled and the frame is VLAN tagged,
8402 * shift the offset by the VLAN header size bytes.
8404 if ((!sp->vlan_strip_flag) &&
8405 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8406 ip_off += HEADER_VLAN_SIZE;
8408 /* LLC, SNAP etc are considered non-mergeable */
8412 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8413 ip_len = (u8)((*ip)->ihl);
8415 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8420 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8423 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8424 if ((lro->iph->saddr != ip->saddr) ||
8425 (lro->iph->daddr != ip->daddr) ||
8426 (lro->tcph->source != tcp->source) ||
8427 (lro->tcph->dest != tcp->dest))
8432 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8434 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8437 static void initiate_new_session(struct lro *lro, u8 *l2h,
8438 struct iphdr *ip, struct tcphdr *tcp,
8439 u32 tcp_pyld_len, u16 vlan_tag)
8441 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8445 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8446 lro->tcp_ack = tcp->ack_seq;
8448 lro->total_len = ntohs(ip->tot_len);
8450 lro->vlan_tag = vlan_tag;
8452 * Check if we saw TCP timestamp.
8453 * Other consistency checks have already been done.
8455 if (tcp->doff == 8) {
8457 ptr = (__be32 *)(tcp+1);
8459 lro->cur_tsval = ntohl(*(ptr+1));
8460 lro->cur_tsecr = *(ptr+2);
8465 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8467 struct iphdr *ip = lro->iph;
8468 struct tcphdr *tcp = lro->tcph;
8470 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8472 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8474 /* Update L3 header */
8475 ip->tot_len = htons(lro->total_len);
8477 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8480 /* Update L4 header */
8481 tcp->ack_seq = lro->tcp_ack;
8482 tcp->window = lro->window;
8484 /* Update tsecr field if this session has timestamps enabled */
8486 __be32 *ptr = (__be32 *)(tcp + 1);
8487 *(ptr+2) = lro->cur_tsecr;
8490 /* Update counters required for calculation of
8491 * average no. of packets aggregated.
8493 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8494 swstats->num_aggregations++;
8497 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8498 struct tcphdr *tcp, u32 l4_pyld)
8500 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8501 lro->total_len += l4_pyld;
8502 lro->frags_len += l4_pyld;
8503 lro->tcp_next_seq += l4_pyld;
8506 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8507 lro->tcp_ack = tcp->ack_seq;
8508 lro->window = tcp->window;
8512 /* Update tsecr and tsval from this packet */
8513 ptr = (__be32 *)(tcp+1);
8514 lro->cur_tsval = ntohl(*(ptr+1));
8515 lro->cur_tsecr = *(ptr + 2);
8519 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8520 struct tcphdr *tcp, u32 tcp_pyld_len)
8524 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8526 if (!tcp_pyld_len) {
8527 /* Runt frame or a pure ack */
8531 if (ip->ihl != 5) /* IP has options */
8534 /* If we see CE codepoint in IP header, packet is not mergeable */
8535 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8538 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8539 if (tcp->urg || tcp->psh || tcp->rst ||
8540 tcp->syn || tcp->fin ||
8541 tcp->ece || tcp->cwr || !tcp->ack) {
8543 * Currently recognize only the ack control word and
8544 * any other control field being set would result in
8545 * flushing the LRO session
8551 * Allow only one TCP timestamp option. Don't aggregate if
8552 * any other options are detected.
8554 if (tcp->doff != 5 && tcp->doff != 8)
8557 if (tcp->doff == 8) {
8558 ptr = (u8 *)(tcp + 1);
8559 while (*ptr == TCPOPT_NOP)
8561 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8564 /* Ensure timestamp value increases monotonically */
8566 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8569 /* timestamp echo reply should be non-zero */
8570 if (*((__be32 *)(ptr+6)) == 0)
8577 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8578 u8 **tcp, u32 *tcp_len, struct lro **lro,
8579 struct RxD_t *rxdp, struct s2io_nic *sp)
8582 struct tcphdr *tcph;
8585 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8587 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8592 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8594 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8595 tcph = (struct tcphdr *)*tcp;
8596 *tcp_len = get_l4_pyld_length(ip, tcph);
8597 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8598 struct lro *l_lro = &ring_data->lro0_n[i];
8599 if (l_lro->in_use) {
8600 if (check_for_socket_match(l_lro, ip, tcph))
8602 /* Sock pair matched */
8605 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8606 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8607 "expected 0x%x, actual 0x%x\n",
8609 (*lro)->tcp_next_seq,
8612 swstats->outof_sequence_pkts++;
8617 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8619 ret = 1; /* Aggregate */
8621 ret = 2; /* Flush both */
8627 /* Before searching for available LRO objects,
8628 * check if the pkt is L3/L4 aggregatable. If not
8629 * don't create new LRO session. Just send this
8632 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8635 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8636 struct lro *l_lro = &ring_data->lro0_n[i];
8637 if (!(l_lro->in_use)) {
8639 ret = 3; /* Begin anew */
8645 if (ret == 0) { /* sessions exceeded */
8646 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8654 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8658 update_L3L4_header(sp, *lro);
8661 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8662 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8663 update_L3L4_header(sp, *lro);
8664 ret = 4; /* Flush the LRO */
8668 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8675 static void clear_lro_session(struct lro *lro)
8677 static u16 lro_struct_size = sizeof(struct lro);
8679 memset(lro, 0, lro_struct_size);
8682 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8684 struct net_device *dev = skb->dev;
8685 struct s2io_nic *sp = netdev_priv(dev);
8687 skb->protocol = eth_type_trans(skb, dev);
8688 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8689 /* Queueing the vlan frame to the upper layer */
8690 if (sp->config.napi)
8691 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8693 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8695 if (sp->config.napi)
8696 netif_receive_skb(skb);
8702 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8703 struct sk_buff *skb, u32 tcp_len)
8705 struct sk_buff *first = lro->parent;
8706 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8708 first->len += tcp_len;
8709 first->data_len = lro->frags_len;
8710 skb_pull(skb, (skb->len - tcp_len));
8711 if (skb_shinfo(first)->frag_list)
8712 lro->last_frag->next = skb;
8714 skb_shinfo(first)->frag_list = skb;
8715 first->truesize += skb->truesize;
8716 lro->last_frag = skb;
8717 swstats->clubbed_frms_cnt++;
8721 * s2io_io_error_detected - called when PCI error is detected
8722 * @pdev: Pointer to PCI device
8723 * @state: The current pci connection state
8725 * This function is called after a PCI bus error affecting
8726 * this device has been detected.
8728 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8729 pci_channel_state_t state)
8731 struct net_device *netdev = pci_get_drvdata(pdev);
8732 struct s2io_nic *sp = netdev_priv(netdev);
8734 netif_device_detach(netdev);
8736 if (state == pci_channel_io_perm_failure)
8737 return PCI_ERS_RESULT_DISCONNECT;
8739 if (netif_running(netdev)) {
8740 /* Bring down the card, while avoiding PCI I/O */
8741 do_s2io_card_down(sp, 0);
8743 pci_disable_device(pdev);
8745 return PCI_ERS_RESULT_NEED_RESET;
8749 * s2io_io_slot_reset - called after the pci bus has been reset.
8750 * @pdev: Pointer to PCI device
8752 * Restart the card from scratch, as if from a cold-boot.
8753 * At this point, the card has exprienced a hard reset,
8754 * followed by fixups by BIOS, and has its config space
8755 * set up identically to what it was at cold boot.
8757 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8759 struct net_device *netdev = pci_get_drvdata(pdev);
8760 struct s2io_nic *sp = netdev_priv(netdev);
8762 if (pci_enable_device(pdev)) {
8763 pr_err("Cannot re-enable PCI device after reset.\n");
8764 return PCI_ERS_RESULT_DISCONNECT;
8767 pci_set_master(pdev);
8770 return PCI_ERS_RESULT_RECOVERED;
8774 * s2io_io_resume - called when traffic can start flowing again.
8775 * @pdev: Pointer to PCI device
8777 * This callback is called when the error recovery driver tells
8778 * us that its OK to resume normal operation.
8780 static void s2io_io_resume(struct pci_dev *pdev)
8782 struct net_device *netdev = pci_get_drvdata(pdev);
8783 struct s2io_nic *sp = netdev_priv(netdev);
8785 if (netif_running(netdev)) {
8786 if (s2io_card_up(sp)) {
8787 pr_err("Can't bring device back up after reset.\n");
8791 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8793 pr_err("Can't restore mac addr after reset.\n");
8798 netif_device_attach(netdev);
8799 netif_tx_wake_all_queues(netdev);
git.samba.org / sfrench / cifs-2.6.git / blob