drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 110          board_82599 },
 111
 112         /* required last entry */
 113         {0, }
 114 };
 115 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 116
 117 #ifdef CONFIG_IXGBE_DCA
 118 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 119                             void *p);
 120 static struct notifier_block dca_notifier = {
 121         .notifier_call = ixgbe_notify_dca,
 122         .next          = NULL,
 123         .priority      = 0
 124 };
 125 #endif
 126
 127 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 128 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 129 MODULE_LICENSE("GPL");
 130 MODULE_VERSION(DRV_VERSION);
 131
 132 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 133
 134 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 135 {
 136         u32 ctrl_ext;
 137
 138         /* Let firmware take over control of h/w */
 139         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 140         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 141                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 142 }
 143
 144 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 145 {
 146         u32 ctrl_ext;
 147
 148         /* Let firmware know the driver has taken over */
 149         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 150         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 151                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 152 }
 153
 154 /*
 155  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 156  * @adapter: pointer to adapter struct
 157  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 158  * @queue: queue to map the corresponding interrupt to
 159  * @msix_vector: the vector to map to the corresponding queue
 160  *
 161  */
 162 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 163                            u8 queue, u8 msix_vector)
 164 {
 165         u32 ivar, index;
 166         struct ixgbe_hw *hw = &adapter->hw;
 167         switch (hw->mac.type) {
 168         case ixgbe_mac_82598EB:
 169                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 170                 if (direction == -1)
 171                         direction = 0;
 172                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 173                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 174                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 175                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 176                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 177                 break;
 178         case ixgbe_mac_82599EB:
 179                 if (direction == -1) {
 180                         /* other causes */
 181                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 182                         index = ((queue & 1) * 8);
 183                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 184                         ivar &= ~(0xFF << index);
 185                         ivar |= (msix_vector << index);
 186                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 187                         break;
 188                 } else {
 189                         /* tx or rx causes */
 190                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 191                         index = ((16 * (queue & 1)) + (8 * direction));
 192                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 193                         ivar &= ~(0xFF << index);
 194                         ivar |= (msix_vector << index);
 195                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 196                         break;
 197                 }
 198         default:
 199                 break;
 200         }
 201 }
 202
 203 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 204                                           u64 qmask)
 205 {
 206         u32 mask;
 207
 208         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 209                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 211         } else {
 212                 mask = (qmask & 0xFFFFFFFF);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 214                 mask = (qmask >> 32);
 215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 216         }
 217 }
 218
 219 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 220                                              struct ixgbe_tx_buffer
 221                                              *tx_buffer_info)
 222 {
 223         if (tx_buffer_info->dma) {
 224                 if (tx_buffer_info->mapped_as_page)
 225                         pci_unmap_page(adapter->pdev,
 226                                        tx_buffer_info->dma,
 227                                        tx_buffer_info->length,
 228                                        PCI_DMA_TODEVICE);
 229                 else
 230                         pci_unmap_single(adapter->pdev,
 231                                          tx_buffer_info->dma,
 232                                          tx_buffer_info->length,
 233                                          PCI_DMA_TODEVICE);
 234                 tx_buffer_info->dma = 0;
 235         }
 236         if (tx_buffer_info->skb) {
 237                 dev_kfree_skb_any(tx_buffer_info->skb);
 238                 tx_buffer_info->skb = NULL;
 239         }
 240         tx_buffer_info->time_stamp = 0;
 241         /* tx_buffer_info must be completely set up in the transmit path */
 242 }
 243
 244 /**
 245  * ixgbe_tx_is_paused - check if the tx ring is paused
 246  * @adapter: the ixgbe adapter
 247  * @tx_ring: the corresponding tx_ring
 248  *
 249  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 250  * corresponding TC of this tx_ring when checking TFCS.
 251  *
 252  * Returns : true if paused
 253  */
 254 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 255                                       struct ixgbe_ring *tx_ring)
 256 {
 257         u32 txoff = IXGBE_TFCS_TXOFF;
 258
 259 #ifdef CONFIG_IXGBE_DCB
 260         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 261                 int tc;
 262                 int reg_idx = tx_ring->reg_idx;
 263                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 264
 265                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 266                         tc = reg_idx >> 2;
 267                         txoff = IXGBE_TFCS_TXOFF0;
 268                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 269                         tc = 0;
 270                         txoff = IXGBE_TFCS_TXOFF;
 271                         if (dcb_i == 8) {
 272                                 /* TC0, TC1 */
 273                                 tc = reg_idx >> 5;
 274                                 if (tc == 2) /* TC2, TC3 */
 275                                         tc += (reg_idx - 64) >> 4;
 276                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 277                                         tc += 1 + ((reg_idx - 96) >> 3);
 278                         } else if (dcb_i == 4) {
 279                                 /* TC0, TC1 */
 280                                 tc = reg_idx >> 6;
 281                                 if (tc == 1) {
 282                                         tc += (reg_idx - 64) >> 5;
 283                                         if (tc == 2) /* TC2, TC3 */
 284                                                 tc += (reg_idx - 96) >> 4;
 285                                 }
 286                         }
 287                 }
 288                 txoff <<= tc;
 289         }
 290 #endif
 291         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 292 }
 293
 294 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 295                                        struct ixgbe_ring *tx_ring,
 296                                        unsigned int eop)
 297 {
 298         struct ixgbe_hw *hw = &adapter->hw;
 299
 300         /* Detect a transmit hang in hardware, this serializes the
 301          * check with the clearing of time_stamp and movement of eop */
 302         adapter->detect_tx_hung = false;
 303         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 304             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 305             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 306                 /* detected Tx unit hang */
 307                 union ixgbe_adv_tx_desc *tx_desc;
 308                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 309                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 310                         "  Tx Queue             <%d>\n"
 311                         "  TDH, TDT             <%x>, <%x>\n"
 312                         "  next_to_use          <%x>\n"
 313                         "  next_to_clean        <%x>\n"
 314                         "tx_buffer_info[next_to_clean]\n"
 315                         "  time_stamp           <%lx>\n"
 316                         "  jiffies              <%lx>\n",
 317                         tx_ring->queue_index,
 318                         IXGBE_READ_REG(hw, tx_ring->head),
 319                         IXGBE_READ_REG(hw, tx_ring->tail),
 320                         tx_ring->next_to_use, eop,
 321                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 322                 return true;
 323         }
 324
 325         return false;
 326 }
 327
 328 #define IXGBE_MAX_TXD_PWR       14
 329 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 330
 331 /* Tx Descriptors needed, worst case */
 332 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 333                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 334 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 335         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 336
 337 static void ixgbe_tx_timeout(struct net_device *netdev);
 338
 339 /**
 340  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 341  * @q_vector: structure containing interrupt and ring information
 342  * @tx_ring: tx ring to clean
 343  **/
 344 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 345                                struct ixgbe_ring *tx_ring)
 346 {
 347         struct ixgbe_adapter *adapter = q_vector->adapter;
 348         struct net_device *netdev = adapter->netdev;
 349         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 350         struct ixgbe_tx_buffer *tx_buffer_info;
 351         unsigned int i, eop, count = 0;
 352         unsigned int total_bytes = 0, total_packets = 0;
 353
 354         i = tx_ring->next_to_clean;
 355         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 356         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 357
 358         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 359                (count < tx_ring->work_limit)) {
 360                 bool cleaned = false;
 361                 for ( ; !cleaned; count++) {
 362                         struct sk_buff *skb;
 363                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 364                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 365                         cleaned = (i == eop);
 366                         skb = tx_buffer_info->skb;
 367
 368                         if (cleaned && skb) {
 369                                 unsigned int segs, bytecount;
 370                                 unsigned int hlen = skb_headlen(skb);
 371
 372                                 /* gso_segs is currently only valid for tcp */
 373                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 374 #ifdef IXGBE_FCOE
 375                                 /* adjust for FCoE Sequence Offload */
 376                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 377                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 378                                     skb_is_gso(skb)) {
 379                                         hlen = skb_transport_offset(skb) +
 380                                                 sizeof(struct fc_frame_header) +
 381                                                 sizeof(struct fcoe_crc_eof);
 382                                         segs = DIV_ROUND_UP(skb->len - hlen,
 383                                                 skb_shinfo(skb)->gso_size);
 384                                 }
 385 #endif /* IXGBE_FCOE */
 386                                 /* multiply data chunks by size of headers */
 387                                 bytecount = ((segs - 1) * hlen) + skb->len;
 388                                 total_packets += segs;
 389                                 total_bytes += bytecount;
 390                         }
 391
 392                         ixgbe_unmap_and_free_tx_resource(adapter,
 393                                                          tx_buffer_info);
 394
 395                         tx_desc->wb.status = 0;
 396
 397                         i++;
 398                         if (i == tx_ring->count)
 399                                 i = 0;
 400                 }
 401
 402                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 403                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 404         }
 405
 406         tx_ring->next_to_clean = i;
 407
 408 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 409         if (unlikely(count && netif_carrier_ok(netdev) &&
 410                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 411                 /* Make sure that anybody stopping the queue after this
 412                  * sees the new next_to_clean.
 413                  */
 414                 smp_mb();
 415                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 416                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 417                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 418                         ++tx_ring->restart_queue;
 419                 }
 420         }
 421
 422         if (adapter->detect_tx_hung) {
 423                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 424                         /* schedule immediate reset if we believe we hung */
 425                         DPRINTK(PROBE, INFO,
 426                                 "tx hang %d detected, resetting adapter\n",
 427                                 adapter->tx_timeout_count + 1);
 428                         ixgbe_tx_timeout(adapter->netdev);
 429                 }
 430         }
 431
 432         /* re-arm the interrupt */
 433         if (count >= tx_ring->work_limit)
 434                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 435
 436         tx_ring->total_bytes += total_bytes;
 437         tx_ring->total_packets += total_packets;
 438         tx_ring->stats.packets += total_packets;
 439         tx_ring->stats.bytes += total_bytes;
 440         return (count < tx_ring->work_limit);
 441 }
 442
 443 #ifdef CONFIG_IXGBE_DCA
 444 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 445                                 struct ixgbe_ring *rx_ring)
 446 {
 447         u32 rxctrl;
 448         int cpu = get_cpu();
 449         int q = rx_ring - adapter->rx_ring;
 450
 451         if (rx_ring->cpu != cpu) {
 452                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 453                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 454                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 455                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 456                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 457                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 458                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 459                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 460                 }
 461                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 462                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 463                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 464                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 465                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 466                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 467                 rx_ring->cpu = cpu;
 468         }
 469         put_cpu();
 470 }
 471
 472 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 473                                 struct ixgbe_ring *tx_ring)
 474 {
 475         u32 txctrl;
 476         int cpu = get_cpu();
 477         int q = tx_ring - adapter->tx_ring;
 478         struct ixgbe_hw *hw = &adapter->hw;
 479
 480         if (tx_ring->cpu != cpu) {
 481                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 482                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 483                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 484                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 485                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 486                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 487                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 488                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 489                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 490                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 491                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 492                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 493                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 494                 }
 495                 tx_ring->cpu = cpu;
 496         }
 497         put_cpu();
 498 }
 499
 500 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 501 {
 502         int i;
 503
 504         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 505                 return;
 506
 507         /* always use CB2 mode, difference is masked in the CB driver */
 508         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 509
 510         for (i = 0; i < adapter->num_tx_queues; i++) {
 511                 adapter->tx_ring[i].cpu = -1;
 512                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 513         }
 514         for (i = 0; i < adapter->num_rx_queues; i++) {
 515                 adapter->rx_ring[i].cpu = -1;
 516                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 517         }
 518 }
 519
 520 static int __ixgbe_notify_dca(struct device *dev, void *data)
 521 {
 522         struct net_device *netdev = dev_get_drvdata(dev);
 523         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 524         unsigned long event = *(unsigned long *)data;
 525
 526         switch (event) {
 527         case DCA_PROVIDER_ADD:
 528                 /* if we're already enabled, don't do it again */
 529                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 530                         break;
 531                 if (dca_add_requester(dev) == 0) {
 532                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 533                         ixgbe_setup_dca(adapter);
 534                         break;
 535                 }
 536                 /* Fall Through since DCA is disabled. */
 537         case DCA_PROVIDER_REMOVE:
 538                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 539                         dca_remove_requester(dev);
 540                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 541                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 542                 }
 543                 break;
 544         }
 545
 546         return 0;
 547 }
 548
 549 #endif /* CONFIG_IXGBE_DCA */
 550 /**
 551  * ixgbe_receive_skb - Send a completed packet up the stack
 552  * @adapter: board private structure
 553  * @skb: packet to send up
 554  * @status: hardware indication of status of receive
 555  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 556  * @rx_desc: rx descriptor
 557  **/
 558 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 559                               struct sk_buff *skb, u8 status,
 560                               struct ixgbe_ring *ring,
 561                               union ixgbe_adv_rx_desc *rx_desc)
 562 {
 563         struct ixgbe_adapter *adapter = q_vector->adapter;
 564         struct napi_struct *napi = &q_vector->napi;
 565         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 566         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 567
 568         skb_record_rx_queue(skb, ring->queue_index);
 569         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 570                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 571                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 572                 else
 573                         napi_gro_receive(napi, skb);
 574         } else {
 575                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 576                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 577                 else
 578                         netif_rx(skb);
 579         }
 580 }
 581
 582 /**
 583  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 584  * @adapter: address of board private structure
 585  * @status_err: hardware indication of status of receive
 586  * @skb: skb currently being received and modified
 587  **/
 588 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 589                                      union ixgbe_adv_rx_desc *rx_desc,
 590                                      struct sk_buff *skb)
 591 {
 592         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 593
 594         skb->ip_summed = CHECKSUM_NONE;
 595
 596         /* Rx csum disabled */
 597         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 598                 return;
 599
 600         /* if IP and error */
 601         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 602             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 603                 adapter->hw_csum_rx_error++;
 604                 return;
 605         }
 606
 607         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 608                 return;
 609
 610         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 611                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 612
 613                 /*
 614                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 615                  * checksum errors.
 616                  */
 617                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 618                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 619                         return;
 620
 621                 adapter->hw_csum_rx_error++;
 622                 return;
 623         }
 624
 625         /* It must be a TCP or UDP packet with a valid checksum */
 626         skb->ip_summed = CHECKSUM_UNNECESSARY;
 627 }
 628
 629 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 630                                          struct ixgbe_ring *rx_ring, u32 val)
 631 {
 632         /*
 633          * Force memory writes to complete before letting h/w
 634          * know there are new descriptors to fetch.  (Only
 635          * applicable for weak-ordered memory model archs,
 636          * such as IA-64).
 637          */
 638         wmb();
 639         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 640 }
 641
 642 /**
 643  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 644  * @adapter: address of board private structure
 645  **/
 646 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 647                                    struct ixgbe_ring *rx_ring,
 648                                    int cleaned_count)
 649 {
 650         struct pci_dev *pdev = adapter->pdev;
 651         union ixgbe_adv_rx_desc *rx_desc;
 652         struct ixgbe_rx_buffer *bi;
 653         unsigned int i;
 654
 655         i = rx_ring->next_to_use;
 656         bi = &rx_ring->rx_buffer_info[i];
 657
 658         while (cleaned_count--) {
 659                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 660
 661                 if (!bi->page_dma &&
 662                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 663                         if (!bi->page) {
 664                                 bi->page = alloc_page(GFP_ATOMIC);
 665                                 if (!bi->page) {
 666                                         adapter->alloc_rx_page_failed++;
 667                                         goto no_buffers;
 668                                 }
 669                                 bi->page_offset = 0;
 670                         } else {
 671                                 /* use a half page if we're re-using */
 672                                 bi->page_offset ^= (PAGE_SIZE / 2);
 673                         }
 674
 675                         bi->page_dma = pci_map_page(pdev, bi->page,
 676                                                     bi->page_offset,
 677                                                     (PAGE_SIZE / 2),
 678                                                     PCI_DMA_FROMDEVICE);
 679                 }
 680
 681                 if (!bi->skb) {
 682                         struct sk_buff *skb;
 683                         /* netdev_alloc_skb reserves 32 bytes up front!! */
 684                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
 685                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 686
 687                         if (!skb) {
 688                                 adapter->alloc_rx_buff_failed++;
 689                                 goto no_buffers;
 690                         }
 691
 692                         /* advance the data pointer to the next cache line */
 693                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
 694                                           - skb->data));
 695
 696                         bi->skb = skb;
 697                         bi->dma = pci_map_single(pdev, skb->data,
 698                                                  rx_ring->rx_buf_len,
 699                                                  PCI_DMA_FROMDEVICE);
 700                 }
 701                 /* Refresh the desc even if buffer_addrs didn't change because
 702                  * each write-back erases this info. */
 703                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 704                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 705                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 706                 } else {
 707                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 708                 }
 709
 710                 i++;
 711                 if (i == rx_ring->count)
 712                         i = 0;
 713                 bi = &rx_ring->rx_buffer_info[i];
 714         }
 715
 716 no_buffers:
 717         if (rx_ring->next_to_use != i) {
 718                 rx_ring->next_to_use = i;
 719                 if (i-- == 0)
 720                         i = (rx_ring->count - 1);
 721
 722                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 723         }
 724 }
 725
 726 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 727 {
 728         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 729 }
 730
 731 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 732 {
 733         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 734 }
 735
 736 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 737 {
 738         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 739                 IXGBE_RXDADV_RSCCNT_MASK) >>
 740                 IXGBE_RXDADV_RSCCNT_SHIFT;
 741 }
 742
 743 /**
 744  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 745  * @skb: pointer to the last skb in the rsc queue
 746  * @count: pointer to number of packets coalesced in this context
 747  *
 748  * This function changes a queue full of hw rsc buffers into a completed
 749  * packet.  It uses the ->prev pointers to find the first packet and then
 750  * turns it into the frag list owner.
 751  **/
 752 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
 753                                                         u64 *count)
 754 {
 755         unsigned int frag_list_size = 0;
 756
 757         while (skb->prev) {
 758                 struct sk_buff *prev = skb->prev;
 759                 frag_list_size += skb->len;
 760                 skb->prev = NULL;
 761                 skb = prev;
 762                 *count += 1;
 763         }
 764
 765         skb_shinfo(skb)->frag_list = skb->next;
 766         skb->next = NULL;
 767         skb->len += frag_list_size;
 768         skb->data_len += frag_list_size;
 769         skb->truesize += frag_list_size;
 770         return skb;
 771 }
 772
 773 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 774                                struct ixgbe_ring *rx_ring,
 775                                int *work_done, int work_to_do)
 776 {
 777         struct ixgbe_adapter *adapter = q_vector->adapter;
 778         struct net_device *netdev = adapter->netdev;
 779         struct pci_dev *pdev = adapter->pdev;
 780         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 781         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 782         struct sk_buff *skb;
 783         unsigned int i, rsc_count = 0;
 784         u32 len, staterr;
 785         u16 hdr_info;
 786         bool cleaned = false;
 787         int cleaned_count = 0;
 788         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 789 #ifdef IXGBE_FCOE
 790         int ddp_bytes = 0;
 791 #endif /* IXGBE_FCOE */
 792
 793         i = rx_ring->next_to_clean;
 794         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 795         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 796         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 797
 798         while (staterr & IXGBE_RXD_STAT_DD) {
 799                 u32 upper_len = 0;
 800                 if (*work_done >= work_to_do)
 801                         break;
 802                 (*work_done)++;
 803
 804                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 805                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 806                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 807                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 808                         if (len > IXGBE_RX_HDR_SIZE)
 809                                 len = IXGBE_RX_HDR_SIZE;
 810                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 811                 } else {
 812                         len = le16_to_cpu(rx_desc->wb.upper.length);
 813                 }
 814
 815                 cleaned = true;
 816                 skb = rx_buffer_info->skb;
 817                 prefetch(skb->data);
 818                 rx_buffer_info->skb = NULL;
 819
 820                 if (rx_buffer_info->dma) {
 821                         pci_unmap_single(pdev, rx_buffer_info->dma,
 822                                          rx_ring->rx_buf_len,
 823                                          PCI_DMA_FROMDEVICE);
 824                         rx_buffer_info->dma = 0;
 825                         skb_put(skb, len);
 826                 }
 827
 828                 if (upper_len) {
 829                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 830                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 831                         rx_buffer_info->page_dma = 0;
 832                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 833                                            rx_buffer_info->page,
 834                                            rx_buffer_info->page_offset,
 835                                            upper_len);
 836
 837                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 838                             (page_count(rx_buffer_info->page) != 1))
 839                                 rx_buffer_info->page = NULL;
 840                         else
 841                                 get_page(rx_buffer_info->page);
 842
 843                         skb->len += upper_len;
 844                         skb->data_len += upper_len;
 845                         skb->truesize += upper_len;
 846                 }
 847
 848                 i++;
 849                 if (i == rx_ring->count)
 850                         i = 0;
 851
 852                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 853                 prefetch(next_rxd);
 854                 cleaned_count++;
 855
 856                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 857                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 858
 859                 if (rsc_count) {
 860                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 861                                      IXGBE_RXDADV_NEXTP_SHIFT;
 862                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 863                 } else {
 864                         next_buffer = &rx_ring->rx_buffer_info[i];
 865                 }
 866
 867                 if (staterr & IXGBE_RXD_STAT_EOP) {
 868                         if (skb->prev)
 869                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
 870                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
 871                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
 872                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
 873                                 else
 874                                         rx_ring->rsc_count++;
 875                                 rx_ring->rsc_flush++;
 876                         }
 877                         rx_ring->stats.packets++;
 878                         rx_ring->stats.bytes += skb->len;
 879                 } else {
 880                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 881                                 rx_buffer_info->skb = next_buffer->skb;
 882                                 rx_buffer_info->dma = next_buffer->dma;
 883                                 next_buffer->skb = skb;
 884                                 next_buffer->dma = 0;
 885                         } else {
 886                                 skb->next = next_buffer->skb;
 887                                 skb->next->prev = skb;
 888                         }
 889                         rx_ring->non_eop_descs++;
 890                         goto next_desc;
 891                 }
 892
 893                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 894                         dev_kfree_skb_irq(skb);
 895                         goto next_desc;
 896                 }
 897
 898                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 899
 900                 /* probably a little skewed due to removing CRC */
 901                 total_rx_bytes += skb->len;
 902                 total_rx_packets++;
 903
 904                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 905 #ifdef IXGBE_FCOE
 906                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 907                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 908                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 909                         if (!ddp_bytes)
 910                                 goto next_desc;
 911                 }
 912 #endif /* IXGBE_FCOE */
 913                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 914
 915 next_desc:
 916                 rx_desc->wb.upper.status_error = 0;
 917
 918                 /* return some buffers to hardware, one at a time is too slow */
 919                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 920                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 921                         cleaned_count = 0;
 922                 }
 923
 924                 /* use prefetched values */
 925                 rx_desc = next_rxd;
 926                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 927
 928                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 929         }
 930
 931         rx_ring->next_to_clean = i;
 932         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 933
 934         if (cleaned_count)
 935                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 936
 937 #ifdef IXGBE_FCOE
 938         /* include DDPed FCoE data */
 939         if (ddp_bytes > 0) {
 940                 unsigned int mss;
 941
 942                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 943                         sizeof(struct fc_frame_header) -
 944                         sizeof(struct fcoe_crc_eof);
 945                 if (mss > 512)
 946                         mss &= ~511;
 947                 total_rx_bytes += ddp_bytes;
 948                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 949         }
 950 #endif /* IXGBE_FCOE */
 951
 952         rx_ring->total_packets += total_rx_packets;
 953         rx_ring->total_bytes += total_rx_bytes;
 954         netdev->stats.rx_bytes += total_rx_bytes;
 955         netdev->stats.rx_packets += total_rx_packets;
 956
 957         return cleaned;
 958 }
 959
 960 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 961 /**
 962  * ixgbe_configure_msix - Configure MSI-X hardware
 963  * @adapter: board private structure
 964  *
 965  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 966  * interrupts.
 967  **/
 968 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 969 {
 970         struct ixgbe_q_vector *q_vector;
 971         int i, j, q_vectors, v_idx, r_idx;
 972         u32 mask;
 973
 974         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 975
 976         /*
 977          * Populate the IVAR table and set the ITR values to the
 978          * corresponding register.
 979          */
 980         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 981                 q_vector = adapter->q_vector[v_idx];
 982                 /* XXX for_each_bit(...) */
 983                 r_idx = find_first_bit(q_vector->rxr_idx,
 984                                        adapter->num_rx_queues);
 985
 986                 for (i = 0; i < q_vector->rxr_count; i++) {
 987                         j = adapter->rx_ring[r_idx].reg_idx;
 988                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 989                         r_idx = find_next_bit(q_vector->rxr_idx,
 990                                               adapter->num_rx_queues,
 991                                               r_idx + 1);
 992                 }
 993                 r_idx = find_first_bit(q_vector->txr_idx,
 994                                        adapter->num_tx_queues);
 995
 996                 for (i = 0; i < q_vector->txr_count; i++) {
 997                         j = adapter->tx_ring[r_idx].reg_idx;
 998                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 999                         r_idx = find_next_bit(q_vector->txr_idx,
1000                                               adapter->num_tx_queues,
1001                                               r_idx + 1);
1002                 }
1003
1004                 if (q_vector->txr_count && !q_vector->rxr_count)
1005                         /* tx only */
1006                         q_vector->eitr = adapter->tx_eitr_param;
1007                 else if (q_vector->rxr_count)
1008                         /* rx or mixed */
1009                         q_vector->eitr = adapter->rx_eitr_param;
1010
1011                 ixgbe_write_eitr(q_vector);
1012         }
1013
1014         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1015                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1016                                v_idx);
1017         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1018                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1019         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1020
1021         /* set up to autoclear timer, and the vectors */
1022         mask = IXGBE_EIMS_ENABLE_MASK;
1023         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1024         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1025 }
1026
1027 enum latency_range {
1028         lowest_latency = 0,
1029         low_latency = 1,
1030         bulk_latency = 2,
1031         latency_invalid = 255
1032 };
1033
1034 /**
1035  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1036  * @adapter: pointer to adapter
1037  * @eitr: eitr setting (ints per sec) to give last timeslice
1038  * @itr_setting: current throttle rate in ints/second
1039  * @packets: the number of packets during this measurement interval
1040  * @bytes: the number of bytes during this measurement interval
1041  *
1042  *      Stores a new ITR value based on packets and byte
1043  *      counts during the last interrupt.  The advantage of per interrupt
1044  *      computation is faster updates and more accurate ITR for the current
1045  *      traffic pattern.  Constants in this function were computed
1046  *      based on theoretical maximum wire speed and thresholds were set based
1047  *      on testing data as well as attempting to minimize response time
1048  *      while increasing bulk throughput.
1049  *      this functionality is controlled by the InterruptThrottleRate module
1050  *      parameter (see ixgbe_param.c)
1051  **/
1052 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1053                            u32 eitr, u8 itr_setting,
1054                            int packets, int bytes)
1055 {
1056         unsigned int retval = itr_setting;
1057         u32 timepassed_us;
1058         u64 bytes_perint;
1059
1060         if (packets == 0)
1061                 goto update_itr_done;
1062
1063
1064         /* simple throttlerate management
1065          *    0-20MB/s lowest (100000 ints/s)
1066          *   20-100MB/s low   (20000 ints/s)
1067          *  100-1249MB/s bulk (8000 ints/s)
1068          */
1069         /* what was last interrupt timeslice? */
1070         timepassed_us = 1000000/eitr;
1071         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1072
1073         switch (itr_setting) {
1074         case lowest_latency:
1075                 if (bytes_perint > adapter->eitr_low)
1076                         retval = low_latency;
1077                 break;
1078         case low_latency:
1079                 if (bytes_perint > adapter->eitr_high)
1080                         retval = bulk_latency;
1081                 else if (bytes_perint <= adapter->eitr_low)
1082                         retval = lowest_latency;
1083                 break;
1084         case bulk_latency:
1085                 if (bytes_perint <= adapter->eitr_high)
1086                         retval = low_latency;
1087                 break;
1088         }
1089
1090 update_itr_done:
1091         return retval;
1092 }
1093
1094 /**
1095  * ixgbe_write_eitr - write EITR register in hardware specific way
1096  * @q_vector: structure containing interrupt and ring information
1097  *
1098  * This function is made to be called by ethtool and by the driver
1099  * when it needs to update EITR registers at runtime.  Hardware
1100  * specific quirks/differences are taken care of here.
1101  */
1102 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1103 {
1104         struct ixgbe_adapter *adapter = q_vector->adapter;
1105         struct ixgbe_hw *hw = &adapter->hw;
1106         int v_idx = q_vector->v_idx;
1107         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1108
1109         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1110                 /* must write high and low 16 bits to reset counter */
1111                 itr_reg |= (itr_reg << 16);
1112         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1113                 /*
1114                  * set the WDIS bit to not clear the timer bits and cause an
1115                  * immediate assertion of the interrupt
1116                  */
1117                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1118         }
1119         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1120 }
1121
1122 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1123 {
1124         struct ixgbe_adapter *adapter = q_vector->adapter;
1125         u32 new_itr;
1126         u8 current_itr, ret_itr;
1127         int i, r_idx;
1128         struct ixgbe_ring *rx_ring, *tx_ring;
1129
1130         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1131         for (i = 0; i < q_vector->txr_count; i++) {
1132                 tx_ring = &(adapter->tx_ring[r_idx]);
1133                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1134                                            q_vector->tx_itr,
1135                                            tx_ring->total_packets,
1136                                            tx_ring->total_bytes);
1137                 /* if the result for this queue would decrease interrupt
1138                  * rate for this vector then use that result */
1139                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1140                                     q_vector->tx_itr - 1 : ret_itr);
1141                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1142                                       r_idx + 1);
1143         }
1144
1145         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1146         for (i = 0; i < q_vector->rxr_count; i++) {
1147                 rx_ring = &(adapter->rx_ring[r_idx]);
1148                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1149                                            q_vector->rx_itr,
1150                                            rx_ring->total_packets,
1151                                            rx_ring->total_bytes);
1152                 /* if the result for this queue would decrease interrupt
1153                  * rate for this vector then use that result */
1154                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1155                                     q_vector->rx_itr - 1 : ret_itr);
1156                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1157                                       r_idx + 1);
1158         }
1159
1160         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1161
1162         switch (current_itr) {
1163         /* counts and packets in update_itr are dependent on these numbers */
1164         case lowest_latency:
1165                 new_itr = 100000;
1166                 break;
1167         case low_latency:
1168                 new_itr = 20000; /* aka hwitr = ~200 */
1169                 break;
1170         case bulk_latency:
1171         default:
1172                 new_itr = 8000;
1173                 break;
1174         }
1175
1176         if (new_itr != q_vector->eitr) {
1177                 /* do an exponential smoothing */
1178                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1179
1180                 /* save the algorithm value here, not the smoothed one */
1181                 q_vector->eitr = new_itr;
1182
1183                 ixgbe_write_eitr(q_vector);
1184         }
1185
1186         return;
1187 }
1188
1189 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1190 {
1191         struct ixgbe_hw *hw = &adapter->hw;
1192
1193         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1194             (eicr & IXGBE_EICR_GPI_SDP1)) {
1195                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1196                 /* write to clear the interrupt */
1197                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1198         }
1199 }
1200
1201 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1202 {
1203         struct ixgbe_hw *hw = &adapter->hw;
1204
1205         if (eicr & IXGBE_EICR_GPI_SDP1) {
1206                 /* Clear the interrupt */
1207                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1208                 schedule_work(&adapter->multispeed_fiber_task);
1209         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1210                 /* Clear the interrupt */
1211                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1212                 schedule_work(&adapter->sfp_config_module_task);
1213         } else {
1214                 /* Interrupt isn't for us... */
1215                 return;
1216         }
1217 }
1218
1219 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1220 {
1221         struct ixgbe_hw *hw = &adapter->hw;
1222
1223         adapter->lsc_int++;
1224         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1225         adapter->link_check_timeout = jiffies;
1226         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1227                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1228                 IXGBE_WRITE_FLUSH(hw);
1229                 schedule_work(&adapter->watchdog_task);
1230         }
1231 }
1232
1233 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1234 {
1235         struct net_device *netdev = data;
1236         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1237         struct ixgbe_hw *hw = &adapter->hw;
1238         u32 eicr;
1239
1240         /*
1241          * Workaround for Silicon errata.  Use clear-by-write instead
1242          * of clear-by-read.  Reading with EICS will return the
1243          * interrupt causes without clearing, which later be done
1244          * with the write to EICR.
1245          */
1246         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1247         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1248
1249         if (eicr & IXGBE_EICR_LSC)
1250                 ixgbe_check_lsc(adapter);
1251
1252         if (hw->mac.type == ixgbe_mac_82598EB)
1253                 ixgbe_check_fan_failure(adapter, eicr);
1254
1255         if (hw->mac.type == ixgbe_mac_82599EB) {
1256                 ixgbe_check_sfp_event(adapter, eicr);
1257
1258                 /* Handle Flow Director Full threshold interrupt */
1259                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1260                         int i;
1261                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1262                         /* Disable transmits before FDIR Re-initialization */
1263                         netif_tx_stop_all_queues(netdev);
1264                         for (i = 0; i < adapter->num_tx_queues; i++) {
1265                                 struct ixgbe_ring *tx_ring =
1266                                                            &adapter->tx_ring[i];
1267                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1268                                                        &tx_ring->reinit_state))
1269                                         schedule_work(&adapter->fdir_reinit_task);
1270                         }
1271                 }
1272         }
1273         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1274                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1275
1276         return IRQ_HANDLED;
1277 }
1278
1279 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1280                                            u64 qmask)
1281 {
1282         u32 mask;
1283
1284         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1285                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1286                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1287         } else {
1288                 mask = (qmask & 0xFFFFFFFF);
1289                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1290                 mask = (qmask >> 32);
1291                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1292         }
1293         /* skip the flush */
1294 }
1295
1296 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1297                                             u64 qmask)
1298 {
1299         u32 mask;
1300
1301         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1302                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1303                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1304         } else {
1305                 mask = (qmask & 0xFFFFFFFF);
1306                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1307                 mask = (qmask >> 32);
1308                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1309         }
1310         /* skip the flush */
1311 }
1312
1313 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1314 {
1315         struct ixgbe_q_vector *q_vector = data;
1316         struct ixgbe_adapter  *adapter = q_vector->adapter;
1317         struct ixgbe_ring     *tx_ring;
1318         int i, r_idx;
1319
1320         if (!q_vector->txr_count)
1321                 return IRQ_HANDLED;
1322
1323         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1324         for (i = 0; i < q_vector->txr_count; i++) {
1325                 tx_ring = &(adapter->tx_ring[r_idx]);
1326                 tx_ring->total_bytes = 0;
1327                 tx_ring->total_packets = 0;
1328                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1329                                       r_idx + 1);
1330         }
1331
1332         /* EIAM disabled interrupts (on this vector) for us */
1333         napi_schedule(&q_vector->napi);
1334
1335         return IRQ_HANDLED;
1336 }
1337
1338 /**
1339  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1340  * @irq: unused
1341  * @data: pointer to our q_vector struct for this interrupt vector
1342  **/
1343 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1344 {
1345         struct ixgbe_q_vector *q_vector = data;
1346         struct ixgbe_adapter  *adapter = q_vector->adapter;
1347         struct ixgbe_ring  *rx_ring;
1348         int r_idx;
1349         int i;
1350
1351         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1352         for (i = 0;  i < q_vector->rxr_count; i++) {
1353                 rx_ring = &(adapter->rx_ring[r_idx]);
1354                 rx_ring->total_bytes = 0;
1355                 rx_ring->total_packets = 0;
1356                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1357                                       r_idx + 1);
1358         }
1359
1360         if (!q_vector->rxr_count)
1361                 return IRQ_HANDLED;
1362
1363         /* disable interrupts on this vector only */
1364         /* EIAM disabled interrupts (on this vector) for us */
1365         napi_schedule(&q_vector->napi);
1366
1367         return IRQ_HANDLED;
1368 }
1369
1370 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1371 {
1372         struct ixgbe_q_vector *q_vector = data;
1373         struct ixgbe_adapter  *adapter = q_vector->adapter;
1374         struct ixgbe_ring  *ring;
1375         int r_idx;
1376         int i;
1377
1378         if (!q_vector->txr_count && !q_vector->rxr_count)
1379                 return IRQ_HANDLED;
1380
1381         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1382         for (i = 0; i < q_vector->txr_count; i++) {
1383                 ring = &(adapter->tx_ring[r_idx]);
1384                 ring->total_bytes = 0;
1385                 ring->total_packets = 0;
1386                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1387                                       r_idx + 1);
1388         }
1389
1390         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1391         for (i = 0; i < q_vector->rxr_count; i++) {
1392                 ring = &(adapter->rx_ring[r_idx]);
1393                 ring->total_bytes = 0;
1394                 ring->total_packets = 0;
1395                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1396                                       r_idx + 1);
1397         }
1398
1399         /* EIAM disabled interrupts (on this vector) for us */
1400         napi_schedule(&q_vector->napi);
1401
1402         return IRQ_HANDLED;
1403 }
1404
1405 /**
1406  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1407  * @napi: napi struct with our devices info in it
1408  * @budget: amount of work driver is allowed to do this pass, in packets
1409  *
1410  * This function is optimized for cleaning one queue only on a single
1411  * q_vector!!!
1412  **/
1413 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1414 {
1415         struct ixgbe_q_vector *q_vector =
1416                                container_of(napi, struct ixgbe_q_vector, napi);
1417         struct ixgbe_adapter *adapter = q_vector->adapter;
1418         struct ixgbe_ring *rx_ring = NULL;
1419         int work_done = 0;
1420         long r_idx;
1421
1422         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1423         rx_ring = &(adapter->rx_ring[r_idx]);
1424 #ifdef CONFIG_IXGBE_DCA
1425         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1426                 ixgbe_update_rx_dca(adapter, rx_ring);
1427 #endif
1428
1429         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1430
1431         /* If all Rx work done, exit the polling mode */
1432         if (work_done < budget) {
1433                 napi_complete(napi);
1434                 if (adapter->rx_itr_setting & 1)
1435                         ixgbe_set_itr_msix(q_vector);
1436                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1437                         ixgbe_irq_enable_queues(adapter,
1438                                                 ((u64)1 << q_vector->v_idx));
1439         }
1440
1441         return work_done;
1442 }
1443
1444 /**
1445  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1446  * @napi: napi struct with our devices info in it
1447  * @budget: amount of work driver is allowed to do this pass, in packets
1448  *
1449  * This function will clean more than one rx queue associated with a
1450  * q_vector.
1451  **/
1452 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1453 {
1454         struct ixgbe_q_vector *q_vector =
1455                                container_of(napi, struct ixgbe_q_vector, napi);
1456         struct ixgbe_adapter *adapter = q_vector->adapter;
1457         struct ixgbe_ring *ring = NULL;
1458         int work_done = 0, i;
1459         long r_idx;
1460         bool tx_clean_complete = true;
1461
1462         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1463         for (i = 0; i < q_vector->txr_count; i++) {
1464                 ring = &(adapter->tx_ring[r_idx]);
1465 #ifdef CONFIG_IXGBE_DCA
1466                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1467                         ixgbe_update_tx_dca(adapter, ring);
1468 #endif
1469                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1470                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1471                                       r_idx + 1);
1472         }
1473
1474         /* attempt to distribute budget to each queue fairly, but don't allow
1475          * the budget to go below 1 because we'll exit polling */
1476         budget /= (q_vector->rxr_count ?: 1);
1477         budget = max(budget, 1);
1478         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1479         for (i = 0; i < q_vector->rxr_count; i++) {
1480                 ring = &(adapter->rx_ring[r_idx]);
1481 #ifdef CONFIG_IXGBE_DCA
1482                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1483                         ixgbe_update_rx_dca(adapter, ring);
1484 #endif
1485                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1486                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1487                                       r_idx + 1);
1488         }
1489
1490         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1491         ring = &(adapter->rx_ring[r_idx]);
1492         /* If all Rx work done, exit the polling mode */
1493         if (work_done < budget) {
1494                 napi_complete(napi);
1495                 if (adapter->rx_itr_setting & 1)
1496                         ixgbe_set_itr_msix(q_vector);
1497                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1498                         ixgbe_irq_enable_queues(adapter,
1499                                                 ((u64)1 << q_vector->v_idx));
1500                 return 0;
1501         }
1502
1503         return work_done;
1504 }
1505
1506 /**
1507  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1508  * @napi: napi struct with our devices info in it
1509  * @budget: amount of work driver is allowed to do this pass, in packets
1510  *
1511  * This function is optimized for cleaning one queue only on a single
1512  * q_vector!!!
1513  **/
1514 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1515 {
1516         struct ixgbe_q_vector *q_vector =
1517                                container_of(napi, struct ixgbe_q_vector, napi);
1518         struct ixgbe_adapter *adapter = q_vector->adapter;
1519         struct ixgbe_ring *tx_ring = NULL;
1520         int work_done = 0;
1521         long r_idx;
1522
1523         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1524         tx_ring = &(adapter->tx_ring[r_idx]);
1525 #ifdef CONFIG_IXGBE_DCA
1526         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1527                 ixgbe_update_tx_dca(adapter, tx_ring);
1528 #endif
1529
1530         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1531                 work_done = budget;
1532
1533         /* If all Tx work done, exit the polling mode */
1534         if (work_done < budget) {
1535                 napi_complete(napi);
1536                 if (adapter->tx_itr_setting & 1)
1537                         ixgbe_set_itr_msix(q_vector);
1538                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1539                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1540         }
1541
1542         return work_done;
1543 }
1544
1545 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1546                                      int r_idx)
1547 {
1548         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1549
1550         set_bit(r_idx, q_vector->rxr_idx);
1551         q_vector->rxr_count++;
1552 }
1553
1554 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1555                                      int t_idx)
1556 {
1557         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1558
1559         set_bit(t_idx, q_vector->txr_idx);
1560         q_vector->txr_count++;
1561 }
1562
1563 /**
1564  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1565  * @adapter: board private structure to initialize
1566  * @vectors: allotted vector count for descriptor rings
1567  *
1568  * This function maps descriptor rings to the queue-specific vectors
1569  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1570  * one vector per ring/queue, but on a constrained vector budget, we
1571  * group the rings as "efficiently" as possible.  You would add new
1572  * mapping configurations in here.
1573  **/
1574 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1575                                       int vectors)
1576 {
1577         int v_start = 0;
1578         int rxr_idx = 0, txr_idx = 0;
1579         int rxr_remaining = adapter->num_rx_queues;
1580         int txr_remaining = adapter->num_tx_queues;
1581         int i, j;
1582         int rqpv, tqpv;
1583         int err = 0;
1584
1585         /* No mapping required if MSI-X is disabled. */
1586         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1587                 goto out;
1588
1589         /*
1590          * The ideal configuration...
1591          * We have enough vectors to map one per queue.
1592          */
1593         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1594                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1595                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1596
1597                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1598                         map_vector_to_txq(adapter, v_start, txr_idx);
1599
1600                 goto out;
1601         }
1602
1603         /*
1604          * If we don't have enough vectors for a 1-to-1
1605          * mapping, we'll have to group them so there are
1606          * multiple queues per vector.
1607          */
1608         /* Re-adjusting *qpv takes care of the remainder. */
1609         for (i = v_start; i < vectors; i++) {
1610                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1611                 for (j = 0; j < rqpv; j++) {
1612                         map_vector_to_rxq(adapter, i, rxr_idx);
1613                         rxr_idx++;
1614                         rxr_remaining--;
1615                 }
1616         }
1617         for (i = v_start; i < vectors; i++) {
1618                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1619                 for (j = 0; j < tqpv; j++) {
1620                         map_vector_to_txq(adapter, i, txr_idx);
1621                         txr_idx++;
1622                         txr_remaining--;
1623                 }
1624         }
1625
1626 out:
1627         return err;
1628 }
1629
1630 /**
1631  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1632  * @adapter: board private structure
1633  *
1634  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1635  * interrupts from the kernel.
1636  **/
1637 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1638 {
1639         struct net_device *netdev = adapter->netdev;
1640         irqreturn_t (*handler)(int, void *);
1641         int i, vector, q_vectors, err;
1642         int ri=0, ti=0;
1643
1644         /* Decrement for Other and TCP Timer vectors */
1645         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1646
1647         /* Map the Tx/Rx rings to the vectors we were allotted. */
1648         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1649         if (err)
1650                 goto out;
1651
1652 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1653                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1654                          &ixgbe_msix_clean_many)
1655         for (vector = 0; vector < q_vectors; vector++) {
1656                 handler = SET_HANDLER(adapter->q_vector[vector]);
1657
1658                 if(handler == &ixgbe_msix_clean_rx) {
1659                         sprintf(adapter->name[vector], "%s-%s-%d",
1660                                 netdev->name, "rx", ri++);
1661                 }
1662                 else if(handler == &ixgbe_msix_clean_tx) {
1663                         sprintf(adapter->name[vector], "%s-%s-%d",
1664                                 netdev->name, "tx", ti++);
1665                 }
1666                 else
1667                         sprintf(adapter->name[vector], "%s-%s-%d",
1668                                 netdev->name, "TxRx", vector);
1669
1670                 err = request_irq(adapter->msix_entries[vector].vector,
1671                                   handler, 0, adapter->name[vector],
1672                                   adapter->q_vector[vector]);
1673                 if (err) {
1674                         DPRINTK(PROBE, ERR,
1675                                 "request_irq failed for MSIX interrupt "
1676                                 "Error: %d\n", err);
1677                         goto free_queue_irqs;
1678                 }
1679         }
1680
1681         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1682         err = request_irq(adapter->msix_entries[vector].vector,
1683                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1684         if (err) {
1685                 DPRINTK(PROBE, ERR,
1686                         "request_irq for msix_lsc failed: %d\n", err);
1687                 goto free_queue_irqs;
1688         }
1689
1690         return 0;
1691
1692 free_queue_irqs:
1693         for (i = vector - 1; i >= 0; i--)
1694                 free_irq(adapter->msix_entries[--vector].vector,
1695                          adapter->q_vector[i]);
1696         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1697         pci_disable_msix(adapter->pdev);
1698         kfree(adapter->msix_entries);
1699         adapter->msix_entries = NULL;
1700 out:
1701         return err;
1702 }
1703
1704 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1705 {
1706         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1707         u8 current_itr;
1708         u32 new_itr = q_vector->eitr;
1709         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1710         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1711
1712         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1713                                             q_vector->tx_itr,
1714                                             tx_ring->total_packets,
1715                                             tx_ring->total_bytes);
1716         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1717                                             q_vector->rx_itr,
1718                                             rx_ring->total_packets,
1719                                             rx_ring->total_bytes);
1720
1721         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1722
1723         switch (current_itr) {
1724         /* counts and packets in update_itr are dependent on these numbers */
1725         case lowest_latency:
1726                 new_itr = 100000;
1727                 break;
1728         case low_latency:
1729                 new_itr = 20000; /* aka hwitr = ~200 */
1730                 break;
1731         case bulk_latency:
1732                 new_itr = 8000;
1733                 break;
1734         default:
1735                 break;
1736         }
1737
1738         if (new_itr != q_vector->eitr) {
1739                 /* do an exponential smoothing */
1740                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1741
1742                 /* save the algorithm value here, not the smoothed one */
1743                 q_vector->eitr = new_itr;
1744
1745                 ixgbe_write_eitr(q_vector);
1746         }
1747
1748         return;
1749 }
1750
1751 /**
1752  * ixgbe_irq_enable - Enable default interrupt generation settings
1753  * @adapter: board private structure
1754  **/
1755 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1756 {
1757         u32 mask;
1758
1759         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1760         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1761                 mask |= IXGBE_EIMS_GPI_SDP1;
1762         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1763                 mask |= IXGBE_EIMS_ECC;
1764                 mask |= IXGBE_EIMS_GPI_SDP1;
1765                 mask |= IXGBE_EIMS_GPI_SDP2;
1766         }
1767         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1768             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1769                 mask |= IXGBE_EIMS_FLOW_DIR;
1770
1771         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1772         ixgbe_irq_enable_queues(adapter, ~0);
1773         IXGBE_WRITE_FLUSH(&adapter->hw);
1774 }
1775
1776 /**
1777  * ixgbe_intr - legacy mode Interrupt Handler
1778  * @irq: interrupt number
1779  * @data: pointer to a network interface device structure
1780  **/
1781 static irqreturn_t ixgbe_intr(int irq, void *data)
1782 {
1783         struct net_device *netdev = data;
1784         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1785         struct ixgbe_hw *hw = &adapter->hw;
1786         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1787         u32 eicr;
1788
1789         /*
1790          * Workaround for silicon errata.  Mask the interrupts
1791          * before the read of EICR.
1792          */
1793         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1794
1795         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1796          * therefore no explict interrupt disable is necessary */
1797         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1798         if (!eicr) {
1799                 /* shared interrupt alert!
1800                  * make sure interrupts are enabled because the read will
1801                  * have disabled interrupts due to EIAM */
1802                 ixgbe_irq_enable(adapter);
1803                 return IRQ_NONE;        /* Not our interrupt */
1804         }
1805
1806         if (eicr & IXGBE_EICR_LSC)
1807                 ixgbe_check_lsc(adapter);
1808
1809         if (hw->mac.type == ixgbe_mac_82599EB)
1810                 ixgbe_check_sfp_event(adapter, eicr);
1811
1812         ixgbe_check_fan_failure(adapter, eicr);
1813
1814         if (napi_schedule_prep(&(q_vector->napi))) {
1815                 adapter->tx_ring[0].total_packets = 0;
1816                 adapter->tx_ring[0].total_bytes = 0;
1817                 adapter->rx_ring[0].total_packets = 0;
1818                 adapter->rx_ring[0].total_bytes = 0;
1819                 /* would disable interrupts here but EIAM disabled it */
1820                 __napi_schedule(&(q_vector->napi));
1821         }
1822
1823         return IRQ_HANDLED;
1824 }
1825
1826 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1827 {
1828         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1829
1830         for (i = 0; i < q_vectors; i++) {
1831                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1832                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1833                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1834                 q_vector->rxr_count = 0;
1835                 q_vector->txr_count = 0;
1836         }
1837 }
1838
1839 /**
1840  * ixgbe_request_irq - initialize interrupts
1841  * @adapter: board private structure
1842  *
1843  * Attempts to configure interrupts using the best available
1844  * capabilities of the hardware and kernel.
1845  **/
1846 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1847 {
1848         struct net_device *netdev = adapter->netdev;
1849         int err;
1850
1851         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1852                 err = ixgbe_request_msix_irqs(adapter);
1853         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1854                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1855                                   netdev->name, netdev);
1856         } else {
1857                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1858                                   netdev->name, netdev);
1859         }
1860
1861         if (err)
1862                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1863
1864         return err;
1865 }
1866
1867 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1868 {
1869         struct net_device *netdev = adapter->netdev;
1870
1871         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1872                 int i, q_vectors;
1873
1874                 q_vectors = adapter->num_msix_vectors;
1875
1876                 i = q_vectors - 1;
1877                 free_irq(adapter->msix_entries[i].vector, netdev);
1878
1879                 i--;
1880                 for (; i >= 0; i--) {
1881                         free_irq(adapter->msix_entries[i].vector,
1882                                  adapter->q_vector[i]);
1883                 }
1884
1885                 ixgbe_reset_q_vectors(adapter);
1886         } else {
1887                 free_irq(adapter->pdev->irq, netdev);
1888         }
1889 }
1890
1891 /**
1892  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1893  * @adapter: board private structure
1894  **/
1895 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1896 {
1897         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1898                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1899         } else {
1900                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1901                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1902                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1903         }
1904         IXGBE_WRITE_FLUSH(&adapter->hw);
1905         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1906                 int i;
1907                 for (i = 0; i < adapter->num_msix_vectors; i++)
1908                         synchronize_irq(adapter->msix_entries[i].vector);
1909         } else {
1910                 synchronize_irq(adapter->pdev->irq);
1911         }
1912 }
1913
1914 /**
1915  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1916  *
1917  **/
1918 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1919 {
1920         struct ixgbe_hw *hw = &adapter->hw;
1921
1922         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1923                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1924
1925         ixgbe_set_ivar(adapter, 0, 0, 0);
1926         ixgbe_set_ivar(adapter, 1, 0, 0);
1927
1928         map_vector_to_rxq(adapter, 0, 0);
1929         map_vector_to_txq(adapter, 0, 0);
1930
1931         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1932 }
1933
1934 /**
1935  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1936  * @adapter: board private structure
1937  *
1938  * Configure the Tx unit of the MAC after a reset.
1939  **/
1940 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1941 {
1942         u64 tdba;
1943         struct ixgbe_hw *hw = &adapter->hw;
1944         u32 i, j, tdlen, txctrl;
1945
1946         /* Setup the HW Tx Head and Tail descriptor pointers */
1947         for (i = 0; i < adapter->num_tx_queues; i++) {
1948                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1949                 j = ring->reg_idx;
1950                 tdba = ring->dma;
1951                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1952                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1953                                 (tdba & DMA_BIT_MASK(32)));
1954                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1955                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1956                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1957                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1958                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1959                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1960                 /*
1961                  * Disable Tx Head Writeback RO bit, since this hoses
1962                  * bookkeeping if things aren't delivered in order.
1963                  */
1964                 switch (hw->mac.type) {
1965                 case ixgbe_mac_82598EB:
1966                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1967                         break;
1968                 case ixgbe_mac_82599EB:
1969                 default:
1970                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1971                         break;
1972                 }
1973                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1974                 switch (hw->mac.type) {
1975                 case ixgbe_mac_82598EB:
1976                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1977                         break;
1978                 case ixgbe_mac_82599EB:
1979                 default:
1980                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1981                         break;
1982                 }
1983         }
1984
1985         if (hw->mac.type == ixgbe_mac_82599EB) {
1986                 u32 rttdcs;
1987
1988                 /* disable the arbiter while setting MTQC */
1989                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1990                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1991                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1992
1993                 /* We enable 8 traffic classes, DCB only */
1994                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1995                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1996                                         IXGBE_MTQC_8TC_8TQ));
1997                 else
1998                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1999
2000                 /* re-eable the arbiter */
2001                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2002                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2003         }
2004 }
2005
2006 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2007
2008 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2009                                    struct ixgbe_ring *rx_ring)
2010 {
2011         u32 srrctl;
2012         int index;
2013         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2014
2015         index = rx_ring->reg_idx;
2016         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2017                 unsigned long mask;
2018                 mask = (unsigned long) feature[RING_F_RSS].mask;
2019                 index = index & mask;
2020         }
2021         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2022
2023         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2024         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2025
2026         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2027                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2028
2029         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2030 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2031                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2032 #else
2033                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2034 #endif
2035                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2036         } else {
2037                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2038                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2039                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2040         }
2041
2042         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2043 }
2044
2045 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2046 {
2047         u32 mrqc = 0;
2048         int mask;
2049
2050         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2051                 return mrqc;
2052
2053         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2054 #ifdef CONFIG_IXGBE_DCB
2055                                  | IXGBE_FLAG_DCB_ENABLED
2056 #endif
2057                                 );
2058
2059         switch (mask) {
2060         case (IXGBE_FLAG_RSS_ENABLED):
2061                 mrqc = IXGBE_MRQC_RSSEN;
2062                 break;
2063 #ifdef CONFIG_IXGBE_DCB
2064         case (IXGBE_FLAG_DCB_ENABLED):
2065                 mrqc = IXGBE_MRQC_RT8TCEN;
2066                 break;
2067 #endif /* CONFIG_IXGBE_DCB */
2068         default:
2069                 break;
2070         }
2071
2072         return mrqc;
2073 }
2074
2075 /**
2076  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2077  * @adapter:    address of board private structure
2078  * @index:      index of ring to set
2079  **/
2080 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2081 {
2082         struct ixgbe_ring *rx_ring;
2083         struct ixgbe_hw *hw = &adapter->hw;
2084         int j;
2085         u32 rscctrl;
2086         int rx_buf_len;
2087
2088         rx_ring = &adapter->rx_ring[index];
2089         j = rx_ring->reg_idx;
2090         rx_buf_len = rx_ring->rx_buf_len;
2091         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2092         rscctrl |= IXGBE_RSCCTL_RSCEN;
2093         /*
2094          * we must limit the number of descriptors so that the
2095          * total size of max desc * buf_len is not greater
2096          * than 65535
2097          */
2098         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2099 #if (MAX_SKB_FRAGS > 16)
2100                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2101 #elif (MAX_SKB_FRAGS > 8)
2102                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2103 #elif (MAX_SKB_FRAGS > 4)
2104                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2105 #else
2106                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2107 #endif
2108         } else {
2109                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2110                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2111                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2112                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2113                 else
2114                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2115         }
2116         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2117 }
2118
2119 /**
2120  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2121  * @adapter: board private structure
2122  *
2123  * Configure the Rx unit of the MAC after a reset.
2124  **/
2125 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2126 {
2127         u64 rdba;
2128         struct ixgbe_hw *hw = &adapter->hw;
2129         struct ixgbe_ring *rx_ring;
2130         struct net_device *netdev = adapter->netdev;
2131         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2132         int i, j;
2133         u32 rdlen, rxctrl, rxcsum;
2134         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2135                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2136                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2137         u32 fctrl, hlreg0;
2138         u32 reta = 0, mrqc = 0;
2139         u32 rdrxctl;
2140         int rx_buf_len;
2141
2142         /* Decide whether to use packet split mode or not */
2143         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2144
2145         /* Set the RX buffer length according to the mode */
2146         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2147                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2148                 if (hw->mac.type == ixgbe_mac_82599EB) {
2149                         /* PSRTYPE must be initialized in 82599 */
2150                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2151                                       IXGBE_PSRTYPE_UDPHDR |
2152                                       IXGBE_PSRTYPE_IPV4HDR |
2153                                       IXGBE_PSRTYPE_IPV6HDR |
2154                                       IXGBE_PSRTYPE_L2HDR;
2155                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2156                 }
2157         } else {
2158                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2159                     (netdev->mtu <= ETH_DATA_LEN))
2160                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2161                 else
2162                         rx_buf_len = ALIGN(max_frame, 1024);
2163         }
2164
2165         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2166         fctrl |= IXGBE_FCTRL_BAM;
2167         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2168         fctrl |= IXGBE_FCTRL_PMCF;
2169         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2170
2171         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2172         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2173                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2174         else
2175                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2176 #ifdef IXGBE_FCOE
2177         if (netdev->features & NETIF_F_FCOE_MTU)
2178                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2179 #endif
2180         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2181
2182         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2183         /* disable receives while setting up the descriptors */
2184         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2185         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2186
2187         /*
2188          * Setup the HW Rx Head and Tail Descriptor Pointers and
2189          * the Base and Length of the Rx Descriptor Ring
2190          */
2191         for (i = 0; i < adapter->num_rx_queues; i++) {
2192                 rx_ring = &adapter->rx_ring[i];
2193                 rdba = rx_ring->dma;
2194                 j = rx_ring->reg_idx;
2195                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2196                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2197                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2198                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2199                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2200                 rx_ring->head = IXGBE_RDH(j);
2201                 rx_ring->tail = IXGBE_RDT(j);
2202                 rx_ring->rx_buf_len = rx_buf_len;
2203
2204                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2205                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2206                 else
2207                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2208
2209 #ifdef IXGBE_FCOE
2210                 if (netdev->features & NETIF_F_FCOE_MTU) {
2211                         struct ixgbe_ring_feature *f;
2212                         f = &adapter->ring_feature[RING_F_FCOE];
2213                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2214                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2215                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2216                                         rx_ring->rx_buf_len =
2217                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2218                         }
2219                 }
2220
2221 #endif /* IXGBE_FCOE */
2222                 ixgbe_configure_srrctl(adapter, rx_ring);
2223         }
2224
2225         if (hw->mac.type == ixgbe_mac_82598EB) {
2226                 /*
2227                  * For VMDq support of different descriptor types or
2228                  * buffer sizes through the use of multiple SRRCTL
2229                  * registers, RDRXCTL.MVMEN must be set to 1
2230                  *
2231                  * also, the manual doesn't mention it clearly but DCA hints
2232                  * will only use queue 0's tags unless this bit is set.  Side
2233                  * effects of setting this bit are only that SRRCTL must be
2234                  * fully programmed [0..15]
2235                  */
2236                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2237                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2238                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2239         }
2240
2241         /* Program MRQC for the distribution of queues */
2242         mrqc = ixgbe_setup_mrqc(adapter);
2243
2244         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2245                 /* Fill out redirection table */
2246                 for (i = 0, j = 0; i < 128; i++, j++) {
2247                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2248                                 j = 0;
2249                         /* reta = 4-byte sliding window of
2250                          * 0x00..(indices-1)(indices-1)00..etc. */
2251                         reta = (reta << 8) | (j * 0x11);
2252                         if ((i & 3) == 3)
2253                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2254                 }
2255
2256                 /* Fill out hash function seeds */
2257                 for (i = 0; i < 10; i++)
2258                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2259
2260                 if (hw->mac.type == ixgbe_mac_82598EB)
2261                         mrqc |= IXGBE_MRQC_RSSEN;
2262                     /* Perform hash on these packet types */
2263                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2264                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2265                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2266                       | IXGBE_MRQC_RSS_FIELD_IPV6
2267                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2268                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2269         }
2270         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2271
2272         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2273
2274         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2275             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2276                 /* Disable indicating checksum in descriptor, enables
2277                  * RSS hash */
2278                 rxcsum |= IXGBE_RXCSUM_PCSD;
2279         }
2280         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2281                 /* Enable IPv4 payload checksum for UDP fragments
2282                  * if PCSD is not set */
2283                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2284         }
2285
2286         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2287
2288         if (hw->mac.type == ixgbe_mac_82599EB) {
2289                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2290                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2291                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2292                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2293         }
2294
2295         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2296                 /* Enable 82599 HW-RSC */
2297                 for (i = 0; i < adapter->num_rx_queues; i++)
2298                         ixgbe_configure_rscctl(adapter, i);
2299
2300                 /* Disable RSC for ACK packets */
2301                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2302                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2303         }
2304 }
2305
2306 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2307 {
2308         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2309         struct ixgbe_hw *hw = &adapter->hw;
2310
2311         /* add VID to filter table */
2312         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2313 }
2314
2315 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2316 {
2317         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2318         struct ixgbe_hw *hw = &adapter->hw;
2319
2320         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2321                 ixgbe_irq_disable(adapter);
2322
2323         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2324
2325         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2326                 ixgbe_irq_enable(adapter);
2327
2328         /* remove VID from filter table */
2329         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2330 }
2331
2332 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2333                                    struct vlan_group *grp)
2334 {
2335         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2336         u32 ctrl;
2337         int i, j;
2338
2339         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2340                 ixgbe_irq_disable(adapter);
2341         adapter->vlgrp = grp;
2342
2343         /*
2344          * For a DCB driver, always enable VLAN tag stripping so we can
2345          * still receive traffic from a DCB-enabled host even if we're
2346          * not in DCB mode.
2347          */
2348         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2349
2350         /* Disable CFI check */
2351         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2352
2353         /* enable VLAN tag stripping */
2354         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2355                 ctrl |= IXGBE_VLNCTRL_VME;
2356         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2357                 for (i = 0; i < adapter->num_rx_queues; i++) {
2358                         u32 ctrl;
2359                         j = adapter->rx_ring[i].reg_idx;
2360                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2361                         ctrl |= IXGBE_RXDCTL_VME;
2362                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2363                 }
2364         }
2365
2366         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2367
2368         ixgbe_vlan_rx_add_vid(netdev, 0);
2369
2370         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2371                 ixgbe_irq_enable(adapter);
2372 }
2373
2374 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2375 {
2376         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2377
2378         if (adapter->vlgrp) {
2379                 u16 vid;
2380                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2381                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2382                                 continue;
2383                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2384                 }
2385         }
2386 }
2387
2388 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2389 {
2390         struct dev_mc_list *mc_ptr;
2391         u8 *addr = *mc_addr_ptr;
2392         *vmdq = 0;
2393
2394         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2395         if (mc_ptr->next)
2396                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2397         else
2398                 *mc_addr_ptr = NULL;
2399
2400         return addr;
2401 }
2402
2403 /**
2404  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2405  * @netdev: network interface device structure
2406  *
2407  * The set_rx_method entry point is called whenever the unicast/multicast
2408  * address list or the network interface flags are updated.  This routine is
2409  * responsible for configuring the hardware for proper unicast, multicast and
2410  * promiscuous mode.
2411  **/
2412 static void ixgbe_set_rx_mode(struct net_device *netdev)
2413 {
2414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2415         struct ixgbe_hw *hw = &adapter->hw;
2416         u32 fctrl, vlnctrl;
2417         u8 *addr_list = NULL;
2418         int addr_count = 0;
2419
2420         /* Check for Promiscuous and All Multicast modes */
2421
2422         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2423         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2424
2425         if (netdev->flags & IFF_PROMISC) {
2426                 hw->addr_ctrl.user_set_promisc = 1;
2427                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2428                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2429         } else {
2430                 if (netdev->flags & IFF_ALLMULTI) {
2431                         fctrl |= IXGBE_FCTRL_MPE;
2432                         fctrl &= ~IXGBE_FCTRL_UPE;
2433                 } else {
2434                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2435                 }
2436                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2437                 hw->addr_ctrl.user_set_promisc = 0;
2438         }
2439
2440         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2441         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2442
2443         /* reprogram secondary unicast list */
2444         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2445
2446         /* reprogram multicast list */
2447         addr_count = netdev->mc_count;
2448         if (addr_count)
2449                 addr_list = netdev->mc_list->dmi_addr;
2450         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2451                                         ixgbe_addr_list_itr);
2452 }
2453
2454 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2455 {
2456         int q_idx;
2457         struct ixgbe_q_vector *q_vector;
2458         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2459
2460         /* legacy and MSI only use one vector */
2461         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2462                 q_vectors = 1;
2463
2464         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2465                 struct napi_struct *napi;
2466                 q_vector = adapter->q_vector[q_idx];
2467                 napi = &q_vector->napi;
2468                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2469                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2470                                 if (q_vector->txr_count == 1)
2471                                         napi->poll = &ixgbe_clean_txonly;
2472                                 else if (q_vector->rxr_count == 1)
2473                                         napi->poll = &ixgbe_clean_rxonly;
2474                         }
2475                 }
2476
2477                 napi_enable(napi);
2478         }
2479 }
2480
2481 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2482 {
2483         int q_idx;
2484         struct ixgbe_q_vector *q_vector;
2485         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2486
2487         /* legacy and MSI only use one vector */
2488         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2489                 q_vectors = 1;
2490
2491         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2492                 q_vector = adapter->q_vector[q_idx];
2493                 napi_disable(&q_vector->napi);
2494         }
2495 }
2496
2497 #ifdef CONFIG_IXGBE_DCB
2498 /*
2499  * ixgbe_configure_dcb - Configure DCB hardware
2500  * @adapter: ixgbe adapter struct
2501  *
2502  * This is called by the driver on open to configure the DCB hardware.
2503  * This is also called by the gennetlink interface when reconfiguring
2504  * the DCB state.
2505  */
2506 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2507 {
2508         struct ixgbe_hw *hw = &adapter->hw;
2509         u32 txdctl, vlnctrl;
2510         int i, j;
2511
2512         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2513         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2514         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2515
2516         /* reconfigure the hardware */
2517         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2518
2519         for (i = 0; i < adapter->num_tx_queues; i++) {
2520                 j = adapter->tx_ring[i].reg_idx;
2521                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2522                 /* PThresh workaround for Tx hang with DFP enabled. */
2523                 txdctl |= 32;
2524                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2525         }
2526         /* Enable VLAN tag insert/strip */
2527         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2528         if (hw->mac.type == ixgbe_mac_82598EB) {
2529                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2530                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2531                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2532         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2533                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2534                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2535                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2536                 for (i = 0; i < adapter->num_rx_queues; i++) {
2537                         j = adapter->rx_ring[i].reg_idx;
2538                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2539                         vlnctrl |= IXGBE_RXDCTL_VME;
2540                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2541                 }
2542         }
2543         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2544 }
2545
2546 #endif
2547 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2548 {
2549         struct net_device *netdev = adapter->netdev;
2550         struct ixgbe_hw *hw = &adapter->hw;
2551         int i;
2552
2553         ixgbe_set_rx_mode(netdev);
2554
2555         ixgbe_restore_vlan(adapter);
2556 #ifdef CONFIG_IXGBE_DCB
2557         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2558                 if (hw->mac.type == ixgbe_mac_82598EB)
2559                         netif_set_gso_max_size(netdev, 32768);
2560                 else
2561                         netif_set_gso_max_size(netdev, 65536);
2562                 ixgbe_configure_dcb(adapter);
2563         } else {
2564                 netif_set_gso_max_size(netdev, 65536);
2565         }
2566 #else
2567         netif_set_gso_max_size(netdev, 65536);
2568 #endif
2569
2570 #ifdef IXGBE_FCOE
2571         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2572                 ixgbe_configure_fcoe(adapter);
2573
2574 #endif /* IXGBE_FCOE */
2575         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2576                 for (i = 0; i < adapter->num_tx_queues; i++)
2577                         adapter->tx_ring[i].atr_sample_rate =
2578                                                        adapter->atr_sample_rate;
2579                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2580         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2581                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2582         }
2583
2584         ixgbe_configure_tx(adapter);
2585         ixgbe_configure_rx(adapter);
2586         for (i = 0; i < adapter->num_rx_queues; i++)
2587                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2588                                        (adapter->rx_ring[i].count - 1));
2589 }
2590
2591 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2592 {
2593         switch (hw->phy.type) {
2594         case ixgbe_phy_sfp_avago:
2595         case ixgbe_phy_sfp_ftl:
2596         case ixgbe_phy_sfp_intel:
2597         case ixgbe_phy_sfp_unknown:
2598         case ixgbe_phy_tw_tyco:
2599         case ixgbe_phy_tw_unknown:
2600                 return true;
2601         default:
2602                 return false;
2603         }
2604 }
2605
2606 /**
2607  * ixgbe_sfp_link_config - set up SFP+ link
2608  * @adapter: pointer to private adapter struct
2609  **/
2610 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2611 {
2612         struct ixgbe_hw *hw = &adapter->hw;
2613
2614                 if (hw->phy.multispeed_fiber) {
2615                         /*
2616                          * In multispeed fiber setups, the device may not have
2617                          * had a physical connection when the driver loaded.
2618                          * If that's the case, the initial link configuration
2619                          * couldn't get the MAC into 10G or 1G mode, so we'll
2620                          * never have a link status change interrupt fire.
2621                          * We need to try and force an autonegotiation
2622                          * session, then bring up link.
2623                          */
2624                         hw->mac.ops.setup_sfp(hw);
2625                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2626                                 schedule_work(&adapter->multispeed_fiber_task);
2627                 } else {
2628                         /*
2629                          * Direct Attach Cu and non-multispeed fiber modules
2630                          * still need to be configured properly prior to
2631                          * attempting link.
2632                          */
2633                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2634                                 schedule_work(&adapter->sfp_config_module_task);
2635                 }
2636 }
2637
2638 /**
2639  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2640  * @hw: pointer to private hardware struct
2641  *
2642  * Returns 0 on success, negative on failure
2643  **/
2644 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2645 {
2646         u32 autoneg;
2647         bool negotiation, link_up = false;
2648         u32 ret = IXGBE_ERR_LINK_SETUP;
2649
2650         if (hw->mac.ops.check_link)
2651                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2652
2653         if (ret)
2654                 goto link_cfg_out;
2655
2656         if (hw->mac.ops.get_link_capabilities)
2657                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2658         if (ret)
2659                 goto link_cfg_out;
2660
2661         if (hw->mac.ops.setup_link)
2662                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2663 link_cfg_out:
2664         return ret;
2665 }
2666
2667 #define IXGBE_MAX_RX_DESC_POLL 10
2668 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2669                                               int rxr)
2670 {
2671         int j = adapter->rx_ring[rxr].reg_idx;
2672         int k;
2673
2674         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2675                 if (IXGBE_READ_REG(&adapter->hw,
2676                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2677                         break;
2678                 else
2679                         msleep(1);
2680         }
2681         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2682                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2683                         "not set within the polling period\n", rxr);
2684         }
2685         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2686                               (adapter->rx_ring[rxr].count - 1));
2687 }
2688
2689 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2690 {
2691         struct net_device *netdev = adapter->netdev;
2692         struct ixgbe_hw *hw = &adapter->hw;
2693         int i, j = 0;
2694         int num_rx_rings = adapter->num_rx_queues;
2695         int err;
2696         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2697         u32 txdctl, rxdctl, mhadd;
2698         u32 dmatxctl;
2699         u32 gpie;
2700
2701         ixgbe_get_hw_control(adapter);
2702
2703         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2704             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2705                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2706                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2707                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2708                 } else {
2709                         /* MSI only */
2710                         gpie = 0;
2711                 }
2712                 /* XXX: to interrupt immediately for EICS writes, enable this */
2713                 /* gpie |= IXGBE_GPIE_EIMEN; */
2714                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2715         }
2716
2717         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2718                 /*
2719                  * use EIAM to auto-mask when MSI-X interrupt is asserted
2720                  * this saves a register write for every interrupt
2721                  */
2722                 switch (hw->mac.type) {
2723                 case ixgbe_mac_82598EB:
2724                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2725                         break;
2726                 default:
2727                 case ixgbe_mac_82599EB:
2728                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2729                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2730                         break;
2731                 }
2732         } else {
2733                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2734                  * specifically only auto mask tx and rx interrupts */
2735                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2736         }
2737
2738         /* Enable fan failure interrupt if media type is copper */
2739         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2740                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2741                 gpie |= IXGBE_SDP1_GPIEN;
2742                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2743         }
2744
2745         if (hw->mac.type == ixgbe_mac_82599EB) {
2746                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2747                 gpie |= IXGBE_SDP1_GPIEN;
2748                 gpie |= IXGBE_SDP2_GPIEN;
2749                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2750         }
2751
2752 #ifdef IXGBE_FCOE
2753         /* adjust max frame to be able to do baby jumbo for FCoE */
2754         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2755             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2756                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2757
2758 #endif /* IXGBE_FCOE */
2759         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2760         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2761                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2762                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2763
2764                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2765         }
2766
2767         for (i = 0; i < adapter->num_tx_queues; i++) {
2768                 j = adapter->tx_ring[i].reg_idx;
2769                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2770                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2771                 txdctl |= (8 << 16);
2772                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2773         }
2774
2775         if (hw->mac.type == ixgbe_mac_82599EB) {
2776                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2777                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2778                 dmatxctl |= IXGBE_DMATXCTL_TE;
2779                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2780         }
2781         for (i = 0; i < adapter->num_tx_queues; i++) {
2782                 j = adapter->tx_ring[i].reg_idx;
2783                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2784                 txdctl |= IXGBE_TXDCTL_ENABLE;
2785                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2786         }
2787
2788         for (i = 0; i < num_rx_rings; i++) {
2789                 j = adapter->rx_ring[i].reg_idx;
2790                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2791                 /* enable PTHRESH=32 descriptors (half the internal cache)
2792                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2793                  * this also removes a pesky rx_no_buffer_count increment */
2794                 rxdctl |= 0x0020;
2795                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2796                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2797                 if (hw->mac.type == ixgbe_mac_82599EB)
2798                         ixgbe_rx_desc_queue_enable(adapter, i);
2799         }
2800         /* enable all receives */
2801         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2802         if (hw->mac.type == ixgbe_mac_82598EB)
2803                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2804         else
2805                 rxdctl |= IXGBE_RXCTRL_RXEN;
2806         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2807
2808         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2809                 ixgbe_configure_msix(adapter);
2810         else
2811                 ixgbe_configure_msi_and_legacy(adapter);
2812
2813         clear_bit(__IXGBE_DOWN, &adapter->state);
2814         ixgbe_napi_enable_all(adapter);
2815
2816         /* clear any pending interrupts, may auto mask */
2817         IXGBE_READ_REG(hw, IXGBE_EICR);
2818
2819         ixgbe_irq_enable(adapter);
2820
2821         /*
2822          * If this adapter has a fan, check to see if we had a failure
2823          * before we enabled the interrupt.
2824          */
2825         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2826                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2827                 if (esdp & IXGBE_ESDP_SDP1)
2828                         DPRINTK(DRV, CRIT,
2829                                 "Fan has stopped, replace the adapter\n");
2830         }
2831
2832         /*
2833          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2834          * arrived before interrupts were enabled but after probe.  Such
2835          * devices wouldn't have their type identified yet. We need to
2836          * kick off the SFP+ module setup first, then try to bring up link.
2837          * If we're not hot-pluggable SFP+, we just need to configure link
2838          * and bring it up.
2839          */
2840         if (hw->phy.type == ixgbe_phy_unknown) {
2841                 err = hw->phy.ops.identify(hw);
2842                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2843                         /*
2844                          * Take the device down and schedule the sfp tasklet
2845                          * which will unregister_netdev and log it.
2846                          */
2847                         ixgbe_down(adapter);
2848                         schedule_work(&adapter->sfp_config_module_task);
2849                         return err;
2850                 }
2851         }
2852
2853         if (ixgbe_is_sfp(hw)) {
2854                 ixgbe_sfp_link_config(adapter);
2855         } else {
2856                 err = ixgbe_non_sfp_link_config(hw);
2857                 if (err)
2858                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2859         }
2860
2861         for (i = 0; i < adapter->num_tx_queues; i++)
2862                 set_bit(__IXGBE_FDIR_INIT_DONE,
2863                         &(adapter->tx_ring[i].reinit_state));
2864
2865         /* enable transmits */
2866         netif_tx_start_all_queues(netdev);
2867
2868         /* bring the link up in the watchdog, this could race with our first
2869          * link up interrupt but shouldn't be a problem */
2870         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2871         adapter->link_check_timeout = jiffies;
2872         mod_timer(&adapter->watchdog_timer, jiffies);
2873         return 0;
2874 }
2875
2876 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2877 {
2878         WARN_ON(in_interrupt());
2879         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2880                 msleep(1);
2881         ixgbe_down(adapter);
2882         ixgbe_up(adapter);
2883         clear_bit(__IXGBE_RESETTING, &adapter->state);
2884 }
2885
2886 int ixgbe_up(struct ixgbe_adapter *adapter)
2887 {
2888         /* hardware has been reset, we need to reload some things */
2889         ixgbe_configure(adapter);
2890
2891         return ixgbe_up_complete(adapter);
2892 }
2893
2894 void ixgbe_reset(struct ixgbe_adapter *adapter)
2895 {
2896         struct ixgbe_hw *hw = &adapter->hw;
2897         int err;
2898
2899         err = hw->mac.ops.init_hw(hw);
2900         switch (err) {
2901         case 0:
2902         case IXGBE_ERR_SFP_NOT_PRESENT:
2903                 break;
2904         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2905                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2906                 break;
2907         case IXGBE_ERR_EEPROM_VERSION:
2908                 /* We are running on a pre-production device, log a warning */
2909                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2910                          "adapter/LOM.  Please be aware there may be issues "
2911                          "associated with your hardware.  If you are "
2912                          "experiencing problems please contact your Intel or "
2913                          "hardware representative who provided you with this "
2914                          "hardware.\n");
2915                 break;
2916         default:
2917                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2918         }
2919
2920         /* reprogram the RAR[0] in case user changed it. */
2921         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2922 }
2923
2924 /**
2925  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2926  * @adapter: board private structure
2927  * @rx_ring: ring to free buffers from
2928  **/
2929 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2930                                 struct ixgbe_ring *rx_ring)
2931 {
2932         struct pci_dev *pdev = adapter->pdev;
2933         unsigned long size;
2934         unsigned int i;
2935
2936         /* Free all the Rx ring sk_buffs */
2937
2938         for (i = 0; i < rx_ring->count; i++) {
2939                 struct ixgbe_rx_buffer *rx_buffer_info;
2940
2941                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2942                 if (rx_buffer_info->dma) {
2943                         pci_unmap_single(pdev, rx_buffer_info->dma,
2944                                          rx_ring->rx_buf_len,
2945                                          PCI_DMA_FROMDEVICE);
2946                         rx_buffer_info->dma = 0;
2947                 }
2948                 if (rx_buffer_info->skb) {
2949                         struct sk_buff *skb = rx_buffer_info->skb;
2950                         rx_buffer_info->skb = NULL;
2951                         do {
2952                                 struct sk_buff *this = skb;
2953                                 skb = skb->prev;
2954                                 dev_kfree_skb(this);
2955                         } while (skb);
2956                 }
2957                 if (!rx_buffer_info->page)
2958                         continue;
2959                 if (rx_buffer_info->page_dma) {
2960                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2961                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2962                         rx_buffer_info->page_dma = 0;
2963                 }
2964                 put_page(rx_buffer_info->page);
2965                 rx_buffer_info->page = NULL;
2966                 rx_buffer_info->page_offset = 0;
2967         }
2968
2969         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2970         memset(rx_ring->rx_buffer_info, 0, size);
2971
2972         /* Zero out the descriptor ring */
2973         memset(rx_ring->desc, 0, rx_ring->size);
2974
2975         rx_ring->next_to_clean = 0;
2976         rx_ring->next_to_use = 0;
2977
2978         if (rx_ring->head)
2979                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2980         if (rx_ring->tail)
2981                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2982 }
2983
2984 /**
2985  * ixgbe_clean_tx_ring - Free Tx Buffers
2986  * @adapter: board private structure
2987  * @tx_ring: ring to be cleaned
2988  **/
2989 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2990                                 struct ixgbe_ring *tx_ring)
2991 {
2992         struct ixgbe_tx_buffer *tx_buffer_info;
2993         unsigned long size;
2994         unsigned int i;
2995
2996         /* Free all the Tx ring sk_buffs */
2997
2998         for (i = 0; i < tx_ring->count; i++) {
2999                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3000                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3001         }
3002
3003         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3004         memset(tx_ring->tx_buffer_info, 0, size);
3005
3006         /* Zero out the descriptor ring */
3007         memset(tx_ring->desc, 0, tx_ring->size);
3008
3009         tx_ring->next_to_use = 0;
3010         tx_ring->next_to_clean = 0;
3011
3012         if (tx_ring->head)
3013                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3014         if (tx_ring->tail)
3015                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3016 }
3017
3018 /**
3019  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3020  * @adapter: board private structure
3021  **/
3022 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3023 {
3024         int i;
3025
3026         for (i = 0; i < adapter->num_rx_queues; i++)
3027                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3028 }
3029
3030 /**
3031  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3032  * @adapter: board private structure
3033  **/
3034 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3035 {
3036         int i;
3037
3038         for (i = 0; i < adapter->num_tx_queues; i++)
3039                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3040 }
3041
3042 void ixgbe_down(struct ixgbe_adapter *adapter)
3043 {
3044         struct net_device *netdev = adapter->netdev;
3045         struct ixgbe_hw *hw = &adapter->hw;
3046         u32 rxctrl;
3047         u32 txdctl;
3048         int i, j;
3049
3050         /* signal that we are down to the interrupt handler */
3051         set_bit(__IXGBE_DOWN, &adapter->state);
3052
3053         /* disable receives */
3054         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3055         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3056
3057         netif_tx_disable(netdev);
3058
3059         IXGBE_WRITE_FLUSH(hw);
3060         msleep(10);
3061
3062         netif_tx_stop_all_queues(netdev);
3063
3064         ixgbe_irq_disable(adapter);
3065
3066         ixgbe_napi_disable_all(adapter);
3067
3068         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3069         del_timer_sync(&adapter->sfp_timer);
3070         del_timer_sync(&adapter->watchdog_timer);
3071         cancel_work_sync(&adapter->watchdog_task);
3072
3073         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3074             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3075                 cancel_work_sync(&adapter->fdir_reinit_task);
3076
3077         /* disable transmits in the hardware now that interrupts are off */
3078         for (i = 0; i < adapter->num_tx_queues; i++) {
3079                 j = adapter->tx_ring[i].reg_idx;
3080                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3081                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3082                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3083         }
3084         /* Disable the Tx DMA engine on 82599 */
3085         if (hw->mac.type == ixgbe_mac_82599EB)
3086                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3087                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3088                                  ~IXGBE_DMATXCTL_TE));
3089
3090         netif_carrier_off(netdev);
3091
3092         if (!pci_channel_offline(adapter->pdev))
3093                 ixgbe_reset(adapter);
3094         ixgbe_clean_all_tx_rings(adapter);
3095         ixgbe_clean_all_rx_rings(adapter);
3096
3097 #ifdef CONFIG_IXGBE_DCA
3098         /* since we reset the hardware DCA settings were cleared */
3099         ixgbe_setup_dca(adapter);
3100 #endif
3101 }
3102
3103 /**
3104  * ixgbe_poll - NAPI Rx polling callback
3105  * @napi: structure for representing this polling device
3106  * @budget: how many packets driver is allowed to clean
3107  *
3108  * This function is used for legacy and MSI, NAPI mode
3109  **/
3110 static int ixgbe_poll(struct napi_struct *napi, int budget)
3111 {
3112         struct ixgbe_q_vector *q_vector =
3113                                 container_of(napi, struct ixgbe_q_vector, napi);
3114         struct ixgbe_adapter *adapter = q_vector->adapter;
3115         int tx_clean_complete, work_done = 0;
3116
3117 #ifdef CONFIG_IXGBE_DCA
3118         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3119                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3120                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3121         }
3122 #endif
3123
3124         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3125         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3126
3127         if (!tx_clean_complete)
3128                 work_done = budget;
3129
3130         /* If budget not fully consumed, exit the polling mode */
3131         if (work_done < budget) {
3132                 napi_complete(napi);
3133                 if (adapter->rx_itr_setting & 1)
3134                         ixgbe_set_itr(adapter);
3135                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3136                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3137         }
3138         return work_done;
3139 }
3140
3141 /**
3142  * ixgbe_tx_timeout - Respond to a Tx Hang
3143  * @netdev: network interface device structure
3144  **/
3145 static void ixgbe_tx_timeout(struct net_device *netdev)
3146 {
3147         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3148
3149         /* Do the reset outside of interrupt context */
3150         schedule_work(&adapter->reset_task);
3151 }
3152
3153 static void ixgbe_reset_task(struct work_struct *work)
3154 {
3155         struct ixgbe_adapter *adapter;
3156         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3157
3158         /* If we're already down or resetting, just bail */
3159         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3160             test_bit(__IXGBE_RESETTING, &adapter->state))
3161                 return;
3162
3163         adapter->tx_timeout_count++;
3164
3165         ixgbe_reinit_locked(adapter);
3166 }
3167
3168 #ifdef CONFIG_IXGBE_DCB
3169 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3170 {
3171         bool ret = false;
3172         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3173
3174         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3175                 return ret;
3176
3177         f->mask = 0x7 << 3;
3178         adapter->num_rx_queues = f->indices;
3179         adapter->num_tx_queues = f->indices;
3180         ret = true;
3181
3182         return ret;
3183 }
3184 #endif
3185
3186 /**
3187  * ixgbe_set_rss_queues: Allocate queues for RSS
3188  * @adapter: board private structure to initialize
3189  *
3190  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3191  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3192  *
3193  **/
3194 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3195 {
3196         bool ret = false;
3197         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3198
3199         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3200                 f->mask = 0xF;
3201                 adapter->num_rx_queues = f->indices;
3202                 adapter->num_tx_queues = f->indices;
3203                 ret = true;
3204         } else {
3205                 ret = false;
3206         }
3207
3208         return ret;
3209 }
3210
3211 /**
3212  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3213  * @adapter: board private structure to initialize
3214  *
3215  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3216  * to the original CPU that initiated the Tx session.  This runs in addition
3217  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3218  * Rx load across CPUs using RSS.
3219  *
3220  **/
3221 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3222 {
3223         bool ret = false;
3224         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3225
3226         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3227         f_fdir->mask = 0;
3228
3229         /* Flow Director must have RSS enabled */
3230         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3231             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3232              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3233                 adapter->num_tx_queues = f_fdir->indices;
3234                 adapter->num_rx_queues = f_fdir->indices;
3235                 ret = true;
3236         } else {
3237                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3238                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3239         }
3240         return ret;
3241 }
3242
3243 #ifdef IXGBE_FCOE
3244 /**
3245  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3246  * @adapter: board private structure to initialize
3247  *
3248  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3249  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3250  * rx queues out of the max number of rx queues, instead, it is used as the
3251  * index of the first rx queue used by FCoE.
3252  *
3253  **/
3254 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3255 {
3256         bool ret = false;
3257         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3258
3259         f->indices = min((int)num_online_cpus(), f->indices);
3260         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3261                 adapter->num_rx_queues = 1;
3262                 adapter->num_tx_queues = 1;
3263 #ifdef CONFIG_IXGBE_DCB
3264                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3265                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3266                         ixgbe_set_dcb_queues(adapter);
3267                 }
3268 #endif
3269                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3270                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3271                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3272                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3273                                 ixgbe_set_fdir_queues(adapter);
3274                         else
3275                                 ixgbe_set_rss_queues(adapter);
3276                 }
3277                 /* adding FCoE rx rings to the end */
3278                 f->mask = adapter->num_rx_queues;
3279                 adapter->num_rx_queues += f->indices;
3280                 adapter->num_tx_queues += f->indices;
3281
3282                 ret = true;
3283         }
3284
3285         return ret;
3286 }
3287
3288 #endif /* IXGBE_FCOE */
3289 /*
3290  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3291  * @adapter: board private structure to initialize
3292  *
3293  * This is the top level queue allocation routine.  The order here is very
3294  * important, starting with the "most" number of features turned on at once,
3295  * and ending with the smallest set of features.  This way large combinations
3296  * can be allocated if they're turned on, and smaller combinations are the
3297  * fallthrough conditions.
3298  *
3299  **/
3300 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3301 {
3302 #ifdef IXGBE_FCOE
3303         if (ixgbe_set_fcoe_queues(adapter))
3304                 goto done;
3305
3306 #endif /* IXGBE_FCOE */
3307 #ifdef CONFIG_IXGBE_DCB
3308         if (ixgbe_set_dcb_queues(adapter))
3309                 goto done;
3310
3311 #endif
3312         if (ixgbe_set_fdir_queues(adapter))
3313                 goto done;
3314
3315         if (ixgbe_set_rss_queues(adapter))
3316                 goto done;
3317
3318         /* fallback to base case */
3319         adapter->num_rx_queues = 1;
3320         adapter->num_tx_queues = 1;
3321
3322 done:
3323         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3324         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3325 }
3326
3327 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3328                                        int vectors)
3329 {
3330         int err, vector_threshold;
3331
3332         /* We'll want at least 3 (vector_threshold):
3333          * 1) TxQ[0] Cleanup
3334          * 2) RxQ[0] Cleanup
3335          * 3) Other (Link Status Change, etc.)
3336          * 4) TCP Timer (optional)
3337          */
3338         vector_threshold = MIN_MSIX_COUNT;
3339
3340         /* The more we get, the more we will assign to Tx/Rx Cleanup
3341          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3342          * Right now, we simply care about how many we'll get; we'll
3343          * set them up later while requesting irq's.
3344          */
3345         while (vectors >= vector_threshold) {
3346                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3347                                       vectors);
3348                 if (!err) /* Success in acquiring all requested vectors. */
3349                         break;
3350                 else if (err < 0)
3351                         vectors = 0; /* Nasty failure, quit now */
3352                 else /* err == number of vectors we should try again with */
3353                         vectors = err;
3354         }
3355
3356         if (vectors < vector_threshold) {
3357                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3358                  * This just means we'll go with either a single MSI
3359                  * vector or fall back to legacy interrupts.
3360                  */
3361                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3362                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3363                 kfree(adapter->msix_entries);
3364                 adapter->msix_entries = NULL;
3365         } else {
3366                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3367                 /*
3368                  * Adjust for only the vectors we'll use, which is minimum
3369                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3370                  * vectors we were allocated.
3371                  */
3372                 adapter->num_msix_vectors = min(vectors,
3373                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3374         }
3375 }
3376
3377 /**
3378  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3379  * @adapter: board private structure to initialize
3380  *
3381  * Cache the descriptor ring offsets for RSS to the assigned rings.
3382  *
3383  **/
3384 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3385 {
3386         int i;
3387         bool ret = false;
3388
3389         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3390                 for (i = 0; i < adapter->num_rx_queues; i++)
3391                         adapter->rx_ring[i].reg_idx = i;
3392                 for (i = 0; i < adapter->num_tx_queues; i++)
3393                         adapter->tx_ring[i].reg_idx = i;
3394                 ret = true;
3395         } else {
3396                 ret = false;
3397         }
3398
3399         return ret;
3400 }
3401
3402 #ifdef CONFIG_IXGBE_DCB
3403 /**
3404  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3405  * @adapter: board private structure to initialize
3406  *
3407  * Cache the descriptor ring offsets for DCB to the assigned rings.
3408  *
3409  **/
3410 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3411 {
3412         int i;
3413         bool ret = false;
3414         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3415
3416         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3417                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3418                         /* the number of queues is assumed to be symmetric */
3419                         for (i = 0; i < dcb_i; i++) {
3420                                 adapter->rx_ring[i].reg_idx = i << 3;
3421                                 adapter->tx_ring[i].reg_idx = i << 2;
3422                         }
3423                         ret = true;
3424                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3425                         if (dcb_i == 8) {
3426                                 /*
3427                                  * Tx TC0 starts at: descriptor queue 0
3428                                  * Tx TC1 starts at: descriptor queue 32
3429                                  * Tx TC2 starts at: descriptor queue 64
3430                                  * Tx TC3 starts at: descriptor queue 80
3431                                  * Tx TC4 starts at: descriptor queue 96
3432                                  * Tx TC5 starts at: descriptor queue 104
3433                                  * Tx TC6 starts at: descriptor queue 112
3434                                  * Tx TC7 starts at: descriptor queue 120
3435                                  *
3436                                  * Rx TC0-TC7 are offset by 16 queues each
3437                                  */
3438                                 for (i = 0; i < 3; i++) {
3439                                         adapter->tx_ring[i].reg_idx = i << 5;
3440                                         adapter->rx_ring[i].reg_idx = i << 4;
3441                                 }
3442                                 for ( ; i < 5; i++) {
3443                                         adapter->tx_ring[i].reg_idx =
3444                                                                  ((i + 2) << 4);
3445                                         adapter->rx_ring[i].reg_idx = i << 4;
3446                                 }
3447                                 for ( ; i < dcb_i; i++) {
3448                                         adapter->tx_ring[i].reg_idx =
3449                                                                  ((i + 8) << 3);
3450                                         adapter->rx_ring[i].reg_idx = i << 4;
3451                                 }
3452
3453                                 ret = true;
3454                         } else if (dcb_i == 4) {
3455                                 /*
3456                                  * Tx TC0 starts at: descriptor queue 0
3457                                  * Tx TC1 starts at: descriptor queue 64
3458                                  * Tx TC2 starts at: descriptor queue 96
3459                                  * Tx TC3 starts at: descriptor queue 112
3460                                  *
3461                                  * Rx TC0-TC3 are offset by 32 queues each
3462                                  */
3463                                 adapter->tx_ring[0].reg_idx = 0;
3464                                 adapter->tx_ring[1].reg_idx = 64;
3465                                 adapter->tx_ring[2].reg_idx = 96;
3466                                 adapter->tx_ring[3].reg_idx = 112;
3467                                 for (i = 0 ; i < dcb_i; i++)
3468                                         adapter->rx_ring[i].reg_idx = i << 5;
3469
3470                                 ret = true;
3471                         } else {
3472                                 ret = false;
3473                         }
3474                 } else {
3475                         ret = false;
3476                 }
3477         } else {
3478                 ret = false;
3479         }
3480
3481         return ret;
3482 }
3483 #endif
3484
3485 /**
3486  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3487  * @adapter: board private structure to initialize
3488  *
3489  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3490  *
3491  **/
3492 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3493 {
3494         int i;
3495         bool ret = false;
3496
3497         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3498             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3499              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3500                 for (i = 0; i < adapter->num_rx_queues; i++)
3501                         adapter->rx_ring[i].reg_idx = i;
3502                 for (i = 0; i < adapter->num_tx_queues; i++)
3503                         adapter->tx_ring[i].reg_idx = i;
3504                 ret = true;
3505         }
3506
3507         return ret;
3508 }
3509
3510 #ifdef IXGBE_FCOE
3511 /**
3512  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3513  * @adapter: board private structure to initialize
3514  *
3515  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3516  *
3517  */
3518 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3519 {
3520         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3521         bool ret = false;
3522         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3523
3524         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3525 #ifdef CONFIG_IXGBE_DCB
3526                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3527                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3528
3529                         ixgbe_cache_ring_dcb(adapter);
3530                         /* find out queues in TC for FCoE */
3531                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3532                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3533                         /*
3534                          * In 82599, the number of Tx queues for each traffic
3535                          * class for both 8-TC and 4-TC modes are:
3536                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3537                          * 8 TCs:  32  32  16  16   8   8   8   8
3538                          * 4 TCs:  64  64  32  32
3539                          * We have max 8 queues for FCoE, where 8 the is
3540                          * FCoE redirection table size. If TC for FCoE is
3541                          * less than or equal to TC3, we have enough queues
3542                          * to add max of 8 queues for FCoE, so we start FCoE
3543                          * tx descriptor from the next one, i.e., reg_idx + 1.
3544                          * If TC for FCoE is above TC3, implying 8 TC mode,
3545                          * and we need 8 for FCoE, we have to take all queues
3546                          * in that traffic class for FCoE.
3547                          */
3548                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3549                                 fcoe_tx_i--;
3550                 }
3551 #endif /* CONFIG_IXGBE_DCB */
3552                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3553                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3554                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3555                                 ixgbe_cache_ring_fdir(adapter);
3556                         else
3557                                 ixgbe_cache_ring_rss(adapter);
3558
3559                         fcoe_rx_i = f->mask;
3560                         fcoe_tx_i = f->mask;
3561                 }
3562                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3563                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3564                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3565                 }
3566                 ret = true;
3567         }
3568         return ret;
3569 }
3570
3571 #endif /* IXGBE_FCOE */
3572 /**
3573  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3574  * @adapter: board private structure to initialize
3575  *
3576  * Once we know the feature-set enabled for the device, we'll cache
3577  * the register offset the descriptor ring is assigned to.
3578  *
3579  * Note, the order the various feature calls is important.  It must start with
3580  * the "most" features enabled at the same time, then trickle down to the
3581  * least amount of features turned on at once.
3582  **/
3583 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3584 {
3585         /* start with default case */
3586         adapter->rx_ring[0].reg_idx = 0;
3587         adapter->tx_ring[0].reg_idx = 0;
3588
3589 #ifdef IXGBE_FCOE
3590         if (ixgbe_cache_ring_fcoe(adapter))
3591                 return;
3592
3593 #endif /* IXGBE_FCOE */
3594 #ifdef CONFIG_IXGBE_DCB
3595         if (ixgbe_cache_ring_dcb(adapter))
3596                 return;
3597
3598 #endif
3599         if (ixgbe_cache_ring_fdir(adapter))
3600                 return;
3601
3602         if (ixgbe_cache_ring_rss(adapter))
3603                 return;
3604 }
3605
3606 /**
3607  * ixgbe_alloc_queues - Allocate memory for all rings
3608  * @adapter: board private structure to initialize
3609  *
3610  * We allocate one ring per queue at run-time since we don't know the
3611  * number of queues at compile-time.  The polling_netdev array is
3612  * intended for Multiqueue, but should work fine with a single queue.
3613  **/
3614 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3615 {
3616         int i;
3617
3618         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3619                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3620         if (!adapter->tx_ring)
3621                 goto err_tx_ring_allocation;
3622
3623         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3624                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3625         if (!adapter->rx_ring)
3626                 goto err_rx_ring_allocation;
3627
3628         for (i = 0; i < adapter->num_tx_queues; i++) {
3629                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3630                 adapter->tx_ring[i].queue_index = i;
3631         }
3632
3633         for (i = 0; i < adapter->num_rx_queues; i++) {
3634                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3635                 adapter->rx_ring[i].queue_index = i;
3636         }
3637
3638         ixgbe_cache_ring_register(adapter);
3639
3640         return 0;
3641
3642 err_rx_ring_allocation:
3643         kfree(adapter->tx_ring);
3644 err_tx_ring_allocation:
3645         return -ENOMEM;
3646 }
3647
3648 /**
3649  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3650  * @adapter: board private structure to initialize
3651  *
3652  * Attempt to configure the interrupts using the best available
3653  * capabilities of the hardware and the kernel.
3654  **/
3655 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3656 {
3657         struct ixgbe_hw *hw = &adapter->hw;
3658         int err = 0;
3659         int vector, v_budget;
3660
3661         /*
3662          * It's easy to be greedy for MSI-X vectors, but it really
3663          * doesn't do us much good if we have a lot more vectors
3664          * than CPU's.  So let's be conservative and only ask for
3665          * (roughly) the same number of vectors as there are CPU's.
3666          */
3667         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3668                        (int)num_online_cpus()) + NON_Q_VECTORS;
3669
3670         /*
3671          * At the same time, hardware can only support a maximum of
3672          * hw.mac->max_msix_vectors vectors.  With features
3673          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3674          * descriptor queues supported by our device.  Thus, we cap it off in
3675          * those rare cases where the cpu count also exceeds our vector limit.
3676          */
3677         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3678
3679         /* A failure in MSI-X entry allocation isn't fatal, but it does
3680          * mean we disable MSI-X capabilities of the adapter. */
3681         adapter->msix_entries = kcalloc(v_budget,
3682                                         sizeof(struct msix_entry), GFP_KERNEL);
3683         if (adapter->msix_entries) {
3684                 for (vector = 0; vector < v_budget; vector++)
3685                         adapter->msix_entries[vector].entry = vector;
3686
3687                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3688
3689                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3690                         goto out;
3691         }
3692
3693         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3694         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3695         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3696         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3697         adapter->atr_sample_rate = 0;
3698         ixgbe_set_num_queues(adapter);
3699
3700         err = pci_enable_msi(adapter->pdev);
3701         if (!err) {
3702                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3703         } else {
3704                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3705                         "falling back to legacy.  Error: %d\n", err);
3706                 /* reset err */
3707                 err = 0;
3708         }
3709
3710 out:
3711         return err;
3712 }
3713
3714 /**
3715  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3716  * @adapter: board private structure to initialize
3717  *
3718  * We allocate one q_vector per queue interrupt.  If allocation fails we
3719  * return -ENOMEM.
3720  **/
3721 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3722 {
3723         int q_idx, num_q_vectors;
3724         struct ixgbe_q_vector *q_vector;
3725         int napi_vectors;
3726         int (*poll)(struct napi_struct *, int);
3727
3728         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3729                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3730                 napi_vectors = adapter->num_rx_queues;
3731                 poll = &ixgbe_clean_rxtx_many;
3732         } else {
3733                 num_q_vectors = 1;
3734                 napi_vectors = 1;
3735                 poll = &ixgbe_poll;
3736         }
3737
3738         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3739                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3740                 if (!q_vector)
3741                         goto err_out;
3742                 q_vector->adapter = adapter;
3743                 if (q_vector->txr_count && !q_vector->rxr_count)
3744                         q_vector->eitr = adapter->tx_eitr_param;
3745                 else
3746                         q_vector->eitr = adapter->rx_eitr_param;
3747                 q_vector->v_idx = q_idx;
3748                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3749                 adapter->q_vector[q_idx] = q_vector;
3750         }
3751
3752         return 0;
3753
3754 err_out:
3755         while (q_idx) {
3756                 q_idx--;
3757                 q_vector = adapter->q_vector[q_idx];
3758                 netif_napi_del(&q_vector->napi);
3759                 kfree(q_vector);
3760                 adapter->q_vector[q_idx] = NULL;
3761         }
3762         return -ENOMEM;
3763 }
3764
3765 /**
3766  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3767  * @adapter: board private structure to initialize
3768  *
3769  * This function frees the memory allocated to the q_vectors.  In addition if
3770  * NAPI is enabled it will delete any references to the NAPI struct prior
3771  * to freeing the q_vector.
3772  **/
3773 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3774 {
3775         int q_idx, num_q_vectors;
3776
3777         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3778                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3779         else
3780                 num_q_vectors = 1;
3781
3782         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3783                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3784                 adapter->q_vector[q_idx] = NULL;
3785                 netif_napi_del(&q_vector->napi);
3786                 kfree(q_vector);
3787         }
3788 }
3789
3790 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3791 {
3792         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3793                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3794                 pci_disable_msix(adapter->pdev);
3795                 kfree(adapter->msix_entries);
3796                 adapter->msix_entries = NULL;
3797         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3798                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3799                 pci_disable_msi(adapter->pdev);
3800         }
3801         return;
3802 }
3803
3804 /**
3805  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3806  * @adapter: board private structure to initialize
3807  *
3808  * We determine which interrupt scheme to use based on...
3809  * - Kernel support (MSI, MSI-X)
3810  *   - which can be user-defined (via MODULE_PARAM)
3811  * - Hardware queue count (num_*_queues)
3812  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3813  **/
3814 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3815 {
3816         int err;
3817
3818         /* Number of supported queues */
3819         ixgbe_set_num_queues(adapter);
3820
3821         err = ixgbe_set_interrupt_capability(adapter);
3822         if (err) {
3823                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3824                 goto err_set_interrupt;
3825         }
3826
3827         err = ixgbe_alloc_q_vectors(adapter);
3828         if (err) {
3829                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3830                         "vectors\n");
3831                 goto err_alloc_q_vectors;
3832         }
3833
3834         err = ixgbe_alloc_queues(adapter);
3835         if (err) {
3836                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3837                 goto err_alloc_queues;
3838         }
3839
3840         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3841                 "Tx Queue count = %u\n",
3842                 (adapter->num_rx_queues > 1) ? "Enabled" :
3843                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3844
3845         set_bit(__IXGBE_DOWN, &adapter->state);
3846
3847         return 0;
3848
3849 err_alloc_queues:
3850         ixgbe_free_q_vectors(adapter);
3851 err_alloc_q_vectors:
3852         ixgbe_reset_interrupt_capability(adapter);
3853 err_set_interrupt:
3854         return err;
3855 }
3856
3857 /**
3858  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3859  * @adapter: board private structure to clear interrupt scheme on
3860  *
3861  * We go through and clear interrupt specific resources and reset the structure
3862  * to pre-load conditions
3863  **/
3864 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3865 {
3866         kfree(adapter->tx_ring);
3867         kfree(adapter->rx_ring);
3868         adapter->tx_ring = NULL;
3869         adapter->rx_ring = NULL;
3870
3871         ixgbe_free_q_vectors(adapter);
3872         ixgbe_reset_interrupt_capability(adapter);
3873 }
3874
3875 /**
3876  * ixgbe_sfp_timer - worker thread to find a missing module
3877  * @data: pointer to our adapter struct
3878  **/
3879 static void ixgbe_sfp_timer(unsigned long data)
3880 {
3881         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3882
3883         /*
3884          * Do the sfp_timer outside of interrupt context due to the
3885          * delays that sfp+ detection requires
3886          */
3887         schedule_work(&adapter->sfp_task);
3888 }
3889
3890 /**
3891  * ixgbe_sfp_task - worker thread to find a missing module
3892  * @work: pointer to work_struct containing our data
3893  **/
3894 static void ixgbe_sfp_task(struct work_struct *work)
3895 {
3896         struct ixgbe_adapter *adapter = container_of(work,
3897                                                      struct ixgbe_adapter,
3898                                                      sfp_task);
3899         struct ixgbe_hw *hw = &adapter->hw;
3900
3901         if ((hw->phy.type == ixgbe_phy_nl) &&
3902             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3903                 s32 ret = hw->phy.ops.identify_sfp(hw);
3904                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3905                         goto reschedule;
3906                 ret = hw->phy.ops.reset(hw);
3907                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3908                         dev_err(&adapter->pdev->dev, "failed to initialize "
3909                                 "because an unsupported SFP+ module type "
3910                                 "was detected.\n"
3911                                 "Reload the driver after installing a "
3912                                 "supported module.\n");
3913                         unregister_netdev(adapter->netdev);
3914                 } else {
3915                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3916                                 hw->phy.sfp_type);
3917                 }
3918                 /* don't need this routine any more */
3919                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3920         }
3921         return;
3922 reschedule:
3923         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3924                 mod_timer(&adapter->sfp_timer,
3925                           round_jiffies(jiffies + (2 * HZ)));
3926 }
3927
3928 /**
3929  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3930  * @adapter: board private structure to initialize
3931  *
3932  * ixgbe_sw_init initializes the Adapter private data structure.
3933  * Fields are initialized based on PCI device information and
3934  * OS network device settings (MTU size).
3935  **/
3936 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3937 {
3938         struct ixgbe_hw *hw = &adapter->hw;
3939         struct pci_dev *pdev = adapter->pdev;
3940         unsigned int rss;
3941 #ifdef CONFIG_IXGBE_DCB
3942         int j;
3943         struct tc_configuration *tc;
3944 #endif
3945
3946         /* PCI config space info */
3947
3948         hw->vendor_id = pdev->vendor;
3949         hw->device_id = pdev->device;
3950         hw->revision_id = pdev->revision;
3951         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3952         hw->subsystem_device_id = pdev->subsystem_device;
3953
3954         /* Set capability flags */
3955         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3956         adapter->ring_feature[RING_F_RSS].indices = rss;
3957         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3958         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3959         if (hw->mac.type == ixgbe_mac_82598EB) {
3960                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3961                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3962                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3963         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3964                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3965                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3966                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3967                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3968                 adapter->ring_feature[RING_F_FDIR].indices =
3969                                                          IXGBE_MAX_FDIR_INDICES;
3970                 adapter->atr_sample_rate = 20;
3971                 adapter->fdir_pballoc = 0;
3972 #ifdef IXGBE_FCOE
3973                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3974                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3975                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3976 #ifdef CONFIG_IXGBE_DCB
3977                 /* Default traffic class to use for FCoE */
3978                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3979 #endif
3980 #endif /* IXGBE_FCOE */
3981         }
3982
3983 #ifdef CONFIG_IXGBE_DCB
3984         /* Configure DCB traffic classes */
3985         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3986                 tc = &adapter->dcb_cfg.tc_config[j];
3987                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3988                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3989                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3990                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3991                 tc->dcb_pfc = pfc_disabled;
3992         }
3993         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3994         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3995         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3996         adapter->dcb_cfg.pfc_mode_enable = false;
3997         adapter->dcb_cfg.round_robin_enable = false;
3998         adapter->dcb_set_bitmap = 0x00;
3999         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4000                            adapter->ring_feature[RING_F_DCB].indices);
4001
4002 #endif
4003
4004         /* default flow control settings */
4005         hw->fc.requested_mode = ixgbe_fc_full;
4006         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4007 #ifdef CONFIG_DCB
4008         adapter->last_lfc_mode = hw->fc.current_mode;
4009 #endif
4010         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4011         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4012         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4013         hw->fc.send_xon = true;
4014         hw->fc.disable_fc_autoneg = false;
4015
4016         /* enable itr by default in dynamic mode */
4017         adapter->rx_itr_setting = 1;
4018         adapter->rx_eitr_param = 20000;
4019         adapter->tx_itr_setting = 1;
4020         adapter->tx_eitr_param = 10000;
4021
4022         /* set defaults for eitr in MegaBytes */
4023         adapter->eitr_low = 10;
4024         adapter->eitr_high = 20;
4025
4026         /* set default ring sizes */
4027         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4028         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4029
4030         /* initialize eeprom parameters */
4031         if (ixgbe_init_eeprom_params_generic(hw)) {
4032                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4033                 return -EIO;
4034         }
4035
4036         /* enable rx csum by default */
4037         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4038
4039         set_bit(__IXGBE_DOWN, &adapter->state);
4040
4041         return 0;
4042 }
4043
4044 /**
4045  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4046  * @adapter: board private structure
4047  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4048  *
4049  * Return 0 on success, negative on failure
4050  **/
4051 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4052                              struct ixgbe_ring *tx_ring)
4053 {
4054         struct pci_dev *pdev = adapter->pdev;
4055         int size;
4056
4057         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4058         tx_ring->tx_buffer_info = vmalloc(size);
4059         if (!tx_ring->tx_buffer_info)
4060                 goto err;
4061         memset(tx_ring->tx_buffer_info, 0, size);
4062
4063         /* round up to nearest 4K */
4064         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4065         tx_ring->size = ALIGN(tx_ring->size, 4096);
4066
4067         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4068                                              &tx_ring->dma);
4069         if (!tx_ring->desc)
4070                 goto err;
4071
4072         tx_ring->next_to_use = 0;
4073         tx_ring->next_to_clean = 0;
4074         tx_ring->work_limit = tx_ring->count;
4075         return 0;
4076
4077 err:
4078         vfree(tx_ring->tx_buffer_info);
4079         tx_ring->tx_buffer_info = NULL;
4080         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4081                             "descriptor ring\n");
4082         return -ENOMEM;
4083 }
4084
4085 /**
4086  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4087  * @adapter: board private structure
4088  *
4089  * If this function returns with an error, then it's possible one or
4090  * more of the rings is populated (while the rest are not).  It is the
4091  * callers duty to clean those orphaned rings.
4092  *
4093  * Return 0 on success, negative on failure
4094  **/
4095 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4096 {
4097         int i, err = 0;
4098
4099         for (i = 0; i < adapter->num_tx_queues; i++) {
4100                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4101                 if (!err)
4102                         continue;
4103                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4104                 break;
4105         }
4106
4107         return err;
4108 }
4109
4110 /**
4111  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4112  * @adapter: board private structure
4113  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4114  *
4115  * Returns 0 on success, negative on failure
4116  **/
4117 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4118                              struct ixgbe_ring *rx_ring)
4119 {
4120         struct pci_dev *pdev = adapter->pdev;
4121         int size;
4122
4123         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4124         rx_ring->rx_buffer_info = vmalloc(size);
4125         if (!rx_ring->rx_buffer_info) {
4126                 DPRINTK(PROBE, ERR,
4127                         "vmalloc allocation failed for the rx desc ring\n");
4128                 goto alloc_failed;
4129         }
4130         memset(rx_ring->rx_buffer_info, 0, size);
4131
4132         /* Round up to nearest 4K */
4133         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4134         rx_ring->size = ALIGN(rx_ring->size, 4096);
4135
4136         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4137
4138         if (!rx_ring->desc) {
4139                 DPRINTK(PROBE, ERR,
4140                         "Memory allocation failed for the rx desc ring\n");
4141                 vfree(rx_ring->rx_buffer_info);
4142                 goto alloc_failed;
4143         }
4144
4145         rx_ring->next_to_clean = 0;
4146         rx_ring->next_to_use = 0;
4147
4148         return 0;
4149
4150 alloc_failed:
4151         return -ENOMEM;
4152 }
4153
4154 /**
4155  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4156  * @adapter: board private structure
4157  *
4158  * If this function returns with an error, then it's possible one or
4159  * more of the rings is populated (while the rest are not).  It is the
4160  * callers duty to clean those orphaned rings.
4161  *
4162  * Return 0 on success, negative on failure
4163  **/
4164
4165 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4166 {
4167         int i, err = 0;
4168
4169         for (i = 0; i < adapter->num_rx_queues; i++) {
4170                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4171                 if (!err)
4172                         continue;
4173                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4174                 break;
4175         }
4176
4177         return err;
4178 }
4179
4180 /**
4181  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4182  * @adapter: board private structure
4183  * @tx_ring: Tx descriptor ring for a specific queue
4184  *
4185  * Free all transmit software resources
4186  **/
4187 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4188                              struct ixgbe_ring *tx_ring)
4189 {
4190         struct pci_dev *pdev = adapter->pdev;
4191
4192         ixgbe_clean_tx_ring(adapter, tx_ring);
4193
4194         vfree(tx_ring->tx_buffer_info);
4195         tx_ring->tx_buffer_info = NULL;
4196
4197         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4198
4199         tx_ring->desc = NULL;
4200 }
4201
4202 /**
4203  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4204  * @adapter: board private structure
4205  *
4206  * Free all transmit software resources
4207  **/
4208 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4209 {
4210         int i;
4211
4212         for (i = 0; i < adapter->num_tx_queues; i++)
4213                 if (adapter->tx_ring[i].desc)
4214                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4215 }
4216
4217 /**
4218  * ixgbe_free_rx_resources - Free Rx Resources
4219  * @adapter: board private structure
4220  * @rx_ring: ring to clean the resources from
4221  *
4222  * Free all receive software resources
4223  **/
4224 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4225                              struct ixgbe_ring *rx_ring)
4226 {
4227         struct pci_dev *pdev = adapter->pdev;
4228
4229         ixgbe_clean_rx_ring(adapter, rx_ring);
4230
4231         vfree(rx_ring->rx_buffer_info);
4232         rx_ring->rx_buffer_info = NULL;
4233
4234         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4235
4236         rx_ring->desc = NULL;
4237 }
4238
4239 /**
4240  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4241  * @adapter: board private structure
4242  *
4243  * Free all receive software resources
4244  **/
4245 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4246 {
4247         int i;
4248
4249         for (i = 0; i < adapter->num_rx_queues; i++)
4250                 if (adapter->rx_ring[i].desc)
4251                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4252 }
4253
4254 /**
4255  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4256  * @netdev: network interface device structure
4257  * @new_mtu: new value for maximum frame size
4258  *
4259  * Returns 0 on success, negative on failure
4260  **/
4261 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4262 {
4263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4264         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4265
4266         /* MTU < 68 is an error and causes problems on some kernels */
4267         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4268                 return -EINVAL;
4269
4270         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4271                 netdev->mtu, new_mtu);
4272         /* must set new MTU before calling down or up */
4273         netdev->mtu = new_mtu;
4274
4275         if (netif_running(netdev))
4276                 ixgbe_reinit_locked(adapter);
4277
4278         return 0;
4279 }
4280
4281 /**
4282  * ixgbe_open - Called when a network interface is made active
4283  * @netdev: network interface device structure
4284  *
4285  * Returns 0 on success, negative value on failure
4286  *
4287  * The open entry point is called when a network interface is made
4288  * active by the system (IFF_UP).  At this point all resources needed
4289  * for transmit and receive operations are allocated, the interrupt
4290  * handler is registered with the OS, the watchdog timer is started,
4291  * and the stack is notified that the interface is ready.
4292  **/
4293 static int ixgbe_open(struct net_device *netdev)
4294 {
4295         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4296         int err;
4297
4298         /* disallow open during test */
4299         if (test_bit(__IXGBE_TESTING, &adapter->state))
4300                 return -EBUSY;
4301
4302         netif_carrier_off(netdev);
4303
4304         /* allocate transmit descriptors */
4305         err = ixgbe_setup_all_tx_resources(adapter);
4306         if (err)
4307                 goto err_setup_tx;
4308
4309         /* allocate receive descriptors */
4310         err = ixgbe_setup_all_rx_resources(adapter);
4311         if (err)
4312                 goto err_setup_rx;
4313
4314         ixgbe_configure(adapter);
4315
4316         err = ixgbe_request_irq(adapter);
4317         if (err)
4318                 goto err_req_irq;
4319
4320         err = ixgbe_up_complete(adapter);
4321         if (err)
4322                 goto err_up;
4323
4324         netif_tx_start_all_queues(netdev);
4325
4326         return 0;
4327
4328 err_up:
4329         ixgbe_release_hw_control(adapter);
4330         ixgbe_free_irq(adapter);
4331 err_req_irq:
4332 err_setup_rx:
4333         ixgbe_free_all_rx_resources(adapter);
4334 err_setup_tx:
4335         ixgbe_free_all_tx_resources(adapter);
4336         ixgbe_reset(adapter);
4337
4338         return err;
4339 }
4340
4341 /**
4342  * ixgbe_close - Disables a network interface
4343  * @netdev: network interface device structure
4344  *
4345  * Returns 0, this is not allowed to fail
4346  *
4347  * The close entry point is called when an interface is de-activated
4348  * by the OS.  The hardware is still under the drivers control, but
4349  * needs to be disabled.  A global MAC reset is issued to stop the
4350  * hardware, and all transmit and receive resources are freed.
4351  **/
4352 static int ixgbe_close(struct net_device *netdev)
4353 {
4354         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4355
4356         ixgbe_down(adapter);
4357         ixgbe_free_irq(adapter);
4358
4359         ixgbe_free_all_tx_resources(adapter);
4360         ixgbe_free_all_rx_resources(adapter);
4361
4362         ixgbe_release_hw_control(adapter);
4363
4364         return 0;
4365 }
4366
4367 #ifdef CONFIG_PM
4368 static int ixgbe_resume(struct pci_dev *pdev)
4369 {
4370         struct net_device *netdev = pci_get_drvdata(pdev);
4371         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4372         u32 err;
4373
4374         pci_set_power_state(pdev, PCI_D0);
4375         pci_restore_state(pdev);
4376         /*
4377          * pci_restore_state clears dev->state_saved so call
4378          * pci_save_state to restore it.
4379          */
4380         pci_save_state(pdev);
4381
4382         err = pci_enable_device_mem(pdev);
4383         if (err) {
4384                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4385                                 "suspend\n");
4386                 return err;
4387         }
4388         pci_set_master(pdev);
4389
4390         pci_wake_from_d3(pdev, false);
4391
4392         err = ixgbe_init_interrupt_scheme(adapter);
4393         if (err) {
4394                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4395                                 "device\n");
4396                 return err;
4397         }
4398
4399         ixgbe_reset(adapter);
4400
4401         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4402
4403         if (netif_running(netdev)) {
4404                 err = ixgbe_open(adapter->netdev);
4405                 if (err)
4406                         return err;
4407         }
4408
4409         netif_device_attach(netdev);
4410
4411         return 0;
4412 }
4413 #endif /* CONFIG_PM */
4414
4415 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4416 {
4417         struct net_device *netdev = pci_get_drvdata(pdev);
4418         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4419         struct ixgbe_hw *hw = &adapter->hw;
4420         u32 ctrl, fctrl;
4421         u32 wufc = adapter->wol;
4422 #ifdef CONFIG_PM
4423         int retval = 0;
4424 #endif
4425
4426         netif_device_detach(netdev);
4427
4428         if (netif_running(netdev)) {
4429                 ixgbe_down(adapter);
4430                 ixgbe_free_irq(adapter);
4431                 ixgbe_free_all_tx_resources(adapter);
4432                 ixgbe_free_all_rx_resources(adapter);
4433         }
4434         ixgbe_clear_interrupt_scheme(adapter);
4435
4436 #ifdef CONFIG_PM
4437         retval = pci_save_state(pdev);
4438         if (retval)
4439                 return retval;
4440
4441 #endif
4442         if (wufc) {
4443                 ixgbe_set_rx_mode(netdev);
4444
4445                 /* turn on all-multi mode if wake on multicast is enabled */
4446                 if (wufc & IXGBE_WUFC_MC) {
4447                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4448                         fctrl |= IXGBE_FCTRL_MPE;
4449                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4450                 }
4451
4452                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4453                 ctrl |= IXGBE_CTRL_GIO_DIS;
4454                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4455
4456                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4457         } else {
4458                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4459                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4460         }
4461
4462         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4463                 pci_wake_from_d3(pdev, true);
4464         else
4465                 pci_wake_from_d3(pdev, false);
4466
4467         *enable_wake = !!wufc;
4468
4469         ixgbe_release_hw_control(adapter);
4470
4471         pci_disable_device(pdev);
4472
4473         return 0;
4474 }
4475
4476 #ifdef CONFIG_PM
4477 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4478 {
4479         int retval;
4480         bool wake;
4481
4482         retval = __ixgbe_shutdown(pdev, &wake);
4483         if (retval)
4484                 return retval;
4485
4486         if (wake) {
4487                 pci_prepare_to_sleep(pdev);
4488         } else {
4489                 pci_wake_from_d3(pdev, false);
4490                 pci_set_power_state(pdev, PCI_D3hot);
4491         }
4492
4493         return 0;
4494 }
4495 #endif /* CONFIG_PM */
4496
4497 static void ixgbe_shutdown(struct pci_dev *pdev)
4498 {
4499         bool wake;
4500
4501         __ixgbe_shutdown(pdev, &wake);
4502
4503         if (system_state == SYSTEM_POWER_OFF) {
4504                 pci_wake_from_d3(pdev, wake);
4505                 pci_set_power_state(pdev, PCI_D3hot);
4506         }
4507 }
4508
4509 /**
4510  * ixgbe_update_stats - Update the board statistics counters.
4511  * @adapter: board private structure
4512  **/
4513 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4514 {
4515         struct net_device *netdev = adapter->netdev;
4516         struct ixgbe_hw *hw = &adapter->hw;
4517         u64 total_mpc = 0;
4518         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4519         u64 non_eop_descs = 0, restart_queue = 0;
4520
4521         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4522                 u64 rsc_count = 0;
4523                 u64 rsc_flush = 0;
4524                 for (i = 0; i < 16; i++)
4525                         adapter->hw_rx_no_dma_resources +=
4526                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4527                 for (i = 0; i < adapter->num_rx_queues; i++) {
4528                         rsc_count += adapter->rx_ring[i].rsc_count;
4529                         rsc_flush += adapter->rx_ring[i].rsc_flush;
4530                 }
4531                 adapter->rsc_total_count = rsc_count;
4532                 adapter->rsc_total_flush = rsc_flush;
4533         }
4534
4535         /* gather some stats to the adapter struct that are per queue */
4536         for (i = 0; i < adapter->num_tx_queues; i++)
4537                 restart_queue += adapter->tx_ring[i].restart_queue;
4538         adapter->restart_queue = restart_queue;
4539
4540         for (i = 0; i < adapter->num_rx_queues; i++)
4541                 non_eop_descs += adapter->rx_ring[i].non_eop_descs;
4542         adapter->non_eop_descs = non_eop_descs;
4543
4544         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4545         for (i = 0; i < 8; i++) {
4546                 /* for packet buffers not used, the register should read 0 */
4547                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4548                 missed_rx += mpc;
4549                 adapter->stats.mpc[i] += mpc;
4550                 total_mpc += adapter->stats.mpc[i];
4551                 if (hw->mac.type == ixgbe_mac_82598EB)
4552                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4553                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4554                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4555                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4556                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4557                 if (hw->mac.type == ixgbe_mac_82599EB) {
4558                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4559                                                             IXGBE_PXONRXCNT(i));
4560                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4561                                                            IXGBE_PXOFFRXCNT(i));
4562                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4563                 } else {
4564                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4565                                                               IXGBE_PXONRXC(i));
4566                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4567                                                              IXGBE_PXOFFRXC(i));
4568                 }
4569                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4570                                                             IXGBE_PXONTXC(i));
4571                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4572                                                              IXGBE_PXOFFTXC(i));
4573         }
4574         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4575         /* work around hardware counting issue */
4576         adapter->stats.gprc -= missed_rx;
4577
4578         /* 82598 hardware only has a 32 bit counter in the high register */
4579         if (hw->mac.type == ixgbe_mac_82599EB) {
4580                 u64 tmp;
4581                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4582                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4583                 adapter->stats.gorc += (tmp << 32);
4584                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4585                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4586                 adapter->stats.gotc += (tmp << 32);
4587                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4588                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4589                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4590                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4591                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4592                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4593 #ifdef IXGBE_FCOE
4594                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4595                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4596                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4597                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4598                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4599                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4600 #endif /* IXGBE_FCOE */
4601         } else {
4602                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4603                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4604                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4605                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4606                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4607         }
4608         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4609         adapter->stats.bprc += bprc;
4610         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4611         if (hw->mac.type == ixgbe_mac_82598EB)
4612                 adapter->stats.mprc -= bprc;
4613         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4614         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4615         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4616         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4617         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4618         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4619         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4620         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4621         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4622         adapter->stats.lxontxc += lxon;
4623         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4624         adapter->stats.lxofftxc += lxoff;
4625         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4626         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4627         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4628         /*
4629          * 82598 errata - tx of flow control packets is included in tx counters
4630          */
4631         xon_off_tot = lxon + lxoff;
4632         adapter->stats.gptc -= xon_off_tot;
4633         adapter->stats.mptc -= xon_off_tot;
4634         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4635         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4636         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4637         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4638         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4639         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4640         adapter->stats.ptc64 -= xon_off_tot;
4641         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4642         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4643         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4644         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4645         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4646         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4647
4648         /* Fill out the OS statistics structure */
4649         netdev->stats.multicast = adapter->stats.mprc;
4650
4651         /* Rx Errors */
4652         netdev->stats.rx_errors = adapter->stats.crcerrs +
4653                                        adapter->stats.rlec;
4654         netdev->stats.rx_dropped = 0;
4655         netdev->stats.rx_length_errors = adapter->stats.rlec;
4656         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4657         netdev->stats.rx_missed_errors = total_mpc;
4658 }
4659
4660 /**
4661  * ixgbe_watchdog - Timer Call-back
4662  * @data: pointer to adapter cast into an unsigned long
4663  **/
4664 static void ixgbe_watchdog(unsigned long data)
4665 {
4666         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4667         struct ixgbe_hw *hw = &adapter->hw;
4668         u64 eics = 0;
4669         int i;
4670
4671         /*
4672          *  Do the watchdog outside of interrupt context due to the lovely
4673          * delays that some of the newer hardware requires
4674          */
4675
4676         if (test_bit(__IXGBE_DOWN, &adapter->state))
4677                 goto watchdog_short_circuit;
4678
4679         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4680                 /*
4681                  * for legacy and MSI interrupts don't set any bits
4682                  * that are enabled for EIAM, because this operation
4683                  * would set *both* EIMS and EICS for any bit in EIAM
4684                  */
4685                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4686                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4687                 goto watchdog_reschedule;
4688         }
4689
4690         /* get one bit for every active tx/rx interrupt vector */
4691         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4692                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4693                 if (qv->rxr_count || qv->txr_count)
4694                         eics |= ((u64)1 << i);
4695         }
4696
4697         /* Cause software interrupt to ensure rx rings are cleaned */
4698         ixgbe_irq_rearm_queues(adapter, eics);
4699
4700 watchdog_reschedule:
4701         /* Reset the timer */
4702         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4703
4704 watchdog_short_circuit:
4705         schedule_work(&adapter->watchdog_task);
4706 }
4707
4708 /**
4709  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4710  * @work: pointer to work_struct containing our data
4711  **/
4712 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4713 {
4714         struct ixgbe_adapter *adapter = container_of(work,
4715                                                      struct ixgbe_adapter,
4716                                                      multispeed_fiber_task);
4717         struct ixgbe_hw *hw = &adapter->hw;
4718         u32 autoneg;
4719         bool negotiation;
4720
4721         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4722         autoneg = hw->phy.autoneg_advertised;
4723         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4724                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4725         if (hw->mac.ops.setup_link)
4726                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4727         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4728         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4729 }
4730
4731 /**
4732  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4733  * @work: pointer to work_struct containing our data
4734  **/
4735 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4736 {
4737         struct ixgbe_adapter *adapter = container_of(work,
4738                                                      struct ixgbe_adapter,
4739                                                      sfp_config_module_task);
4740         struct ixgbe_hw *hw = &adapter->hw;
4741         u32 err;
4742
4743         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4744
4745         /* Time for electrical oscillations to settle down */
4746         msleep(100);
4747         err = hw->phy.ops.identify_sfp(hw);
4748
4749         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4750                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4751                         "an unsupported SFP+ module type was detected.\n"
4752                         "Reload the driver after installing a supported "
4753                         "module.\n");
4754                 unregister_netdev(adapter->netdev);
4755                 return;
4756         }
4757         hw->mac.ops.setup_sfp(hw);
4758
4759         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4760                 /* This will also work for DA Twinax connections */
4761                 schedule_work(&adapter->multispeed_fiber_task);
4762         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4763 }
4764
4765 /**
4766  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4767  * @work: pointer to work_struct containing our data
4768  **/
4769 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4770 {
4771         struct ixgbe_adapter *adapter = container_of(work,
4772                                                      struct ixgbe_adapter,
4773                                                      fdir_reinit_task);
4774         struct ixgbe_hw *hw = &adapter->hw;
4775         int i;
4776
4777         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4778                 for (i = 0; i < adapter->num_tx_queues; i++)
4779                         set_bit(__IXGBE_FDIR_INIT_DONE,
4780                                 &(adapter->tx_ring[i].reinit_state));
4781         } else {
4782                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4783                         "ignored adding FDIR ATR filters \n");
4784         }
4785         /* Done FDIR Re-initialization, enable transmits */
4786         netif_tx_start_all_queues(adapter->netdev);
4787 }
4788
4789 /**
4790  * ixgbe_watchdog_task - worker thread to bring link up
4791  * @work: pointer to work_struct containing our data
4792  **/
4793 static void ixgbe_watchdog_task(struct work_struct *work)
4794 {
4795         struct ixgbe_adapter *adapter = container_of(work,
4796                                                      struct ixgbe_adapter,
4797                                                      watchdog_task);
4798         struct net_device *netdev = adapter->netdev;
4799         struct ixgbe_hw *hw = &adapter->hw;
4800         u32 link_speed = adapter->link_speed;
4801         bool link_up = adapter->link_up;
4802         int i;
4803         struct ixgbe_ring *tx_ring;
4804         int some_tx_pending = 0;
4805
4806         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4807
4808         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4809                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4810                 if (link_up) {
4811 #ifdef CONFIG_DCB
4812                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4813                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4814                                         hw->mac.ops.fc_enable(hw, i);
4815                         } else {
4816                                 hw->mac.ops.fc_enable(hw, 0);
4817                         }
4818 #else
4819                         hw->mac.ops.fc_enable(hw, 0);
4820 #endif
4821                 }
4822
4823                 if (link_up ||
4824                     time_after(jiffies, (adapter->link_check_timeout +
4825                                          IXGBE_TRY_LINK_TIMEOUT))) {
4826                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4827                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4828                 }
4829                 adapter->link_up = link_up;
4830                 adapter->link_speed = link_speed;
4831         }
4832
4833         if (link_up) {
4834                 if (!netif_carrier_ok(netdev)) {
4835                         bool flow_rx, flow_tx;
4836
4837                         if (hw->mac.type == ixgbe_mac_82599EB) {
4838                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4839                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4840                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4841                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4842                         } else {
4843                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4844                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4845                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4846                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4847                         }
4848
4849                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4850                                "Flow Control: %s\n",
4851                                netdev->name,
4852                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4853                                 "10 Gbps" :
4854                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4855                                  "1 Gbps" : "unknown speed")),
4856                                ((flow_rx && flow_tx) ? "RX/TX" :
4857                                 (flow_rx ? "RX" :
4858                                 (flow_tx ? "TX" : "None"))));
4859
4860                         netif_carrier_on(netdev);
4861                 } else {
4862                         /* Force detection of hung controller */
4863                         adapter->detect_tx_hung = true;
4864                 }
4865         } else {
4866                 adapter->link_up = false;
4867                 adapter->link_speed = 0;
4868                 if (netif_carrier_ok(netdev)) {
4869                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4870                                netdev->name);
4871                         netif_carrier_off(netdev);
4872                 }
4873         }
4874
4875         if (!netif_carrier_ok(netdev)) {
4876                 for (i = 0; i < adapter->num_tx_queues; i++) {
4877                         tx_ring = &adapter->tx_ring[i];
4878                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4879                                 some_tx_pending = 1;
4880                                 break;
4881                         }
4882                 }
4883
4884                 if (some_tx_pending) {
4885                         /* We've lost link, so the controller stops DMA,
4886                          * but we've got queued Tx work that's never going
4887                          * to get done, so reset controller to flush Tx.
4888                          * (Do the reset outside of interrupt context).
4889                          */
4890                          schedule_work(&adapter->reset_task);
4891                 }
4892         }
4893
4894         ixgbe_update_stats(adapter);
4895         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4896 }
4897
4898 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4899                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4900                      u32 tx_flags, u8 *hdr_len)
4901 {
4902         struct ixgbe_adv_tx_context_desc *context_desc;
4903         unsigned int i;
4904         int err;
4905         struct ixgbe_tx_buffer *tx_buffer_info;
4906         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4907         u32 mss_l4len_idx, l4len;
4908
4909         if (skb_is_gso(skb)) {
4910                 if (skb_header_cloned(skb)) {
4911                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4912                         if (err)
4913                                 return err;
4914                 }
4915                 l4len = tcp_hdrlen(skb);
4916                 *hdr_len += l4len;
4917
4918                 if (skb->protocol == htons(ETH_P_IP)) {
4919                         struct iphdr *iph = ip_hdr(skb);
4920                         iph->tot_len = 0;
4921                         iph->check = 0;
4922                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4923                                                                  iph->daddr, 0,
4924                                                                  IPPROTO_TCP,
4925                                                                  0);
4926                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4927                         ipv6_hdr(skb)->payload_len = 0;
4928                         tcp_hdr(skb)->check =
4929                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4930                                              &ipv6_hdr(skb)->daddr,
4931                                              0, IPPROTO_TCP, 0);
4932                 }
4933
4934                 i = tx_ring->next_to_use;
4935
4936                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4937                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4938
4939                 /* VLAN MACLEN IPLEN */
4940                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4941                         vlan_macip_lens |=
4942                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4943                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4944                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4945                 *hdr_len += skb_network_offset(skb);
4946                 vlan_macip_lens |=
4947                     (skb_transport_header(skb) - skb_network_header(skb));
4948                 *hdr_len +=
4949                     (skb_transport_header(skb) - skb_network_header(skb));
4950                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4951                 context_desc->seqnum_seed = 0;
4952
4953                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4954                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4955                                    IXGBE_ADVTXD_DTYP_CTXT);
4956
4957                 if (skb->protocol == htons(ETH_P_IP))
4958                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4959                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4960                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4961
4962                 /* MSS L4LEN IDX */
4963                 mss_l4len_idx =
4964                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4965                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4966                 /* use index 1 for TSO */
4967                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4968                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4969
4970                 tx_buffer_info->time_stamp = jiffies;
4971                 tx_buffer_info->next_to_watch = i;
4972
4973                 i++;
4974                 if (i == tx_ring->count)
4975                         i = 0;
4976                 tx_ring->next_to_use = i;
4977
4978                 return true;
4979         }
4980         return false;
4981 }
4982
4983 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4984                           struct ixgbe_ring *tx_ring,
4985                           struct sk_buff *skb, u32 tx_flags)
4986 {
4987         struct ixgbe_adv_tx_context_desc *context_desc;
4988         unsigned int i;
4989         struct ixgbe_tx_buffer *tx_buffer_info;
4990         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4991
4992         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4993             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4994                 i = tx_ring->next_to_use;
4995                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4996                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4997
4998                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4999                         vlan_macip_lens |=
5000                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5001                 vlan_macip_lens |= (skb_network_offset(skb) <<
5002                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5003                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5004                         vlan_macip_lens |= (skb_transport_header(skb) -
5005                                             skb_network_header(skb));
5006
5007                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5008                 context_desc->seqnum_seed = 0;
5009
5010                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5011                                     IXGBE_ADVTXD_DTYP_CTXT);
5012
5013                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5014                         __be16 protocol;
5015
5016                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5017                                 const struct vlan_ethhdr *vhdr =
5018                                         (const struct vlan_ethhdr *)skb->data;
5019
5020                                 protocol = vhdr->h_vlan_encapsulated_proto;
5021                         } else {
5022                                 protocol = skb->protocol;
5023                         }
5024
5025                         switch (protocol) {
5026                         case cpu_to_be16(ETH_P_IP):
5027                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5028                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5029                                         type_tucmd_mlhl |=
5030                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5031                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5032                                         type_tucmd_mlhl |=
5033                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5034                                 break;
5035                         case cpu_to_be16(ETH_P_IPV6):
5036                                 /* XXX what about other V6 headers?? */
5037                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5038                                         type_tucmd_mlhl |=
5039                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5040                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5041                                         type_tucmd_mlhl |=
5042                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5043                                 break;
5044                         default:
5045                                 if (unlikely(net_ratelimit())) {
5046                                         DPRINTK(PROBE, WARNING,
5047                                          "partial checksum but proto=%x!\n",
5048                                          skb->protocol);
5049                                 }
5050                                 break;
5051                         }
5052                 }
5053
5054                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5055                 /* use index zero for tx checksum offload */
5056                 context_desc->mss_l4len_idx = 0;
5057
5058                 tx_buffer_info->time_stamp = jiffies;
5059                 tx_buffer_info->next_to_watch = i;
5060
5061                 i++;
5062                 if (i == tx_ring->count)
5063                         i = 0;
5064                 tx_ring->next_to_use = i;
5065
5066                 return true;
5067         }
5068
5069         return false;
5070 }
5071
5072 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5073                         struct ixgbe_ring *tx_ring,
5074                         struct sk_buff *skb, u32 tx_flags,
5075                         unsigned int first)
5076 {
5077         struct pci_dev *pdev = adapter->pdev;
5078         struct ixgbe_tx_buffer *tx_buffer_info;
5079         unsigned int len;
5080         unsigned int total = skb->len;
5081         unsigned int offset = 0, size, count = 0, i;
5082         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5083         unsigned int f;
5084
5085         i = tx_ring->next_to_use;
5086
5087         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5088                 /* excluding fcoe_crc_eof for FCoE */
5089                 total -= sizeof(struct fcoe_crc_eof);
5090
5091         len = min(skb_headlen(skb), total);
5092         while (len) {
5093                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5094                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5095
5096                 tx_buffer_info->length = size;
5097                 tx_buffer_info->mapped_as_page = false;
5098                 tx_buffer_info->dma = pci_map_single(pdev,
5099                                                      skb->data + offset,
5100                                                      size, PCI_DMA_TODEVICE);
5101                 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5102                         goto dma_error;
5103                 tx_buffer_info->time_stamp = jiffies;
5104                 tx_buffer_info->next_to_watch = i;
5105
5106                 len -= size;
5107                 total -= size;
5108                 offset += size;
5109                 count++;
5110
5111                 if (len) {
5112                         i++;
5113                         if (i == tx_ring->count)
5114                                 i = 0;
5115                 }
5116         }
5117
5118         for (f = 0; f < nr_frags; f++) {
5119                 struct skb_frag_struct *frag;
5120
5121                 frag = &skb_shinfo(skb)->frags[f];
5122                 len = min((unsigned int)frag->size, total);
5123                 offset = frag->page_offset;
5124
5125                 while (len) {
5126                         i++;
5127                         if (i == tx_ring->count)
5128                                 i = 0;
5129
5130                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5131                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5132
5133                         tx_buffer_info->length = size;
5134                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
5135                                                            frag->page,
5136                                                            offset, size,
5137                                                            PCI_DMA_TODEVICE);
5138                         tx_buffer_info->mapped_as_page = true;
5139                         if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5140                                 goto dma_error;
5141                         tx_buffer_info->time_stamp = jiffies;
5142                         tx_buffer_info->next_to_watch = i;
5143
5144                         len -= size;
5145                         total -= size;
5146                         offset += size;
5147                         count++;
5148                 }
5149                 if (total == 0)
5150                         break;
5151         }
5152
5153         tx_ring->tx_buffer_info[i].skb = skb;
5154         tx_ring->tx_buffer_info[first].next_to_watch = i;
5155
5156         return count;
5157
5158 dma_error:
5159         dev_err(&pdev->dev, "TX DMA map failed\n");
5160
5161         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5162         tx_buffer_info->dma = 0;
5163         tx_buffer_info->time_stamp = 0;
5164         tx_buffer_info->next_to_watch = 0;
5165         count--;
5166
5167         /* clear timestamp and dma mappings for remaining portion of packet */
5168         while (count >= 0) {
5169                 count--;
5170                 i--;
5171                 if (i < 0)
5172                         i += tx_ring->count;
5173                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5174                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5175         }
5176
5177         return count;
5178 }
5179
5180 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5181                            struct ixgbe_ring *tx_ring,
5182                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5183 {
5184         union ixgbe_adv_tx_desc *tx_desc = NULL;
5185         struct ixgbe_tx_buffer *tx_buffer_info;
5186         u32 olinfo_status = 0, cmd_type_len = 0;
5187         unsigned int i;
5188         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5189
5190         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5191
5192         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5193
5194         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5195                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5196
5197         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5198                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5199
5200                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5201                                  IXGBE_ADVTXD_POPTS_SHIFT;
5202
5203                 /* use index 1 context for tso */
5204                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5205                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5206                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5207                                          IXGBE_ADVTXD_POPTS_SHIFT;
5208
5209         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5210                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5211                                  IXGBE_ADVTXD_POPTS_SHIFT;
5212
5213         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5214                 olinfo_status |= IXGBE_ADVTXD_CC;
5215                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5216                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5217                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5218         }
5219
5220         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5221
5222         i = tx_ring->next_to_use;
5223         while (count--) {
5224                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5225                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5226                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5227                 tx_desc->read.cmd_type_len =
5228                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5229                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5230                 i++;
5231                 if (i == tx_ring->count)
5232                         i = 0;
5233         }
5234
5235         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5236
5237         /*
5238          * Force memory writes to complete before letting h/w
5239          * know there are new descriptors to fetch.  (Only
5240          * applicable for weak-ordered memory model archs,
5241          * such as IA-64).
5242          */
5243         wmb();
5244
5245         tx_ring->next_to_use = i;
5246         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5247 }
5248
5249 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5250                       int queue, u32 tx_flags)
5251 {
5252         /* Right now, we support IPv4 only */
5253         struct ixgbe_atr_input atr_input;
5254         struct tcphdr *th;
5255         struct iphdr *iph = ip_hdr(skb);
5256         struct ethhdr *eth = (struct ethhdr *)skb->data;
5257         u16 vlan_id, src_port, dst_port, flex_bytes;
5258         u32 src_ipv4_addr, dst_ipv4_addr;
5259         u8 l4type = 0;
5260
5261         /* check if we're UDP or TCP */
5262         if (iph->protocol == IPPROTO_TCP) {
5263                 th = tcp_hdr(skb);
5264                 src_port = th->source;
5265                 dst_port = th->dest;
5266                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5267                 /* l4type IPv4 type is 0, no need to assign */
5268         } else {
5269                 /* Unsupported L4 header, just bail here */
5270                 return;
5271         }
5272
5273         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5274
5275         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5276                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5277         src_ipv4_addr = iph->saddr;
5278         dst_ipv4_addr = iph->daddr;
5279         flex_bytes = eth->h_proto;
5280
5281         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5282         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5283         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5284         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5285         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5286         /* src and dst are inverted, think how the receiver sees them */
5287         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5288         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5289
5290         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5291         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5292 }
5293
5294 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5295                                  struct ixgbe_ring *tx_ring, int size)
5296 {
5297         netif_stop_subqueue(netdev, tx_ring->queue_index);
5298         /* Herbert's original patch had:
5299          *  smp_mb__after_netif_stop_queue();
5300          * but since that doesn't exist yet, just open code it. */
5301         smp_mb();
5302
5303         /* We need to check again in a case another CPU has just
5304          * made room available. */
5305         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5306                 return -EBUSY;
5307
5308         /* A reprieve! - use start_queue because it doesn't call schedule */
5309         netif_start_subqueue(netdev, tx_ring->queue_index);
5310         ++tx_ring->restart_queue;
5311         return 0;
5312 }
5313
5314 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5315                               struct ixgbe_ring *tx_ring, int size)
5316 {
5317         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5318                 return 0;
5319         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5320 }
5321
5322 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5323 {
5324         struct ixgbe_adapter *adapter = netdev_priv(dev);
5325         int txq = smp_processor_id();
5326
5327         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5328                 return txq;
5329
5330 #ifdef IXGBE_FCOE
5331         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5332             (skb->protocol == htons(ETH_P_FCOE))) {
5333                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5334                 txq += adapter->ring_feature[RING_F_FCOE].mask;
5335                 return txq;
5336         }
5337 #endif
5338         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5339                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5340
5341         return skb_tx_hash(dev, skb);
5342 }
5343
5344 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5345                                     struct net_device *netdev)
5346 {
5347         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5348         struct ixgbe_ring *tx_ring;
5349         struct netdev_queue *txq;
5350         unsigned int first;
5351         unsigned int tx_flags = 0;
5352         u8 hdr_len = 0;
5353         int tso;
5354         int count = 0;
5355         unsigned int f;
5356
5357         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5358                 tx_flags |= vlan_tx_tag_get(skb);
5359                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5360                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5361                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5362                 }
5363                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5364                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5365         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5366                 if (skb->priority != TC_PRIO_CONTROL) {
5367                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
5368                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5369                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5370                 } else {
5371                         skb->queue_mapping =
5372                                 adapter->ring_feature[RING_F_DCB].indices-1;
5373                 }
5374         }
5375
5376         tx_ring = &adapter->tx_ring[skb->queue_mapping];
5377
5378         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5379             (skb->protocol == htons(ETH_P_FCOE))) {
5380                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5381 #ifdef IXGBE_FCOE
5382 #ifdef CONFIG_IXGBE_DCB
5383                 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5384                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5385                 tx_flags |= ((adapter->fcoe.up << 13)
5386                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5387 #endif
5388 #endif
5389         }
5390         /* four things can cause us to need a context descriptor */
5391         if (skb_is_gso(skb) ||
5392             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5393             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5394             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5395                 count++;
5396
5397         count += TXD_USE_COUNT(skb_headlen(skb));
5398         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5399                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5400
5401         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5402                 adapter->tx_busy++;
5403                 return NETDEV_TX_BUSY;
5404         }
5405
5406         first = tx_ring->next_to_use;
5407         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5408 #ifdef IXGBE_FCOE
5409                 /* setup tx offload for FCoE */
5410                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5411                 if (tso < 0) {
5412                         dev_kfree_skb_any(skb);
5413                         return NETDEV_TX_OK;
5414                 }
5415                 if (tso)
5416                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5417 #endif /* IXGBE_FCOE */
5418         } else {
5419                 if (skb->protocol == htons(ETH_P_IP))
5420                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5421                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5422                 if (tso < 0) {
5423                         dev_kfree_skb_any(skb);
5424                         return NETDEV_TX_OK;
5425                 }
5426
5427                 if (tso)
5428                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5429                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5430                          (skb->ip_summed == CHECKSUM_PARTIAL))
5431                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5432         }
5433
5434         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5435         if (count) {
5436                 /* add the ATR filter if ATR is on */
5437                 if (tx_ring->atr_sample_rate) {
5438                         ++tx_ring->atr_count;
5439                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5440                              test_bit(__IXGBE_FDIR_INIT_DONE,
5441                                       &tx_ring->reinit_state)) {
5442                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5443                                           tx_flags);
5444                                 tx_ring->atr_count = 0;
5445                         }
5446                 }
5447                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
5448                 txq->tx_bytes += skb->len;
5449                 txq->tx_packets++;
5450                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5451                                hdr_len);
5452                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5453
5454         } else {
5455                 dev_kfree_skb_any(skb);
5456                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5457                 tx_ring->next_to_use = first;
5458         }
5459
5460         return NETDEV_TX_OK;
5461 }
5462
5463 /**
5464  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5465  * @netdev: network interface device structure
5466  * @p: pointer to an address structure
5467  *
5468  * Returns 0 on success, negative on failure
5469  **/
5470 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5471 {
5472         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5473         struct ixgbe_hw *hw = &adapter->hw;
5474         struct sockaddr *addr = p;
5475
5476         if (!is_valid_ether_addr(addr->sa_data))
5477                 return -EADDRNOTAVAIL;
5478
5479         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5480         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5481
5482         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5483
5484         return 0;
5485 }
5486
5487 static int
5488 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5489 {
5490         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5491         struct ixgbe_hw *hw = &adapter->hw;
5492         u16 value;
5493         int rc;
5494
5495         if (prtad != hw->phy.mdio.prtad)
5496                 return -EINVAL;
5497         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5498         if (!rc)
5499                 rc = value;
5500         return rc;
5501 }
5502
5503 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5504                             u16 addr, u16 value)
5505 {
5506         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5507         struct ixgbe_hw *hw = &adapter->hw;
5508
5509         if (prtad != hw->phy.mdio.prtad)
5510                 return -EINVAL;
5511         return hw->phy.ops.write_reg(hw, addr, devad, value);
5512 }
5513
5514 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5515 {
5516         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5517
5518         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5519 }
5520
5521 /**
5522  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5523  * netdev->dev_addrs
5524  * @netdev: network interface device structure
5525  *
5526  * Returns non-zero on failure
5527  **/
5528 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5529 {
5530         int err = 0;
5531         struct ixgbe_adapter *adapter = netdev_priv(dev);
5532         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5533
5534         if (is_valid_ether_addr(mac->san_addr)) {
5535                 rtnl_lock();
5536                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5537                 rtnl_unlock();
5538         }
5539         return err;
5540 }
5541
5542 /**
5543  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5544  * netdev->dev_addrs
5545  * @netdev: network interface device structure
5546  *
5547  * Returns non-zero on failure
5548  **/
5549 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5550 {
5551         int err = 0;
5552         struct ixgbe_adapter *adapter = netdev_priv(dev);
5553         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5554
5555         if (is_valid_ether_addr(mac->san_addr)) {
5556                 rtnl_lock();
5557                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5558                 rtnl_unlock();
5559         }
5560         return err;
5561 }
5562
5563 #ifdef CONFIG_NET_POLL_CONTROLLER
5564 /*
5565  * Polling 'interrupt' - used by things like netconsole to send skbs
5566  * without having to re-enable interrupts. It's not called while
5567  * the interrupt routine is executing.
5568  */
5569 static void ixgbe_netpoll(struct net_device *netdev)
5570 {
5571         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5572         int i;
5573
5574         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5575         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5576                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5577                 for (i = 0; i < num_q_vectors; i++) {
5578                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5579                         ixgbe_msix_clean_many(0, q_vector);
5580                 }
5581         } else {
5582                 ixgbe_intr(adapter->pdev->irq, netdev);
5583         }
5584         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5585 }
5586 #endif
5587
5588 static const struct net_device_ops ixgbe_netdev_ops = {
5589         .ndo_open               = ixgbe_open,
5590         .ndo_stop               = ixgbe_close,
5591         .ndo_start_xmit         = ixgbe_xmit_frame,
5592         .ndo_select_queue       = ixgbe_select_queue,
5593         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5594         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5595         .ndo_validate_addr      = eth_validate_addr,
5596         .ndo_set_mac_address    = ixgbe_set_mac,
5597         .ndo_change_mtu         = ixgbe_change_mtu,
5598         .ndo_tx_timeout         = ixgbe_tx_timeout,
5599         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5600         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5601         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5602         .ndo_do_ioctl           = ixgbe_ioctl,
5603 #ifdef CONFIG_NET_POLL_CONTROLLER
5604         .ndo_poll_controller    = ixgbe_netpoll,
5605 #endif
5606 #ifdef IXGBE_FCOE
5607         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5608         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5609         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5610         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5611         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5612 #endif /* IXGBE_FCOE */
5613 };
5614
5615 /**
5616  * ixgbe_probe - Device Initialization Routine
5617  * @pdev: PCI device information struct
5618  * @ent: entry in ixgbe_pci_tbl
5619  *
5620  * Returns 0 on success, negative on failure
5621  *
5622  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5623  * The OS initialization, configuring of the adapter private structure,
5624  * and a hardware reset occur.
5625  **/
5626 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5627                                  const struct pci_device_id *ent)
5628 {
5629         struct net_device *netdev;
5630         struct ixgbe_adapter *adapter = NULL;
5631         struct ixgbe_hw *hw;
5632         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5633         static int cards_found;
5634         int i, err, pci_using_dac;
5635 #ifdef IXGBE_FCOE
5636         u16 device_caps;
5637 #endif
5638         u32 part_num, eec;
5639
5640         err = pci_enable_device_mem(pdev);
5641         if (err)
5642                 return err;
5643
5644         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5645             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5646                 pci_using_dac = 1;
5647         } else {
5648                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5649                 if (err) {
5650                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5651                         if (err) {
5652                                 dev_err(&pdev->dev, "No usable DMA "
5653                                         "configuration, aborting\n");
5654                                 goto err_dma;
5655                         }
5656                 }
5657                 pci_using_dac = 0;
5658         }
5659
5660         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5661                                            IORESOURCE_MEM), ixgbe_driver_name);
5662         if (err) {
5663                 dev_err(&pdev->dev,
5664                         "pci_request_selected_regions failed 0x%x\n", err);
5665                 goto err_pci_reg;
5666         }
5667
5668         pci_enable_pcie_error_reporting(pdev);
5669
5670         pci_set_master(pdev);
5671         pci_save_state(pdev);
5672
5673         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5674         if (!netdev) {
5675                 err = -ENOMEM;
5676                 goto err_alloc_etherdev;
5677         }
5678
5679         SET_NETDEV_DEV(netdev, &pdev->dev);
5680
5681         pci_set_drvdata(pdev, netdev);
5682         adapter = netdev_priv(netdev);
5683
5684         adapter->netdev = netdev;
5685         adapter->pdev = pdev;
5686         hw = &adapter->hw;
5687         hw->back = adapter;
5688         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5689
5690         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5691                               pci_resource_len(pdev, 0));
5692         if (!hw->hw_addr) {
5693                 err = -EIO;
5694                 goto err_ioremap;
5695         }
5696
5697         for (i = 1; i <= 5; i++) {
5698                 if (pci_resource_len(pdev, i) == 0)
5699                         continue;
5700         }
5701
5702         netdev->netdev_ops = &ixgbe_netdev_ops;
5703         ixgbe_set_ethtool_ops(netdev);
5704         netdev->watchdog_timeo = 5 * HZ;
5705         strcpy(netdev->name, pci_name(pdev));
5706
5707         adapter->bd_number = cards_found;
5708
5709         /* Setup hw api */
5710         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5711         hw->mac.type  = ii->mac;
5712
5713         /* EEPROM */
5714         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5715         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5716         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5717         if (!(eec & (1 << 8)))
5718                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5719
5720         /* PHY */
5721         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5722         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5723         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5724         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5725         hw->phy.mdio.mmds = 0;
5726         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5727         hw->phy.mdio.dev = netdev;
5728         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5729         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5730
5731         /* set up this timer and work struct before calling get_invariants
5732          * which might start the timer
5733          */
5734         init_timer(&adapter->sfp_timer);
5735         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5736         adapter->sfp_timer.data = (unsigned long) adapter;
5737
5738         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5739
5740         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5741         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5742
5743         /* a new SFP+ module arrival, called from GPI SDP2 context */
5744         INIT_WORK(&adapter->sfp_config_module_task,
5745                   ixgbe_sfp_config_module_task);
5746
5747         ii->get_invariants(hw);
5748
5749         /* setup the private structure */
5750         err = ixgbe_sw_init(adapter);
5751         if (err)
5752                 goto err_sw_init;
5753
5754         /*
5755          * If there is a fan on this device and it has failed log the
5756          * failure.
5757          */
5758         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5759                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5760                 if (esdp & IXGBE_ESDP_SDP1)
5761                         DPRINTK(PROBE, CRIT,
5762                                 "Fan has stopped, replace the adapter\n");
5763         }
5764
5765         /* reset_hw fills in the perm_addr as well */
5766         err = hw->mac.ops.reset_hw(hw);
5767         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5768             hw->mac.type == ixgbe_mac_82598EB) {
5769                 /*
5770                  * Start a kernel thread to watch for a module to arrive.
5771                  * Only do this for 82598, since 82599 will generate
5772                  * interrupts on module arrival.
5773                  */
5774                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5775                 mod_timer(&adapter->sfp_timer,
5776                           round_jiffies(jiffies + (2 * HZ)));
5777                 err = 0;
5778         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5779                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5780                         "an unsupported SFP+ module type was detected.\n"
5781                         "Reload the driver after installing a supported "
5782                         "module.\n");
5783                 goto err_sw_init;
5784         } else if (err) {
5785                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5786                 goto err_sw_init;
5787         }
5788
5789         netdev->features = NETIF_F_SG |
5790                            NETIF_F_IP_CSUM |
5791                            NETIF_F_HW_VLAN_TX |
5792                            NETIF_F_HW_VLAN_RX |
5793                            NETIF_F_HW_VLAN_FILTER;
5794
5795         netdev->features |= NETIF_F_IPV6_CSUM;
5796         netdev->features |= NETIF_F_TSO;
5797         netdev->features |= NETIF_F_TSO6;
5798         netdev->features |= NETIF_F_GRO;
5799
5800         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5801                 netdev->features |= NETIF_F_SCTP_CSUM;
5802
5803         netdev->vlan_features |= NETIF_F_TSO;
5804         netdev->vlan_features |= NETIF_F_TSO6;
5805         netdev->vlan_features |= NETIF_F_IP_CSUM;
5806         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5807         netdev->vlan_features |= NETIF_F_SG;
5808
5809         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5810                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5811
5812 #ifdef CONFIG_IXGBE_DCB
5813         netdev->dcbnl_ops = &dcbnl_ops;
5814 #endif
5815
5816 #ifdef IXGBE_FCOE
5817         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5818                 if (hw->mac.ops.get_device_caps) {
5819                         hw->mac.ops.get_device_caps(hw, &device_caps);
5820                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5821                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5822                 }
5823         }
5824 #endif /* IXGBE_FCOE */
5825         if (pci_using_dac)
5826                 netdev->features |= NETIF_F_HIGHDMA;
5827
5828         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5829                 netdev->features |= NETIF_F_LRO;
5830
5831         /* make sure the EEPROM is good */
5832         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5833                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5834                 err = -EIO;
5835                 goto err_eeprom;
5836         }
5837
5838         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5839         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5840
5841         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5842                 dev_err(&pdev->dev, "invalid MAC address\n");
5843                 err = -EIO;
5844                 goto err_eeprom;
5845         }
5846
5847         init_timer(&adapter->watchdog_timer);
5848         adapter->watchdog_timer.function = &ixgbe_watchdog;
5849         adapter->watchdog_timer.data = (unsigned long)adapter;
5850
5851         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5852         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5853
5854         err = ixgbe_init_interrupt_scheme(adapter);
5855         if (err)
5856                 goto err_sw_init;
5857
5858         switch (pdev->device) {
5859         case IXGBE_DEV_ID_82599_KX4:
5860                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5861                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5862                 /* Enable ACPI wakeup in GRC */
5863                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5864                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5865                 break;
5866         default:
5867                 adapter->wol = 0;
5868                 break;
5869         }
5870         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5871
5872         /* pick up the PCI bus settings for reporting later */
5873         hw->mac.ops.get_bus_info(hw);
5874
5875         /* print bus type/speed/width info */
5876         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5877                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5878                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5879                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5880                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5881                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5882                  "Unknown"),
5883                 netdev->dev_addr);
5884         ixgbe_read_pba_num_generic(hw, &part_num);
5885         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5886                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5887                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5888                          (part_num >> 8), (part_num & 0xff));
5889         else
5890                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5891                          hw->mac.type, hw->phy.type,
5892                          (part_num >> 8), (part_num & 0xff));
5893
5894         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5895                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5896                          "this card is not sufficient for optimal "
5897                          "performance.\n");
5898                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5899                          "PCI-Express slot is required.\n");
5900         }
5901
5902         /* save off EEPROM version number */
5903         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5904
5905         /* reset the hardware with the new settings */
5906         err = hw->mac.ops.start_hw(hw);
5907
5908         if (err == IXGBE_ERR_EEPROM_VERSION) {
5909                 /* We are running on a pre-production device, log a warning */
5910                 dev_warn(&pdev->dev, "This device is a pre-production "
5911                          "adapter/LOM.  Please be aware there may be issues "
5912                          "associated with your hardware.  If you are "
5913                          "experiencing problems please contact your Intel or "
5914                          "hardware representative who provided you with this "
5915                          "hardware.\n");
5916         }
5917         strcpy(netdev->name, "eth%d");
5918         err = register_netdev(netdev);
5919         if (err)
5920                 goto err_register;
5921
5922         /* carrier off reporting is important to ethtool even BEFORE open */
5923         netif_carrier_off(netdev);
5924
5925         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5926             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5927                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5928
5929 #ifdef CONFIG_IXGBE_DCA
5930         if (dca_add_requester(&pdev->dev) == 0) {
5931                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5932                 ixgbe_setup_dca(adapter);
5933         }
5934 #endif
5935         /* add san mac addr to netdev */
5936         ixgbe_add_sanmac_netdev(netdev);
5937
5938         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5939         cards_found++;
5940         return 0;
5941
5942 err_register:
5943         ixgbe_release_hw_control(adapter);
5944         ixgbe_clear_interrupt_scheme(adapter);
5945 err_sw_init:
5946 err_eeprom:
5947         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5948         del_timer_sync(&adapter->sfp_timer);
5949         cancel_work_sync(&adapter->sfp_task);
5950         cancel_work_sync(&adapter->multispeed_fiber_task);
5951         cancel_work_sync(&adapter->sfp_config_module_task);
5952         iounmap(hw->hw_addr);
5953 err_ioremap:
5954         free_netdev(netdev);
5955 err_alloc_etherdev:
5956         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5957                                      IORESOURCE_MEM));
5958 err_pci_reg:
5959 err_dma:
5960         pci_disable_device(pdev);
5961         return err;
5962 }
5963
5964 /**
5965  * ixgbe_remove - Device Removal Routine
5966  * @pdev: PCI device information struct
5967  *
5968  * ixgbe_remove is called by the PCI subsystem to alert the driver
5969  * that it should release a PCI device.  The could be caused by a
5970  * Hot-Plug event, or because the driver is going to be removed from
5971  * memory.
5972  **/
5973 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5974 {
5975         struct net_device *netdev = pci_get_drvdata(pdev);
5976         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5977
5978         set_bit(__IXGBE_DOWN, &adapter->state);
5979         /* clear the module not found bit to make sure the worker won't
5980          * reschedule
5981          */
5982         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5983         del_timer_sync(&adapter->watchdog_timer);
5984
5985         del_timer_sync(&adapter->sfp_timer);
5986         cancel_work_sync(&adapter->watchdog_task);
5987         cancel_work_sync(&adapter->sfp_task);
5988         cancel_work_sync(&adapter->multispeed_fiber_task);
5989         cancel_work_sync(&adapter->sfp_config_module_task);
5990         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5991             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5992                 cancel_work_sync(&adapter->fdir_reinit_task);
5993         flush_scheduled_work();
5994
5995 #ifdef CONFIG_IXGBE_DCA
5996         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5997                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5998                 dca_remove_requester(&pdev->dev);
5999                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6000         }
6001
6002 #endif
6003 #ifdef IXGBE_FCOE
6004         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6005                 ixgbe_cleanup_fcoe(adapter);
6006
6007 #endif /* IXGBE_FCOE */
6008
6009         /* remove the added san mac */
6010         ixgbe_del_sanmac_netdev(netdev);
6011
6012         if (netdev->reg_state == NETREG_REGISTERED)
6013                 unregister_netdev(netdev);
6014
6015         ixgbe_clear_interrupt_scheme(adapter);
6016
6017         ixgbe_release_hw_control(adapter);
6018
6019         iounmap(adapter->hw.hw_addr);
6020         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6021                                      IORESOURCE_MEM));
6022
6023         DPRINTK(PROBE, INFO, "complete\n");
6024
6025         free_netdev(netdev);
6026
6027         pci_disable_pcie_error_reporting(pdev);
6028
6029         pci_disable_device(pdev);
6030 }
6031
6032 /**
6033  * ixgbe_io_error_detected - called when PCI error is detected
6034  * @pdev: Pointer to PCI device
6035  * @state: The current pci connection state
6036  *
6037  * This function is called after a PCI bus error affecting
6038  * this device has been detected.
6039  */
6040 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6041                                                 pci_channel_state_t state)
6042 {
6043         struct net_device *netdev = pci_get_drvdata(pdev);
6044         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6045
6046         netif_device_detach(netdev);
6047
6048         if (state == pci_channel_io_perm_failure)
6049                 return PCI_ERS_RESULT_DISCONNECT;
6050
6051         if (netif_running(netdev))
6052                 ixgbe_down(adapter);
6053         pci_disable_device(pdev);
6054
6055         /* Request a slot reset. */
6056         return PCI_ERS_RESULT_NEED_RESET;
6057 }
6058
6059 /**
6060  * ixgbe_io_slot_reset - called after the pci bus has been reset.
6061  * @pdev: Pointer to PCI device
6062  *
6063  * Restart the card from scratch, as if from a cold-boot.
6064  */
6065 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6066 {
6067         struct net_device *netdev = pci_get_drvdata(pdev);
6068         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6069         pci_ers_result_t result;
6070         int err;
6071
6072         if (pci_enable_device_mem(pdev)) {
6073                 DPRINTK(PROBE, ERR,
6074                         "Cannot re-enable PCI device after reset.\n");
6075                 result = PCI_ERS_RESULT_DISCONNECT;
6076         } else {
6077                 pci_set_master(pdev);
6078                 pci_restore_state(pdev);
6079                 pci_save_state(pdev);
6080
6081                 pci_wake_from_d3(pdev, false);
6082
6083                 ixgbe_reset(adapter);
6084                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6085                 result = PCI_ERS_RESULT_RECOVERED;
6086         }
6087
6088         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6089         if (err) {
6090                 dev_err(&pdev->dev,
6091                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6092                 /* non-fatal, continue */
6093         }
6094
6095         return result;
6096 }
6097
6098 /**
6099  * ixgbe_io_resume - called when traffic can start flowing again.
6100  * @pdev: Pointer to PCI device
6101  *
6102  * This callback is called when the error recovery driver tells us that
6103  * its OK to resume normal operation.
6104  */
6105 static void ixgbe_io_resume(struct pci_dev *pdev)
6106 {
6107         struct net_device *netdev = pci_get_drvdata(pdev);
6108         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6109
6110         if (netif_running(netdev)) {
6111                 if (ixgbe_up(adapter)) {
6112                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6113                         return;
6114                 }
6115         }
6116
6117         netif_device_attach(netdev);
6118 }
6119
6120 static struct pci_error_handlers ixgbe_err_handler = {
6121         .error_detected = ixgbe_io_error_detected,
6122         .slot_reset = ixgbe_io_slot_reset,
6123         .resume = ixgbe_io_resume,
6124 };
6125
6126 static struct pci_driver ixgbe_driver = {
6127         .name     = ixgbe_driver_name,
6128         .id_table = ixgbe_pci_tbl,
6129         .probe    = ixgbe_probe,
6130         .remove   = __devexit_p(ixgbe_remove),
6131 #ifdef CONFIG_PM
6132         .suspend  = ixgbe_suspend,
6133         .resume   = ixgbe_resume,
6134 #endif
6135         .shutdown = ixgbe_shutdown,
6136         .err_handler = &ixgbe_err_handler
6137 };
6138
6139 /**
6140  * ixgbe_init_module - Driver Registration Routine
6141  *
6142  * ixgbe_init_module is the first routine called when the driver is
6143  * loaded. All it does is register with the PCI subsystem.
6144  **/
6145 static int __init ixgbe_init_module(void)
6146 {
6147         int ret;
6148         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6149                ixgbe_driver_string, ixgbe_driver_version);
6150
6151         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6152
6153 #ifdef CONFIG_IXGBE_DCA
6154         dca_register_notify(&dca_notifier);
6155 #endif
6156
6157         ret = pci_register_driver(&ixgbe_driver);
6158         return ret;
6159 }
6160
6161 module_init(ixgbe_init_module);
6162
6163 /**
6164  * ixgbe_exit_module - Driver Exit Cleanup Routine
6165  *
6166  * ixgbe_exit_module is called just before the driver is removed
6167  * from memory.
6168  **/
6169 static void __exit ixgbe_exit_module(void)
6170 {
6171 #ifdef CONFIG_IXGBE_DCA
6172         dca_unregister_notify(&dca_notifier);
6173 #endif
6174         pci_unregister_driver(&ixgbe_driver);
6175 }
6176
6177 #ifdef CONFIG_IXGBE_DCA
6178 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6179                             void *p)
6180 {
6181         int ret_val;
6182
6183         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6184                                          __ixgbe_notify_dca);
6185
6186         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6187 }
6188
6189 #endif /* CONFIG_IXGBE_DCA */
6190 #ifdef DEBUG
6191 /**
6192  * ixgbe_get_hw_dev_name - return device name string
6193  * used by hardware layer to print debugging information
6194  **/
6195 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6196 {
6197         struct ixgbe_adapter *adapter = hw->back;
6198         return adapter->netdev->name;
6199 }
6200
6201 #endif
6202 module_exit(ixgbe_exit_module);
6203
6204 /* ixgbe_main.c */