drivers/net/igb/igb_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/sched.h>
  38
  39 #include "igb.h"
  40
  41 struct igb_stats {
  42         char stat_string[ETH_GSTRING_LEN];
  43         int sizeof_stat;
  44         int stat_offset;
  45 };
  46
  47 #define IGB_STAT(_name, _stat) { \
  48         .stat_string = _name, \
  49         .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
  50         .stat_offset = offsetof(struct igb_adapter, _stat) \
  51 }
  52 static const struct igb_stats igb_gstrings_stats[] = {
  53         IGB_STAT("rx_packets", stats.gprc),
  54         IGB_STAT("tx_packets", stats.gptc),
  55         IGB_STAT("rx_bytes", stats.gorc),
  56         IGB_STAT("tx_bytes", stats.gotc),
  57         IGB_STAT("rx_broadcast", stats.bprc),
  58         IGB_STAT("tx_broadcast", stats.bptc),
  59         IGB_STAT("rx_multicast", stats.mprc),
  60         IGB_STAT("tx_multicast", stats.mptc),
  61         IGB_STAT("multicast", stats.mprc),
  62         IGB_STAT("collisions", stats.colc),
  63         IGB_STAT("rx_crc_errors", stats.crcerrs),
  64         IGB_STAT("rx_no_buffer_count", stats.rnbc),
  65         IGB_STAT("rx_missed_errors", stats.mpc),
  66         IGB_STAT("tx_aborted_errors", stats.ecol),
  67         IGB_STAT("tx_carrier_errors", stats.tncrs),
  68         IGB_STAT("tx_window_errors", stats.latecol),
  69         IGB_STAT("tx_abort_late_coll", stats.latecol),
  70         IGB_STAT("tx_deferred_ok", stats.dc),
  71         IGB_STAT("tx_single_coll_ok", stats.scc),
  72         IGB_STAT("tx_multi_coll_ok", stats.mcc),
  73         IGB_STAT("tx_timeout_count", tx_timeout_count),
  74         IGB_STAT("rx_long_length_errors", stats.roc),
  75         IGB_STAT("rx_short_length_errors", stats.ruc),
  76         IGB_STAT("rx_align_errors", stats.algnerrc),
  77         IGB_STAT("tx_tcp_seg_good", stats.tsctc),
  78         IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
  79         IGB_STAT("rx_flow_control_xon", stats.xonrxc),
  80         IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
  81         IGB_STAT("tx_flow_control_xon", stats.xontxc),
  82         IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
  83         IGB_STAT("rx_long_byte_count", stats.gorc),
  84         IGB_STAT("tx_dma_out_of_sync", stats.doosync),
  85         IGB_STAT("tx_smbus", stats.mgptc),
  86         IGB_STAT("rx_smbus", stats.mgprc),
  87         IGB_STAT("dropped_smbus", stats.mgpdc),
  88 };
  89
  90 #define IGB_NETDEV_STAT(_net_stat) { \
  91         .stat_string = __stringify(_net_stat), \
  92         .sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \
  93         .stat_offset = offsetof(struct net_device_stats, _net_stat) \
  94 }
  95 static const struct igb_stats igb_gstrings_net_stats[] = {
  96         IGB_NETDEV_STAT(rx_errors),
  97         IGB_NETDEV_STAT(tx_errors),
  98         IGB_NETDEV_STAT(tx_dropped),
  99         IGB_NETDEV_STAT(rx_length_errors),
 100         IGB_NETDEV_STAT(rx_over_errors),
 101         IGB_NETDEV_STAT(rx_frame_errors),
 102         IGB_NETDEV_STAT(rx_fifo_errors),
 103         IGB_NETDEV_STAT(tx_fifo_errors),
 104         IGB_NETDEV_STAT(tx_heartbeat_errors)
 105 };
 106
 107 #define IGB_GLOBAL_STATS_LEN    \
 108         (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
 109 #define IGB_NETDEV_STATS_LEN    \
 110         (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
 111 #define IGB_RX_QUEUE_STATS_LEN \
 112         (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
 113 #define IGB_TX_QUEUE_STATS_LEN \
 114         (sizeof(struct igb_tx_queue_stats) / sizeof(u64))
 115 #define IGB_QUEUE_STATS_LEN \
 116         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
 117           IGB_RX_QUEUE_STATS_LEN) + \
 118          (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
 119           IGB_TX_QUEUE_STATS_LEN))
 120 #define IGB_STATS_LEN \
 121         (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
 122
 123 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 124         "Register test  (offline)", "Eeprom test    (offline)",
 125         "Interrupt test (offline)", "Loopback test  (offline)",
 126         "Link test   (on/offline)"
 127 };
 128 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
 129
 130 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 131 {
 132         struct igb_adapter *adapter = netdev_priv(netdev);
 133         struct e1000_hw *hw = &adapter->hw;
 134         u32 status;
 135
 136         if (hw->phy.media_type == e1000_media_type_copper) {
 137
 138                 ecmd->supported = (SUPPORTED_10baseT_Half |
 139                                    SUPPORTED_10baseT_Full |
 140                                    SUPPORTED_100baseT_Half |
 141                                    SUPPORTED_100baseT_Full |
 142                                    SUPPORTED_1000baseT_Full|
 143                                    SUPPORTED_Autoneg |
 144                                    SUPPORTED_TP);
 145                 ecmd->advertising = ADVERTISED_TP;
 146
 147                 if (hw->mac.autoneg == 1) {
 148                         ecmd->advertising |= ADVERTISED_Autoneg;
 149                         /* the e1000 autoneg seems to match ethtool nicely */
 150                         ecmd->advertising |= hw->phy.autoneg_advertised;
 151                 }
 152
 153                 ecmd->port = PORT_TP;
 154                 ecmd->phy_address = hw->phy.addr;
 155         } else {
 156                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 157                                      SUPPORTED_FIBRE |
 158                                      SUPPORTED_Autoneg);
 159
 160                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 161                                      ADVERTISED_FIBRE |
 162                                      ADVERTISED_Autoneg);
 163
 164                 ecmd->port = PORT_FIBRE;
 165         }
 166
 167         ecmd->transceiver = XCVR_INTERNAL;
 168
 169         status = rd32(E1000_STATUS);
 170
 171         if (status & E1000_STATUS_LU) {
 172
 173                 if ((status & E1000_STATUS_SPEED_1000) ||
 174                     hw->phy.media_type != e1000_media_type_copper)
 175                         ecmd->speed = SPEED_1000;
 176                 else if (status & E1000_STATUS_SPEED_100)
 177                         ecmd->speed = SPEED_100;
 178                 else
 179                         ecmd->speed = SPEED_10;
 180
 181                 if ((status & E1000_STATUS_FD) ||
 182                     hw->phy.media_type != e1000_media_type_copper)
 183                         ecmd->duplex = DUPLEX_FULL;
 184                 else
 185                         ecmd->duplex = DUPLEX_HALF;
 186         } else {
 187                 ecmd->speed = -1;
 188                 ecmd->duplex = -1;
 189         }
 190
 191         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 192         return 0;
 193 }
 194
 195 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 196 {
 197         struct igb_adapter *adapter = netdev_priv(netdev);
 198         struct e1000_hw *hw = &adapter->hw;
 199
 200         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 201          * cannot be changed */
 202         if (igb_check_reset_block(hw)) {
 203                 dev_err(&adapter->pdev->dev, "Cannot change link "
 204                         "characteristics when SoL/IDER is active.\n");
 205                 return -EINVAL;
 206         }
 207
 208         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 209                 msleep(1);
 210
 211         if (ecmd->autoneg == AUTONEG_ENABLE) {
 212                 hw->mac.autoneg = 1;
 213                 hw->phy.autoneg_advertised = ecmd->advertising |
 214                                              ADVERTISED_TP |
 215                                              ADVERTISED_Autoneg;
 216                 ecmd->advertising = hw->phy.autoneg_advertised;
 217                 if (adapter->fc_autoneg)
 218                         hw->fc.requested_mode = e1000_fc_default;
 219         } else {
 220                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 221                         clear_bit(__IGB_RESETTING, &adapter->state);
 222                         return -EINVAL;
 223                 }
 224         }
 225
 226         /* reset the link */
 227         if (netif_running(adapter->netdev)) {
 228                 igb_down(adapter);
 229                 igb_up(adapter);
 230         } else
 231                 igb_reset(adapter);
 232
 233         clear_bit(__IGB_RESETTING, &adapter->state);
 234         return 0;
 235 }
 236
 237 static void igb_get_pauseparam(struct net_device *netdev,
 238                                struct ethtool_pauseparam *pause)
 239 {
 240         struct igb_adapter *adapter = netdev_priv(netdev);
 241         struct e1000_hw *hw = &adapter->hw;
 242
 243         pause->autoneg =
 244                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 245
 246         if (hw->fc.current_mode == e1000_fc_rx_pause)
 247                 pause->rx_pause = 1;
 248         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 249                 pause->tx_pause = 1;
 250         else if (hw->fc.current_mode == e1000_fc_full) {
 251                 pause->rx_pause = 1;
 252                 pause->tx_pause = 1;
 253         }
 254 }
 255
 256 static int igb_set_pauseparam(struct net_device *netdev,
 257                               struct ethtool_pauseparam *pause)
 258 {
 259         struct igb_adapter *adapter = netdev_priv(netdev);
 260         struct e1000_hw *hw = &adapter->hw;
 261         int retval = 0;
 262
 263         adapter->fc_autoneg = pause->autoneg;
 264
 265         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 266                 msleep(1);
 267
 268         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 269                 hw->fc.requested_mode = e1000_fc_default;
 270                 if (netif_running(adapter->netdev)) {
 271                         igb_down(adapter);
 272                         igb_up(adapter);
 273                 } else {
 274                         igb_reset(adapter);
 275                 }
 276         } else {
 277                 if (pause->rx_pause && pause->tx_pause)
 278                         hw->fc.requested_mode = e1000_fc_full;
 279                 else if (pause->rx_pause && !pause->tx_pause)
 280                         hw->fc.requested_mode = e1000_fc_rx_pause;
 281                 else if (!pause->rx_pause && pause->tx_pause)
 282                         hw->fc.requested_mode = e1000_fc_tx_pause;
 283                 else if (!pause->rx_pause && !pause->tx_pause)
 284                         hw->fc.requested_mode = e1000_fc_none;
 285
 286                 hw->fc.current_mode = hw->fc.requested_mode;
 287
 288                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 289                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 290         }
 291
 292         clear_bit(__IGB_RESETTING, &adapter->state);
 293         return retval;
 294 }
 295
 296 static u32 igb_get_rx_csum(struct net_device *netdev)
 297 {
 298         struct igb_adapter *adapter = netdev_priv(netdev);
 299         return !!(adapter->rx_ring[0].flags & IGB_RING_FLAG_RX_CSUM);
 300 }
 301
 302 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 303 {
 304         struct igb_adapter *adapter = netdev_priv(netdev);
 305         int i;
 306
 307         for (i = 0; i < adapter->num_rx_queues; i++) {
 308                 if (data)
 309                         adapter->rx_ring[i].flags |= IGB_RING_FLAG_RX_CSUM;
 310                 else
 311                         adapter->rx_ring[i].flags &= ~IGB_RING_FLAG_RX_CSUM;
 312         }
 313
 314         return 0;
 315 }
 316
 317 static u32 igb_get_tx_csum(struct net_device *netdev)
 318 {
 319         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 320 }
 321
 322 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 323 {
 324         struct igb_adapter *adapter = netdev_priv(netdev);
 325
 326         if (data) {
 327                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 328                 if (adapter->hw.mac.type >= e1000_82576)
 329                         netdev->features |= NETIF_F_SCTP_CSUM;
 330         } else {
 331                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 332                                       NETIF_F_SCTP_CSUM);
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int igb_set_tso(struct net_device *netdev, u32 data)
 339 {
 340         struct igb_adapter *adapter = netdev_priv(netdev);
 341
 342         if (data) {
 343                 netdev->features |= NETIF_F_TSO;
 344                 netdev->features |= NETIF_F_TSO6;
 345         } else {
 346                 netdev->features &= ~NETIF_F_TSO;
 347                 netdev->features &= ~NETIF_F_TSO6;
 348         }
 349
 350         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 351                  data ? "Enabled" : "Disabled");
 352         return 0;
 353 }
 354
 355 static u32 igb_get_msglevel(struct net_device *netdev)
 356 {
 357         struct igb_adapter *adapter = netdev_priv(netdev);
 358         return adapter->msg_enable;
 359 }
 360
 361 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 362 {
 363         struct igb_adapter *adapter = netdev_priv(netdev);
 364         adapter->msg_enable = data;
 365 }
 366
 367 static int igb_get_regs_len(struct net_device *netdev)
 368 {
 369 #define IGB_REGS_LEN 551
 370         return IGB_REGS_LEN * sizeof(u32);
 371 }
 372
 373 static void igb_get_regs(struct net_device *netdev,
 374                          struct ethtool_regs *regs, void *p)
 375 {
 376         struct igb_adapter *adapter = netdev_priv(netdev);
 377         struct e1000_hw *hw = &adapter->hw;
 378         u32 *regs_buff = p;
 379         u8 i;
 380
 381         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 382
 383         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 384
 385         /* General Registers */
 386         regs_buff[0] = rd32(E1000_CTRL);
 387         regs_buff[1] = rd32(E1000_STATUS);
 388         regs_buff[2] = rd32(E1000_CTRL_EXT);
 389         regs_buff[3] = rd32(E1000_MDIC);
 390         regs_buff[4] = rd32(E1000_SCTL);
 391         regs_buff[5] = rd32(E1000_CONNSW);
 392         regs_buff[6] = rd32(E1000_VET);
 393         regs_buff[7] = rd32(E1000_LEDCTL);
 394         regs_buff[8] = rd32(E1000_PBA);
 395         regs_buff[9] = rd32(E1000_PBS);
 396         regs_buff[10] = rd32(E1000_FRTIMER);
 397         regs_buff[11] = rd32(E1000_TCPTIMER);
 398
 399         /* NVM Register */
 400         regs_buff[12] = rd32(E1000_EECD);
 401
 402         /* Interrupt */
 403         /* Reading EICS for EICR because they read the
 404          * same but EICS does not clear on read */
 405         regs_buff[13] = rd32(E1000_EICS);
 406         regs_buff[14] = rd32(E1000_EICS);
 407         regs_buff[15] = rd32(E1000_EIMS);
 408         regs_buff[16] = rd32(E1000_EIMC);
 409         regs_buff[17] = rd32(E1000_EIAC);
 410         regs_buff[18] = rd32(E1000_EIAM);
 411         /* Reading ICS for ICR because they read the
 412          * same but ICS does not clear on read */
 413         regs_buff[19] = rd32(E1000_ICS);
 414         regs_buff[20] = rd32(E1000_ICS);
 415         regs_buff[21] = rd32(E1000_IMS);
 416         regs_buff[22] = rd32(E1000_IMC);
 417         regs_buff[23] = rd32(E1000_IAC);
 418         regs_buff[24] = rd32(E1000_IAM);
 419         regs_buff[25] = rd32(E1000_IMIRVP);
 420
 421         /* Flow Control */
 422         regs_buff[26] = rd32(E1000_FCAL);
 423         regs_buff[27] = rd32(E1000_FCAH);
 424         regs_buff[28] = rd32(E1000_FCTTV);
 425         regs_buff[29] = rd32(E1000_FCRTL);
 426         regs_buff[30] = rd32(E1000_FCRTH);
 427         regs_buff[31] = rd32(E1000_FCRTV);
 428
 429         /* Receive */
 430         regs_buff[32] = rd32(E1000_RCTL);
 431         regs_buff[33] = rd32(E1000_RXCSUM);
 432         regs_buff[34] = rd32(E1000_RLPML);
 433         regs_buff[35] = rd32(E1000_RFCTL);
 434         regs_buff[36] = rd32(E1000_MRQC);
 435         regs_buff[37] = rd32(E1000_VT_CTL);
 436
 437         /* Transmit */
 438         regs_buff[38] = rd32(E1000_TCTL);
 439         regs_buff[39] = rd32(E1000_TCTL_EXT);
 440         regs_buff[40] = rd32(E1000_TIPG);
 441         regs_buff[41] = rd32(E1000_DTXCTL);
 442
 443         /* Wake Up */
 444         regs_buff[42] = rd32(E1000_WUC);
 445         regs_buff[43] = rd32(E1000_WUFC);
 446         regs_buff[44] = rd32(E1000_WUS);
 447         regs_buff[45] = rd32(E1000_IPAV);
 448         regs_buff[46] = rd32(E1000_WUPL);
 449
 450         /* MAC */
 451         regs_buff[47] = rd32(E1000_PCS_CFG0);
 452         regs_buff[48] = rd32(E1000_PCS_LCTL);
 453         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 454         regs_buff[50] = rd32(E1000_PCS_ANADV);
 455         regs_buff[51] = rd32(E1000_PCS_LPAB);
 456         regs_buff[52] = rd32(E1000_PCS_NPTX);
 457         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 458
 459         /* Statistics */
 460         regs_buff[54] = adapter->stats.crcerrs;
 461         regs_buff[55] = adapter->stats.algnerrc;
 462         regs_buff[56] = adapter->stats.symerrs;
 463         regs_buff[57] = adapter->stats.rxerrc;
 464         regs_buff[58] = adapter->stats.mpc;
 465         regs_buff[59] = adapter->stats.scc;
 466         regs_buff[60] = adapter->stats.ecol;
 467         regs_buff[61] = adapter->stats.mcc;
 468         regs_buff[62] = adapter->stats.latecol;
 469         regs_buff[63] = adapter->stats.colc;
 470         regs_buff[64] = adapter->stats.dc;
 471         regs_buff[65] = adapter->stats.tncrs;
 472         regs_buff[66] = adapter->stats.sec;
 473         regs_buff[67] = adapter->stats.htdpmc;
 474         regs_buff[68] = adapter->stats.rlec;
 475         regs_buff[69] = adapter->stats.xonrxc;
 476         regs_buff[70] = adapter->stats.xontxc;
 477         regs_buff[71] = adapter->stats.xoffrxc;
 478         regs_buff[72] = adapter->stats.xofftxc;
 479         regs_buff[73] = adapter->stats.fcruc;
 480         regs_buff[74] = adapter->stats.prc64;
 481         regs_buff[75] = adapter->stats.prc127;
 482         regs_buff[76] = adapter->stats.prc255;
 483         regs_buff[77] = adapter->stats.prc511;
 484         regs_buff[78] = adapter->stats.prc1023;
 485         regs_buff[79] = adapter->stats.prc1522;
 486         regs_buff[80] = adapter->stats.gprc;
 487         regs_buff[81] = adapter->stats.bprc;
 488         regs_buff[82] = adapter->stats.mprc;
 489         regs_buff[83] = adapter->stats.gptc;
 490         regs_buff[84] = adapter->stats.gorc;
 491         regs_buff[86] = adapter->stats.gotc;
 492         regs_buff[88] = adapter->stats.rnbc;
 493         regs_buff[89] = adapter->stats.ruc;
 494         regs_buff[90] = adapter->stats.rfc;
 495         regs_buff[91] = adapter->stats.roc;
 496         regs_buff[92] = adapter->stats.rjc;
 497         regs_buff[93] = adapter->stats.mgprc;
 498         regs_buff[94] = adapter->stats.mgpdc;
 499         regs_buff[95] = adapter->stats.mgptc;
 500         regs_buff[96] = adapter->stats.tor;
 501         regs_buff[98] = adapter->stats.tot;
 502         regs_buff[100] = adapter->stats.tpr;
 503         regs_buff[101] = adapter->stats.tpt;
 504         regs_buff[102] = adapter->stats.ptc64;
 505         regs_buff[103] = adapter->stats.ptc127;
 506         regs_buff[104] = adapter->stats.ptc255;
 507         regs_buff[105] = adapter->stats.ptc511;
 508         regs_buff[106] = adapter->stats.ptc1023;
 509         regs_buff[107] = adapter->stats.ptc1522;
 510         regs_buff[108] = adapter->stats.mptc;
 511         regs_buff[109] = adapter->stats.bptc;
 512         regs_buff[110] = adapter->stats.tsctc;
 513         regs_buff[111] = adapter->stats.iac;
 514         regs_buff[112] = adapter->stats.rpthc;
 515         regs_buff[113] = adapter->stats.hgptc;
 516         regs_buff[114] = adapter->stats.hgorc;
 517         regs_buff[116] = adapter->stats.hgotc;
 518         regs_buff[118] = adapter->stats.lenerrs;
 519         regs_buff[119] = adapter->stats.scvpc;
 520         regs_buff[120] = adapter->stats.hrmpc;
 521
 522         for (i = 0; i < 4; i++)
 523                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 524         for (i = 0; i < 4; i++)
 525                 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
 526         for (i = 0; i < 4; i++)
 527                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 528         for (i = 0; i < 4; i++)
 529                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 530         for (i = 0; i < 4; i++)
 531                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 532         for (i = 0; i < 4; i++)
 533                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 534         for (i = 0; i < 4; i++)
 535                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 536         for (i = 0; i < 4; i++)
 537                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 538
 539         for (i = 0; i < 10; i++)
 540                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 541         for (i = 0; i < 8; i++)
 542                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 543         for (i = 0; i < 8; i++)
 544                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 545         for (i = 0; i < 16; i++)
 546                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 547         for (i = 0; i < 16; i++)
 548                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 549
 550         for (i = 0; i < 4; i++)
 551                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 552         for (i = 0; i < 4; i++)
 553                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 554         for (i = 0; i < 4; i++)
 555                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 556         for (i = 0; i < 4; i++)
 557                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 558         for (i = 0; i < 4; i++)
 559                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 560         for (i = 0; i < 4; i++)
 561                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 562         for (i = 0; i < 4; i++)
 563                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 564         for (i = 0; i < 4; i++)
 565                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 566         for (i = 0; i < 4; i++)
 567                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 568
 569         for (i = 0; i < 4; i++)
 570                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 571         for (i = 0; i < 4; i++)
 572                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 573         for (i = 0; i < 32; i++)
 574                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 575         for (i = 0; i < 128; i++)
 576                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 577         for (i = 0; i < 128; i++)
 578                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 579         for (i = 0; i < 4; i++)
 580                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 581
 582         regs_buff[547] = rd32(E1000_TDFH);
 583         regs_buff[548] = rd32(E1000_TDFT);
 584         regs_buff[549] = rd32(E1000_TDFHS);
 585         regs_buff[550] = rd32(E1000_TDFPC);
 586
 587 }
 588
 589 static int igb_get_eeprom_len(struct net_device *netdev)
 590 {
 591         struct igb_adapter *adapter = netdev_priv(netdev);
 592         return adapter->hw.nvm.word_size * 2;
 593 }
 594
 595 static int igb_get_eeprom(struct net_device *netdev,
 596                           struct ethtool_eeprom *eeprom, u8 *bytes)
 597 {
 598         struct igb_adapter *adapter = netdev_priv(netdev);
 599         struct e1000_hw *hw = &adapter->hw;
 600         u16 *eeprom_buff;
 601         int first_word, last_word;
 602         int ret_val = 0;
 603         u16 i;
 604
 605         if (eeprom->len == 0)
 606                 return -EINVAL;
 607
 608         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 609
 610         first_word = eeprom->offset >> 1;
 611         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 612
 613         eeprom_buff = kmalloc(sizeof(u16) *
 614                         (last_word - first_word + 1), GFP_KERNEL);
 615         if (!eeprom_buff)
 616                 return -ENOMEM;
 617
 618         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 619                 ret_val = hw->nvm.ops.read(hw, first_word,
 620                                             last_word - first_word + 1,
 621                                             eeprom_buff);
 622         else {
 623                 for (i = 0; i < last_word - first_word + 1; i++) {
 624                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 625                                                     &eeprom_buff[i]);
 626                         if (ret_val)
 627                                 break;
 628                 }
 629         }
 630
 631         /* Device's eeprom is always little-endian, word addressable */
 632         for (i = 0; i < last_word - first_word + 1; i++)
 633                 le16_to_cpus(&eeprom_buff[i]);
 634
 635         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 636                         eeprom->len);
 637         kfree(eeprom_buff);
 638
 639         return ret_val;
 640 }
 641
 642 static int igb_set_eeprom(struct net_device *netdev,
 643                           struct ethtool_eeprom *eeprom, u8 *bytes)
 644 {
 645         struct igb_adapter *adapter = netdev_priv(netdev);
 646         struct e1000_hw *hw = &adapter->hw;
 647         u16 *eeprom_buff;
 648         void *ptr;
 649         int max_len, first_word, last_word, ret_val = 0;
 650         u16 i;
 651
 652         if (eeprom->len == 0)
 653                 return -EOPNOTSUPP;
 654
 655         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 656                 return -EFAULT;
 657
 658         max_len = hw->nvm.word_size * 2;
 659
 660         first_word = eeprom->offset >> 1;
 661         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 662         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 663         if (!eeprom_buff)
 664                 return -ENOMEM;
 665
 666         ptr = (void *)eeprom_buff;
 667
 668         if (eeprom->offset & 1) {
 669                 /* need read/modify/write of first changed EEPROM word */
 670                 /* only the second byte of the word is being modified */
 671                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 672                                             &eeprom_buff[0]);
 673                 ptr++;
 674         }
 675         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 676                 /* need read/modify/write of last changed EEPROM word */
 677                 /* only the first byte of the word is being modified */
 678                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 679                                    &eeprom_buff[last_word - first_word]);
 680         }
 681
 682         /* Device's eeprom is always little-endian, word addressable */
 683         for (i = 0; i < last_word - first_word + 1; i++)
 684                 le16_to_cpus(&eeprom_buff[i]);
 685
 686         memcpy(ptr, bytes, eeprom->len);
 687
 688         for (i = 0; i < last_word - first_word + 1; i++)
 689                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 690
 691         ret_val = hw->nvm.ops.write(hw, first_word,
 692                                      last_word - first_word + 1, eeprom_buff);
 693
 694         /* Update the checksum over the first part of the EEPROM if needed
 695          * and flush shadow RAM for 82573 controllers */
 696         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 697                 igb_update_nvm_checksum(hw);
 698
 699         kfree(eeprom_buff);
 700         return ret_val;
 701 }
 702
 703 static void igb_get_drvinfo(struct net_device *netdev,
 704                             struct ethtool_drvinfo *drvinfo)
 705 {
 706         struct igb_adapter *adapter = netdev_priv(netdev);
 707         char firmware_version[32];
 708         u16 eeprom_data;
 709
 710         strncpy(drvinfo->driver,  igb_driver_name, 32);
 711         strncpy(drvinfo->version, igb_driver_version, 32);
 712
 713         /* EEPROM image version # is reported as firmware version # for
 714          * 82575 controllers */
 715         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
 716         sprintf(firmware_version, "%d.%d-%d",
 717                 (eeprom_data & 0xF000) >> 12,
 718                 (eeprom_data & 0x0FF0) >> 4,
 719                 eeprom_data & 0x000F);
 720
 721         strncpy(drvinfo->fw_version, firmware_version, 32);
 722         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 723         drvinfo->n_stats = IGB_STATS_LEN;
 724         drvinfo->testinfo_len = IGB_TEST_LEN;
 725         drvinfo->regdump_len = igb_get_regs_len(netdev);
 726         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 727 }
 728
 729 static void igb_get_ringparam(struct net_device *netdev,
 730                               struct ethtool_ringparam *ring)
 731 {
 732         struct igb_adapter *adapter = netdev_priv(netdev);
 733
 734         ring->rx_max_pending = IGB_MAX_RXD;
 735         ring->tx_max_pending = IGB_MAX_TXD;
 736         ring->rx_mini_max_pending = 0;
 737         ring->rx_jumbo_max_pending = 0;
 738         ring->rx_pending = adapter->rx_ring_count;
 739         ring->tx_pending = adapter->tx_ring_count;
 740         ring->rx_mini_pending = 0;
 741         ring->rx_jumbo_pending = 0;
 742 }
 743
 744 static int igb_set_ringparam(struct net_device *netdev,
 745                              struct ethtool_ringparam *ring)
 746 {
 747         struct igb_adapter *adapter = netdev_priv(netdev);
 748         struct igb_ring *temp_ring;
 749         int i, err = 0;
 750         u16 new_rx_count, new_tx_count;
 751
 752         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 753                 return -EINVAL;
 754
 755         new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
 756         new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
 757         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 758
 759         new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
 760         new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
 761         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 762
 763         if ((new_tx_count == adapter->tx_ring_count) &&
 764             (new_rx_count == adapter->rx_ring_count)) {
 765                 /* nothing to do */
 766                 return 0;
 767         }
 768
 769         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 770                 msleep(1);
 771
 772         if (!netif_running(adapter->netdev)) {
 773                 for (i = 0; i < adapter->num_tx_queues; i++)
 774                         adapter->tx_ring[i].count = new_tx_count;
 775                 for (i = 0; i < adapter->num_rx_queues; i++)
 776                         adapter->rx_ring[i].count = new_rx_count;
 777                 adapter->tx_ring_count = new_tx_count;
 778                 adapter->rx_ring_count = new_rx_count;
 779                 goto clear_reset;
 780         }
 781
 782         if (adapter->num_tx_queues > adapter->num_rx_queues)
 783                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 784         else
 785                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 786
 787         if (!temp_ring) {
 788                 err = -ENOMEM;
 789                 goto clear_reset;
 790         }
 791
 792         igb_down(adapter);
 793
 794         /*
 795          * We can't just free everything and then setup again,
 796          * because the ISRs in MSI-X mode get passed pointers
 797          * to the tx and rx ring structs.
 798          */
 799         if (new_tx_count != adapter->tx_ring_count) {
 800                 memcpy(temp_ring, adapter->tx_ring,
 801                        adapter->num_tx_queues * sizeof(struct igb_ring));
 802
 803                 for (i = 0; i < adapter->num_tx_queues; i++) {
 804                         temp_ring[i].count = new_tx_count;
 805                         err = igb_setup_tx_resources(&temp_ring[i]);
 806                         if (err) {
 807                                 while (i) {
 808                                         i--;
 809                                         igb_free_tx_resources(&temp_ring[i]);
 810                                 }
 811                                 goto err_setup;
 812                         }
 813                 }
 814
 815                 for (i = 0; i < adapter->num_tx_queues; i++)
 816                         igb_free_tx_resources(&adapter->tx_ring[i]);
 817
 818                 memcpy(adapter->tx_ring, temp_ring,
 819                        adapter->num_tx_queues * sizeof(struct igb_ring));
 820
 821                 adapter->tx_ring_count = new_tx_count;
 822         }
 823
 824         if (new_rx_count != adapter->rx_ring->count) {
 825                 memcpy(temp_ring, adapter->rx_ring,
 826                        adapter->num_rx_queues * sizeof(struct igb_ring));
 827
 828                 for (i = 0; i < adapter->num_rx_queues; i++) {
 829                         temp_ring[i].count = new_rx_count;
 830                         err = igb_setup_rx_resources(&temp_ring[i]);
 831                         if (err) {
 832                                 while (i) {
 833                                         i--;
 834                                         igb_free_rx_resources(&temp_ring[i]);
 835                                 }
 836                                 goto err_setup;
 837                         }
 838
 839                 }
 840
 841                 for (i = 0; i < adapter->num_rx_queues; i++)
 842                         igb_free_rx_resources(&adapter->rx_ring[i]);
 843
 844                 memcpy(adapter->rx_ring, temp_ring,
 845                        adapter->num_rx_queues * sizeof(struct igb_ring));
 846
 847                 adapter->rx_ring_count = new_rx_count;
 848         }
 849 err_setup:
 850         igb_up(adapter);
 851         vfree(temp_ring);
 852 clear_reset:
 853         clear_bit(__IGB_RESETTING, &adapter->state);
 854         return err;
 855 }
 856
 857 /* ethtool register test data */
 858 struct igb_reg_test {
 859         u16 reg;
 860         u16 reg_offset;
 861         u16 array_len;
 862         u16 test_type;
 863         u32 mask;
 864         u32 write;
 865 };
 866
 867 /* In the hardware, registers are laid out either singly, in arrays
 868  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 869  * most tests take place on arrays or single registers (handled
 870  * as a single-element array) and special-case the tables.
 871  * Table tests are always pattern tests.
 872  *
 873  * We also make provision for some required setup steps by specifying
 874  * registers to be written without any read-back testing.
 875  */
 876
 877 #define PATTERN_TEST    1
 878 #define SET_READ_TEST   2
 879 #define WRITE_NO_TEST   3
 880 #define TABLE32_TEST    4
 881 #define TABLE64_TEST_LO 5
 882 #define TABLE64_TEST_HI 6
 883
 884 /* 82580 reg test */
 885 static struct igb_reg_test reg_test_82580[] = {
 886         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 887         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 888         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 889         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 890         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 891         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 892         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 893         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 894         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 895         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 896         /* RDH is read-only for 82580, only test RDT. */
 897         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 898         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 899         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 900         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 901         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 902         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 903         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 904         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 905         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 906         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 907         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 908         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 909         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 910         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 911         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 912         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 913         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 914         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 915                                                 0xFFFFFFFF, 0xFFFFFFFF },
 916         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 917                                                 0x83FFFFFF, 0xFFFFFFFF },
 918         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
 919                                                 0xFFFFFFFF, 0xFFFFFFFF },
 920         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
 921                                                 0x83FFFFFF, 0xFFFFFFFF },
 922         { E1000_MTA,       0, 128, TABLE32_TEST,
 923                                                 0xFFFFFFFF, 0xFFFFFFFF },
 924         { 0, 0, 0, 0 }
 925 };
 926
 927 /* 82576 reg test */
 928 static struct igb_reg_test reg_test_82576[] = {
 929         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 930         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 931         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 932         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 933         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 934         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 935         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 936         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 937         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 938         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 939         /* Enable all RX queues before testing. */
 940         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 941         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 942         /* RDH is read-only for 82576, only test RDT. */
 943         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 944         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 945         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 946         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
 947         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 948         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 949         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 950         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 951         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 952         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 953         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 954         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 955         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 956         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 957         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 958         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 959         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 960         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 961         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 962         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 963         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 964         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 965         { 0, 0, 0, 0 }
 966 };
 967
 968 /* 82575 register test */
 969 static struct igb_reg_test reg_test_82575[] = {
 970         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 971         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 972         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 973         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 974         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 975         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 976         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 977         /* Enable all four RX queues before testing. */
 978         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 979         /* RDH is read-only for 82575, only test RDT. */
 980         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 981         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
 982         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 983         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 984         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 985         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 986         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 987         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 988         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 989         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 990         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 991         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 992         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 993         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 994         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
 995         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 996         { 0, 0, 0, 0 }
 997 };
 998
 999 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1000                              int reg, u32 mask, u32 write)
1001 {
1002         struct e1000_hw *hw = &adapter->hw;
1003         u32 pat, val;
1004         static const u32 _test[] =
1005                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1006         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1007                 wr32(reg, (_test[pat] & write));
1008                 val = rd32(reg);
1009                 if (val != (_test[pat] & write & mask)) {
1010                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1011                                 "failed: got 0x%08X expected 0x%08X\n",
1012                                 reg, val, (_test[pat] & write & mask));
1013                         *data = reg;
1014                         return 1;
1015                 }
1016         }
1017
1018         return 0;
1019 }
1020
1021 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1022                               int reg, u32 mask, u32 write)
1023 {
1024         struct e1000_hw *hw = &adapter->hw;
1025         u32 val;
1026         wr32(reg, write & mask);
1027         val = rd32(reg);
1028         if ((write & mask) != (val & mask)) {
1029                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1030                         " got 0x%08X expected 0x%08X\n", reg,
1031                         (val & mask), (write & mask));
1032                 *data = reg;
1033                 return 1;
1034         }
1035
1036         return 0;
1037 }
1038
1039 #define REG_PATTERN_TEST(reg, mask, write) \
1040         do { \
1041                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1042                         return 1; \
1043         } while (0)
1044
1045 #define REG_SET_AND_CHECK(reg, mask, write) \
1046         do { \
1047                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1048                         return 1; \
1049         } while (0)
1050
1051 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1052 {
1053         struct e1000_hw *hw = &adapter->hw;
1054         struct igb_reg_test *test;
1055         u32 value, before, after;
1056         u32 i, toggle;
1057
1058         switch (adapter->hw.mac.type) {
1059         case e1000_82580:
1060                 test = reg_test_82580;
1061                 toggle = 0x7FEFF3FF;
1062                 break;
1063         case e1000_82576:
1064                 test = reg_test_82576;
1065                 toggle = 0x7FFFF3FF;
1066                 break;
1067         default:
1068                 test = reg_test_82575;
1069                 toggle = 0x7FFFF3FF;
1070                 break;
1071         }
1072
1073         /* Because the status register is such a special case,
1074          * we handle it separately from the rest of the register
1075          * tests.  Some bits are read-only, some toggle, and some
1076          * are writable on newer MACs.
1077          */
1078         before = rd32(E1000_STATUS);
1079         value = (rd32(E1000_STATUS) & toggle);
1080         wr32(E1000_STATUS, toggle);
1081         after = rd32(E1000_STATUS) & toggle;
1082         if (value != after) {
1083                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1084                         "got: 0x%08X expected: 0x%08X\n", after, value);
1085                 *data = 1;
1086                 return 1;
1087         }
1088         /* restore previous status */
1089         wr32(E1000_STATUS, before);
1090
1091         /* Perform the remainder of the register test, looping through
1092          * the test table until we either fail or reach the null entry.
1093          */
1094         while (test->reg) {
1095                 for (i = 0; i < test->array_len; i++) {
1096                         switch (test->test_type) {
1097                         case PATTERN_TEST:
1098                                 REG_PATTERN_TEST(test->reg +
1099                                                 (i * test->reg_offset),
1100                                                 test->mask,
1101                                                 test->write);
1102                                 break;
1103                         case SET_READ_TEST:
1104                                 REG_SET_AND_CHECK(test->reg +
1105                                                 (i * test->reg_offset),
1106                                                 test->mask,
1107                                                 test->write);
1108                                 break;
1109                         case WRITE_NO_TEST:
1110                                 writel(test->write,
1111                                     (adapter->hw.hw_addr + test->reg)
1112                                         + (i * test->reg_offset));
1113                                 break;
1114                         case TABLE32_TEST:
1115                                 REG_PATTERN_TEST(test->reg + (i * 4),
1116                                                 test->mask,
1117                                                 test->write);
1118                                 break;
1119                         case TABLE64_TEST_LO:
1120                                 REG_PATTERN_TEST(test->reg + (i * 8),
1121                                                 test->mask,
1122                                                 test->write);
1123                                 break;
1124                         case TABLE64_TEST_HI:
1125                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1126                                                 test->mask,
1127                                                 test->write);
1128                                 break;
1129                         }
1130                 }
1131                 test++;
1132         }
1133
1134         *data = 0;
1135         return 0;
1136 }
1137
1138 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1139 {
1140         u16 temp;
1141         u16 checksum = 0;
1142         u16 i;
1143
1144         *data = 0;
1145         /* Read and add up the contents of the EEPROM */
1146         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1147                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
1148                         *data = 1;
1149                         break;
1150                 }
1151                 checksum += temp;
1152         }
1153
1154         /* If Checksum is not Correct return error else test passed */
1155         if ((checksum != (u16) NVM_SUM) && !(*data))
1156                 *data = 2;
1157
1158         return *data;
1159 }
1160
1161 static irqreturn_t igb_test_intr(int irq, void *data)
1162 {
1163         struct igb_adapter *adapter = (struct igb_adapter *) data;
1164         struct e1000_hw *hw = &adapter->hw;
1165
1166         adapter->test_icr |= rd32(E1000_ICR);
1167
1168         return IRQ_HANDLED;
1169 }
1170
1171 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1172 {
1173         struct e1000_hw *hw = &adapter->hw;
1174         struct net_device *netdev = adapter->netdev;
1175         u32 mask, ics_mask, i = 0, shared_int = true;
1176         u32 irq = adapter->pdev->irq;
1177
1178         *data = 0;
1179
1180         /* Hook up test interrupt handler just for this test */
1181         if (adapter->msix_entries) {
1182                 if (request_irq(adapter->msix_entries[0].vector,
1183                                 igb_test_intr, 0, netdev->name, adapter)) {
1184                         *data = 1;
1185                         return -1;
1186                 }
1187         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1188                 shared_int = false;
1189                 if (request_irq(irq,
1190                                 igb_test_intr, 0, netdev->name, adapter)) {
1191                         *data = 1;
1192                         return -1;
1193                 }
1194         } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1195                                 netdev->name, adapter)) {
1196                 shared_int = false;
1197         } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1198                  netdev->name, adapter)) {
1199                 *data = 1;
1200                 return -1;
1201         }
1202         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1203                 (shared_int ? "shared" : "unshared"));
1204
1205         /* Disable all the interrupts */
1206         wr32(E1000_IMC, ~0);
1207         msleep(10);
1208
1209         /* Define all writable bits for ICS */
1210         switch (hw->mac.type) {
1211         case e1000_82575:
1212                 ics_mask = 0x37F47EDD;
1213                 break;
1214         case e1000_82576:
1215                 ics_mask = 0x77D4FBFD;
1216                 break;
1217         case e1000_82580:
1218                 ics_mask = 0x77DCFED5;
1219                 break;
1220         default:
1221                 ics_mask = 0x7FFFFFFF;
1222                 break;
1223         }
1224
1225         /* Test each interrupt */
1226         for (; i < 31; i++) {
1227                 /* Interrupt to test */
1228                 mask = 1 << i;
1229
1230                 if (!(mask & ics_mask))
1231                         continue;
1232
1233                 if (!shared_int) {
1234                         /* Disable the interrupt to be reported in
1235                          * the cause register and then force the same
1236                          * interrupt and see if one gets posted.  If
1237                          * an interrupt was posted to the bus, the
1238                          * test failed.
1239                          */
1240                         adapter->test_icr = 0;
1241
1242                         /* Flush any pending interrupts */
1243                         wr32(E1000_ICR, ~0);
1244
1245                         wr32(E1000_IMC, mask);
1246                         wr32(E1000_ICS, mask);
1247                         msleep(10);
1248
1249                         if (adapter->test_icr & mask) {
1250                                 *data = 3;
1251                                 break;
1252                         }
1253                 }
1254
1255                 /* Enable the interrupt to be reported in
1256                  * the cause register and then force the same
1257                  * interrupt and see if one gets posted.  If
1258                  * an interrupt was not posted to the bus, the
1259                  * test failed.
1260                  */
1261                 adapter->test_icr = 0;
1262
1263                 /* Flush any pending interrupts */
1264                 wr32(E1000_ICR, ~0);
1265
1266                 wr32(E1000_IMS, mask);
1267                 wr32(E1000_ICS, mask);
1268                 msleep(10);
1269
1270                 if (!(adapter->test_icr & mask)) {
1271                         *data = 4;
1272                         break;
1273                 }
1274
1275                 if (!shared_int) {
1276                         /* Disable the other interrupts to be reported in
1277                          * the cause register and then force the other
1278                          * interrupts and see if any get posted.  If
1279                          * an interrupt was posted to the bus, the
1280                          * test failed.
1281                          */
1282                         adapter->test_icr = 0;
1283
1284                         /* Flush any pending interrupts */
1285                         wr32(E1000_ICR, ~0);
1286
1287                         wr32(E1000_IMC, ~mask);
1288                         wr32(E1000_ICS, ~mask);
1289                         msleep(10);
1290
1291                         if (adapter->test_icr & mask) {
1292                                 *data = 5;
1293                                 break;
1294                         }
1295                 }
1296         }
1297
1298         /* Disable all the interrupts */
1299         wr32(E1000_IMC, ~0);
1300         msleep(10);
1301
1302         /* Unhook test interrupt handler */
1303         if (adapter->msix_entries)
1304                 free_irq(adapter->msix_entries[0].vector, adapter);
1305         else
1306                 free_irq(irq, adapter);
1307
1308         return *data;
1309 }
1310
1311 static void igb_free_desc_rings(struct igb_adapter *adapter)
1312 {
1313         igb_free_tx_resources(&adapter->test_tx_ring);
1314         igb_free_rx_resources(&adapter->test_rx_ring);
1315 }
1316
1317 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1318 {
1319         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1320         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1321         struct e1000_hw *hw = &adapter->hw;
1322         int ret_val;
1323
1324         /* Setup Tx descriptor ring and Tx buffers */
1325         tx_ring->count = IGB_DEFAULT_TXD;
1326         tx_ring->pdev = adapter->pdev;
1327         tx_ring->netdev = adapter->netdev;
1328         tx_ring->reg_idx = adapter->vfs_allocated_count;
1329
1330         if (igb_setup_tx_resources(tx_ring)) {
1331                 ret_val = 1;
1332                 goto err_nomem;
1333         }
1334
1335         igb_setup_tctl(adapter);
1336         igb_configure_tx_ring(adapter, tx_ring);
1337
1338         /* Setup Rx descriptor ring and Rx buffers */
1339         rx_ring->count = IGB_DEFAULT_RXD;
1340         rx_ring->pdev = adapter->pdev;
1341         rx_ring->netdev = adapter->netdev;
1342         rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1343         rx_ring->reg_idx = adapter->vfs_allocated_count;
1344
1345         if (igb_setup_rx_resources(rx_ring)) {
1346                 ret_val = 3;
1347                 goto err_nomem;
1348         }
1349
1350         /* set the default queue to queue 0 of PF */
1351         wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1352
1353         /* enable receive ring */
1354         igb_setup_rctl(adapter);
1355         igb_configure_rx_ring(adapter, rx_ring);
1356
1357         igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
1358
1359         return 0;
1360
1361 err_nomem:
1362         igb_free_desc_rings(adapter);
1363         return ret_val;
1364 }
1365
1366 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1367 {
1368         struct e1000_hw *hw = &adapter->hw;
1369
1370         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1371         igb_write_phy_reg(hw, 29, 0x001F);
1372         igb_write_phy_reg(hw, 30, 0x8FFC);
1373         igb_write_phy_reg(hw, 29, 0x001A);
1374         igb_write_phy_reg(hw, 30, 0x8FF0);
1375 }
1376
1377 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1378 {
1379         struct e1000_hw *hw = &adapter->hw;
1380         u32 ctrl_reg = 0;
1381
1382         hw->mac.autoneg = false;
1383
1384         if (hw->phy.type == e1000_phy_m88) {
1385                 /* Auto-MDI/MDIX Off */
1386                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1387                 /* reset to update Auto-MDI/MDIX */
1388                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1389                 /* autoneg off */
1390                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1391         } else if (hw->phy.type == e1000_phy_82580) {
1392                 /* enable MII loopback */
1393                 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1394         }
1395
1396         ctrl_reg = rd32(E1000_CTRL);
1397
1398         /* force 1000, set loopback */
1399         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1400
1401         /* Now set up the MAC to the same speed/duplex as the PHY. */
1402         ctrl_reg = rd32(E1000_CTRL);
1403         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1404         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1405                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1406                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1407                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1408                      E1000_CTRL_SLU);    /* Set link up enable bit */
1409
1410         if (hw->phy.type == e1000_phy_m88)
1411                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1412
1413         wr32(E1000_CTRL, ctrl_reg);
1414
1415         /* Disable the receiver on the PHY so when a cable is plugged in, the
1416          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1417          */
1418         if (hw->phy.type == e1000_phy_m88)
1419                 igb_phy_disable_receiver(adapter);
1420
1421         udelay(500);
1422
1423         return 0;
1424 }
1425
1426 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1427 {
1428         return igb_integrated_phy_loopback(adapter);
1429 }
1430
1431 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1432 {
1433         struct e1000_hw *hw = &adapter->hw;
1434         u32 reg;
1435
1436         reg = rd32(E1000_CTRL_EXT);
1437
1438         /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1439         if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1440                 reg = rd32(E1000_RCTL);
1441                 reg |= E1000_RCTL_LBM_TCVR;
1442                 wr32(E1000_RCTL, reg);
1443
1444                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1445
1446                 reg = rd32(E1000_CTRL);
1447                 reg &= ~(E1000_CTRL_RFCE |
1448                          E1000_CTRL_TFCE |
1449                          E1000_CTRL_LRST);
1450                 reg |= E1000_CTRL_SLU |
1451                        E1000_CTRL_FD;
1452                 wr32(E1000_CTRL, reg);
1453
1454                 /* Unset switch control to serdes energy detect */
1455                 reg = rd32(E1000_CONNSW);
1456                 reg &= ~E1000_CONNSW_ENRGSRC;
1457                 wr32(E1000_CONNSW, reg);
1458
1459                 /* Set PCS register for forced speed */
1460                 reg = rd32(E1000_PCS_LCTL);
1461                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1462                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1463                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1464                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1465                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1466                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1467                 wr32(E1000_PCS_LCTL, reg);
1468
1469                 return 0;
1470         }
1471
1472         return igb_set_phy_loopback(adapter);
1473 }
1474
1475 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1476 {
1477         struct e1000_hw *hw = &adapter->hw;
1478         u32 rctl;
1479         u16 phy_reg;
1480
1481         rctl = rd32(E1000_RCTL);
1482         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1483         wr32(E1000_RCTL, rctl);
1484
1485         hw->mac.autoneg = true;
1486         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1487         if (phy_reg & MII_CR_LOOPBACK) {
1488                 phy_reg &= ~MII_CR_LOOPBACK;
1489                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1490                 igb_phy_sw_reset(hw);
1491         }
1492 }
1493
1494 static void igb_create_lbtest_frame(struct sk_buff *skb,
1495                                     unsigned int frame_size)
1496 {
1497         memset(skb->data, 0xFF, frame_size);
1498         frame_size /= 2;
1499         memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1500         memset(&skb->data[frame_size + 10], 0xBE, 1);
1501         memset(&skb->data[frame_size + 12], 0xAF, 1);
1502 }
1503
1504 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1505 {
1506         frame_size /= 2;
1507         if (*(skb->data + 3) == 0xFF) {
1508                 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1509                    (*(skb->data + frame_size + 12) == 0xAF)) {
1510                         return 0;
1511                 }
1512         }
1513         return 13;
1514 }
1515
1516 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1517                                 struct igb_ring *tx_ring,
1518                                 unsigned int size)
1519 {
1520         union e1000_adv_rx_desc *rx_desc;
1521         struct igb_buffer *buffer_info;
1522         int rx_ntc, tx_ntc, count = 0;
1523         u32 staterr;
1524
1525         /* initialize next to clean and descriptor values */
1526         rx_ntc = rx_ring->next_to_clean;
1527         tx_ntc = tx_ring->next_to_clean;
1528         rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1529         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1530
1531         while (staterr & E1000_RXD_STAT_DD) {
1532                 /* check rx buffer */
1533                 buffer_info = &rx_ring->buffer_info[rx_ntc];
1534
1535                 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1536                 pci_unmap_single(rx_ring->pdev,
1537                                  buffer_info->dma,
1538                                  rx_ring->rx_buffer_len,
1539                                  PCI_DMA_FROMDEVICE);
1540                 buffer_info->dma = 0;
1541
1542                 /* verify contents of skb */
1543                 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1544                         count++;
1545
1546                 /* unmap buffer on tx side */
1547                 buffer_info = &tx_ring->buffer_info[tx_ntc];
1548                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1549
1550                 /* increment rx/tx next to clean counters */
1551                 rx_ntc++;
1552                 if (rx_ntc == rx_ring->count)
1553                         rx_ntc = 0;
1554                 tx_ntc++;
1555                 if (tx_ntc == tx_ring->count)
1556                         tx_ntc = 0;
1557
1558                 /* fetch next descriptor */
1559                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1560                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1561         }
1562
1563         /* re-map buffers to ring, store next to clean values */
1564         igb_alloc_rx_buffers_adv(rx_ring, count);
1565         rx_ring->next_to_clean = rx_ntc;
1566         tx_ring->next_to_clean = tx_ntc;
1567
1568         return count;
1569 }
1570
1571 static int igb_run_loopback_test(struct igb_adapter *adapter)
1572 {
1573         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1574         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1575         int i, j, lc, good_cnt, ret_val = 0;
1576         unsigned int size = 1024;
1577         netdev_tx_t tx_ret_val;
1578         struct sk_buff *skb;
1579
1580         /* allocate test skb */
1581         skb = alloc_skb(size, GFP_KERNEL);
1582         if (!skb)
1583                 return 11;
1584
1585         /* place data into test skb */
1586         igb_create_lbtest_frame(skb, size);
1587         skb_put(skb, size);
1588
1589         /*
1590          * Calculate the loop count based on the largest descriptor ring
1591          * The idea is to wrap the largest ring a number of times using 64
1592          * send/receive pairs during each loop
1593          */
1594
1595         if (rx_ring->count <= tx_ring->count)
1596                 lc = ((tx_ring->count / 64) * 2) + 1;
1597         else
1598                 lc = ((rx_ring->count / 64) * 2) + 1;
1599
1600         for (j = 0; j <= lc; j++) { /* loop count loop */
1601                 /* reset count of good packets */
1602                 good_cnt = 0;
1603
1604                 /* place 64 packets on the transmit queue*/
1605                 for (i = 0; i < 64; i++) {
1606                         skb_get(skb);
1607                         tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1608                         if (tx_ret_val == NETDEV_TX_OK)
1609                                 good_cnt++;
1610                 }
1611
1612                 if (good_cnt != 64) {
1613                         ret_val = 12;
1614                         break;
1615                 }
1616
1617                 /* allow 200 milliseconds for packets to go from tx to rx */
1618                 msleep(200);
1619
1620                 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1621                 if (good_cnt != 64) {
1622                         ret_val = 13;
1623                         break;
1624                 }
1625         } /* end loop count loop */
1626
1627         /* free the original skb */
1628         kfree_skb(skb);
1629
1630         return ret_val;
1631 }
1632
1633 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1634 {
1635         /* PHY loopback cannot be performed if SoL/IDER
1636          * sessions are active */
1637         if (igb_check_reset_block(&adapter->hw)) {
1638                 dev_err(&adapter->pdev->dev,
1639                         "Cannot do PHY loopback test "
1640                         "when SoL/IDER is active.\n");
1641                 *data = 0;
1642                 goto out;
1643         }
1644         *data = igb_setup_desc_rings(adapter);
1645         if (*data)
1646                 goto out;
1647         *data = igb_setup_loopback_test(adapter);
1648         if (*data)
1649                 goto err_loopback;
1650         *data = igb_run_loopback_test(adapter);
1651         igb_loopback_cleanup(adapter);
1652
1653 err_loopback:
1654         igb_free_desc_rings(adapter);
1655 out:
1656         return *data;
1657 }
1658
1659 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1660 {
1661         struct e1000_hw *hw = &adapter->hw;
1662         *data = 0;
1663         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1664                 int i = 0;
1665                 hw->mac.serdes_has_link = false;
1666
1667                 /* On some blade server designs, link establishment
1668                  * could take as long as 2-3 minutes */
1669                 do {
1670                         hw->mac.ops.check_for_link(&adapter->hw);
1671                         if (hw->mac.serdes_has_link)
1672                                 return *data;
1673                         msleep(20);
1674                 } while (i++ < 3750);
1675
1676                 *data = 1;
1677         } else {
1678                 hw->mac.ops.check_for_link(&adapter->hw);
1679                 if (hw->mac.autoneg)
1680                         msleep(4000);
1681
1682                 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1683                         *data = 1;
1684         }
1685         return *data;
1686 }
1687
1688 static void igb_diag_test(struct net_device *netdev,
1689                           struct ethtool_test *eth_test, u64 *data)
1690 {
1691         struct igb_adapter *adapter = netdev_priv(netdev);
1692         u16 autoneg_advertised;
1693         u8 forced_speed_duplex, autoneg;
1694         bool if_running = netif_running(netdev);
1695
1696         set_bit(__IGB_TESTING, &adapter->state);
1697         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1698                 /* Offline tests */
1699
1700                 /* save speed, duplex, autoneg settings */
1701                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1702                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1703                 autoneg = adapter->hw.mac.autoneg;
1704
1705                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1706
1707                 /* Link test performed before hardware reset so autoneg doesn't
1708                  * interfere with test result */
1709                 if (igb_link_test(adapter, &data[4]))
1710                         eth_test->flags |= ETH_TEST_FL_FAILED;
1711
1712                 if (if_running)
1713                         /* indicate we're in test mode */
1714                         dev_close(netdev);
1715                 else
1716                         igb_reset(adapter);
1717
1718                 if (igb_reg_test(adapter, &data[0]))
1719                         eth_test->flags |= ETH_TEST_FL_FAILED;
1720
1721                 igb_reset(adapter);
1722                 if (igb_eeprom_test(adapter, &data[1]))
1723                         eth_test->flags |= ETH_TEST_FL_FAILED;
1724
1725                 igb_reset(adapter);
1726                 if (igb_intr_test(adapter, &data[2]))
1727                         eth_test->flags |= ETH_TEST_FL_FAILED;
1728
1729                 igb_reset(adapter);
1730                 if (igb_loopback_test(adapter, &data[3]))
1731                         eth_test->flags |= ETH_TEST_FL_FAILED;
1732
1733                 /* restore speed, duplex, autoneg settings */
1734                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1735                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1736                 adapter->hw.mac.autoneg = autoneg;
1737
1738                 /* force this routine to wait until autoneg complete/timeout */
1739                 adapter->hw.phy.autoneg_wait_to_complete = true;
1740                 igb_reset(adapter);
1741                 adapter->hw.phy.autoneg_wait_to_complete = false;
1742
1743                 clear_bit(__IGB_TESTING, &adapter->state);
1744                 if (if_running)
1745                         dev_open(netdev);
1746         } else {
1747                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1748                 /* Online tests */
1749                 if (igb_link_test(adapter, &data[4]))
1750                         eth_test->flags |= ETH_TEST_FL_FAILED;
1751
1752                 /* Online tests aren't run; pass by default */
1753                 data[0] = 0;
1754                 data[1] = 0;
1755                 data[2] = 0;
1756                 data[3] = 0;
1757
1758                 clear_bit(__IGB_TESTING, &adapter->state);
1759         }
1760         msleep_interruptible(4 * 1000);
1761 }
1762
1763 static int igb_wol_exclusion(struct igb_adapter *adapter,
1764                              struct ethtool_wolinfo *wol)
1765 {
1766         struct e1000_hw *hw = &adapter->hw;
1767         int retval = 1; /* fail by default */
1768
1769         switch (hw->device_id) {
1770         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1771                 /* WoL not supported */
1772                 wol->supported = 0;
1773                 break;
1774         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1775         case E1000_DEV_ID_82576_FIBER:
1776         case E1000_DEV_ID_82576_SERDES:
1777                 /* Wake events not supported on port B */
1778                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1779                         wol->supported = 0;
1780                         break;
1781                 }
1782                 /* return success for non excluded adapter ports */
1783                 retval = 0;
1784                 break;
1785         case E1000_DEV_ID_82576_QUAD_COPPER:
1786                 /* quad port adapters only support WoL on port A */
1787                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1788                         wol->supported = 0;
1789                         break;
1790                 }
1791                 /* return success for non excluded adapter ports */
1792                 retval = 0;
1793                 break;
1794         default:
1795                 /* dual port cards only support WoL on port A from now on
1796                  * unless it was enabled in the eeprom for port B
1797                  * so exclude FUNC_1 ports from having WoL enabled */
1798                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1799                     !adapter->eeprom_wol) {
1800                         wol->supported = 0;
1801                         break;
1802                 }
1803
1804                 retval = 0;
1805         }
1806
1807         return retval;
1808 }
1809
1810 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1811 {
1812         struct igb_adapter *adapter = netdev_priv(netdev);
1813
1814         wol->supported = WAKE_UCAST | WAKE_MCAST |
1815                          WAKE_BCAST | WAKE_MAGIC;
1816         wol->wolopts = 0;
1817
1818         /* this function will set ->supported = 0 and return 1 if wol is not
1819          * supported by this hardware */
1820         if (igb_wol_exclusion(adapter, wol) ||
1821             !device_can_wakeup(&adapter->pdev->dev))
1822                 return;
1823
1824         /* apply any specific unsupported masks here */
1825         switch (adapter->hw.device_id) {
1826         default:
1827                 break;
1828         }
1829
1830         if (adapter->wol & E1000_WUFC_EX)
1831                 wol->wolopts |= WAKE_UCAST;
1832         if (adapter->wol & E1000_WUFC_MC)
1833                 wol->wolopts |= WAKE_MCAST;
1834         if (adapter->wol & E1000_WUFC_BC)
1835                 wol->wolopts |= WAKE_BCAST;
1836         if (adapter->wol & E1000_WUFC_MAG)
1837                 wol->wolopts |= WAKE_MAGIC;
1838
1839         return;
1840 }
1841
1842 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1843 {
1844         struct igb_adapter *adapter = netdev_priv(netdev);
1845
1846         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1847                 return -EOPNOTSUPP;
1848
1849         if (igb_wol_exclusion(adapter, wol) ||
1850             !device_can_wakeup(&adapter->pdev->dev))
1851                 return wol->wolopts ? -EOPNOTSUPP : 0;
1852
1853         /* these settings will always override what we currently have */
1854         adapter->wol = 0;
1855
1856         if (wol->wolopts & WAKE_UCAST)
1857                 adapter->wol |= E1000_WUFC_EX;
1858         if (wol->wolopts & WAKE_MCAST)
1859                 adapter->wol |= E1000_WUFC_MC;
1860         if (wol->wolopts & WAKE_BCAST)
1861                 adapter->wol |= E1000_WUFC_BC;
1862         if (wol->wolopts & WAKE_MAGIC)
1863                 adapter->wol |= E1000_WUFC_MAG;
1864         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1865
1866         return 0;
1867 }
1868
1869 /* bit defines for adapter->led_status */
1870 #define IGB_LED_ON              0
1871
1872 static int igb_phys_id(struct net_device *netdev, u32 data)
1873 {
1874         struct igb_adapter *adapter = netdev_priv(netdev);
1875         struct e1000_hw *hw = &adapter->hw;
1876         unsigned long timeout;
1877
1878         timeout = data * 1000;
1879
1880         /*
1881          *  msleep_interruptable only accepts unsigned int so we are limited
1882          * in how long a duration we can wait
1883          */
1884         if (!timeout || timeout > UINT_MAX)
1885                 timeout = UINT_MAX;
1886
1887         igb_blink_led(hw);
1888         msleep_interruptible(timeout);
1889
1890         igb_led_off(hw);
1891         clear_bit(IGB_LED_ON, &adapter->led_status);
1892         igb_cleanup_led(hw);
1893
1894         return 0;
1895 }
1896
1897 static int igb_set_coalesce(struct net_device *netdev,
1898                             struct ethtool_coalesce *ec)
1899 {
1900         struct igb_adapter *adapter = netdev_priv(netdev);
1901         int i;
1902
1903         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1904             ((ec->rx_coalesce_usecs > 3) &&
1905              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1906             (ec->rx_coalesce_usecs == 2))
1907                 return -EINVAL;
1908
1909         if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1910             ((ec->tx_coalesce_usecs > 3) &&
1911              (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1912             (ec->tx_coalesce_usecs == 2))
1913                 return -EINVAL;
1914
1915         if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
1916                 return -EINVAL;
1917
1918         /* convert to rate of irq's per second */
1919         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
1920                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
1921         else
1922                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
1923
1924         /* convert to rate of irq's per second */
1925         if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
1926                 adapter->tx_itr_setting = adapter->rx_itr_setting;
1927         else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
1928                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
1929         else
1930                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
1931
1932         for (i = 0; i < adapter->num_q_vectors; i++) {
1933                 struct igb_q_vector *q_vector = adapter->q_vector[i];
1934                 if (q_vector->rx_ring)
1935                         q_vector->itr_val = adapter->rx_itr_setting;
1936                 else
1937                         q_vector->itr_val = adapter->tx_itr_setting;
1938                 if (q_vector->itr_val && q_vector->itr_val <= 3)
1939                         q_vector->itr_val = IGB_START_ITR;
1940                 q_vector->set_itr = 1;
1941         }
1942
1943         return 0;
1944 }
1945
1946 static int igb_get_coalesce(struct net_device *netdev,
1947                             struct ethtool_coalesce *ec)
1948 {
1949         struct igb_adapter *adapter = netdev_priv(netdev);
1950
1951         if (adapter->rx_itr_setting <= 3)
1952                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
1953         else
1954                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
1955
1956         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
1957                 if (adapter->tx_itr_setting <= 3)
1958                         ec->tx_coalesce_usecs = adapter->tx_itr_setting;
1959                 else
1960                         ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
1961         }
1962
1963         return 0;
1964 }
1965
1966 static int igb_nway_reset(struct net_device *netdev)
1967 {
1968         struct igb_adapter *adapter = netdev_priv(netdev);
1969         if (netif_running(netdev))
1970                 igb_reinit_locked(adapter);
1971         return 0;
1972 }
1973
1974 static int igb_get_sset_count(struct net_device *netdev, int sset)
1975 {
1976         switch (sset) {
1977         case ETH_SS_STATS:
1978                 return IGB_STATS_LEN;
1979         case ETH_SS_TEST:
1980                 return IGB_TEST_LEN;
1981         default:
1982                 return -ENOTSUPP;
1983         }
1984 }
1985
1986 static void igb_get_ethtool_stats(struct net_device *netdev,
1987                                   struct ethtool_stats *stats, u64 *data)
1988 {
1989         struct igb_adapter *adapter = netdev_priv(netdev);
1990         struct net_device_stats *net_stats = &netdev->stats;
1991         u64 *queue_stat;
1992         int i, j, k;
1993         char *p;
1994
1995         igb_update_stats(adapter);
1996
1997         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1998                 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
1999                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2000                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2001         }
2002         for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2003                 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2004                 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2005                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2006         }
2007         for (j = 0; j < adapter->num_tx_queues; j++) {
2008                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
2009                 for (k = 0; k < IGB_TX_QUEUE_STATS_LEN; k++, i++)
2010                         data[i] = queue_stat[k];
2011         }
2012         for (j = 0; j < adapter->num_rx_queues; j++) {
2013                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
2014                 for (k = 0; k < IGB_RX_QUEUE_STATS_LEN; k++, i++)
2015                         data[i] = queue_stat[k];
2016         }
2017 }
2018
2019 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2020 {
2021         struct igb_adapter *adapter = netdev_priv(netdev);
2022         u8 *p = data;
2023         int i;
2024
2025         switch (stringset) {
2026         case ETH_SS_TEST:
2027                 memcpy(data, *igb_gstrings_test,
2028                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2029                 break;
2030         case ETH_SS_STATS:
2031                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2032                         memcpy(p, igb_gstrings_stats[i].stat_string,
2033                                ETH_GSTRING_LEN);
2034                         p += ETH_GSTRING_LEN;
2035                 }
2036                 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2037                         memcpy(p, igb_gstrings_net_stats[i].stat_string,
2038                                ETH_GSTRING_LEN);
2039                         p += ETH_GSTRING_LEN;
2040                 }
2041                 for (i = 0; i < adapter->num_tx_queues; i++) {
2042                         sprintf(p, "tx_queue_%u_packets", i);
2043                         p += ETH_GSTRING_LEN;
2044                         sprintf(p, "tx_queue_%u_bytes", i);
2045                         p += ETH_GSTRING_LEN;
2046                         sprintf(p, "tx_queue_%u_restart", i);
2047                         p += ETH_GSTRING_LEN;
2048                 }
2049                 for (i = 0; i < adapter->num_rx_queues; i++) {
2050                         sprintf(p, "rx_queue_%u_packets", i);
2051                         p += ETH_GSTRING_LEN;
2052                         sprintf(p, "rx_queue_%u_bytes", i);
2053                         p += ETH_GSTRING_LEN;
2054                         sprintf(p, "rx_queue_%u_drops", i);
2055                         p += ETH_GSTRING_LEN;
2056                         sprintf(p, "rx_queue_%u_csum_err", i);
2057                         p += ETH_GSTRING_LEN;
2058                         sprintf(p, "rx_queue_%u_alloc_failed", i);
2059                         p += ETH_GSTRING_LEN;
2060                 }
2061 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2062                 break;
2063         }
2064 }
2065
2066 static const struct ethtool_ops igb_ethtool_ops = {
2067         .get_settings           = igb_get_settings,
2068         .set_settings           = igb_set_settings,
2069         .get_drvinfo            = igb_get_drvinfo,
2070         .get_regs_len           = igb_get_regs_len,
2071         .get_regs               = igb_get_regs,
2072         .get_wol                = igb_get_wol,
2073         .set_wol                = igb_set_wol,
2074         .get_msglevel           = igb_get_msglevel,
2075         .set_msglevel           = igb_set_msglevel,
2076         .nway_reset             = igb_nway_reset,
2077         .get_link               = ethtool_op_get_link,
2078         .get_eeprom_len         = igb_get_eeprom_len,
2079         .get_eeprom             = igb_get_eeprom,
2080         .set_eeprom             = igb_set_eeprom,
2081         .get_ringparam          = igb_get_ringparam,
2082         .set_ringparam          = igb_set_ringparam,
2083         .get_pauseparam         = igb_get_pauseparam,
2084         .set_pauseparam         = igb_set_pauseparam,
2085         .get_rx_csum            = igb_get_rx_csum,
2086         .set_rx_csum            = igb_set_rx_csum,
2087         .get_tx_csum            = igb_get_tx_csum,
2088         .set_tx_csum            = igb_set_tx_csum,
2089         .get_sg                 = ethtool_op_get_sg,
2090         .set_sg                 = ethtool_op_set_sg,
2091         .get_tso                = ethtool_op_get_tso,
2092         .set_tso                = igb_set_tso,
2093         .self_test              = igb_diag_test,
2094         .get_strings            = igb_get_strings,
2095         .phys_id                = igb_phys_id,
2096         .get_sset_count         = igb_get_sset_count,
2097         .get_ethtool_stats      = igb_get_ethtool_stats,
2098         .get_coalesce           = igb_get_coalesce,
2099         .set_coalesce           = igb_set_coalesce,
2100 };
2101
2102 void igb_set_ethtool_ops(struct net_device *netdev)
2103 {
2104         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2105 }