drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 112  *
 113  * Known bugs:
 114  * We suspect that on some hardware no TX done interrupts are generated.
 115  * This means recovery from netif_stop_queue only happens if the hw timer
 116  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 117  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 118  * If your hardware reliably generates tx done interrupts, then you can remove
 119  * DEV_NEED_TIMERIRQ from the driver_data flags.
 120  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 121  * superfluous timer interrupts from the nic.
 122  */
 123 #define FORCEDETH_VERSION               "0.56"
 124 #define DRV_NAME                        "forcedeth"
 125
 126 #include <linux/module.h>
 127 #include <linux/types.h>
 128 #include <linux/pci.h>
 129 #include <linux/interrupt.h>
 130 #include <linux/netdevice.h>
 131 #include <linux/etherdevice.h>
 132 #include <linux/delay.h>
 133 #include <linux/spinlock.h>
 134 #include <linux/ethtool.h>
 135 #include <linux/timer.h>
 136 #include <linux/skbuff.h>
 137 #include <linux/mii.h>
 138 #include <linux/random.h>
 139 #include <linux/init.h>
 140 #include <linux/if_vlan.h>
 141 #include <linux/dma-mapping.h>
 142
 143 #include <asm/irq.h>
 144 #include <asm/io.h>
 145 #include <asm/uaccess.h>
 146 #include <asm/system.h>
 147
 148 #if 0
 149 #define dprintk                 printk
 150 #else
 151 #define dprintk(x...)           do { } while (0)
 152 #endif
 153
 154
 155 /*
 156  * Hardware access:
 157  */
 158
 159 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 160 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 161 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 162 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 163 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 164 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 165 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 166 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 167 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 168 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 169 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 170 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 171
 172 enum {
 173         NvRegIrqStatus = 0x000,
 174 #define NVREG_IRQSTAT_MIIEVENT  0x040
 175 #define NVREG_IRQSTAT_MASK              0x1ff
 176         NvRegIrqMask = 0x004,
 177 #define NVREG_IRQ_RX_ERROR              0x0001
 178 #define NVREG_IRQ_RX                    0x0002
 179 #define NVREG_IRQ_RX_NOBUF              0x0004
 180 #define NVREG_IRQ_TX_ERR                0x0008
 181 #define NVREG_IRQ_TX_OK                 0x0010
 182 #define NVREG_IRQ_TIMER                 0x0020
 183 #define NVREG_IRQ_LINK                  0x0040
 184 #define NVREG_IRQ_RX_FORCED             0x0080
 185 #define NVREG_IRQ_TX_FORCED             0x0100
 186 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 187 #define NVREG_IRQMASK_CPU               0x0040
 188 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 189 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 190 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 191
 192 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 193                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 194                                         NVREG_IRQ_TX_FORCED))
 195
 196         NvRegUnknownSetupReg6 = 0x008,
 197 #define NVREG_UNKSETUP6_VAL             3
 198
 199 /*
 200  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 201  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 202  */
 203         NvRegPollingInterval = 0x00c,
 204 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 205 #define NVREG_POLL_DEFAULT_CPU  13
 206         NvRegMSIMap0 = 0x020,
 207         NvRegMSIMap1 = 0x024,
 208         NvRegMSIIrqMask = 0x030,
 209 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 210         NvRegMisc1 = 0x080,
 211 #define NVREG_MISC1_PAUSE_TX    0x01
 212 #define NVREG_MISC1_HD          0x02
 213 #define NVREG_MISC1_FORCE       0x3b0f3c
 214
 215         NvRegMacReset = 0x3c,
 216 #define NVREG_MAC_RESET_ASSERT  0x0F3
 217         NvRegTransmitterControl = 0x084,
 218 #define NVREG_XMITCTL_START     0x01
 219         NvRegTransmitterStatus = 0x088,
 220 #define NVREG_XMITSTAT_BUSY     0x01
 221
 222         NvRegPacketFilterFlags = 0x8c,
 223 #define NVREG_PFF_PAUSE_RX      0x08
 224 #define NVREG_PFF_ALWAYS        0x7F0000
 225 #define NVREG_PFF_PROMISC       0x80
 226 #define NVREG_PFF_MYADDR        0x20
 227 #define NVREG_PFF_LOOPBACK      0x10
 228
 229         NvRegOffloadConfig = 0x90,
 230 #define NVREG_OFFLOAD_HOMEPHY   0x601
 231 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 232         NvRegReceiverControl = 0x094,
 233 #define NVREG_RCVCTL_START      0x01
 234         NvRegReceiverStatus = 0x98,
 235 #define NVREG_RCVSTAT_BUSY      0x01
 236
 237         NvRegRandomSeed = 0x9c,
 238 #define NVREG_RNDSEED_MASK      0x00ff
 239 #define NVREG_RNDSEED_FORCE     0x7f00
 240 #define NVREG_RNDSEED_FORCE2    0x2d00
 241 #define NVREG_RNDSEED_FORCE3    0x7400
 242
 243         NvRegUnknownSetupReg1 = 0xA0,
 244 #define NVREG_UNKSETUP1_VAL     0x16070f
 245         NvRegUnknownSetupReg2 = 0xA4,
 246 #define NVREG_UNKSETUP2_VAL     0x16
 247         NvRegMacAddrA = 0xA8,
 248         NvRegMacAddrB = 0xAC,
 249         NvRegMulticastAddrA = 0xB0,
 250 #define NVREG_MCASTADDRA_FORCE  0x01
 251         NvRegMulticastAddrB = 0xB4,
 252         NvRegMulticastMaskA = 0xB8,
 253         NvRegMulticastMaskB = 0xBC,
 254
 255         NvRegPhyInterface = 0xC0,
 256 #define PHY_RGMII               0x10000000
 257
 258         NvRegTxRingPhysAddr = 0x100,
 259         NvRegRxRingPhysAddr = 0x104,
 260         NvRegRingSizes = 0x108,
 261 #define NVREG_RINGSZ_TXSHIFT 0
 262 #define NVREG_RINGSZ_RXSHIFT 16
 263         NvRegUnknownTransmitterReg = 0x10c,
 264         NvRegLinkSpeed = 0x110,
 265 #define NVREG_LINKSPEED_FORCE 0x10000
 266 #define NVREG_LINKSPEED_10      1000
 267 #define NVREG_LINKSPEED_100     100
 268 #define NVREG_LINKSPEED_1000    50
 269 #define NVREG_LINKSPEED_MASK    (0xFFF)
 270         NvRegUnknownSetupReg5 = 0x130,
 271 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 272         NvRegUnknownSetupReg3 = 0x13c,
 273 #define NVREG_UNKSETUP3_VAL1    0x200010
 274         NvRegTxRxControl = 0x144,
 275 #define NVREG_TXRXCTL_KICK      0x0001
 276 #define NVREG_TXRXCTL_BIT1      0x0002
 277 #define NVREG_TXRXCTL_BIT2      0x0004
 278 #define NVREG_TXRXCTL_IDLE      0x0008
 279 #define NVREG_TXRXCTL_RESET     0x0010
 280 #define NVREG_TXRXCTL_RXCHECK   0x0400
 281 #define NVREG_TXRXCTL_DESC_1    0
 282 #define NVREG_TXRXCTL_DESC_2    0x02100
 283 #define NVREG_TXRXCTL_DESC_3    0x02200
 284 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 285 #define NVREG_TXRXCTL_VLANINS   0x00080
 286         NvRegTxRingPhysAddrHigh = 0x148,
 287         NvRegRxRingPhysAddrHigh = 0x14C,
 288         NvRegTxPauseFrame = 0x170,
 289 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 290 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 291         NvRegMIIStatus = 0x180,
 292 #define NVREG_MIISTAT_ERROR             0x0001
 293 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 294 #define NVREG_MIISTAT_MASK              0x000f
 295 #define NVREG_MIISTAT_MASK2             0x000f
 296         NvRegUnknownSetupReg4 = 0x184,
 297 #define NVREG_UNKSETUP4_VAL     8
 298
 299         NvRegAdapterControl = 0x188,
 300 #define NVREG_ADAPTCTL_START    0x02
 301 #define NVREG_ADAPTCTL_LINKUP   0x04
 302 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 303 #define NVREG_ADAPTCTL_RUNNING  0x100000
 304 #define NVREG_ADAPTCTL_PHYSHIFT 24
 305         NvRegMIISpeed = 0x18c,
 306 #define NVREG_MIISPEED_BIT8     (1<<8)
 307 #define NVREG_MIIDELAY  5
 308         NvRegMIIControl = 0x190,
 309 #define NVREG_MIICTL_INUSE      0x08000
 310 #define NVREG_MIICTL_WRITE      0x00400
 311 #define NVREG_MIICTL_ADDRSHIFT  5
 312         NvRegMIIData = 0x194,
 313         NvRegWakeUpFlags = 0x200,
 314 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 315 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 316 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 317 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 318 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 319 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 320 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 321 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 322 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 323 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 324 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 325
 326         NvRegPatternCRC = 0x204,
 327         NvRegPatternMask = 0x208,
 328         NvRegPowerCap = 0x268,
 329 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 330 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 331 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 332         NvRegPowerState = 0x26c,
 333 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 334 #define NVREG_POWERSTATE_VALID          0x0100
 335 #define NVREG_POWERSTATE_MASK           0x0003
 336 #define NVREG_POWERSTATE_D0             0x0000
 337 #define NVREG_POWERSTATE_D1             0x0001
 338 #define NVREG_POWERSTATE_D2             0x0002
 339 #define NVREG_POWERSTATE_D3             0x0003
 340         NvRegTxCnt = 0x280,
 341         NvRegTxZeroReXmt = 0x284,
 342         NvRegTxOneReXmt = 0x288,
 343         NvRegTxManyReXmt = 0x28c,
 344         NvRegTxLateCol = 0x290,
 345         NvRegTxUnderflow = 0x294,
 346         NvRegTxLossCarrier = 0x298,
 347         NvRegTxExcessDef = 0x29c,
 348         NvRegTxRetryErr = 0x2a0,
 349         NvRegRxFrameErr = 0x2a4,
 350         NvRegRxExtraByte = 0x2a8,
 351         NvRegRxLateCol = 0x2ac,
 352         NvRegRxRunt = 0x2b0,
 353         NvRegRxFrameTooLong = 0x2b4,
 354         NvRegRxOverflow = 0x2b8,
 355         NvRegRxFCSErr = 0x2bc,
 356         NvRegRxFrameAlignErr = 0x2c0,
 357         NvRegRxLenErr = 0x2c4,
 358         NvRegRxUnicast = 0x2c8,
 359         NvRegRxMulticast = 0x2cc,
 360         NvRegRxBroadcast = 0x2d0,
 361         NvRegTxDef = 0x2d4,
 362         NvRegTxFrame = 0x2d8,
 363         NvRegRxCnt = 0x2dc,
 364         NvRegTxPause = 0x2e0,
 365         NvRegRxPause = 0x2e4,
 366         NvRegRxDropFrame = 0x2e8,
 367         NvRegVlanControl = 0x300,
 368 #define NVREG_VLANCONTROL_ENABLE        0x2000
 369         NvRegMSIXMap0 = 0x3e0,
 370         NvRegMSIXMap1 = 0x3e4,
 371         NvRegMSIXIrqStatus = 0x3f0,
 372
 373         NvRegPowerState2 = 0x600,
 374 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 375 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 376 };
 377
 378 /* Big endian: should work, but is untested */
 379 struct ring_desc {
 380         u32 PacketBuffer;
 381         u32 FlagLen;
 382 };
 383
 384 struct ring_desc_ex {
 385         u32 PacketBufferHigh;
 386         u32 PacketBufferLow;
 387         u32 TxVlan;
 388         u32 FlagLen;
 389 };
 390
 391 typedef union _ring_type {
 392         struct ring_desc* orig;
 393         struct ring_desc_ex* ex;
 394 } ring_type;
 395
 396 #define FLAG_MASK_V1 0xffff0000
 397 #define FLAG_MASK_V2 0xffffc000
 398 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 399 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 400
 401 #define NV_TX_LASTPACKET        (1<<16)
 402 #define NV_TX_RETRYERROR        (1<<19)
 403 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 404 #define NV_TX_DEFERRED          (1<<26)
 405 #define NV_TX_CARRIERLOST       (1<<27)
 406 #define NV_TX_LATECOLLISION     (1<<28)
 407 #define NV_TX_UNDERFLOW         (1<<29)
 408 #define NV_TX_ERROR             (1<<30)
 409 #define NV_TX_VALID             (1<<31)
 410
 411 #define NV_TX2_LASTPACKET       (1<<29)
 412 #define NV_TX2_RETRYERROR       (1<<18)
 413 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 414 #define NV_TX2_DEFERRED         (1<<25)
 415 #define NV_TX2_CARRIERLOST      (1<<26)
 416 #define NV_TX2_LATECOLLISION    (1<<27)
 417 #define NV_TX2_UNDERFLOW        (1<<28)
 418 /* error and valid are the same for both */
 419 #define NV_TX2_ERROR            (1<<30)
 420 #define NV_TX2_VALID            (1<<31)
 421 #define NV_TX2_TSO              (1<<28)
 422 #define NV_TX2_TSO_SHIFT        14
 423 #define NV_TX2_TSO_MAX_SHIFT    14
 424 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 425 #define NV_TX2_CHECKSUM_L3      (1<<27)
 426 #define NV_TX2_CHECKSUM_L4      (1<<26)
 427
 428 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 429
 430 #define NV_RX_DESCRIPTORVALID   (1<<16)
 431 #define NV_RX_MISSEDFRAME       (1<<17)
 432 #define NV_RX_SUBSTRACT1        (1<<18)
 433 #define NV_RX_ERROR1            (1<<23)
 434 #define NV_RX_ERROR2            (1<<24)
 435 #define NV_RX_ERROR3            (1<<25)
 436 #define NV_RX_ERROR4            (1<<26)
 437 #define NV_RX_CRCERR            (1<<27)
 438 #define NV_RX_OVERFLOW          (1<<28)
 439 #define NV_RX_FRAMINGERR        (1<<29)
 440 #define NV_RX_ERROR             (1<<30)
 441 #define NV_RX_AVAIL             (1<<31)
 442
 443 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 444 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 445 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 446 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 447 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 448 #define NV_RX2_SUBSTRACT1       (1<<25)
 449 #define NV_RX2_ERROR1           (1<<18)
 450 #define NV_RX2_ERROR2           (1<<19)
 451 #define NV_RX2_ERROR3           (1<<20)
 452 #define NV_RX2_ERROR4           (1<<21)
 453 #define NV_RX2_CRCERR           (1<<22)
 454 #define NV_RX2_OVERFLOW         (1<<23)
 455 #define NV_RX2_FRAMINGERR       (1<<24)
 456 /* error and avail are the same for both */
 457 #define NV_RX2_ERROR            (1<<30)
 458 #define NV_RX2_AVAIL            (1<<31)
 459
 460 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 461 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 462
 463 /* Miscelaneous hardware related defines: */
 464 #define NV_PCI_REGSZ_VER1       0x270
 465 #define NV_PCI_REGSZ_VER2       0x604
 466
 467 /* various timeout delays: all in usec */
 468 #define NV_TXRX_RESET_DELAY     4
 469 #define NV_TXSTOP_DELAY1        10
 470 #define NV_TXSTOP_DELAY1MAX     500000
 471 #define NV_TXSTOP_DELAY2        100
 472 #define NV_RXSTOP_DELAY1        10
 473 #define NV_RXSTOP_DELAY1MAX     500000
 474 #define NV_RXSTOP_DELAY2        100
 475 #define NV_SETUP5_DELAY         5
 476 #define NV_SETUP5_DELAYMAX      50000
 477 #define NV_POWERUP_DELAY        5
 478 #define NV_POWERUP_DELAYMAX     5000
 479 #define NV_MIIBUSY_DELAY        50
 480 #define NV_MIIPHY_DELAY 10
 481 #define NV_MIIPHY_DELAYMAX      10000
 482 #define NV_MAC_RESET_DELAY      64
 483
 484 #define NV_WAKEUPPATTERNS       5
 485 #define NV_WAKEUPMASKENTRIES    4
 486
 487 /* General driver defaults */
 488 #define NV_WATCHDOG_TIMEO       (5*HZ)
 489
 490 #define RX_RING_DEFAULT         128
 491 #define TX_RING_DEFAULT         256
 492 #define RX_RING_MIN             128
 493 #define TX_RING_MIN             64
 494 #define RING_MAX_DESC_VER_1     1024
 495 #define RING_MAX_DESC_VER_2_3   16384
 496 /*
 497  * Difference between the get and put pointers for the tx ring.
 498  * This is used to throttle the amount of data outstanding in the
 499  * tx ring.
 500  */
 501 #define TX_LIMIT_DIFFERENCE     1
 502
 503 /* rx/tx mac addr + type + vlan + align + slack*/
 504 #define NV_RX_HEADERS           (64)
 505 /* even more slack. */
 506 #define NV_RX_ALLOC_PAD         (64)
 507
 508 /* maximum mtu size */
 509 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 510 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 511
 512 #define OOM_REFILL      (1+HZ/20)
 513 #define POLL_WAIT       (1+HZ/100)
 514 #define LINK_TIMEOUT    (3*HZ)
 515 #define STATS_INTERVAL  (10*HZ)
 516
 517 /*
 518  * desc_ver values:
 519  * The nic supports three different descriptor types:
 520  * - DESC_VER_1: Original
 521  * - DESC_VER_2: support for jumbo frames.
 522  * - DESC_VER_3: 64-bit format.
 523  */
 524 #define DESC_VER_1      1
 525 #define DESC_VER_2      2
 526 #define DESC_VER_3      3
 527
 528 /* PHY defines */
 529 #define PHY_OUI_MARVELL 0x5043
 530 #define PHY_OUI_CICADA  0x03f1
 531 #define PHYID1_OUI_MASK 0x03ff
 532 #define PHYID1_OUI_SHFT 6
 533 #define PHYID2_OUI_MASK 0xfc00
 534 #define PHYID2_OUI_SHFT 10
 535 #define PHY_INIT1       0x0f000
 536 #define PHY_INIT2       0x0e00
 537 #define PHY_INIT3       0x01000
 538 #define PHY_INIT4       0x0200
 539 #define PHY_INIT5       0x0004
 540 #define PHY_INIT6       0x02000
 541 #define PHY_GIGABIT     0x0100
 542
 543 #define PHY_TIMEOUT     0x1
 544 #define PHY_ERROR       0x2
 545
 546 #define PHY_100 0x1
 547 #define PHY_1000        0x2
 548 #define PHY_HALF        0x100
 549
 550 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 551 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 552 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 553 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 554 #define NV_PAUSEFRAME_RX_REQ     0x0010
 555 #define NV_PAUSEFRAME_TX_REQ     0x0020
 556 #define NV_PAUSEFRAME_AUTONEG    0x0040
 557
 558 /* MSI/MSI-X defines */
 559 #define NV_MSI_X_MAX_VECTORS  8
 560 #define NV_MSI_X_VECTORS_MASK 0x000f
 561 #define NV_MSI_CAPABLE        0x0010
 562 #define NV_MSI_X_CAPABLE      0x0020
 563 #define NV_MSI_ENABLED        0x0040
 564 #define NV_MSI_X_ENABLED      0x0080
 565
 566 #define NV_MSI_X_VECTOR_ALL   0x0
 567 #define NV_MSI_X_VECTOR_RX    0x0
 568 #define NV_MSI_X_VECTOR_TX    0x1
 569 #define NV_MSI_X_VECTOR_OTHER 0x2
 570
 571 /* statistics */
 572 struct nv_ethtool_str {
 573         char name[ETH_GSTRING_LEN];
 574 };
 575
 576 static const struct nv_ethtool_str nv_estats_str[] = {
 577         { "tx_bytes" },
 578         { "tx_zero_rexmt" },
 579         { "tx_one_rexmt" },
 580         { "tx_many_rexmt" },
 581         { "tx_late_collision" },
 582         { "tx_fifo_errors" },
 583         { "tx_carrier_errors" },
 584         { "tx_excess_deferral" },
 585         { "tx_retry_error" },
 586         { "tx_deferral" },
 587         { "tx_packets" },
 588         { "tx_pause" },
 589         { "rx_frame_error" },
 590         { "rx_extra_byte" },
 591         { "rx_late_collision" },
 592         { "rx_runt" },
 593         { "rx_frame_too_long" },
 594         { "rx_over_errors" },
 595         { "rx_crc_errors" },
 596         { "rx_frame_align_error" },
 597         { "rx_length_error" },
 598         { "rx_unicast" },
 599         { "rx_multicast" },
 600         { "rx_broadcast" },
 601         { "rx_bytes" },
 602         { "rx_pause" },
 603         { "rx_drop_frame" },
 604         { "rx_packets" },
 605         { "rx_errors_total" }
 606 };
 607
 608 struct nv_ethtool_stats {
 609         u64 tx_bytes;
 610         u64 tx_zero_rexmt;
 611         u64 tx_one_rexmt;
 612         u64 tx_many_rexmt;
 613         u64 tx_late_collision;
 614         u64 tx_fifo_errors;
 615         u64 tx_carrier_errors;
 616         u64 tx_excess_deferral;
 617         u64 tx_retry_error;
 618         u64 tx_deferral;
 619         u64 tx_packets;
 620         u64 tx_pause;
 621         u64 rx_frame_error;
 622         u64 rx_extra_byte;
 623         u64 rx_late_collision;
 624         u64 rx_runt;
 625         u64 rx_frame_too_long;
 626         u64 rx_over_errors;
 627         u64 rx_crc_errors;
 628         u64 rx_frame_align_error;
 629         u64 rx_length_error;
 630         u64 rx_unicast;
 631         u64 rx_multicast;
 632         u64 rx_broadcast;
 633         u64 rx_bytes;
 634         u64 rx_pause;
 635         u64 rx_drop_frame;
 636         u64 rx_packets;
 637         u64 rx_errors_total;
 638 };
 639
 640 /* diagnostics */
 641 #define NV_TEST_COUNT_BASE 3
 642 #define NV_TEST_COUNT_EXTENDED 4
 643
 644 static const struct nv_ethtool_str nv_etests_str[] = {
 645         { "link      (online/offline)" },
 646         { "register  (offline)       " },
 647         { "interrupt (offline)       " },
 648         { "loopback  (offline)       " }
 649 };
 650
 651 struct register_test {
 652         u32 reg;
 653         u32 mask;
 654 };
 655
 656 static const struct register_test nv_registers_test[] = {
 657         { NvRegUnknownSetupReg6, 0x01 },
 658         { NvRegMisc1, 0x03c },
 659         { NvRegOffloadConfig, 0x03ff },
 660         { NvRegMulticastAddrA, 0xffffffff },
 661         { NvRegUnknownSetupReg3, 0x0ff },
 662         { NvRegWakeUpFlags, 0x07777 },
 663         { 0,0 }
 664 };
 665
 666 /*
 667  * SMP locking:
 668  * All hardware access under dev->priv->lock, except the performance
 669  * critical parts:
 670  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 671  *      by the arch code for interrupts.
 672  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 673  *      needs dev->priv->lock :-(
 674  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 675  */
 676
 677 /* in dev: base, irq */
 678 struct fe_priv {
 679         spinlock_t lock;
 680
 681         /* General data:
 682          * Locking: spin_lock(&np->lock); */
 683         struct net_device_stats stats;
 684         struct nv_ethtool_stats estats;
 685         int in_shutdown;
 686         u32 linkspeed;
 687         int duplex;
 688         int autoneg;
 689         int fixed_mode;
 690         int phyaddr;
 691         int wolenabled;
 692         unsigned int phy_oui;
 693         u16 gigabit;
 694         int intr_test;
 695
 696         /* General data: RO fields */
 697         dma_addr_t ring_addr;
 698         struct pci_dev *pci_dev;
 699         u32 orig_mac[2];
 700         u32 irqmask;
 701         u32 desc_ver;
 702         u32 txrxctl_bits;
 703         u32 vlanctl_bits;
 704         u32 driver_data;
 705         u32 register_size;
 706
 707         void __iomem *base;
 708
 709         /* rx specific fields.
 710          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 711          */
 712         ring_type rx_ring;
 713         unsigned int cur_rx, refill_rx;
 714         struct sk_buff **rx_skbuff;
 715         dma_addr_t *rx_dma;
 716         unsigned int rx_buf_sz;
 717         unsigned int pkt_limit;
 718         struct timer_list oom_kick;
 719         struct timer_list nic_poll;
 720         struct timer_list stats_poll;
 721         u32 nic_poll_irq;
 722         int rx_ring_size;
 723
 724         /* media detection workaround.
 725          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 726          */
 727         int need_linktimer;
 728         unsigned long link_timeout;
 729         /*
 730          * tx specific fields.
 731          */
 732         ring_type tx_ring;
 733         unsigned int next_tx, nic_tx;
 734         struct sk_buff **tx_skbuff;
 735         dma_addr_t *tx_dma;
 736         unsigned int *tx_dma_len;
 737         u32 tx_flags;
 738         int tx_ring_size;
 739         int tx_limit_start;
 740         int tx_limit_stop;
 741
 742         /* vlan fields */
 743         struct vlan_group *vlangrp;
 744
 745         /* msi/msi-x fields */
 746         u32 msi_flags;
 747         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 748
 749         /* flow control */
 750         u32 pause_flags;
 751 };
 752
 753 /*
 754  * Maximum number of loops until we assume that a bit in the irq mask
 755  * is stuck. Overridable with module param.
 756  */
 757 static int max_interrupt_work = 5;
 758
 759 /*
 760  * Optimization can be either throuput mode or cpu mode
 761  *
 762  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 763  * CPU Mode: Interrupts are controlled by a timer.
 764  */
 765 enum {
 766         NV_OPTIMIZATION_MODE_THROUGHPUT,
 767         NV_OPTIMIZATION_MODE_CPU
 768 };
 769 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 770
 771 /*
 772  * Poll interval for timer irq
 773  *
 774  * This interval determines how frequent an interrupt is generated.
 775  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 776  * Min = 0, and Max = 65535
 777  */
 778 static int poll_interval = -1;
 779
 780 /*
 781  * MSI interrupts
 782  */
 783 enum {
 784         NV_MSI_INT_DISABLED,
 785         NV_MSI_INT_ENABLED
 786 };
 787 static int msi = NV_MSI_INT_ENABLED;
 788
 789 /*
 790  * MSIX interrupts
 791  */
 792 enum {
 793         NV_MSIX_INT_DISABLED,
 794         NV_MSIX_INT_ENABLED
 795 };
 796 static int msix = NV_MSIX_INT_ENABLED;
 797
 798 /*
 799  * DMA 64bit
 800  */
 801 enum {
 802         NV_DMA_64BIT_DISABLED,
 803         NV_DMA_64BIT_ENABLED
 804 };
 805 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 806
 807 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 808 {
 809         return netdev_priv(dev);
 810 }
 811
 812 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 813 {
 814         return ((struct fe_priv *)netdev_priv(dev))->base;
 815 }
 816
 817 static inline void pci_push(u8 __iomem *base)
 818 {
 819         /* force out pending posted writes */
 820         readl(base);
 821 }
 822
 823 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 824 {
 825         return le32_to_cpu(prd->FlagLen)
 826                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 827 }
 828
 829 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 830 {
 831         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 832 }
 833
 834 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 835                                 int delay, int delaymax, const char *msg)
 836 {
 837         u8 __iomem *base = get_hwbase(dev);
 838
 839         pci_push(base);
 840         do {
 841                 udelay(delay);
 842                 delaymax -= delay;
 843                 if (delaymax < 0) {
 844                         if (msg)
 845                                 printk(msg);
 846                         return 1;
 847                 }
 848         } while ((readl(base + offset) & mask) != target);
 849         return 0;
 850 }
 851
 852 #define NV_SETUP_RX_RING 0x01
 853 #define NV_SETUP_TX_RING 0x02
 854
 855 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 856 {
 857         struct fe_priv *np = get_nvpriv(dev);
 858         u8 __iomem *base = get_hwbase(dev);
 859
 860         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 861                 if (rxtx_flags & NV_SETUP_RX_RING) {
 862                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 863                 }
 864                 if (rxtx_flags & NV_SETUP_TX_RING) {
 865                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 866                 }
 867         } else {
 868                 if (rxtx_flags & NV_SETUP_RX_RING) {
 869                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 870                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 871                 }
 872                 if (rxtx_flags & NV_SETUP_TX_RING) {
 873                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 874                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 875                 }
 876         }
 877 }
 878
 879 static void free_rings(struct net_device *dev)
 880 {
 881         struct fe_priv *np = get_nvpriv(dev);
 882
 883         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 884                 if(np->rx_ring.orig)
 885                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 886                                             np->rx_ring.orig, np->ring_addr);
 887         } else {
 888                 if (np->rx_ring.ex)
 889                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 890                                             np->rx_ring.ex, np->ring_addr);
 891         }
 892         if (np->rx_skbuff)
 893                 kfree(np->rx_skbuff);
 894         if (np->rx_dma)
 895                 kfree(np->rx_dma);
 896         if (np->tx_skbuff)
 897                 kfree(np->tx_skbuff);
 898         if (np->tx_dma)
 899                 kfree(np->tx_dma);
 900         if (np->tx_dma_len)
 901                 kfree(np->tx_dma_len);
 902 }
 903
 904 static int using_multi_irqs(struct net_device *dev)
 905 {
 906         struct fe_priv *np = get_nvpriv(dev);
 907
 908         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 909             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 910              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 911                 return 0;
 912         else
 913                 return 1;
 914 }
 915
 916 static void nv_enable_irq(struct net_device *dev)
 917 {
 918         struct fe_priv *np = get_nvpriv(dev);
 919
 920         if (!using_multi_irqs(dev)) {
 921                 if (np->msi_flags & NV_MSI_X_ENABLED)
 922                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 923                 else
 924                         enable_irq(dev->irq);
 925         } else {
 926                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 927                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 928                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 929         }
 930 }
 931
 932 static void nv_disable_irq(struct net_device *dev)
 933 {
 934         struct fe_priv *np = get_nvpriv(dev);
 935
 936         if (!using_multi_irqs(dev)) {
 937                 if (np->msi_flags & NV_MSI_X_ENABLED)
 938                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 939                 else
 940                         disable_irq(dev->irq);
 941         } else {
 942                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 943                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 944                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 945         }
 946 }
 947
 948 /* In MSIX mode, a write to irqmask behaves as XOR */
 949 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 950 {
 951         u8 __iomem *base = get_hwbase(dev);
 952
 953         writel(mask, base + NvRegIrqMask);
 954 }
 955
 956 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 957 {
 958         struct fe_priv *np = get_nvpriv(dev);
 959         u8 __iomem *base = get_hwbase(dev);
 960
 961         if (np->msi_flags & NV_MSI_X_ENABLED) {
 962                 writel(mask, base + NvRegIrqMask);
 963         } else {
 964                 if (np->msi_flags & NV_MSI_ENABLED)
 965                         writel(0, base + NvRegMSIIrqMask);
 966                 writel(0, base + NvRegIrqMask);
 967         }
 968 }
 969
 970 #define MII_READ        (-1)
 971 /* mii_rw: read/write a register on the PHY.
 972  *
 973  * Caller must guarantee serialization
 974  */
 975 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 976 {
 977         u8 __iomem *base = get_hwbase(dev);
 978         u32 reg;
 979         int retval;
 980
 981         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 982
 983         reg = readl(base + NvRegMIIControl);
 984         if (reg & NVREG_MIICTL_INUSE) {
 985                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 986                 udelay(NV_MIIBUSY_DELAY);
 987         }
 988
 989         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 990         if (value != MII_READ) {
 991                 writel(value, base + NvRegMIIData);
 992                 reg |= NVREG_MIICTL_WRITE;
 993         }
 994         writel(reg, base + NvRegMIIControl);
 995
 996         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 997                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 998                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 999                                 dev->name, miireg, addr);
1000                 retval = -1;
1001         } else if (value != MII_READ) {
1002                 /* it was a write operation - fewer failures are detectable */
1003                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1004                                 dev->name, value, miireg, addr);
1005                 retval = 0;
1006         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1007                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1008                                 dev->name, miireg, addr);
1009                 retval = -1;
1010         } else {
1011                 retval = readl(base + NvRegMIIData);
1012                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1013                                 dev->name, miireg, addr, retval);
1014         }
1015
1016         return retval;
1017 }
1018
1019 static int phy_reset(struct net_device *dev)
1020 {
1021         struct fe_priv *np = netdev_priv(dev);
1022         u32 miicontrol;
1023         unsigned int tries = 0;
1024
1025         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1026         miicontrol |= BMCR_RESET;
1027         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1028                 return -1;
1029         }
1030
1031         /* wait for 500ms */
1032         msleep(500);
1033
1034         /* must wait till reset is deasserted */
1035         while (miicontrol & BMCR_RESET) {
1036                 msleep(10);
1037                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1038                 /* FIXME: 100 tries seem excessive */
1039                 if (tries++ > 100)
1040                         return -1;
1041         }
1042         return 0;
1043 }
1044
1045 static int phy_init(struct net_device *dev)
1046 {
1047         struct fe_priv *np = get_nvpriv(dev);
1048         u8 __iomem *base = get_hwbase(dev);
1049         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1050
1051         /* set advertise register */
1052         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1053         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1054         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1055                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1056                 return PHY_ERROR;
1057         }
1058
1059         /* get phy interface type */
1060         phyinterface = readl(base + NvRegPhyInterface);
1061
1062         /* see if gigabit phy */
1063         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1064         if (mii_status & PHY_GIGABIT) {
1065                 np->gigabit = PHY_GIGABIT;
1066                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1067                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1068                 if (phyinterface & PHY_RGMII)
1069                         mii_control_1000 |= ADVERTISE_1000FULL;
1070                 else
1071                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1072
1073                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1074                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1075                         return PHY_ERROR;
1076                 }
1077         }
1078         else
1079                 np->gigabit = 0;
1080
1081         /* reset the phy */
1082         if (phy_reset(dev)) {
1083                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1084                 return PHY_ERROR;
1085         }
1086
1087         /* phy vendor specific configuration */
1088         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1089                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1090                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1091                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1092                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1093                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1094                         return PHY_ERROR;
1095                 }
1096                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1097                 phy_reserved |= PHY_INIT5;
1098                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1099                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1100                         return PHY_ERROR;
1101                 }
1102         }
1103         if (np->phy_oui == PHY_OUI_CICADA) {
1104                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1105                 phy_reserved |= PHY_INIT6;
1106                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1107                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1108                         return PHY_ERROR;
1109                 }
1110         }
1111         /* some phys clear out pause advertisment on reset, set it back */
1112         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1113
1114         /* restart auto negotiation */
1115         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1116         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1117         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1118                 return PHY_ERROR;
1119         }
1120
1121         return 0;
1122 }
1123
1124 static void nv_start_rx(struct net_device *dev)
1125 {
1126         struct fe_priv *np = netdev_priv(dev);
1127         u8 __iomem *base = get_hwbase(dev);
1128
1129         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1130         /* Already running? Stop it. */
1131         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1132                 writel(0, base + NvRegReceiverControl);
1133                 pci_push(base);
1134         }
1135         writel(np->linkspeed, base + NvRegLinkSpeed);
1136         pci_push(base);
1137         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1138         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1139                                 dev->name, np->duplex, np->linkspeed);
1140         pci_push(base);
1141 }
1142
1143 static void nv_stop_rx(struct net_device *dev)
1144 {
1145         u8 __iomem *base = get_hwbase(dev);
1146
1147         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1148         writel(0, base + NvRegReceiverControl);
1149         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1150                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1151                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1152
1153         udelay(NV_RXSTOP_DELAY2);
1154         writel(0, base + NvRegLinkSpeed);
1155 }
1156
1157 static void nv_start_tx(struct net_device *dev)
1158 {
1159         u8 __iomem *base = get_hwbase(dev);
1160
1161         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1162         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1163         pci_push(base);
1164 }
1165
1166 static void nv_stop_tx(struct net_device *dev)
1167 {
1168         u8 __iomem *base = get_hwbase(dev);
1169
1170         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1171         writel(0, base + NvRegTransmitterControl);
1172         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1173                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1174                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1175
1176         udelay(NV_TXSTOP_DELAY2);
1177         writel(0, base + NvRegUnknownTransmitterReg);
1178 }
1179
1180 static void nv_txrx_reset(struct net_device *dev)
1181 {
1182         struct fe_priv *np = netdev_priv(dev);
1183         u8 __iomem *base = get_hwbase(dev);
1184
1185         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1186         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1187         pci_push(base);
1188         udelay(NV_TXRX_RESET_DELAY);
1189         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1190         pci_push(base);
1191 }
1192
1193 static void nv_mac_reset(struct net_device *dev)
1194 {
1195         struct fe_priv *np = netdev_priv(dev);
1196         u8 __iomem *base = get_hwbase(dev);
1197
1198         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1199         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1200         pci_push(base);
1201         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1202         pci_push(base);
1203         udelay(NV_MAC_RESET_DELAY);
1204         writel(0, base + NvRegMacReset);
1205         pci_push(base);
1206         udelay(NV_MAC_RESET_DELAY);
1207         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1208         pci_push(base);
1209 }
1210
1211 /*
1212  * nv_get_stats: dev->get_stats function
1213  * Get latest stats value from the nic.
1214  * Called with read_lock(&dev_base_lock) held for read -
1215  * only synchronized against unregister_netdevice.
1216  */
1217 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1218 {
1219         struct fe_priv *np = netdev_priv(dev);
1220
1221         /* It seems that the nic always generates interrupts and doesn't
1222          * accumulate errors internally. Thus the current values in np->stats
1223          * are already up to date.
1224          */
1225         return &np->stats;
1226 }
1227
1228 /*
1229  * nv_alloc_rx: fill rx ring entries.
1230  * Return 1 if the allocations for the skbs failed and the
1231  * rx engine is without Available descriptors
1232  */
1233 static int nv_alloc_rx(struct net_device *dev)
1234 {
1235         struct fe_priv *np = netdev_priv(dev);
1236         unsigned int refill_rx = np->refill_rx;
1237         int nr;
1238
1239         while (np->cur_rx != refill_rx) {
1240                 struct sk_buff *skb;
1241
1242                 nr = refill_rx % np->rx_ring_size;
1243                 if (np->rx_skbuff[nr] == NULL) {
1244
1245                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1246                         if (!skb)
1247                                 break;
1248
1249                         skb->dev = dev;
1250                         np->rx_skbuff[nr] = skb;
1251                 } else {
1252                         skb = np->rx_skbuff[nr];
1253                 }
1254                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1255                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1256                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1257                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1258                         wmb();
1259                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1260                 } else {
1261                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1262                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1263                         wmb();
1264                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1265                 }
1266                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1267                                         dev->name, refill_rx);
1268                 refill_rx++;
1269         }
1270         np->refill_rx = refill_rx;
1271         if (np->cur_rx - refill_rx == np->rx_ring_size)
1272                 return 1;
1273         return 0;
1274 }
1275
1276 static void nv_do_rx_refill(unsigned long data)
1277 {
1278         struct net_device *dev = (struct net_device *) data;
1279         struct fe_priv *np = netdev_priv(dev);
1280
1281         if (!using_multi_irqs(dev)) {
1282                 if (np->msi_flags & NV_MSI_X_ENABLED)
1283                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1284                 else
1285                         disable_irq(dev->irq);
1286         } else {
1287                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1288         }
1289         if (nv_alloc_rx(dev)) {
1290                 spin_lock_irq(&np->lock);
1291                 if (!np->in_shutdown)
1292                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1293                 spin_unlock_irq(&np->lock);
1294         }
1295         if (!using_multi_irqs(dev)) {
1296                 if (np->msi_flags & NV_MSI_X_ENABLED)
1297                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1298                 else
1299                         enable_irq(dev->irq);
1300         } else {
1301                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1302         }
1303 }
1304
1305 static void nv_init_rx(struct net_device *dev)
1306 {
1307         struct fe_priv *np = netdev_priv(dev);
1308         int i;
1309
1310         np->cur_rx = np->rx_ring_size;
1311         np->refill_rx = 0;
1312         for (i = 0; i < np->rx_ring_size; i++)
1313                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1314                         np->rx_ring.orig[i].FlagLen = 0;
1315                 else
1316                         np->rx_ring.ex[i].FlagLen = 0;
1317 }
1318
1319 static void nv_init_tx(struct net_device *dev)
1320 {
1321         struct fe_priv *np = netdev_priv(dev);
1322         int i;
1323
1324         np->next_tx = np->nic_tx = 0;
1325         for (i = 0; i < np->tx_ring_size; i++) {
1326                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1327                         np->tx_ring.orig[i].FlagLen = 0;
1328                 else
1329                         np->tx_ring.ex[i].FlagLen = 0;
1330                 np->tx_skbuff[i] = NULL;
1331                 np->tx_dma[i] = 0;
1332         }
1333 }
1334
1335 static int nv_init_ring(struct net_device *dev)
1336 {
1337         nv_init_tx(dev);
1338         nv_init_rx(dev);
1339         return nv_alloc_rx(dev);
1340 }
1341
1342 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1343 {
1344         struct fe_priv *np = netdev_priv(dev);
1345
1346         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1347                 dev->name, skbnr);
1348
1349         if (np->tx_dma[skbnr]) {
1350                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1351                                np->tx_dma_len[skbnr],
1352                                PCI_DMA_TODEVICE);
1353                 np->tx_dma[skbnr] = 0;
1354         }
1355
1356         if (np->tx_skbuff[skbnr]) {
1357                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1358                 np->tx_skbuff[skbnr] = NULL;
1359                 return 1;
1360         } else {
1361                 return 0;
1362         }
1363 }
1364
1365 static void nv_drain_tx(struct net_device *dev)
1366 {
1367         struct fe_priv *np = netdev_priv(dev);
1368         unsigned int i;
1369
1370         for (i = 0; i < np->tx_ring_size; i++) {
1371                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1372                         np->tx_ring.orig[i].FlagLen = 0;
1373                 else
1374                         np->tx_ring.ex[i].FlagLen = 0;
1375                 if (nv_release_txskb(dev, i))
1376                         np->stats.tx_dropped++;
1377         }
1378 }
1379
1380 static void nv_drain_rx(struct net_device *dev)
1381 {
1382         struct fe_priv *np = netdev_priv(dev);
1383         int i;
1384         for (i = 0; i < np->rx_ring_size; i++) {
1385                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1386                         np->rx_ring.orig[i].FlagLen = 0;
1387                 else
1388                         np->rx_ring.ex[i].FlagLen = 0;
1389                 wmb();
1390                 if (np->rx_skbuff[i]) {
1391                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1392                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1393                                                 PCI_DMA_FROMDEVICE);
1394                         dev_kfree_skb(np->rx_skbuff[i]);
1395                         np->rx_skbuff[i] = NULL;
1396                 }
1397         }
1398 }
1399
1400 static void drain_ring(struct net_device *dev)
1401 {
1402         nv_drain_tx(dev);
1403         nv_drain_rx(dev);
1404 }
1405
1406 /*
1407  * nv_start_xmit: dev->hard_start_xmit function
1408  * Called with netif_tx_lock held.
1409  */
1410 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1411 {
1412         struct fe_priv *np = netdev_priv(dev);
1413         u32 tx_flags = 0;
1414         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1415         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1416         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1417         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1418         unsigned int i;
1419         u32 offset = 0;
1420         u32 bcnt;
1421         u32 size = skb->len-skb->data_len;
1422         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1423         u32 tx_flags_vlan = 0;
1424
1425         /* add fragments to entries count */
1426         for (i = 0; i < fragments; i++) {
1427                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1428                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1429         }
1430
1431         spin_lock_irq(&np->lock);
1432
1433         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1434                 spin_unlock_irq(&np->lock);
1435                 netif_stop_queue(dev);
1436                 return NETDEV_TX_BUSY;
1437         }
1438
1439         /* setup the header buffer */
1440         do {
1441                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1442                 nr = (nr + 1) % np->tx_ring_size;
1443
1444                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1445                                                 PCI_DMA_TODEVICE);
1446                 np->tx_dma_len[nr] = bcnt;
1447
1448                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1449                         np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1450                         np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1451                 } else {
1452                         np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1453                         np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1454                         np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1455                 }
1456                 tx_flags = np->tx_flags;
1457                 offset += bcnt;
1458                 size -= bcnt;
1459         } while(size);
1460
1461         /* setup the fragments */
1462         for (i = 0; i < fragments; i++) {
1463                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1464                 u32 size = frag->size;
1465                 offset = 0;
1466
1467                 do {
1468                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1469                         nr = (nr + 1) % np->tx_ring_size;
1470
1471                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1472                                                       PCI_DMA_TODEVICE);
1473                         np->tx_dma_len[nr] = bcnt;
1474
1475                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1476                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1477                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1478                         } else {
1479                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1480                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1481                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1482                         }
1483                         offset += bcnt;
1484                         size -= bcnt;
1485                 } while (size);
1486         }
1487
1488         /* set last fragment flag  */
1489         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1490                 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1491         } else {
1492                 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1493         }
1494
1495         np->tx_skbuff[nr] = skb;
1496
1497 #ifdef NETIF_F_TSO
1498         if (skb_is_gso(skb))
1499                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1500         else
1501 #endif
1502         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1503
1504         /* vlan tag */
1505         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1506                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1507         }
1508
1509         /* set tx flags */
1510         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1511                 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1512         } else {
1513                 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1514                 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1515         }
1516
1517         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1518                 dev->name, np->next_tx, entries, tx_flags_extra);
1519         {
1520                 int j;
1521                 for (j=0; j<64; j++) {
1522                         if ((j%16) == 0)
1523                                 dprintk("\n%03x:", j);
1524                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1525                 }
1526                 dprintk("\n");
1527         }
1528
1529         np->next_tx += entries;
1530
1531         dev->trans_start = jiffies;
1532         spin_unlock_irq(&np->lock);
1533         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1534         pci_push(get_hwbase(dev));
1535         return NETDEV_TX_OK;
1536 }
1537
1538 /*
1539  * nv_tx_done: check for completed packets, release the skbs.
1540  *
1541  * Caller must own np->lock.
1542  */
1543 static void nv_tx_done(struct net_device *dev)
1544 {
1545         struct fe_priv *np = netdev_priv(dev);
1546         u32 Flags;
1547         unsigned int i;
1548         struct sk_buff *skb;
1549
1550         while (np->nic_tx != np->next_tx) {
1551                 i = np->nic_tx % np->tx_ring_size;
1552
1553                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1554                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1555                 else
1556                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1557
1558                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1559                                         dev->name, np->nic_tx, Flags);
1560                 if (Flags & NV_TX_VALID)
1561                         break;
1562                 if (np->desc_ver == DESC_VER_1) {
1563                         if (Flags & NV_TX_LASTPACKET) {
1564                                 skb = np->tx_skbuff[i];
1565                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1566                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1567                                         if (Flags & NV_TX_UNDERFLOW)
1568                                                 np->stats.tx_fifo_errors++;
1569                                         if (Flags & NV_TX_CARRIERLOST)
1570                                                 np->stats.tx_carrier_errors++;
1571                                         np->stats.tx_errors++;
1572                                 } else {
1573                                         np->stats.tx_packets++;
1574                                         np->stats.tx_bytes += skb->len;
1575                                 }
1576                         }
1577                 } else {
1578                         if (Flags & NV_TX2_LASTPACKET) {
1579                                 skb = np->tx_skbuff[i];
1580                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1581                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1582                                         if (Flags & NV_TX2_UNDERFLOW)
1583                                                 np->stats.tx_fifo_errors++;
1584                                         if (Flags & NV_TX2_CARRIERLOST)
1585                                                 np->stats.tx_carrier_errors++;
1586                                         np->stats.tx_errors++;
1587                                 } else {
1588                                         np->stats.tx_packets++;
1589                                         np->stats.tx_bytes += skb->len;
1590                                 }
1591                         }
1592                 }
1593                 nv_release_txskb(dev, i);
1594                 np->nic_tx++;
1595         }
1596         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1597                 netif_wake_queue(dev);
1598 }
1599
1600 /*
1601  * nv_tx_timeout: dev->tx_timeout function
1602  * Called with netif_tx_lock held.
1603  */
1604 static void nv_tx_timeout(struct net_device *dev)
1605 {
1606         struct fe_priv *np = netdev_priv(dev);
1607         u8 __iomem *base = get_hwbase(dev);
1608         u32 status;
1609
1610         if (np->msi_flags & NV_MSI_X_ENABLED)
1611                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1612         else
1613                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1614
1615         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1616
1617         {
1618                 int i;
1619
1620                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1621                                 dev->name, (unsigned long)np->ring_addr,
1622                                 np->next_tx, np->nic_tx);
1623                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1624                 for (i=0;i<=np->register_size;i+= 32) {
1625                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1626                                         i,
1627                                         readl(base + i + 0), readl(base + i + 4),
1628                                         readl(base + i + 8), readl(base + i + 12),
1629                                         readl(base + i + 16), readl(base + i + 20),
1630                                         readl(base + i + 24), readl(base + i + 28));
1631                 }
1632                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1633                 for (i=0;i<np->tx_ring_size;i+= 4) {
1634                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1635                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1636                                        i,
1637                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1638                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1639                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1640                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1641                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1642                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1643                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1644                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1645                         } else {
1646                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1647                                        i,
1648                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1649                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1650                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1651                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1652                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1653                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1654                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1655                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1656                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1657                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1658                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1659                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1660                         }
1661                 }
1662         }
1663
1664         spin_lock_irq(&np->lock);
1665
1666         /* 1) stop tx engine */
1667         nv_stop_tx(dev);
1668
1669         /* 2) check that the packets were not sent already: */
1670         nv_tx_done(dev);
1671
1672         /* 3) if there are dead entries: clear everything */
1673         if (np->next_tx != np->nic_tx) {
1674                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1675                 nv_drain_tx(dev);
1676                 np->next_tx = np->nic_tx = 0;
1677                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1678                 netif_wake_queue(dev);
1679         }
1680
1681         /* 4) restart tx engine */
1682         nv_start_tx(dev);
1683         spin_unlock_irq(&np->lock);
1684 }
1685
1686 /*
1687  * Called when the nic notices a mismatch between the actual data len on the
1688  * wire and the len indicated in the 802 header
1689  */
1690 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1691 {
1692         int hdrlen;     /* length of the 802 header */
1693         int protolen;   /* length as stored in the proto field */
1694
1695         /* 1) calculate len according to header */
1696         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1697                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1698                 hdrlen = VLAN_HLEN;
1699         } else {
1700                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1701                 hdrlen = ETH_HLEN;
1702         }
1703         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1704                                 dev->name, datalen, protolen, hdrlen);
1705         if (protolen > ETH_DATA_LEN)
1706                 return datalen; /* Value in proto field not a len, no checks possible */
1707
1708         protolen += hdrlen;
1709         /* consistency checks: */
1710         if (datalen > ETH_ZLEN) {
1711                 if (datalen >= protolen) {
1712                         /* more data on wire than in 802 header, trim of
1713                          * additional data.
1714                          */
1715                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1716                                         dev->name, protolen);
1717                         return protolen;
1718                 } else {
1719                         /* less data on wire than mentioned in header.
1720                          * Discard the packet.
1721                          */
1722                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1723                                         dev->name);
1724                         return -1;
1725                 }
1726         } else {
1727                 /* short packet. Accept only if 802 values are also short */
1728                 if (protolen > ETH_ZLEN) {
1729                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1730                                         dev->name);
1731                         return -1;
1732                 }
1733                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1734                                 dev->name, datalen);
1735                 return datalen;
1736         }
1737 }
1738
1739 static void nv_rx_process(struct net_device *dev)
1740 {
1741         struct fe_priv *np = netdev_priv(dev);
1742         u32 Flags;
1743         u32 vlanflags = 0;
1744
1745         for (;;) {
1746                 struct sk_buff *skb;
1747                 int len;
1748                 int i;
1749                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1750                         break;  /* we scanned the whole ring - do not continue */
1751
1752                 i = np->cur_rx % np->rx_ring_size;
1753                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1754                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1755                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1756                 } else {
1757                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1758                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1759                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1760                 }
1761
1762                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1763                                         dev->name, np->cur_rx, Flags);
1764
1765                 if (Flags & NV_RX_AVAIL)
1766                         break;  /* still owned by hardware, */
1767
1768                 /*
1769                  * the packet is for us - immediately tear down the pci mapping.
1770                  * TODO: check if a prefetch of the first cacheline improves
1771                  * the performance.
1772                  */
1773                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1774                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1775                                 PCI_DMA_FROMDEVICE);
1776
1777                 {
1778                         int j;
1779                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1780                         for (j=0; j<64; j++) {
1781                                 if ((j%16) == 0)
1782                                         dprintk("\n%03x:", j);
1783                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1784                         }
1785                         dprintk("\n");
1786                 }
1787                 /* look at what we actually got: */
1788                 if (np->desc_ver == DESC_VER_1) {
1789                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1790                                 goto next_pkt;
1791
1792                         if (Flags & NV_RX_ERROR) {
1793                                 if (Flags & NV_RX_MISSEDFRAME) {
1794                                         np->stats.rx_missed_errors++;
1795                                         np->stats.rx_errors++;
1796                                         goto next_pkt;
1797                                 }
1798                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1799                                         np->stats.rx_errors++;
1800                                         goto next_pkt;
1801                                 }
1802                                 if (Flags & NV_RX_CRCERR) {
1803                                         np->stats.rx_crc_errors++;
1804                                         np->stats.rx_errors++;
1805                                         goto next_pkt;
1806                                 }
1807                                 if (Flags & NV_RX_OVERFLOW) {
1808                                         np->stats.rx_over_errors++;
1809                                         np->stats.rx_errors++;
1810                                         goto next_pkt;
1811                                 }
1812                                 if (Flags & NV_RX_ERROR4) {
1813                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1814                                         if (len < 0) {
1815                                                 np->stats.rx_errors++;
1816                                                 goto next_pkt;
1817                                         }
1818                                 }
1819                                 /* framing errors are soft errors. */
1820                                 if (Flags & NV_RX_FRAMINGERR) {
1821                                         if (Flags & NV_RX_SUBSTRACT1) {
1822                                                 len--;
1823                                         }
1824                                 }
1825                         }
1826                 } else {
1827                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1828                                 goto next_pkt;
1829
1830                         if (Flags & NV_RX2_ERROR) {
1831                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1832                                         np->stats.rx_errors++;
1833                                         goto next_pkt;
1834                                 }
1835                                 if (Flags & NV_RX2_CRCERR) {
1836                                         np->stats.rx_crc_errors++;
1837                                         np->stats.rx_errors++;
1838                                         goto next_pkt;
1839                                 }
1840                                 if (Flags & NV_RX2_OVERFLOW) {
1841                                         np->stats.rx_over_errors++;
1842                                         np->stats.rx_errors++;
1843                                         goto next_pkt;
1844                                 }
1845                                 if (Flags & NV_RX2_ERROR4) {
1846                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1847                                         if (len < 0) {
1848                                                 np->stats.rx_errors++;
1849                                                 goto next_pkt;
1850                                         }
1851                                 }
1852                                 /* framing errors are soft errors */
1853                                 if (Flags & NV_RX2_FRAMINGERR) {
1854                                         if (Flags & NV_RX2_SUBSTRACT1) {
1855                                                 len--;
1856                                         }
1857                                 }
1858                         }
1859                         if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1860                                 Flags &= NV_RX2_CHECKSUMMASK;
1861                                 if (Flags == NV_RX2_CHECKSUMOK1 ||
1862                                     Flags == NV_RX2_CHECKSUMOK2 ||
1863                                     Flags == NV_RX2_CHECKSUMOK3) {
1864                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1865                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1866                                 } else {
1867                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1868                                 }
1869                         }
1870                 }
1871                 /* got a valid packet - forward it to the network core */
1872                 skb = np->rx_skbuff[i];
1873                 np->rx_skbuff[i] = NULL;
1874
1875                 skb_put(skb, len);
1876                 skb->protocol = eth_type_trans(skb, dev);
1877                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1878                                         dev->name, np->cur_rx, len, skb->protocol);
1879                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1880                         vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1881                 } else {
1882                         netif_rx(skb);
1883                 }
1884                 dev->last_rx = jiffies;
1885                 np->stats.rx_packets++;
1886                 np->stats.rx_bytes += len;
1887 next_pkt:
1888                 np->cur_rx++;
1889         }
1890 }
1891
1892 static void set_bufsize(struct net_device *dev)
1893 {
1894         struct fe_priv *np = netdev_priv(dev);
1895
1896         if (dev->mtu <= ETH_DATA_LEN)
1897                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1898         else
1899                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1900 }
1901
1902 /*
1903  * nv_change_mtu: dev->change_mtu function
1904  * Called with dev_base_lock held for read.
1905  */
1906 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1907 {
1908         struct fe_priv *np = netdev_priv(dev);
1909         int old_mtu;
1910
1911         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1912                 return -EINVAL;
1913
1914         old_mtu = dev->mtu;
1915         dev->mtu = new_mtu;
1916
1917         /* return early if the buffer sizes will not change */
1918         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1919                 return 0;
1920         if (old_mtu == new_mtu)
1921                 return 0;
1922
1923         /* synchronized against open : rtnl_lock() held by caller */
1924         if (netif_running(dev)) {
1925                 u8 __iomem *base = get_hwbase(dev);
1926                 /*
1927                  * It seems that the nic preloads valid ring entries into an
1928                  * internal buffer. The procedure for flushing everything is
1929                  * guessed, there is probably a simpler approach.
1930                  * Changing the MTU is a rare event, it shouldn't matter.
1931                  */
1932                 nv_disable_irq(dev);
1933                 netif_tx_lock_bh(dev);
1934                 spin_lock(&np->lock);
1935                 /* stop engines */
1936                 nv_stop_rx(dev);
1937                 nv_stop_tx(dev);
1938                 nv_txrx_reset(dev);
1939                 /* drain rx queue */
1940                 nv_drain_rx(dev);
1941                 nv_drain_tx(dev);
1942                 /* reinit driver view of the rx queue */
1943                 set_bufsize(dev);
1944                 if (nv_init_ring(dev)) {
1945                         if (!np->in_shutdown)
1946                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1947                 }
1948                 /* reinit nic view of the rx queue */
1949                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1950                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1951                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1952                         base + NvRegRingSizes);
1953                 pci_push(base);
1954                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1955                 pci_push(base);
1956
1957                 /* restart rx engine */
1958                 nv_start_rx(dev);
1959                 nv_start_tx(dev);
1960                 spin_unlock(&np->lock);
1961                 netif_tx_unlock_bh(dev);
1962                 nv_enable_irq(dev);
1963         }
1964         return 0;
1965 }
1966
1967 static void nv_copy_mac_to_hw(struct net_device *dev)
1968 {
1969         u8 __iomem *base = get_hwbase(dev);
1970         u32 mac[2];
1971
1972         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1973                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1974         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1975
1976         writel(mac[0], base + NvRegMacAddrA);
1977         writel(mac[1], base + NvRegMacAddrB);
1978 }
1979
1980 /*
1981  * nv_set_mac_address: dev->set_mac_address function
1982  * Called with rtnl_lock() held.
1983  */
1984 static int nv_set_mac_address(struct net_device *dev, void *addr)
1985 {
1986         struct fe_priv *np = netdev_priv(dev);
1987         struct sockaddr *macaddr = (struct sockaddr*)addr;
1988
1989         if(!is_valid_ether_addr(macaddr->sa_data))
1990                 return -EADDRNOTAVAIL;
1991
1992         /* synchronized against open : rtnl_lock() held by caller */
1993         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1994
1995         if (netif_running(dev)) {
1996                 netif_tx_lock_bh(dev);
1997                 spin_lock_irq(&np->lock);
1998
1999                 /* stop rx engine */
2000                 nv_stop_rx(dev);
2001
2002                 /* set mac address */
2003                 nv_copy_mac_to_hw(dev);
2004
2005                 /* restart rx engine */
2006                 nv_start_rx(dev);
2007                 spin_unlock_irq(&np->lock);
2008                 netif_tx_unlock_bh(dev);
2009         } else {
2010                 nv_copy_mac_to_hw(dev);
2011         }
2012         return 0;
2013 }
2014
2015 /*
2016  * nv_set_multicast: dev->set_multicast function
2017  * Called with netif_tx_lock held.
2018  */
2019 static void nv_set_multicast(struct net_device *dev)
2020 {
2021         struct fe_priv *np = netdev_priv(dev);
2022         u8 __iomem *base = get_hwbase(dev);
2023         u32 addr[2];
2024         u32 mask[2];
2025         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2026
2027         memset(addr, 0, sizeof(addr));
2028         memset(mask, 0, sizeof(mask));
2029
2030         if (dev->flags & IFF_PROMISC) {
2031                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2032                 pff |= NVREG_PFF_PROMISC;
2033         } else {
2034                 pff |= NVREG_PFF_MYADDR;
2035
2036                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2037                         u32 alwaysOff[2];
2038                         u32 alwaysOn[2];
2039
2040                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2041                         if (dev->flags & IFF_ALLMULTI) {
2042                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2043                         } else {
2044                                 struct dev_mc_list *walk;
2045
2046                                 walk = dev->mc_list;
2047                                 while (walk != NULL) {
2048                                         u32 a, b;
2049                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2050                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2051                                         alwaysOn[0] &= a;
2052                                         alwaysOff[0] &= ~a;
2053                                         alwaysOn[1] &= b;
2054                                         alwaysOff[1] &= ~b;
2055                                         walk = walk->next;
2056                                 }
2057                         }
2058                         addr[0] = alwaysOn[0];
2059                         addr[1] = alwaysOn[1];
2060                         mask[0] = alwaysOn[0] | alwaysOff[0];
2061                         mask[1] = alwaysOn[1] | alwaysOff[1];
2062                 }
2063         }
2064         addr[0] |= NVREG_MCASTADDRA_FORCE;
2065         pff |= NVREG_PFF_ALWAYS;
2066         spin_lock_irq(&np->lock);
2067         nv_stop_rx(dev);
2068         writel(addr[0], base + NvRegMulticastAddrA);
2069         writel(addr[1], base + NvRegMulticastAddrB);
2070         writel(mask[0], base + NvRegMulticastMaskA);
2071         writel(mask[1], base + NvRegMulticastMaskB);
2072         writel(pff, base + NvRegPacketFilterFlags);
2073         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2074                 dev->name);
2075         nv_start_rx(dev);
2076         spin_unlock_irq(&np->lock);
2077 }
2078
2079 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2080 {
2081         struct fe_priv *np = netdev_priv(dev);
2082         u8 __iomem *base = get_hwbase(dev);
2083
2084         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2085
2086         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2087                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2088                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2089                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2090                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2091                 } else {
2092                         writel(pff, base + NvRegPacketFilterFlags);
2093                 }
2094         }
2095         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2096                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2097                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2098                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2099                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2100                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2101                 } else {
2102                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2103                         writel(regmisc, base + NvRegMisc1);
2104                 }
2105         }
2106 }
2107
2108 /**
2109  * nv_update_linkspeed: Setup the MAC according to the link partner
2110  * @dev: Network device to be configured
2111  *
2112  * The function queries the PHY and checks if there is a link partner.
2113  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2114  * set to 10 MBit HD.
2115  *
2116  * The function returns 0 if there is no link partner and 1 if there is
2117  * a good link partner.
2118  */
2119 static int nv_update_linkspeed(struct net_device *dev)
2120 {
2121         struct fe_priv *np = netdev_priv(dev);
2122         u8 __iomem *base = get_hwbase(dev);
2123         int adv = 0;
2124         int lpa = 0;
2125         int adv_lpa, adv_pause, lpa_pause;
2126         int newls = np->linkspeed;
2127         int newdup = np->duplex;
2128         int mii_status;
2129         int retval = 0;
2130         u32 control_1000, status_1000, phyreg, pause_flags;
2131
2132         /* BMSR_LSTATUS is latched, read it twice:
2133          * we want the current value.
2134          */
2135         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2136         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2137
2138         if (!(mii_status & BMSR_LSTATUS)) {
2139                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2140                                 dev->name);
2141                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2142                 newdup = 0;
2143                 retval = 0;
2144                 goto set_speed;
2145         }
2146
2147         if (np->autoneg == 0) {
2148                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2149                                 dev->name, np->fixed_mode);
2150                 if (np->fixed_mode & LPA_100FULL) {
2151                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2152                         newdup = 1;
2153                 } else if (np->fixed_mode & LPA_100HALF) {
2154                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2155                         newdup = 0;
2156                 } else if (np->fixed_mode & LPA_10FULL) {
2157                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2158                         newdup = 1;
2159                 } else {
2160                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2161                         newdup = 0;
2162                 }
2163                 retval = 1;
2164                 goto set_speed;
2165         }
2166         /* check auto negotiation is complete */
2167         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2168                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2169                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2170                 newdup = 0;
2171                 retval = 0;
2172                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2173                 goto set_speed;
2174         }
2175
2176         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2177         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2178         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2179                                 dev->name, adv, lpa);
2180
2181         retval = 1;
2182         if (np->gigabit == PHY_GIGABIT) {
2183                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2184                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2185
2186                 if ((control_1000 & ADVERTISE_1000FULL) &&
2187                         (status_1000 & LPA_1000FULL)) {
2188                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2189                                 dev->name);
2190                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2191                         newdup = 1;
2192                         goto set_speed;
2193                 }
2194         }
2195
2196         /* FIXME: handle parallel detection properly */
2197         adv_lpa = lpa & adv;
2198         if (adv_lpa & LPA_100FULL) {
2199                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2200                 newdup = 1;
2201         } else if (adv_lpa & LPA_100HALF) {
2202                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2203                 newdup = 0;
2204         } else if (adv_lpa & LPA_10FULL) {
2205                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2206                 newdup = 1;
2207         } else if (adv_lpa & LPA_10HALF) {
2208                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2209                 newdup = 0;
2210         } else {
2211                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2212                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2213                 newdup = 0;
2214         }
2215
2216 set_speed:
2217         if (np->duplex == newdup && np->linkspeed == newls)
2218                 return retval;
2219
2220         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2221                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2222
2223         np->duplex = newdup;
2224         np->linkspeed = newls;
2225
2226         if (np->gigabit == PHY_GIGABIT) {
2227                 phyreg = readl(base + NvRegRandomSeed);
2228                 phyreg &= ~(0x3FF00);
2229                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2230                         phyreg |= NVREG_RNDSEED_FORCE3;
2231                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2232                         phyreg |= NVREG_RNDSEED_FORCE2;
2233                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2234                         phyreg |= NVREG_RNDSEED_FORCE;
2235                 writel(phyreg, base + NvRegRandomSeed);
2236         }
2237
2238         phyreg = readl(base + NvRegPhyInterface);
2239         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2240         if (np->duplex == 0)
2241                 phyreg |= PHY_HALF;
2242         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2243                 phyreg |= PHY_100;
2244         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2245                 phyreg |= PHY_1000;
2246         writel(phyreg, base + NvRegPhyInterface);
2247
2248         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2249                 base + NvRegMisc1);
2250         pci_push(base);
2251         writel(np->linkspeed, base + NvRegLinkSpeed);
2252         pci_push(base);
2253
2254         pause_flags = 0;
2255         /* setup pause frame */
2256         if (np->duplex != 0) {
2257                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2258                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2259                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2260
2261                         switch (adv_pause) {
2262                         case (ADVERTISE_PAUSE_CAP):
2263                                 if (lpa_pause & LPA_PAUSE_CAP) {
2264                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2265                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2266                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2267                                 }
2268                                 break;
2269                         case (ADVERTISE_PAUSE_ASYM):
2270                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2271                                 {
2272                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2273                                 }
2274                                 break;
2275                         case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2276                                 if (lpa_pause & LPA_PAUSE_CAP)
2277                                 {
2278                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2279                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2280                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2281                                 }
2282                                 if (lpa_pause == LPA_PAUSE_ASYM)
2283                                 {
2284                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2285                                 }
2286                                 break;
2287                         }
2288                 } else {
2289                         pause_flags = np->pause_flags;
2290                 }
2291         }
2292         nv_update_pause(dev, pause_flags);
2293
2294         return retval;
2295 }
2296
2297 static void nv_linkchange(struct net_device *dev)
2298 {
2299         if (nv_update_linkspeed(dev)) {
2300                 if (!netif_carrier_ok(dev)) {
2301                         netif_carrier_on(dev);
2302                         printk(KERN_INFO "%s: link up.\n", dev->name);
2303                         nv_start_rx(dev);
2304                 }
2305         } else {
2306                 if (netif_carrier_ok(dev)) {
2307                         netif_carrier_off(dev);
2308                         printk(KERN_INFO "%s: link down.\n", dev->name);
2309                         nv_stop_rx(dev);
2310                 }
2311         }
2312 }
2313
2314 static void nv_link_irq(struct net_device *dev)
2315 {
2316         u8 __iomem *base = get_hwbase(dev);
2317         u32 miistat;
2318
2319         miistat = readl(base + NvRegMIIStatus);
2320         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2321         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2322
2323         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2324                 nv_linkchange(dev);
2325         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2326 }
2327
2328 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2329 {
2330         struct net_device *dev = (struct net_device *) data;
2331         struct fe_priv *np = netdev_priv(dev);
2332         u8 __iomem *base = get_hwbase(dev);
2333         u32 events;
2334         int i;
2335
2336         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2337
2338         for (i=0; ; i++) {
2339                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2340                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2341                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2342                 } else {
2343                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2344                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2345                 }
2346                 pci_push(base);
2347                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2348                 if (!(events & np->irqmask))
2349                         break;
2350
2351                 spin_lock(&np->lock);
2352                 nv_tx_done(dev);
2353                 spin_unlock(&np->lock);
2354
2355                 nv_rx_process(dev);
2356                 if (nv_alloc_rx(dev)) {
2357                         spin_lock(&np->lock);
2358                         if (!np->in_shutdown)
2359                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2360                         spin_unlock(&np->lock);
2361                 }
2362
2363                 if (events & NVREG_IRQ_LINK) {
2364                         spin_lock(&np->lock);
2365                         nv_link_irq(dev);
2366                         spin_unlock(&np->lock);
2367                 }
2368                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2369                         spin_lock(&np->lock);
2370                         nv_linkchange(dev);
2371                         spin_unlock(&np->lock);
2372                         np->link_timeout = jiffies + LINK_TIMEOUT;
2373                 }
2374                 if (events & (NVREG_IRQ_TX_ERR)) {
2375                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2376                                                 dev->name, events);
2377                 }
2378                 if (events & (NVREG_IRQ_UNKNOWN)) {
2379                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2380                                                 dev->name, events);
2381                 }
2382                 if (i > max_interrupt_work) {
2383                         spin_lock(&np->lock);
2384                         /* disable interrupts on the nic */
2385                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2386                                 writel(0, base + NvRegIrqMask);
2387                         else
2388                                 writel(np->irqmask, base + NvRegIrqMask);
2389                         pci_push(base);
2390
2391                         if (!np->in_shutdown) {
2392                                 np->nic_poll_irq = np->irqmask;
2393                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2394                         }
2395                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2396                         spin_unlock(&np->lock);
2397                         break;
2398                 }
2399
2400         }
2401         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2402
2403         return IRQ_RETVAL(i);
2404 }
2405
2406 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2407 {
2408         struct net_device *dev = (struct net_device *) data;
2409         struct fe_priv *np = netdev_priv(dev);
2410         u8 __iomem *base = get_hwbase(dev);
2411         u32 events;
2412         int i;
2413
2414         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2415
2416         for (i=0; ; i++) {
2417                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2418                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2419                 pci_push(base);
2420                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2421                 if (!(events & np->irqmask))
2422                         break;
2423
2424                 spin_lock_irq(&np->lock);
2425                 nv_tx_done(dev);
2426                 spin_unlock_irq(&np->lock);
2427
2428                 if (events & (NVREG_IRQ_TX_ERR)) {
2429                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2430                                                 dev->name, events);
2431                 }
2432                 if (i > max_interrupt_work) {
2433                         spin_lock_irq(&np->lock);
2434                         /* disable interrupts on the nic */
2435                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2436                         pci_push(base);
2437
2438                         if (!np->in_shutdown) {
2439                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2440                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2441                         }
2442                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2443                         spin_unlock_irq(&np->lock);
2444                         break;
2445                 }
2446
2447         }
2448         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2449
2450         return IRQ_RETVAL(i);
2451 }
2452
2453 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2454 {
2455         struct net_device *dev = (struct net_device *) data;
2456         struct fe_priv *np = netdev_priv(dev);
2457         u8 __iomem *base = get_hwbase(dev);
2458         u32 events;
2459         int i;
2460
2461         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2462
2463         for (i=0; ; i++) {
2464                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2465                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2466                 pci_push(base);
2467                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2468                 if (!(events & np->irqmask))
2469                         break;
2470
2471                 nv_rx_process(dev);
2472                 if (nv_alloc_rx(dev)) {
2473                         spin_lock_irq(&np->lock);
2474                         if (!np->in_shutdown)
2475                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2476                         spin_unlock_irq(&np->lock);
2477                 }
2478
2479                 if (i > max_interrupt_work) {
2480                         spin_lock_irq(&np->lock);
2481                         /* disable interrupts on the nic */
2482                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2483                         pci_push(base);
2484
2485                         if (!np->in_shutdown) {
2486                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2487                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2488                         }
2489                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2490                         spin_unlock_irq(&np->lock);
2491                         break;
2492                 }
2493
2494         }
2495         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2496
2497         return IRQ_RETVAL(i);
2498 }
2499
2500 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2501 {
2502         struct net_device *dev = (struct net_device *) data;
2503         struct fe_priv *np = netdev_priv(dev);
2504         u8 __iomem *base = get_hwbase(dev);
2505         u32 events;
2506         int i;
2507
2508         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2509
2510         for (i=0; ; i++) {
2511                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2512                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2513                 pci_push(base);
2514                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2515                 if (!(events & np->irqmask))
2516                         break;
2517
2518                 if (events & NVREG_IRQ_LINK) {
2519                         spin_lock_irq(&np->lock);
2520                         nv_link_irq(dev);
2521                         spin_unlock_irq(&np->lock);
2522                 }
2523                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2524                         spin_lock_irq(&np->lock);
2525                         nv_linkchange(dev);
2526                         spin_unlock_irq(&np->lock);
2527                         np->link_timeout = jiffies + LINK_TIMEOUT;
2528                 }
2529                 if (events & (NVREG_IRQ_UNKNOWN)) {
2530                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2531                                                 dev->name, events);
2532                 }
2533                 if (i > max_interrupt_work) {
2534                         spin_lock_irq(&np->lock);
2535                         /* disable interrupts on the nic */
2536                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2537                         pci_push(base);
2538
2539                         if (!np->in_shutdown) {
2540                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2541                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2542                         }
2543                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2544                         spin_unlock_irq(&np->lock);
2545                         break;
2546                 }
2547
2548         }
2549         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2550
2551         return IRQ_RETVAL(i);
2552 }
2553
2554 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2555 {
2556         struct net_device *dev = (struct net_device *) data;
2557         struct fe_priv *np = netdev_priv(dev);
2558         u8 __iomem *base = get_hwbase(dev);
2559         u32 events;
2560
2561         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2562
2563         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2564                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2565                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2566         } else {
2567                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2568                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2569         }
2570         pci_push(base);
2571         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2572         if (!(events & NVREG_IRQ_TIMER))
2573                 return IRQ_RETVAL(0);
2574
2575         spin_lock(&np->lock);
2576         np->intr_test = 1;
2577         spin_unlock(&np->lock);
2578
2579         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2580
2581         return IRQ_RETVAL(1);
2582 }
2583
2584 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2585 {
2586         u8 __iomem *base = get_hwbase(dev);
2587         int i;
2588         u32 msixmap = 0;
2589
2590         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2591          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2592          * the remaining 8 interrupts.
2593          */
2594         for (i = 0; i < 8; i++) {
2595                 if ((irqmask >> i) & 0x1) {
2596                         msixmap |= vector << (i << 2);
2597                 }
2598         }
2599         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2600
2601         msixmap = 0;
2602         for (i = 0; i < 8; i++) {
2603                 if ((irqmask >> (i + 8)) & 0x1) {
2604                         msixmap |= vector << (i << 2);
2605                 }
2606         }
2607         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2608 }
2609
2610 static int nv_request_irq(struct net_device *dev, int intr_test)
2611 {
2612         struct fe_priv *np = get_nvpriv(dev);
2613         u8 __iomem *base = get_hwbase(dev);
2614         int ret = 1;
2615         int i;
2616
2617         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2618                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2619                         np->msi_x_entry[i].entry = i;
2620                 }
2621                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2622                         np->msi_flags |= NV_MSI_X_ENABLED;
2623                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2624                                 /* Request irq for rx handling */
2625                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2626                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2627                                         pci_disable_msix(np->pci_dev);
2628                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2629                                         goto out_err;
2630                                 }
2631                                 /* Request irq for tx handling */
2632                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2633                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2634                                         pci_disable_msix(np->pci_dev);
2635                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2636                                         goto out_free_rx;
2637                                 }
2638                                 /* Request irq for link and timer handling */
2639                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2640                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2641                                         pci_disable_msix(np->pci_dev);
2642                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2643                                         goto out_free_tx;
2644                                 }
2645                                 /* map interrupts to their respective vector */
2646                                 writel(0, base + NvRegMSIXMap0);
2647                                 writel(0, base + NvRegMSIXMap1);
2648                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2649                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2650                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2651                         } else {
2652                                 /* Request irq for all interrupts */
2653                                 if ((!intr_test &&
2654                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2655                                     (intr_test &&
2656                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2657                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2658                                         pci_disable_msix(np->pci_dev);
2659                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2660                                         goto out_err;
2661                                 }
2662
2663                                 /* map interrupts to vector 0 */
2664                                 writel(0, base + NvRegMSIXMap0);
2665                                 writel(0, base + NvRegMSIXMap1);
2666                         }
2667                 }
2668         }
2669         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2670                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2671                         np->msi_flags |= NV_MSI_ENABLED;
2672                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2673                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2674                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2675                                 pci_disable_msi(np->pci_dev);
2676                                 np->msi_flags &= ~NV_MSI_ENABLED;
2677                                 goto out_err;
2678                         }
2679
2680                         /* map interrupts to vector 0 */
2681                         writel(0, base + NvRegMSIMap0);
2682                         writel(0, base + NvRegMSIMap1);
2683                         /* enable msi vector 0 */
2684                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2685                 }
2686         }
2687         if (ret != 0) {
2688                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2689                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2690                         goto out_err;
2691
2692         }
2693
2694         return 0;
2695 out_free_tx:
2696         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2697 out_free_rx:
2698         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2699 out_err:
2700         return 1;
2701 }
2702
2703 static void nv_free_irq(struct net_device *dev)
2704 {
2705         struct fe_priv *np = get_nvpriv(dev);
2706         int i;
2707
2708         if (np->msi_flags & NV_MSI_X_ENABLED) {
2709                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2710                         free_irq(np->msi_x_entry[i].vector, dev);
2711                 }
2712                 pci_disable_msix(np->pci_dev);
2713                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2714         } else {
2715                 free_irq(np->pci_dev->irq, dev);
2716                 if (np->msi_flags & NV_MSI_ENABLED) {
2717                         pci_disable_msi(np->pci_dev);
2718                         np->msi_flags &= ~NV_MSI_ENABLED;
2719                 }
2720         }
2721 }
2722
2723 static void nv_do_nic_poll(unsigned long data)
2724 {
2725         struct net_device *dev = (struct net_device *) data;
2726         struct fe_priv *np = netdev_priv(dev);
2727         u8 __iomem *base = get_hwbase(dev);
2728         u32 mask = 0;
2729
2730         /*
2731          * First disable irq(s) and then
2732          * reenable interrupts on the nic, we have to do this before calling
2733          * nv_nic_irq because that may decide to do otherwise
2734          */
2735
2736         if (!using_multi_irqs(dev)) {
2737                 if (np->msi_flags & NV_MSI_X_ENABLED)
2738                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2739                 else
2740                         disable_irq_lockdep(dev->irq);
2741                 mask = np->irqmask;
2742         } else {
2743                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2744                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2745                         mask |= NVREG_IRQ_RX_ALL;
2746                 }
2747                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2748                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2749                         mask |= NVREG_IRQ_TX_ALL;
2750                 }
2751                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2752                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2753                         mask |= NVREG_IRQ_OTHER;
2754                 }
2755         }
2756         np->nic_poll_irq = 0;
2757
2758         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2759
2760         writel(mask, base + NvRegIrqMask);
2761         pci_push(base);
2762
2763         if (!using_multi_irqs(dev)) {
2764                 nv_nic_irq(0, dev, NULL);
2765                 if (np->msi_flags & NV_MSI_X_ENABLED)
2766                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2767                 else
2768                         enable_irq_lockdep(dev->irq);
2769         } else {
2770                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2771                         nv_nic_irq_rx(0, dev, NULL);
2772                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2773                 }
2774                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2775                         nv_nic_irq_tx(0, dev, NULL);
2776                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2777                 }
2778                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2779                         nv_nic_irq_other(0, dev, NULL);
2780                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2781                 }
2782         }
2783 }
2784
2785 #ifdef CONFIG_NET_POLL_CONTROLLER
2786 static void nv_poll_controller(struct net_device *dev)
2787 {
2788         nv_do_nic_poll((unsigned long) dev);
2789 }
2790 #endif
2791
2792 static void nv_do_stats_poll(unsigned long data)
2793 {
2794         struct net_device *dev = (struct net_device *) data;
2795         struct fe_priv *np = netdev_priv(dev);
2796         u8 __iomem *base = get_hwbase(dev);
2797
2798         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2799         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2800         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2801         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2802         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2803         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2804         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2805         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2806         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2807         np->estats.tx_deferral += readl(base + NvRegTxDef);
2808         np->estats.tx_packets += readl(base + NvRegTxFrame);
2809         np->estats.tx_pause += readl(base + NvRegTxPause);
2810         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2811         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2812         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2813         np->estats.rx_runt += readl(base + NvRegRxRunt);
2814         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2815         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2816         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2817         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2818         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2819         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2820         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2821         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2822         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2823         np->estats.rx_pause += readl(base + NvRegRxPause);
2824         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2825         np->estats.rx_packets =
2826                 np->estats.rx_unicast +
2827                 np->estats.rx_multicast +
2828                 np->estats.rx_broadcast;
2829         np->estats.rx_errors_total =
2830                 np->estats.rx_crc_errors +
2831                 np->estats.rx_over_errors +
2832                 np->estats.rx_frame_error +
2833                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2834                 np->estats.rx_late_collision +
2835                 np->estats.rx_runt +
2836                 np->estats.rx_frame_too_long;
2837
2838         if (!np->in_shutdown)
2839                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2840 }
2841
2842 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2843 {
2844         struct fe_priv *np = netdev_priv(dev);
2845         strcpy(info->driver, "forcedeth");
2846         strcpy(info->version, FORCEDETH_VERSION);
2847         strcpy(info->bus_info, pci_name(np->pci_dev));
2848 }
2849
2850 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2851 {
2852         struct fe_priv *np = netdev_priv(dev);
2853         wolinfo->supported = WAKE_MAGIC;
2854
2855         spin_lock_irq(&np->lock);
2856         if (np->wolenabled)
2857                 wolinfo->wolopts = WAKE_MAGIC;
2858         spin_unlock_irq(&np->lock);
2859 }
2860
2861 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2862 {
2863         struct fe_priv *np = netdev_priv(dev);
2864         u8 __iomem *base = get_hwbase(dev);
2865         u32 flags = 0;
2866
2867         if (wolinfo->wolopts == 0) {
2868                 np->wolenabled = 0;
2869         } else if (wolinfo->wolopts & WAKE_MAGIC) {
2870                 np->wolenabled = 1;
2871                 flags = NVREG_WAKEUPFLAGS_ENABLE;
2872         }
2873         if (netif_running(dev)) {
2874                 spin_lock_irq(&np->lock);
2875                 writel(flags, base + NvRegWakeUpFlags);
2876                 spin_unlock_irq(&np->lock);
2877         }
2878         return 0;
2879 }
2880
2881 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2882 {
2883         struct fe_priv *np = netdev_priv(dev);
2884         int adv;
2885
2886         spin_lock_irq(&np->lock);
2887         ecmd->port = PORT_MII;
2888         if (!netif_running(dev)) {
2889                 /* We do not track link speed / duplex setting if the
2890                  * interface is disabled. Force a link check */
2891                 if (nv_update_linkspeed(dev)) {
2892                         if (!netif_carrier_ok(dev))
2893                                 netif_carrier_on(dev);
2894                 } else {
2895                         if (netif_carrier_ok(dev))
2896                                 netif_carrier_off(dev);
2897                 }
2898         }
2899
2900         if (netif_carrier_ok(dev)) {
2901                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2902                 case NVREG_LINKSPEED_10:
2903                         ecmd->speed = SPEED_10;
2904                         break;
2905                 case NVREG_LINKSPEED_100:
2906                         ecmd->speed = SPEED_100;
2907                         break;
2908                 case NVREG_LINKSPEED_1000:
2909                         ecmd->speed = SPEED_1000;
2910                         break;
2911                 }
2912                 ecmd->duplex = DUPLEX_HALF;
2913                 if (np->duplex)
2914                         ecmd->duplex = DUPLEX_FULL;
2915         } else {
2916                 ecmd->speed = -1;
2917                 ecmd->duplex = -1;
2918         }
2919
2920         ecmd->autoneg = np->autoneg;
2921
2922         ecmd->advertising = ADVERTISED_MII;
2923         if (np->autoneg) {
2924                 ecmd->advertising |= ADVERTISED_Autoneg;
2925                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2926                 if (adv & ADVERTISE_10HALF)
2927                         ecmd->advertising |= ADVERTISED_10baseT_Half;
2928                 if (adv & ADVERTISE_10FULL)
2929                         ecmd->advertising |= ADVERTISED_10baseT_Full;
2930                 if (adv & ADVERTISE_100HALF)
2931                         ecmd->advertising |= ADVERTISED_100baseT_Half;
2932                 if (adv & ADVERTISE_100FULL)
2933                         ecmd->advertising |= ADVERTISED_100baseT_Full;
2934                 if (np->gigabit == PHY_GIGABIT) {
2935                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2936                         if (adv & ADVERTISE_1000FULL)
2937                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2938                 }
2939         }
2940         ecmd->supported = (SUPPORTED_Autoneg |
2941                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2942                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2943                 SUPPORTED_MII);
2944         if (np->gigabit == PHY_GIGABIT)
2945                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2946
2947         ecmd->phy_address = np->phyaddr;
2948         ecmd->transceiver = XCVR_EXTERNAL;
2949
2950         /* ignore maxtxpkt, maxrxpkt for now */
2951         spin_unlock_irq(&np->lock);
2952         return 0;
2953 }
2954
2955 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2956 {
2957         struct fe_priv *np = netdev_priv(dev);
2958
2959         if (ecmd->port != PORT_MII)
2960                 return -EINVAL;
2961         if (ecmd->transceiver != XCVR_EXTERNAL)
2962                 return -EINVAL;
2963         if (ecmd->phy_address != np->phyaddr) {
2964                 /* TODO: support switching between multiple phys. Should be
2965                  * trivial, but not enabled due to lack of test hardware. */
2966                 return -EINVAL;
2967         }
2968         if (ecmd->autoneg == AUTONEG_ENABLE) {
2969                 u32 mask;
2970
2971                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2972                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2973                 if (np->gigabit == PHY_GIGABIT)
2974                         mask |= ADVERTISED_1000baseT_Full;
2975
2976                 if ((ecmd->advertising & mask) == 0)
2977                         return -EINVAL;
2978
2979         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2980                 /* Note: autonegotiation disable, speed 1000 intentionally
2981                  * forbidden - noone should need that. */
2982
2983                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2984                         return -EINVAL;
2985                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2986                         return -EINVAL;
2987         } else {
2988                 return -EINVAL;
2989         }
2990
2991         netif_carrier_off(dev);
2992         if (netif_running(dev)) {
2993                 nv_disable_irq(dev);
2994                 netif_tx_lock_bh(dev);
2995                 spin_lock(&np->lock);
2996                 /* stop engines */
2997                 nv_stop_rx(dev);
2998                 nv_stop_tx(dev);
2999                 spin_unlock(&np->lock);
3000                 netif_tx_unlock_bh(dev);
3001         }
3002
3003         if (ecmd->autoneg == AUTONEG_ENABLE) {
3004                 int adv, bmcr;
3005
3006                 np->autoneg = 1;
3007
3008                 /* advertise only what has been requested */
3009                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3010                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3011                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3012                         adv |= ADVERTISE_10HALF;
3013                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3014                         adv |= ADVERTISE_10FULL;
3015                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3016                         adv |= ADVERTISE_100HALF;
3017                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3018                         adv |= ADVERTISE_100FULL;
3019                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3020                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3021                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3022                         adv |=  ADVERTISE_PAUSE_ASYM;
3023                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3024
3025                 if (np->gigabit == PHY_GIGABIT) {
3026                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3027                         adv &= ~ADVERTISE_1000FULL;
3028                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3029                                 adv |= ADVERTISE_1000FULL;
3030                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3031                 }
3032
3033                 if (netif_running(dev))
3034                         printk(KERN_INFO "%s: link down.\n", dev->name);
3035                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3036                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3037                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3038
3039         } else {
3040                 int adv, bmcr;
3041
3042                 np->autoneg = 0;
3043
3044                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3045                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3046                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3047                         adv |= ADVERTISE_10HALF;
3048                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3049                         adv |= ADVERTISE_10FULL;
3050                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3051                         adv |= ADVERTISE_100HALF;
3052                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3053                         adv |= ADVERTISE_100FULL;
3054                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3055                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3056                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3057                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3058                 }
3059                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3060                         adv |=  ADVERTISE_PAUSE_ASYM;
3061                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3062                 }
3063                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3064                 np->fixed_mode = adv;
3065
3066                 if (np->gigabit == PHY_GIGABIT) {
3067                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3068                         adv &= ~ADVERTISE_1000FULL;
3069                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3070                 }
3071
3072                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3073                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3074                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3075                         bmcr |= BMCR_FULLDPLX;
3076                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3077                         bmcr |= BMCR_SPEED100;
3078                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3079                 if (np->phy_oui == PHY_OUI_MARVELL) {
3080                         /* reset the phy */
3081                         if (phy_reset(dev)) {
3082                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3083                                 return -EINVAL;
3084                         }
3085                 } else if (netif_running(dev)) {
3086                         /* Wait a bit and then reconfigure the nic. */
3087                         udelay(10);
3088                         nv_linkchange(dev);
3089                 }
3090         }
3091
3092         if (netif_running(dev)) {
3093                 nv_start_rx(dev);
3094                 nv_start_tx(dev);
3095                 nv_enable_irq(dev);
3096         }
3097
3098         return 0;
3099 }
3100
3101 #define FORCEDETH_REGS_VER      1
3102
3103 static int nv_get_regs_len(struct net_device *dev)
3104 {
3105         struct fe_priv *np = netdev_priv(dev);
3106         return np->register_size;
3107 }
3108
3109 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3110 {
3111         struct fe_priv *np = netdev_priv(dev);
3112         u8 __iomem *base = get_hwbase(dev);
3113         u32 *rbuf = buf;
3114         int i;
3115
3116         regs->version = FORCEDETH_REGS_VER;
3117         spin_lock_irq(&np->lock);
3118         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3119                 rbuf[i] = readl(base + i*sizeof(u32));
3120         spin_unlock_irq(&np->lock);
3121 }
3122
3123 static int nv_nway_reset(struct net_device *dev)
3124 {
3125         struct fe_priv *np = netdev_priv(dev);
3126         int ret;
3127
3128         if (np->autoneg) {
3129                 int bmcr;
3130
3131                 netif_carrier_off(dev);
3132                 if (netif_running(dev)) {
3133                         nv_disable_irq(dev);
3134                         netif_tx_lock_bh(dev);
3135                         spin_lock(&np->lock);
3136                         /* stop engines */
3137                         nv_stop_rx(dev);
3138                         nv_stop_tx(dev);
3139                         spin_unlock(&np->lock);
3140                         netif_tx_unlock_bh(dev);
3141                         printk(KERN_INFO "%s: link down.\n", dev->name);
3142                 }
3143
3144                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3145                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3146                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3147
3148                 if (netif_running(dev)) {
3149                         nv_start_rx(dev);
3150                         nv_start_tx(dev);
3151                         nv_enable_irq(dev);
3152                 }
3153                 ret = 0;
3154         } else {
3155                 ret = -EINVAL;
3156         }
3157
3158         return ret;
3159 }
3160
3161 static int nv_set_tso(struct net_device *dev, u32 value)
3162 {
3163         struct fe_priv *np = netdev_priv(dev);
3164
3165         if ((np->driver_data & DEV_HAS_CHECKSUM))
3166                 return ethtool_op_set_tso(dev, value);
3167         else
3168                 return -EOPNOTSUPP;
3169 }
3170
3171 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3172 {
3173         struct fe_priv *np = netdev_priv(dev);
3174
3175         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3176         ring->rx_mini_max_pending = 0;
3177         ring->rx_jumbo_max_pending = 0;
3178         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3179
3180         ring->rx_pending = np->rx_ring_size;
3181         ring->rx_mini_pending = 0;
3182         ring->rx_jumbo_pending = 0;
3183         ring->tx_pending = np->tx_ring_size;
3184 }
3185
3186 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3187 {
3188         struct fe_priv *np = netdev_priv(dev);
3189         u8 __iomem *base = get_hwbase(dev);
3190         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3191         dma_addr_t ring_addr;
3192
3193         if (ring->rx_pending < RX_RING_MIN ||
3194             ring->tx_pending < TX_RING_MIN ||
3195             ring->rx_mini_pending != 0 ||
3196             ring->rx_jumbo_pending != 0 ||
3197             (np->desc_ver == DESC_VER_1 &&
3198              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3199               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3200             (np->desc_ver != DESC_VER_1 &&
3201              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3202               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3203                 return -EINVAL;
3204         }
3205
3206         /* allocate new rings */
3207         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3208                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3209                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3210                                             &ring_addr);
3211         } else {
3212                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3213                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3214                                             &ring_addr);
3215         }
3216         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3217         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3218         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3219         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3220         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3221         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3222                 /* fall back to old rings */
3223                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3224                         if(rxtx_ring)
3225                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3226                                                     rxtx_ring, ring_addr);
3227                 } else {
3228                         if (rxtx_ring)
3229                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3230                                                     rxtx_ring, ring_addr);
3231                 }
3232                 if (rx_skbuff)
3233                         kfree(rx_skbuff);
3234                 if (rx_dma)
3235                         kfree(rx_dma);
3236                 if (tx_skbuff)
3237                         kfree(tx_skbuff);
3238                 if (tx_dma)
3239                         kfree(tx_dma);
3240                 if (tx_dma_len)
3241                         kfree(tx_dma_len);
3242                 goto exit;
3243         }
3244
3245         if (netif_running(dev)) {
3246                 nv_disable_irq(dev);
3247                 netif_tx_lock_bh(dev);
3248                 spin_lock(&np->lock);
3249                 /* stop engines */
3250                 nv_stop_rx(dev);
3251                 nv_stop_tx(dev);
3252                 nv_txrx_reset(dev);
3253                 /* drain queues */
3254                 nv_drain_rx(dev);
3255                 nv_drain_tx(dev);
3256                 /* delete queues */
3257                 free_rings(dev);
3258         }
3259
3260         /* set new values */
3261         np->rx_ring_size = ring->rx_pending;
3262         np->tx_ring_size = ring->tx_pending;
3263         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3264         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3265         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3266                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3267                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3268         } else {
3269                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3270                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3271         }
3272         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3273         np->rx_dma = (dma_addr_t*)rx_dma;
3274         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3275         np->tx_dma = (dma_addr_t*)tx_dma;
3276         np->tx_dma_len = (unsigned int*)tx_dma_len;
3277         np->ring_addr = ring_addr;
3278
3279         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3280         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3281         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3282         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3283         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3284
3285         if (netif_running(dev)) {
3286                 /* reinit driver view of the queues */
3287                 set_bufsize(dev);
3288                 if (nv_init_ring(dev)) {
3289                         if (!np->in_shutdown)
3290                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3291                 }
3292
3293                 /* reinit nic view of the queues */
3294                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3295                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3296                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3297                         base + NvRegRingSizes);
3298                 pci_push(base);
3299                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3300                 pci_push(base);
3301
3302                 /* restart engines */
3303                 nv_start_rx(dev);
3304                 nv_start_tx(dev);
3305                 spin_unlock(&np->lock);
3306                 netif_tx_unlock_bh(dev);
3307                 nv_enable_irq(dev);
3308         }
3309         return 0;
3310 exit:
3311         return -ENOMEM;
3312 }
3313
3314 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3315 {
3316         struct fe_priv *np = netdev_priv(dev);
3317
3318         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3319         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3320         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3321 }
3322
3323 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3324 {
3325         struct fe_priv *np = netdev_priv(dev);
3326         int adv, bmcr;
3327
3328         if ((!np->autoneg && np->duplex == 0) ||
3329             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3330                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3331                        dev->name);
3332                 return -EINVAL;
3333         }
3334         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3335                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3336                 return -EINVAL;
3337         }
3338
3339         netif_carrier_off(dev);
3340         if (netif_running(dev)) {
3341                 nv_disable_irq(dev);
3342                 netif_tx_lock_bh(dev);
3343                 spin_lock(&np->lock);
3344                 /* stop engines */
3345                 nv_stop_rx(dev);
3346                 nv_stop_tx(dev);
3347                 spin_unlock(&np->lock);
3348                 netif_tx_unlock_bh(dev);
3349         }
3350
3351         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3352         if (pause->rx_pause)
3353                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3354         if (pause->tx_pause)
3355                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3356
3357         if (np->autoneg && pause->autoneg) {
3358                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3359
3360                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3361                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3362                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3363                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3364                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3365                         adv |=  ADVERTISE_PAUSE_ASYM;
3366                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3367
3368                 if (netif_running(dev))
3369                         printk(KERN_INFO "%s: link down.\n", dev->name);
3370                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3371                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3372                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3373         } else {
3374                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3375                 if (pause->rx_pause)
3376                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3377                 if (pause->tx_pause)
3378                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3379
3380                 if (!netif_running(dev))
3381                         nv_update_linkspeed(dev);
3382                 else
3383                         nv_update_pause(dev, np->pause_flags);
3384         }
3385
3386         if (netif_running(dev)) {
3387                 nv_start_rx(dev);
3388                 nv_start_tx(dev);
3389                 nv_enable_irq(dev);
3390         }
3391         return 0;
3392 }
3393
3394 static u32 nv_get_rx_csum(struct net_device *dev)
3395 {
3396         struct fe_priv *np = netdev_priv(dev);
3397         return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3398 }
3399
3400 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3401 {
3402         struct fe_priv *np = netdev_priv(dev);
3403         u8 __iomem *base = get_hwbase(dev);
3404         int retcode = 0;
3405
3406         if (np->driver_data & DEV_HAS_CHECKSUM) {
3407
3408                 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3409                     (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3410                         /* already set or unset */
3411                         return 0;
3412                 }
3413
3414                 if (data) {
3415                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3416                 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3417                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3418                 } else {
3419                         printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3420                         return -EINVAL;
3421                 }
3422
3423                 if (netif_running(dev)) {
3424                         spin_lock_irq(&np->lock);
3425                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3426                         spin_unlock_irq(&np->lock);
3427                 }
3428         } else {
3429                 return -EINVAL;
3430         }
3431
3432         return retcode;
3433 }
3434
3435 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3436 {
3437         struct fe_priv *np = netdev_priv(dev);
3438
3439         if (np->driver_data & DEV_HAS_CHECKSUM)
3440                 return ethtool_op_set_tx_hw_csum(dev, data);
3441         else
3442                 return -EOPNOTSUPP;
3443 }
3444
3445 static int nv_set_sg(struct net_device *dev, u32 data)
3446 {
3447         struct fe_priv *np = netdev_priv(dev);
3448
3449         if (np->driver_data & DEV_HAS_CHECKSUM)
3450                 return ethtool_op_set_sg(dev, data);
3451         else
3452                 return -EOPNOTSUPP;
3453 }
3454
3455 static int nv_get_stats_count(struct net_device *dev)
3456 {
3457         struct fe_priv *np = netdev_priv(dev);
3458
3459         if (np->driver_data & DEV_HAS_STATISTICS)
3460                 return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3461         else
3462                 return 0;
3463 }
3464
3465 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3466 {
3467         struct fe_priv *np = netdev_priv(dev);
3468
3469         /* update stats */
3470         nv_do_stats_poll((unsigned long)dev);
3471
3472         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3473 }
3474
3475 static int nv_self_test_count(struct net_device *dev)
3476 {
3477         struct fe_priv *np = netdev_priv(dev);
3478
3479         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3480                 return NV_TEST_COUNT_EXTENDED;
3481         else
3482                 return NV_TEST_COUNT_BASE;
3483 }
3484
3485 static int nv_link_test(struct net_device *dev)
3486 {
3487         struct fe_priv *np = netdev_priv(dev);
3488         int mii_status;
3489
3490         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3491         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3492
3493         /* check phy link status */
3494         if (!(mii_status & BMSR_LSTATUS))
3495                 return 0;
3496         else
3497                 return 1;
3498 }
3499
3500 static int nv_register_test(struct net_device *dev)
3501 {
3502         u8 __iomem *base = get_hwbase(dev);
3503         int i = 0;
3504         u32 orig_read, new_read;
3505
3506         do {
3507                 orig_read = readl(base + nv_registers_test[i].reg);
3508
3509                 /* xor with mask to toggle bits */
3510                 orig_read ^= nv_registers_test[i].mask;
3511
3512                 writel(orig_read, base + nv_registers_test[i].reg);
3513
3514                 new_read = readl(base + nv_registers_test[i].reg);
3515
3516                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3517                         return 0;
3518
3519                 /* restore original value */
3520                 orig_read ^= nv_registers_test[i].mask;
3521                 writel(orig_read, base + nv_registers_test[i].reg);
3522
3523         } while (nv_registers_test[++i].reg != 0);
3524
3525         return 1;
3526 }
3527
3528 static int nv_interrupt_test(struct net_device *dev)
3529 {
3530         struct fe_priv *np = netdev_priv(dev);
3531         u8 __iomem *base = get_hwbase(dev);
3532         int ret = 1;
3533         int testcnt;
3534         u32 save_msi_flags, save_poll_interval = 0;
3535
3536         if (netif_running(dev)) {
3537                 /* free current irq */
3538                 nv_free_irq(dev);
3539                 save_poll_interval = readl(base+NvRegPollingInterval);
3540         }
3541
3542         /* flag to test interrupt handler */
3543         np->intr_test = 0;
3544
3545         /* setup test irq */
3546         save_msi_flags = np->msi_flags;
3547         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3548         np->msi_flags |= 0x001; /* setup 1 vector */
3549         if (nv_request_irq(dev, 1))
3550                 return 0;
3551
3552         /* setup timer interrupt */
3553         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3554         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3555
3556         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3557
3558         /* wait for at least one interrupt */
3559         msleep(100);
3560
3561         spin_lock_irq(&np->lock);
3562
3563         /* flag should be set within ISR */
3564         testcnt = np->intr_test;
3565         if (!testcnt)
3566                 ret = 2;
3567
3568         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3569         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3570                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3571         else
3572                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3573
3574         spin_unlock_irq(&np->lock);
3575
3576         nv_free_irq(dev);
3577
3578         np->msi_flags = save_msi_flags;
3579
3580         if (netif_running(dev)) {
3581                 writel(save_poll_interval, base + NvRegPollingInterval);
3582                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3583                 /* restore original irq */
3584                 if (nv_request_irq(dev, 0))
3585                         return 0;
3586         }
3587
3588         return ret;
3589 }
3590
3591 static int nv_loopback_test(struct net_device *dev)
3592 {
3593         struct fe_priv *np = netdev_priv(dev);
3594         u8 __iomem *base = get_hwbase(dev);
3595         struct sk_buff *tx_skb, *rx_skb;
3596         dma_addr_t test_dma_addr;
3597         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3598         u32 Flags;
3599         int len, i, pkt_len;
3600         u8 *pkt_data;
3601         u32 filter_flags = 0;
3602         u32 misc1_flags = 0;
3603         int ret = 1;
3604
3605         if (netif_running(dev)) {
3606                 nv_disable_irq(dev);
3607                 filter_flags = readl(base + NvRegPacketFilterFlags);
3608                 misc1_flags = readl(base + NvRegMisc1);
3609         } else {
3610                 nv_txrx_reset(dev);
3611         }
3612
3613         /* reinit driver view of the rx queue */
3614         set_bufsize(dev);
3615         nv_init_ring(dev);
3616
3617         /* setup hardware for loopback */
3618         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3619         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3620
3621         /* reinit nic view of the rx queue */
3622         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3623         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3624         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3625                 base + NvRegRingSizes);
3626         pci_push(base);
3627
3628         /* restart rx engine */
3629         nv_start_rx(dev);
3630         nv_start_tx(dev);
3631
3632         /* setup packet for tx */
3633         pkt_len = ETH_DATA_LEN;
3634         tx_skb = dev_alloc_skb(pkt_len);
3635         pkt_data = skb_put(tx_skb, pkt_len);
3636         for (i = 0; i < pkt_len; i++)
3637                 pkt_data[i] = (u8)(i & 0xff);
3638         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3639                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3640
3641         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3642                 np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr);
3643                 np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3644         } else {
3645                 np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32;
3646                 np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3647                 np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3648         }
3649         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3650         pci_push(get_hwbase(dev));
3651
3652         msleep(500);
3653
3654         /* check for rx of the packet */
3655         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3656                 Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
3657                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3658
3659         } else {
3660                 Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
3661                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3662         }
3663
3664         if (Flags & NV_RX_AVAIL) {
3665                 ret = 0;
3666         } else if (np->desc_ver == DESC_VER_1) {
3667                 if (Flags & NV_RX_ERROR)
3668                         ret = 0;
3669         } else {
3670                 if (Flags & NV_RX2_ERROR) {
3671                         ret = 0;
3672                 }
3673         }
3674
3675         if (ret) {
3676                 if (len != pkt_len) {
3677                         ret = 0;
3678                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3679                                 dev->name, len, pkt_len);
3680                 } else {
3681                         rx_skb = np->rx_skbuff[0];
3682                         for (i = 0; i < pkt_len; i++) {
3683                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3684                                         ret = 0;
3685                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3686                                                 dev->name, i);
3687                                         break;
3688                                 }
3689                         }
3690                 }
3691         } else {
3692                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3693         }
3694
3695         pci_unmap_page(np->pci_dev, test_dma_addr,
3696                        tx_skb->end-tx_skb->data,
3697                        PCI_DMA_TODEVICE);
3698         dev_kfree_skb_any(tx_skb);
3699
3700         /* stop engines */
3701         nv_stop_rx(dev);
3702         nv_stop_tx(dev);
3703         nv_txrx_reset(dev);
3704         /* drain rx queue */
3705         nv_drain_rx(dev);
3706         nv_drain_tx(dev);
3707
3708         if (netif_running(dev)) {
3709                 writel(misc1_flags, base + NvRegMisc1);
3710                 writel(filter_flags, base + NvRegPacketFilterFlags);
3711                 nv_enable_irq(dev);
3712         }
3713
3714         return ret;
3715 }
3716
3717 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3718 {
3719         struct fe_priv *np = netdev_priv(dev);
3720         u8 __iomem *base = get_hwbase(dev);
3721         int result;
3722         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3723
3724         if (!nv_link_test(dev)) {
3725                 test->flags |= ETH_TEST_FL_FAILED;
3726                 buffer[0] = 1;
3727         }
3728
3729         if (test->flags & ETH_TEST_FL_OFFLINE) {
3730                 if (netif_running(dev)) {
3731                         netif_stop_queue(dev);
3732                         netif_tx_lock_bh(dev);
3733                         spin_lock_irq(&np->lock);
3734                         nv_disable_hw_interrupts(dev, np->irqmask);
3735                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3736                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3737                         } else {
3738                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3739                         }
3740                         /* stop engines */
3741                         nv_stop_rx(dev);
3742                         nv_stop_tx(dev);
3743                         nv_txrx_reset(dev);
3744                         /* drain rx queue */
3745                         nv_drain_rx(dev);
3746                         nv_drain_tx(dev);
3747                         spin_unlock_irq(&np->lock);
3748                         netif_tx_unlock_bh(dev);
3749                 }
3750
3751                 if (!nv_register_test(dev)) {
3752                         test->flags |= ETH_TEST_FL_FAILED;
3753                         buffer[1] = 1;
3754                 }
3755
3756                 result = nv_interrupt_test(dev);
3757                 if (result != 1) {
3758                         test->flags |= ETH_TEST_FL_FAILED;
3759                         buffer[2] = 1;
3760                 }
3761                 if (result == 0) {
3762                         /* bail out */
3763                         return;
3764                 }
3765
3766                 if (!nv_loopback_test(dev)) {
3767                         test->flags |= ETH_TEST_FL_FAILED;
3768                         buffer[3] = 1;
3769                 }
3770
3771                 if (netif_running(dev)) {
3772                         /* reinit driver view of the rx queue */
3773                         set_bufsize(dev);
3774                         if (nv_init_ring(dev)) {
3775                                 if (!np->in_shutdown)
3776                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3777                         }
3778                         /* reinit nic view of the rx queue */
3779                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3780                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3781                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3782                                 base + NvRegRingSizes);
3783                         pci_push(base);
3784                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3785                         pci_push(base);
3786                         /* restart rx engine */
3787                         nv_start_rx(dev);
3788                         nv_start_tx(dev);
3789                         netif_start_queue(dev);
3790                         nv_enable_hw_interrupts(dev, np->irqmask);
3791                 }
3792         }
3793 }
3794
3795 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3796 {
3797         switch (stringset) {
3798         case ETH_SS_STATS:
3799                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3800                 break;
3801         case ETH_SS_TEST:
3802                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3803                 break;
3804         }
3805 }
3806
3807 static struct ethtool_ops ops = {
3808         .get_drvinfo = nv_get_drvinfo,
3809         .get_link = ethtool_op_get_link,
3810         .get_wol = nv_get_wol,
3811         .set_wol = nv_set_wol,
3812         .get_settings = nv_get_settings,
3813         .set_settings = nv_set_settings,
3814         .get_regs_len = nv_get_regs_len,
3815         .get_regs = nv_get_regs,
3816         .nway_reset = nv_nway_reset,
3817         .get_perm_addr = ethtool_op_get_perm_addr,
3818         .get_tso = ethtool_op_get_tso,
3819         .set_tso = nv_set_tso,
3820         .get_ringparam = nv_get_ringparam,
3821         .set_ringparam = nv_set_ringparam,
3822         .get_pauseparam = nv_get_pauseparam,
3823         .set_pauseparam = nv_set_pauseparam,
3824         .get_rx_csum = nv_get_rx_csum,
3825         .set_rx_csum = nv_set_rx_csum,
3826         .get_tx_csum = ethtool_op_get_tx_csum,
3827         .set_tx_csum = nv_set_tx_csum,
3828         .get_sg = ethtool_op_get_sg,
3829         .set_sg = nv_set_sg,
3830         .get_strings = nv_get_strings,
3831         .get_stats_count = nv_get_stats_count,
3832         .get_ethtool_stats = nv_get_ethtool_stats,
3833         .self_test_count = nv_self_test_count,
3834         .self_test = nv_self_test,
3835 };
3836
3837 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3838 {
3839         struct fe_priv *np = get_nvpriv(dev);
3840
3841         spin_lock_irq(&np->lock);
3842
3843         /* save vlan group */
3844         np->vlangrp = grp;
3845
3846         if (grp) {
3847                 /* enable vlan on MAC */
3848                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3849         } else {
3850                 /* disable vlan on MAC */
3851                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3852                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3853         }
3854
3855         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3856
3857         spin_unlock_irq(&np->lock);
3858 };
3859
3860 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3861 {
3862         /* nothing to do */
3863 };
3864
3865 static int nv_open(struct net_device *dev)
3866 {
3867         struct fe_priv *np = netdev_priv(dev);
3868         u8 __iomem *base = get_hwbase(dev);
3869         int ret = 1;
3870         int oom, i;
3871
3872         dprintk(KERN_DEBUG "nv_open: begin\n");
3873
3874         /* 1) erase previous misconfiguration */
3875         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3876                 nv_mac_reset(dev);
3877         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3878         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3879         writel(0, base + NvRegMulticastAddrB);
3880         writel(0, base + NvRegMulticastMaskA);
3881         writel(0, base + NvRegMulticastMaskB);
3882         writel(0, base + NvRegPacketFilterFlags);
3883
3884         writel(0, base + NvRegTransmitterControl);
3885         writel(0, base + NvRegReceiverControl);
3886
3887         writel(0, base + NvRegAdapterControl);
3888
3889         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3890                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3891
3892         /* 2) initialize descriptor rings */
3893         set_bufsize(dev);
3894         oom = nv_init_ring(dev);
3895
3896         writel(0, base + NvRegLinkSpeed);
3897         writel(0, base + NvRegUnknownTransmitterReg);
3898         nv_txrx_reset(dev);
3899         writel(0, base + NvRegUnknownSetupReg6);
3900
3901         np->in_shutdown = 0;
3902
3903         /* 3) set mac address */
3904         nv_copy_mac_to_hw(dev);
3905
3906         /* 4) give hw rings */
3907         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3908         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3909                 base + NvRegRingSizes);
3910
3911         /* 5) continue setup */
3912         writel(np->linkspeed, base + NvRegLinkSpeed);
3913         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
3914         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3915         writel(np->vlanctl_bits, base + NvRegVlanControl);
3916         pci_push(base);
3917         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3918         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3919                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3920                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3921
3922         writel(0, base + NvRegUnknownSetupReg4);
3923         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3924         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3925
3926         /* 6) continue setup */
3927         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3928         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3929         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3930         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3931
3932         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3933         get_random_bytes(&i, sizeof(i));
3934         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3935         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
3936         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
3937         if (poll_interval == -1) {
3938                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3939                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3940                 else
3941                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3942         }
3943         else
3944                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3945         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3946         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3947                         base + NvRegAdapterControl);
3948         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3949         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3950         if (np->wolenabled)
3951                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3952
3953         i = readl(base + NvRegPowerState);
3954         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3955                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3956
3957         pci_push(base);
3958         udelay(10);
3959         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3960
3961         nv_disable_hw_interrupts(dev, np->irqmask);
3962         pci_push(base);
3963         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3964         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3965         pci_push(base);
3966
3967         if (nv_request_irq(dev, 0)) {
3968                 goto out_drain;
3969         }
3970
3971         /* ask for interrupts */
3972         nv_enable_hw_interrupts(dev, np->irqmask);
3973
3974         spin_lock_irq(&np->lock);
3975         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3976         writel(0, base + NvRegMulticastAddrB);
3977         writel(0, base + NvRegMulticastMaskA);
3978         writel(0, base + NvRegMulticastMaskB);
3979         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
3980         /* One manual link speed update: Interrupts are enabled, future link
3981          * speed changes cause interrupts and are handled by nv_link_irq().
3982          */
3983         {
3984                 u32 miistat;
3985                 miistat = readl(base + NvRegMIIStatus);
3986                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
3987                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
3988         }
3989         /* set linkspeed to invalid value, thus force nv_update_linkspeed
3990          * to init hw */
3991         np->linkspeed = 0;
3992         ret = nv_update_linkspeed(dev);
3993         nv_start_rx(dev);
3994         nv_start_tx(dev);
3995         netif_start_queue(dev);
3996         if (ret) {
3997                 netif_carrier_on(dev);
3998         } else {
3999                 printk("%s: no link during initialization.\n", dev->name);
4000                 netif_carrier_off(dev);
4001         }
4002         if (oom)
4003                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4004
4005         /* start statistics timer */
4006         if (np->driver_data & DEV_HAS_STATISTICS)
4007                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4008
4009         spin_unlock_irq(&np->lock);
4010
4011         return 0;
4012 out_drain:
4013         drain_ring(dev);
4014         return ret;
4015 }
4016
4017 static int nv_close(struct net_device *dev)
4018 {
4019         struct fe_priv *np = netdev_priv(dev);
4020         u8 __iomem *base;
4021
4022         spin_lock_irq(&np->lock);
4023         np->in_shutdown = 1;
4024         spin_unlock_irq(&np->lock);
4025         synchronize_irq(dev->irq);
4026
4027         del_timer_sync(&np->oom_kick);
4028         del_timer_sync(&np->nic_poll);
4029         del_timer_sync(&np->stats_poll);
4030
4031         netif_stop_queue(dev);
4032         spin_lock_irq(&np->lock);
4033         nv_stop_tx(dev);
4034         nv_stop_rx(dev);
4035         nv_txrx_reset(dev);
4036
4037         /* disable interrupts on the nic or we will lock up */
4038         base = get_hwbase(dev);
4039         nv_disable_hw_interrupts(dev, np->irqmask);
4040         pci_push(base);
4041         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4042
4043         spin_unlock_irq(&np->lock);
4044
4045         nv_free_irq(dev);
4046
4047         drain_ring(dev);
4048
4049         if (np->wolenabled)
4050                 nv_start_rx(dev);
4051
4052         /* special op: write back the misordered MAC address - otherwise
4053          * the next nv_probe would see a wrong address.
4054          */
4055         writel(np->orig_mac[0], base + NvRegMacAddrA);
4056         writel(np->orig_mac[1], base + NvRegMacAddrB);
4057
4058         /* FIXME: power down nic */
4059
4060         return 0;
4061 }
4062
4063 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4064 {
4065         struct net_device *dev;
4066         struct fe_priv *np;
4067         unsigned long addr;
4068         u8 __iomem *base;
4069         int err, i;
4070         u32 powerstate;
4071
4072         dev = alloc_etherdev(sizeof(struct fe_priv));
4073         err = -ENOMEM;
4074         if (!dev)
4075                 goto out;
4076
4077         np = netdev_priv(dev);
4078         np->pci_dev = pci_dev;
4079         spin_lock_init(&np->lock);
4080         SET_MODULE_OWNER(dev);
4081         SET_NETDEV_DEV(dev, &pci_dev->dev);
4082
4083         init_timer(&np->oom_kick);
4084         np->oom_kick.data = (unsigned long) dev;
4085         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4086         init_timer(&np->nic_poll);
4087         np->nic_poll.data = (unsigned long) dev;
4088         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4089         init_timer(&np->stats_poll);
4090         np->stats_poll.data = (unsigned long) dev;
4091         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4092
4093         err = pci_enable_device(pci_dev);
4094         if (err) {
4095                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4096                                 err, pci_name(pci_dev));
4097                 goto out_free;
4098         }
4099
4100         pci_set_master(pci_dev);
4101
4102         err = pci_request_regions(pci_dev, DRV_NAME);
4103         if (err < 0)
4104                 goto out_disable;
4105
4106         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4107                 np->register_size = NV_PCI_REGSZ_VER2;
4108         else
4109                 np->register_size = NV_PCI_REGSZ_VER1;
4110
4111         err = -EINVAL;
4112         addr = 0;
4113         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4114                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4115                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4116                                 pci_resource_len(pci_dev, i),
4117                                 pci_resource_flags(pci_dev, i));
4118                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4119                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4120                         addr = pci_resource_start(pci_dev, i);
4121                         break;
4122                 }
4123         }
4124         if (i == DEVICE_COUNT_RESOURCE) {
4125                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4126                                         pci_name(pci_dev));
4127                 goto out_relreg;
4128         }
4129
4130         /* copy of driver data */
4131         np->driver_data = id->driver_data;
4132
4133         /* handle different descriptor versions */
4134         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4135                 /* packet format 3: supports 40-bit addressing */
4136                 np->desc_ver = DESC_VER_3;
4137                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4138                 if (dma_64bit) {
4139                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4140                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4141                                        pci_name(pci_dev));
4142                         } else {
4143                                 dev->features |= NETIF_F_HIGHDMA;
4144                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4145                         }
4146                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4147                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4148                                        pci_name(pci_dev));
4149                         }
4150                 }
4151         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4152                 /* packet format 2: supports jumbo frames */
4153                 np->desc_ver = DESC_VER_2;
4154                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4155         } else {
4156                 /* original packet format */
4157                 np->desc_ver = DESC_VER_1;
4158                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4159         }
4160
4161         np->pkt_limit = NV_PKTLIMIT_1;
4162         if (id->driver_data & DEV_HAS_LARGEDESC)
4163                 np->pkt_limit = NV_PKTLIMIT_2;
4164
4165         if (id->driver_data & DEV_HAS_CHECKSUM) {
4166                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4167                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4168 #ifdef NETIF_F_TSO
4169                 dev->features |= NETIF_F_TSO;
4170 #endif
4171         }
4172
4173         np->vlanctl_bits = 0;
4174         if (id->driver_data & DEV_HAS_VLAN) {
4175                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4176                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4177                 dev->vlan_rx_register = nv_vlan_rx_register;
4178                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4179         }
4180
4181         np->msi_flags = 0;
4182         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4183                 np->msi_flags |= NV_MSI_CAPABLE;
4184         }
4185         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4186                 np->msi_flags |= NV_MSI_X_CAPABLE;
4187         }
4188
4189         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4190         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4191                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4192         }
4193
4194
4195         err = -ENOMEM;
4196         np->base = ioremap(addr, np->register_size);
4197         if (!np->base)
4198                 goto out_relreg;
4199         dev->base_addr = (unsigned long)np->base;
4200
4201         dev->irq = pci_dev->irq;
4202
4203         np->rx_ring_size = RX_RING_DEFAULT;
4204         np->tx_ring_size = TX_RING_DEFAULT;
4205         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4206         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4207
4208         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4209                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4210                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4211                                         &np->ring_addr);
4212                 if (!np->rx_ring.orig)
4213                         goto out_unmap;
4214                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4215         } else {
4216                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4217                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4218                                         &np->ring_addr);
4219                 if (!np->rx_ring.ex)
4220                         goto out_unmap;
4221                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4222         }
4223         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4224         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4225         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4226         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4227         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4228         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4229                 goto out_freering;
4230         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4231         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4232         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4233         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4234         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4235
4236         dev->open = nv_open;
4237         dev->stop = nv_close;
4238         dev->hard_start_xmit = nv_start_xmit;
4239         dev->get_stats = nv_get_stats;
4240         dev->change_mtu = nv_change_mtu;
4241         dev->set_mac_address = nv_set_mac_address;
4242         dev->set_multicast_list = nv_set_multicast;
4243 #ifdef CONFIG_NET_POLL_CONTROLLER
4244         dev->poll_controller = nv_poll_controller;
4245 #endif
4246         SET_ETHTOOL_OPS(dev, &ops);
4247         dev->tx_timeout = nv_tx_timeout;
4248         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4249
4250         pci_set_drvdata(pci_dev, dev);
4251
4252         /* read the mac address */
4253         base = get_hwbase(dev);
4254         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4255         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4256
4257         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4258         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4259         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4260         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4261         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4262         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4263         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4264
4265         if (!is_valid_ether_addr(dev->perm_addr)) {
4266                 /*
4267                  * Bad mac address. At least one bios sets the mac address
4268                  * to 01:23:45:67:89:ab
4269                  */
4270                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4271                         pci_name(pci_dev),
4272                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4273                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4274                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4275                 dev->dev_addr[0] = 0x00;
4276                 dev->dev_addr[1] = 0x00;
4277                 dev->dev_addr[2] = 0x6c;
4278                 get_random_bytes(&dev->dev_addr[3], 3);
4279         }
4280
4281         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4282                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4283                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4284
4285         /* disable WOL */
4286         writel(0, base + NvRegWakeUpFlags);
4287         np->wolenabled = 0;
4288
4289         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4290                 u8 revision_id;
4291                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4292
4293                 /* take phy and nic out of low power mode */
4294                 powerstate = readl(base + NvRegPowerState2);
4295                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4296                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4297                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4298                     revision_id >= 0xA3)
4299                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4300                 writel(powerstate, base + NvRegPowerState2);
4301         }
4302
4303         if (np->desc_ver == DESC_VER_1) {
4304                 np->tx_flags = NV_TX_VALID;
4305         } else {
4306                 np->tx_flags = NV_TX2_VALID;
4307         }
4308         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4309                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4310                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4311                         np->msi_flags |= 0x0003;
4312         } else {
4313                 np->irqmask = NVREG_IRQMASK_CPU;
4314                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4315                         np->msi_flags |= 0x0001;
4316         }
4317
4318         if (id->driver_data & DEV_NEED_TIMERIRQ)
4319                 np->irqmask |= NVREG_IRQ_TIMER;
4320         if (id->driver_data & DEV_NEED_LINKTIMER) {
4321                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4322                 np->need_linktimer = 1;
4323                 np->link_timeout = jiffies + LINK_TIMEOUT;
4324         } else {
4325                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4326                 np->need_linktimer = 0;
4327         }
4328
4329         /* find a suitable phy */
4330         for (i = 1; i <= 32; i++) {
4331                 int id1, id2;
4332                 int phyaddr = i & 0x1F;
4333
4334                 spin_lock_irq(&np->lock);
4335                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4336                 spin_unlock_irq(&np->lock);
4337                 if (id1 < 0 || id1 == 0xffff)
4338                         continue;
4339                 spin_lock_irq(&np->lock);
4340                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4341                 spin_unlock_irq(&np->lock);
4342                 if (id2 < 0 || id2 == 0xffff)
4343                         continue;
4344
4345                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4346                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4347                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4348                         pci_name(pci_dev), id1, id2, phyaddr);
4349                 np->phyaddr = phyaddr;
4350                 np->phy_oui = id1 | id2;
4351                 break;
4352         }
4353         if (i == 33) {
4354                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4355                        pci_name(pci_dev));
4356                 goto out_error;
4357         }
4358
4359         /* reset it */
4360         phy_init(dev);
4361
4362         /* set default link speed settings */
4363         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4364         np->duplex = 0;
4365         np->autoneg = 1;
4366
4367         err = register_netdev(dev);
4368         if (err) {
4369                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4370                 goto out_error;
4371         }
4372         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4373                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4374                         pci_name(pci_dev));
4375
4376         return 0;
4377
4378 out_error:
4379         pci_set_drvdata(pci_dev, NULL);
4380 out_freering:
4381         free_rings(dev);
4382 out_unmap:
4383         iounmap(get_hwbase(dev));
4384 out_relreg:
4385         pci_release_regions(pci_dev);
4386 out_disable:
4387         pci_disable_device(pci_dev);
4388 out_free:
4389         free_netdev(dev);
4390 out:
4391         return err;
4392 }
4393
4394 static void __devexit nv_remove(struct pci_dev *pci_dev)
4395 {
4396         struct net_device *dev = pci_get_drvdata(pci_dev);
4397
4398         unregister_netdev(dev);
4399
4400         /* free all structures */
4401         free_rings(dev);
4402         iounmap(get_hwbase(dev));
4403         pci_release_regions(pci_dev);
4404         pci_disable_device(pci_dev);
4405         free_netdev(dev);
4406         pci_set_drvdata(pci_dev, NULL);
4407 }
4408
4409 static struct pci_device_id pci_tbl[] = {
4410         {       /* nForce Ethernet Controller */
4411                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4412                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4413         },
4414         {       /* nForce2 Ethernet Controller */
4415                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4416                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4417         },
4418         {       /* nForce3 Ethernet Controller */
4419                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4420                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4421         },
4422         {       /* nForce3 Ethernet Controller */
4423                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4424                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4425         },
4426         {       /* nForce3 Ethernet Controller */
4427                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4428                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4429         },
4430         {       /* nForce3 Ethernet Controller */
4431                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4432                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4433         },
4434         {       /* nForce3 Ethernet Controller */
4435                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4436                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4437         },
4438         {       /* CK804 Ethernet Controller */
4439                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4440                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4441         },
4442         {       /* CK804 Ethernet Controller */
4443                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4444                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4445         },
4446         {       /* MCP04 Ethernet Controller */
4447                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4448                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4449         },
4450         {       /* MCP04 Ethernet Controller */
4451                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4452                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4453         },
4454         {       /* MCP51 Ethernet Controller */
4455                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4456                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4457         },
4458         {       /* MCP51 Ethernet Controller */
4459                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4460                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4461         },
4462         {       /* MCP55 Ethernet Controller */
4463                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4464                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4465         },
4466         {       /* MCP55 Ethernet Controller */
4467                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4468                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4469         },
4470         {       /* MCP61 Ethernet Controller */
4471                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4472                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4473         },
4474         {       /* MCP61 Ethernet Controller */
4475                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4476                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4477         },
4478         {       /* MCP61 Ethernet Controller */
4479                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4480                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4481         },
4482         {       /* MCP61 Ethernet Controller */
4483                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4484                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4485         },
4486         {       /* MCP65 Ethernet Controller */
4487                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4488                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4489         },
4490         {       /* MCP65 Ethernet Controller */
4491                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4492                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4493         },
4494         {       /* MCP65 Ethernet Controller */
4495                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4496                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4497         },
4498         {       /* MCP65 Ethernet Controller */
4499                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4500                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4501         },
4502         {0,},
4503 };
4504
4505 static struct pci_driver driver = {
4506         .name = "forcedeth",
4507         .id_table = pci_tbl,
4508         .probe = nv_probe,
4509         .remove = __devexit_p(nv_remove),
4510 };
4511
4512
4513 static int __init init_nic(void)
4514 {
4515         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4516         return pci_module_init(&driver);
4517 }
4518
4519 static void __exit exit_nic(void)
4520 {
4521         pci_unregister_driver(&driver);
4522 }
4523
4524 module_param(max_interrupt_work, int, 0);
4525 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4526 module_param(optimization_mode, int, 0);
4527 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4528 module_param(poll_interval, int, 0);
4529 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4530 module_param(msi, int, 0);
4531 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4532 module_param(msix, int, 0);
4533 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4534 module_param(dma_64bit, int, 0);
4535 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4536
4537 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4538 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4539 MODULE_LICENSE("GPL");
4540
4541 MODULE_DEVICE_TABLE(pci, pci_tbl);
4542
4543 module_init(init_nic);
4544 module_exit(exit_nic);