drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 106  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 107  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 108  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 109  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 110  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 111  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 112  *
 113  * Known bugs:
 114  * We suspect that on some hardware no TX done interrupts are generated.
 115  * This means recovery from netif_stop_queue only happens if the hw timer
 116  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 117  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 118  * If your hardware reliably generates tx done interrupts, then you can remove
 119  * DEV_NEED_TIMERIRQ from the driver_data flags.
 120  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 121  * superfluous timer interrupts from the nic.
 122  */
 123 #define FORCEDETH_VERSION               "0.56"
 124 #define DRV_NAME                        "forcedeth"
 125
 126 #include <linux/module.h>
 127 #include <linux/types.h>
 128 #include <linux/pci.h>
 129 #include <linux/interrupt.h>
 130 #include <linux/netdevice.h>
 131 #include <linux/etherdevice.h>
 132 #include <linux/delay.h>
 133 #include <linux/spinlock.h>
 134 #include <linux/ethtool.h>
 135 #include <linux/timer.h>
 136 #include <linux/skbuff.h>
 137 #include <linux/mii.h>
 138 #include <linux/random.h>
 139 #include <linux/init.h>
 140 #include <linux/if_vlan.h>
 141 #include <linux/dma-mapping.h>
 142
 143 #include <asm/irq.h>
 144 #include <asm/io.h>
 145 #include <asm/uaccess.h>
 146 #include <asm/system.h>
 147
 148 #if 0
 149 #define dprintk                 printk
 150 #else
 151 #define dprintk(x...)           do { } while (0)
 152 #endif
 153
 154
 155 /*
 156  * Hardware access:
 157  */
 158
 159 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 160 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 161 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 162 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 163 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 164 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 165 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 166 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 167 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 168 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 169 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 170 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 171
 172 enum {
 173         NvRegIrqStatus = 0x000,
 174 #define NVREG_IRQSTAT_MIIEVENT  0x040
 175 #define NVREG_IRQSTAT_MASK              0x1ff
 176         NvRegIrqMask = 0x004,
 177 #define NVREG_IRQ_RX_ERROR              0x0001
 178 #define NVREG_IRQ_RX                    0x0002
 179 #define NVREG_IRQ_RX_NOBUF              0x0004
 180 #define NVREG_IRQ_TX_ERR                0x0008
 181 #define NVREG_IRQ_TX_OK                 0x0010
 182 #define NVREG_IRQ_TIMER                 0x0020
 183 #define NVREG_IRQ_LINK                  0x0040
 184 #define NVREG_IRQ_RX_FORCED             0x0080
 185 #define NVREG_IRQ_TX_FORCED             0x0100
 186 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 187 #define NVREG_IRQMASK_CPU               0x0040
 188 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 189 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 190 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
 191
 192 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 193                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 194                                         NVREG_IRQ_TX_FORCED))
 195
 196         NvRegUnknownSetupReg6 = 0x008,
 197 #define NVREG_UNKSETUP6_VAL             3
 198
 199 /*
 200  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 201  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 202  */
 203         NvRegPollingInterval = 0x00c,
 204 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 205 #define NVREG_POLL_DEFAULT_CPU  13
 206         NvRegMSIMap0 = 0x020,
 207         NvRegMSIMap1 = 0x024,
 208         NvRegMSIIrqMask = 0x030,
 209 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 210         NvRegMisc1 = 0x080,
 211 #define NVREG_MISC1_PAUSE_TX    0x01
 212 #define NVREG_MISC1_HD          0x02
 213 #define NVREG_MISC1_FORCE       0x3b0f3c
 214
 215         NvRegMacReset = 0x3c,
 216 #define NVREG_MAC_RESET_ASSERT  0x0F3
 217         NvRegTransmitterControl = 0x084,
 218 #define NVREG_XMITCTL_START     0x01
 219         NvRegTransmitterStatus = 0x088,
 220 #define NVREG_XMITSTAT_BUSY     0x01
 221
 222         NvRegPacketFilterFlags = 0x8c,
 223 #define NVREG_PFF_PAUSE_RX      0x08
 224 #define NVREG_PFF_ALWAYS        0x7F0000
 225 #define NVREG_PFF_PROMISC       0x80
 226 #define NVREG_PFF_MYADDR        0x20
 227 #define NVREG_PFF_LOOPBACK      0x10
 228
 229         NvRegOffloadConfig = 0x90,
 230 #define NVREG_OFFLOAD_HOMEPHY   0x601
 231 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 232         NvRegReceiverControl = 0x094,
 233 #define NVREG_RCVCTL_START      0x01
 234         NvRegReceiverStatus = 0x98,
 235 #define NVREG_RCVSTAT_BUSY      0x01
 236
 237         NvRegRandomSeed = 0x9c,
 238 #define NVREG_RNDSEED_MASK      0x00ff
 239 #define NVREG_RNDSEED_FORCE     0x7f00
 240 #define NVREG_RNDSEED_FORCE2    0x2d00
 241 #define NVREG_RNDSEED_FORCE3    0x7400
 242
 243         NvRegTxDeferral = 0xA0,
 244 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 245 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 246 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 247         NvRegRxDeferral = 0xA4,
 248 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 249         NvRegMacAddrA = 0xA8,
 250         NvRegMacAddrB = 0xAC,
 251         NvRegMulticastAddrA = 0xB0,
 252 #define NVREG_MCASTADDRA_FORCE  0x01
 253         NvRegMulticastAddrB = 0xB4,
 254         NvRegMulticastMaskA = 0xB8,
 255         NvRegMulticastMaskB = 0xBC,
 256
 257         NvRegPhyInterface = 0xC0,
 258 #define PHY_RGMII               0x10000000
 259
 260         NvRegTxRingPhysAddr = 0x100,
 261         NvRegRxRingPhysAddr = 0x104,
 262         NvRegRingSizes = 0x108,
 263 #define NVREG_RINGSZ_TXSHIFT 0
 264 #define NVREG_RINGSZ_RXSHIFT 16
 265         NvRegUnknownTransmitterReg = 0x10c,
 266         NvRegLinkSpeed = 0x110,
 267 #define NVREG_LINKSPEED_FORCE 0x10000
 268 #define NVREG_LINKSPEED_10      1000
 269 #define NVREG_LINKSPEED_100     100
 270 #define NVREG_LINKSPEED_1000    50
 271 #define NVREG_LINKSPEED_MASK    (0xFFF)
 272         NvRegUnknownSetupReg5 = 0x130,
 273 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 274         NvRegTxWatermark = 0x13c,
 275 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 276 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 277 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 278         NvRegTxRxControl = 0x144,
 279 #define NVREG_TXRXCTL_KICK      0x0001
 280 #define NVREG_TXRXCTL_BIT1      0x0002
 281 #define NVREG_TXRXCTL_BIT2      0x0004
 282 #define NVREG_TXRXCTL_IDLE      0x0008
 283 #define NVREG_TXRXCTL_RESET     0x0010
 284 #define NVREG_TXRXCTL_RXCHECK   0x0400
 285 #define NVREG_TXRXCTL_DESC_1    0
 286 #define NVREG_TXRXCTL_DESC_2    0x02100
 287 #define NVREG_TXRXCTL_DESC_3    0x02200
 288 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 289 #define NVREG_TXRXCTL_VLANINS   0x00080
 290         NvRegTxRingPhysAddrHigh = 0x148,
 291         NvRegRxRingPhysAddrHigh = 0x14C,
 292         NvRegTxPauseFrame = 0x170,
 293 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 294 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 295         NvRegMIIStatus = 0x180,
 296 #define NVREG_MIISTAT_ERROR             0x0001
 297 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 298 #define NVREG_MIISTAT_MASK              0x000f
 299 #define NVREG_MIISTAT_MASK2             0x000f
 300         NvRegUnknownSetupReg4 = 0x184,
 301 #define NVREG_UNKSETUP4_VAL     8
 302
 303         NvRegAdapterControl = 0x188,
 304 #define NVREG_ADAPTCTL_START    0x02
 305 #define NVREG_ADAPTCTL_LINKUP   0x04
 306 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 307 #define NVREG_ADAPTCTL_RUNNING  0x100000
 308 #define NVREG_ADAPTCTL_PHYSHIFT 24
 309         NvRegMIISpeed = 0x18c,
 310 #define NVREG_MIISPEED_BIT8     (1<<8)
 311 #define NVREG_MIIDELAY  5
 312         NvRegMIIControl = 0x190,
 313 #define NVREG_MIICTL_INUSE      0x08000
 314 #define NVREG_MIICTL_WRITE      0x00400
 315 #define NVREG_MIICTL_ADDRSHIFT  5
 316         NvRegMIIData = 0x194,
 317         NvRegWakeUpFlags = 0x200,
 318 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 319 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 320 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 321 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 322 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 323 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 324 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 325 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 326 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 327 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 328 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 329
 330         NvRegPatternCRC = 0x204,
 331         NvRegPatternMask = 0x208,
 332         NvRegPowerCap = 0x268,
 333 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 334 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 335 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 336         NvRegPowerState = 0x26c,
 337 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 338 #define NVREG_POWERSTATE_VALID          0x0100
 339 #define NVREG_POWERSTATE_MASK           0x0003
 340 #define NVREG_POWERSTATE_D0             0x0000
 341 #define NVREG_POWERSTATE_D1             0x0001
 342 #define NVREG_POWERSTATE_D2             0x0002
 343 #define NVREG_POWERSTATE_D3             0x0003
 344         NvRegTxCnt = 0x280,
 345         NvRegTxZeroReXmt = 0x284,
 346         NvRegTxOneReXmt = 0x288,
 347         NvRegTxManyReXmt = 0x28c,
 348         NvRegTxLateCol = 0x290,
 349         NvRegTxUnderflow = 0x294,
 350         NvRegTxLossCarrier = 0x298,
 351         NvRegTxExcessDef = 0x29c,
 352         NvRegTxRetryErr = 0x2a0,
 353         NvRegRxFrameErr = 0x2a4,
 354         NvRegRxExtraByte = 0x2a8,
 355         NvRegRxLateCol = 0x2ac,
 356         NvRegRxRunt = 0x2b0,
 357         NvRegRxFrameTooLong = 0x2b4,
 358         NvRegRxOverflow = 0x2b8,
 359         NvRegRxFCSErr = 0x2bc,
 360         NvRegRxFrameAlignErr = 0x2c0,
 361         NvRegRxLenErr = 0x2c4,
 362         NvRegRxUnicast = 0x2c8,
 363         NvRegRxMulticast = 0x2cc,
 364         NvRegRxBroadcast = 0x2d0,
 365         NvRegTxDef = 0x2d4,
 366         NvRegTxFrame = 0x2d8,
 367         NvRegRxCnt = 0x2dc,
 368         NvRegTxPause = 0x2e0,
 369         NvRegRxPause = 0x2e4,
 370         NvRegRxDropFrame = 0x2e8,
 371         NvRegVlanControl = 0x300,
 372 #define NVREG_VLANCONTROL_ENABLE        0x2000
 373         NvRegMSIXMap0 = 0x3e0,
 374         NvRegMSIXMap1 = 0x3e4,
 375         NvRegMSIXIrqStatus = 0x3f0,
 376
 377         NvRegPowerState2 = 0x600,
 378 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 379 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 380 };
 381
 382 /* Big endian: should work, but is untested */
 383 struct ring_desc {
 384         u32 PacketBuffer;
 385         u32 FlagLen;
 386 };
 387
 388 struct ring_desc_ex {
 389         u32 PacketBufferHigh;
 390         u32 PacketBufferLow;
 391         u32 TxVlan;
 392         u32 FlagLen;
 393 };
 394
 395 typedef union _ring_type {
 396         struct ring_desc* orig;
 397         struct ring_desc_ex* ex;
 398 } ring_type;
 399
 400 #define FLAG_MASK_V1 0xffff0000
 401 #define FLAG_MASK_V2 0xffffc000
 402 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 403 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 404
 405 #define NV_TX_LASTPACKET        (1<<16)
 406 #define NV_TX_RETRYERROR        (1<<19)
 407 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 408 #define NV_TX_DEFERRED          (1<<26)
 409 #define NV_TX_CARRIERLOST       (1<<27)
 410 #define NV_TX_LATECOLLISION     (1<<28)
 411 #define NV_TX_UNDERFLOW         (1<<29)
 412 #define NV_TX_ERROR             (1<<30)
 413 #define NV_TX_VALID             (1<<31)
 414
 415 #define NV_TX2_LASTPACKET       (1<<29)
 416 #define NV_TX2_RETRYERROR       (1<<18)
 417 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 418 #define NV_TX2_DEFERRED         (1<<25)
 419 #define NV_TX2_CARRIERLOST      (1<<26)
 420 #define NV_TX2_LATECOLLISION    (1<<27)
 421 #define NV_TX2_UNDERFLOW        (1<<28)
 422 /* error and valid are the same for both */
 423 #define NV_TX2_ERROR            (1<<30)
 424 #define NV_TX2_VALID            (1<<31)
 425 #define NV_TX2_TSO              (1<<28)
 426 #define NV_TX2_TSO_SHIFT        14
 427 #define NV_TX2_TSO_MAX_SHIFT    14
 428 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 429 #define NV_TX2_CHECKSUM_L3      (1<<27)
 430 #define NV_TX2_CHECKSUM_L4      (1<<26)
 431
 432 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 433
 434 #define NV_RX_DESCRIPTORVALID   (1<<16)
 435 #define NV_RX_MISSEDFRAME       (1<<17)
 436 #define NV_RX_SUBSTRACT1        (1<<18)
 437 #define NV_RX_ERROR1            (1<<23)
 438 #define NV_RX_ERROR2            (1<<24)
 439 #define NV_RX_ERROR3            (1<<25)
 440 #define NV_RX_ERROR4            (1<<26)
 441 #define NV_RX_CRCERR            (1<<27)
 442 #define NV_RX_OVERFLOW          (1<<28)
 443 #define NV_RX_FRAMINGERR        (1<<29)
 444 #define NV_RX_ERROR             (1<<30)
 445 #define NV_RX_AVAIL             (1<<31)
 446
 447 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 448 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 449 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 450 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 451 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 452 #define NV_RX2_SUBSTRACT1       (1<<25)
 453 #define NV_RX2_ERROR1           (1<<18)
 454 #define NV_RX2_ERROR2           (1<<19)
 455 #define NV_RX2_ERROR3           (1<<20)
 456 #define NV_RX2_ERROR4           (1<<21)
 457 #define NV_RX2_CRCERR           (1<<22)
 458 #define NV_RX2_OVERFLOW         (1<<23)
 459 #define NV_RX2_FRAMINGERR       (1<<24)
 460 /* error and avail are the same for both */
 461 #define NV_RX2_ERROR            (1<<30)
 462 #define NV_RX2_AVAIL            (1<<31)
 463
 464 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 465 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 466
 467 /* Miscelaneous hardware related defines: */
 468 #define NV_PCI_REGSZ_VER1       0x270
 469 #define NV_PCI_REGSZ_VER2       0x604
 470
 471 /* various timeout delays: all in usec */
 472 #define NV_TXRX_RESET_DELAY     4
 473 #define NV_TXSTOP_DELAY1        10
 474 #define NV_TXSTOP_DELAY1MAX     500000
 475 #define NV_TXSTOP_DELAY2        100
 476 #define NV_RXSTOP_DELAY1        10
 477 #define NV_RXSTOP_DELAY1MAX     500000
 478 #define NV_RXSTOP_DELAY2        100
 479 #define NV_SETUP5_DELAY         5
 480 #define NV_SETUP5_DELAYMAX      50000
 481 #define NV_POWERUP_DELAY        5
 482 #define NV_POWERUP_DELAYMAX     5000
 483 #define NV_MIIBUSY_DELAY        50
 484 #define NV_MIIPHY_DELAY 10
 485 #define NV_MIIPHY_DELAYMAX      10000
 486 #define NV_MAC_RESET_DELAY      64
 487
 488 #define NV_WAKEUPPATTERNS       5
 489 #define NV_WAKEUPMASKENTRIES    4
 490
 491 /* General driver defaults */
 492 #define NV_WATCHDOG_TIMEO       (5*HZ)
 493
 494 #define RX_RING_DEFAULT         128
 495 #define TX_RING_DEFAULT         256
 496 #define RX_RING_MIN             128
 497 #define TX_RING_MIN             64
 498 #define RING_MAX_DESC_VER_1     1024
 499 #define RING_MAX_DESC_VER_2_3   16384
 500 /*
 501  * Difference between the get and put pointers for the tx ring.
 502  * This is used to throttle the amount of data outstanding in the
 503  * tx ring.
 504  */
 505 #define TX_LIMIT_DIFFERENCE     1
 506
 507 /* rx/tx mac addr + type + vlan + align + slack*/
 508 #define NV_RX_HEADERS           (64)
 509 /* even more slack. */
 510 #define NV_RX_ALLOC_PAD         (64)
 511
 512 /* maximum mtu size */
 513 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 514 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 515
 516 #define OOM_REFILL      (1+HZ/20)
 517 #define POLL_WAIT       (1+HZ/100)
 518 #define LINK_TIMEOUT    (3*HZ)
 519 #define STATS_INTERVAL  (10*HZ)
 520
 521 /*
 522  * desc_ver values:
 523  * The nic supports three different descriptor types:
 524  * - DESC_VER_1: Original
 525  * - DESC_VER_2: support for jumbo frames.
 526  * - DESC_VER_3: 64-bit format.
 527  */
 528 #define DESC_VER_1      1
 529 #define DESC_VER_2      2
 530 #define DESC_VER_3      3
 531
 532 /* PHY defines */
 533 #define PHY_OUI_MARVELL 0x5043
 534 #define PHY_OUI_CICADA  0x03f1
 535 #define PHYID1_OUI_MASK 0x03ff
 536 #define PHYID1_OUI_SHFT 6
 537 #define PHYID2_OUI_MASK 0xfc00
 538 #define PHYID2_OUI_SHFT 10
 539 #define PHY_INIT1       0x0f000
 540 #define PHY_INIT2       0x0e00
 541 #define PHY_INIT3       0x01000
 542 #define PHY_INIT4       0x0200
 543 #define PHY_INIT5       0x0004
 544 #define PHY_INIT6       0x02000
 545 #define PHY_GIGABIT     0x0100
 546
 547 #define PHY_TIMEOUT     0x1
 548 #define PHY_ERROR       0x2
 549
 550 #define PHY_100 0x1
 551 #define PHY_1000        0x2
 552 #define PHY_HALF        0x100
 553
 554 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 555 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 556 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 557 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 558 #define NV_PAUSEFRAME_RX_REQ     0x0010
 559 #define NV_PAUSEFRAME_TX_REQ     0x0020
 560 #define NV_PAUSEFRAME_AUTONEG    0x0040
 561
 562 /* MSI/MSI-X defines */
 563 #define NV_MSI_X_MAX_VECTORS  8
 564 #define NV_MSI_X_VECTORS_MASK 0x000f
 565 #define NV_MSI_CAPABLE        0x0010
 566 #define NV_MSI_X_CAPABLE      0x0020
 567 #define NV_MSI_ENABLED        0x0040
 568 #define NV_MSI_X_ENABLED      0x0080
 569
 570 #define NV_MSI_X_VECTOR_ALL   0x0
 571 #define NV_MSI_X_VECTOR_RX    0x0
 572 #define NV_MSI_X_VECTOR_TX    0x1
 573 #define NV_MSI_X_VECTOR_OTHER 0x2
 574
 575 /* statistics */
 576 struct nv_ethtool_str {
 577         char name[ETH_GSTRING_LEN];
 578 };
 579
 580 static const struct nv_ethtool_str nv_estats_str[] = {
 581         { "tx_bytes" },
 582         { "tx_zero_rexmt" },
 583         { "tx_one_rexmt" },
 584         { "tx_many_rexmt" },
 585         { "tx_late_collision" },
 586         { "tx_fifo_errors" },
 587         { "tx_carrier_errors" },
 588         { "tx_excess_deferral" },
 589         { "tx_retry_error" },
 590         { "tx_deferral" },
 591         { "tx_packets" },
 592         { "tx_pause" },
 593         { "rx_frame_error" },
 594         { "rx_extra_byte" },
 595         { "rx_late_collision" },
 596         { "rx_runt" },
 597         { "rx_frame_too_long" },
 598         { "rx_over_errors" },
 599         { "rx_crc_errors" },
 600         { "rx_frame_align_error" },
 601         { "rx_length_error" },
 602         { "rx_unicast" },
 603         { "rx_multicast" },
 604         { "rx_broadcast" },
 605         { "rx_bytes" },
 606         { "rx_pause" },
 607         { "rx_drop_frame" },
 608         { "rx_packets" },
 609         { "rx_errors_total" }
 610 };
 611
 612 struct nv_ethtool_stats {
 613         u64 tx_bytes;
 614         u64 tx_zero_rexmt;
 615         u64 tx_one_rexmt;
 616         u64 tx_many_rexmt;
 617         u64 tx_late_collision;
 618         u64 tx_fifo_errors;
 619         u64 tx_carrier_errors;
 620         u64 tx_excess_deferral;
 621         u64 tx_retry_error;
 622         u64 tx_deferral;
 623         u64 tx_packets;
 624         u64 tx_pause;
 625         u64 rx_frame_error;
 626         u64 rx_extra_byte;
 627         u64 rx_late_collision;
 628         u64 rx_runt;
 629         u64 rx_frame_too_long;
 630         u64 rx_over_errors;
 631         u64 rx_crc_errors;
 632         u64 rx_frame_align_error;
 633         u64 rx_length_error;
 634         u64 rx_unicast;
 635         u64 rx_multicast;
 636         u64 rx_broadcast;
 637         u64 rx_bytes;
 638         u64 rx_pause;
 639         u64 rx_drop_frame;
 640         u64 rx_packets;
 641         u64 rx_errors_total;
 642 };
 643
 644 /* diagnostics */
 645 #define NV_TEST_COUNT_BASE 3
 646 #define NV_TEST_COUNT_EXTENDED 4
 647
 648 static const struct nv_ethtool_str nv_etests_str[] = {
 649         { "link      (online/offline)" },
 650         { "register  (offline)       " },
 651         { "interrupt (offline)       " },
 652         { "loopback  (offline)       " }
 653 };
 654
 655 struct register_test {
 656         u32 reg;
 657         u32 mask;
 658 };
 659
 660 static const struct register_test nv_registers_test[] = {
 661         { NvRegUnknownSetupReg6, 0x01 },
 662         { NvRegMisc1, 0x03c },
 663         { NvRegOffloadConfig, 0x03ff },
 664         { NvRegMulticastAddrA, 0xffffffff },
 665         { NvRegTxWatermark, 0x0ff },
 666         { NvRegWakeUpFlags, 0x07777 },
 667         { 0,0 }
 668 };
 669
 670 /*
 671  * SMP locking:
 672  * All hardware access under dev->priv->lock, except the performance
 673  * critical parts:
 674  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 675  *      by the arch code for interrupts.
 676  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 677  *      needs dev->priv->lock :-(
 678  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 679  */
 680
 681 /* in dev: base, irq */
 682 struct fe_priv {
 683         spinlock_t lock;
 684
 685         /* General data:
 686          * Locking: spin_lock(&np->lock); */
 687         struct net_device_stats stats;
 688         struct nv_ethtool_stats estats;
 689         int in_shutdown;
 690         u32 linkspeed;
 691         int duplex;
 692         int autoneg;
 693         int fixed_mode;
 694         int phyaddr;
 695         int wolenabled;
 696         unsigned int phy_oui;
 697         u16 gigabit;
 698         int intr_test;
 699
 700         /* General data: RO fields */
 701         dma_addr_t ring_addr;
 702         struct pci_dev *pci_dev;
 703         u32 orig_mac[2];
 704         u32 irqmask;
 705         u32 desc_ver;
 706         u32 txrxctl_bits;
 707         u32 vlanctl_bits;
 708         u32 driver_data;
 709         u32 register_size;
 710
 711         void __iomem *base;
 712
 713         /* rx specific fields.
 714          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 715          */
 716         ring_type rx_ring;
 717         unsigned int cur_rx, refill_rx;
 718         struct sk_buff **rx_skbuff;
 719         dma_addr_t *rx_dma;
 720         unsigned int rx_buf_sz;
 721         unsigned int pkt_limit;
 722         struct timer_list oom_kick;
 723         struct timer_list nic_poll;
 724         struct timer_list stats_poll;
 725         u32 nic_poll_irq;
 726         int rx_ring_size;
 727
 728         /* media detection workaround.
 729          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 730          */
 731         int need_linktimer;
 732         unsigned long link_timeout;
 733         /*
 734          * tx specific fields.
 735          */
 736         ring_type tx_ring;
 737         unsigned int next_tx, nic_tx;
 738         struct sk_buff **tx_skbuff;
 739         dma_addr_t *tx_dma;
 740         unsigned int *tx_dma_len;
 741         u32 tx_flags;
 742         int tx_ring_size;
 743         int tx_limit_start;
 744         int tx_limit_stop;
 745
 746         /* vlan fields */
 747         struct vlan_group *vlangrp;
 748
 749         /* msi/msi-x fields */
 750         u32 msi_flags;
 751         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 752
 753         /* flow control */
 754         u32 pause_flags;
 755 };
 756
 757 /*
 758  * Maximum number of loops until we assume that a bit in the irq mask
 759  * is stuck. Overridable with module param.
 760  */
 761 static int max_interrupt_work = 5;
 762
 763 /*
 764  * Optimization can be either throuput mode or cpu mode
 765  *
 766  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 767  * CPU Mode: Interrupts are controlled by a timer.
 768  */
 769 enum {
 770         NV_OPTIMIZATION_MODE_THROUGHPUT,
 771         NV_OPTIMIZATION_MODE_CPU
 772 };
 773 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 774
 775 /*
 776  * Poll interval for timer irq
 777  *
 778  * This interval determines how frequent an interrupt is generated.
 779  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 780  * Min = 0, and Max = 65535
 781  */
 782 static int poll_interval = -1;
 783
 784 /*
 785  * MSI interrupts
 786  */
 787 enum {
 788         NV_MSI_INT_DISABLED,
 789         NV_MSI_INT_ENABLED
 790 };
 791 static int msi = NV_MSI_INT_ENABLED;
 792
 793 /*
 794  * MSIX interrupts
 795  */
 796 enum {
 797         NV_MSIX_INT_DISABLED,
 798         NV_MSIX_INT_ENABLED
 799 };
 800 static int msix = NV_MSIX_INT_ENABLED;
 801
 802 /*
 803  * DMA 64bit
 804  */
 805 enum {
 806         NV_DMA_64BIT_DISABLED,
 807         NV_DMA_64BIT_ENABLED
 808 };
 809 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 810
 811 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 812 {
 813         return netdev_priv(dev);
 814 }
 815
 816 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 817 {
 818         return ((struct fe_priv *)netdev_priv(dev))->base;
 819 }
 820
 821 static inline void pci_push(u8 __iomem *base)
 822 {
 823         /* force out pending posted writes */
 824         readl(base);
 825 }
 826
 827 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 828 {
 829         return le32_to_cpu(prd->FlagLen)
 830                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 831 }
 832
 833 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 834 {
 835         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 836 }
 837
 838 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 839                                 int delay, int delaymax, const char *msg)
 840 {
 841         u8 __iomem *base = get_hwbase(dev);
 842
 843         pci_push(base);
 844         do {
 845                 udelay(delay);
 846                 delaymax -= delay;
 847                 if (delaymax < 0) {
 848                         if (msg)
 849                                 printk(msg);
 850                         return 1;
 851                 }
 852         } while ((readl(base + offset) & mask) != target);
 853         return 0;
 854 }
 855
 856 #define NV_SETUP_RX_RING 0x01
 857 #define NV_SETUP_TX_RING 0x02
 858
 859 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 860 {
 861         struct fe_priv *np = get_nvpriv(dev);
 862         u8 __iomem *base = get_hwbase(dev);
 863
 864         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 865                 if (rxtx_flags & NV_SETUP_RX_RING) {
 866                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 867                 }
 868                 if (rxtx_flags & NV_SETUP_TX_RING) {
 869                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 870                 }
 871         } else {
 872                 if (rxtx_flags & NV_SETUP_RX_RING) {
 873                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 874                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 875                 }
 876                 if (rxtx_flags & NV_SETUP_TX_RING) {
 877                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 878                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 879                 }
 880         }
 881 }
 882
 883 static void free_rings(struct net_device *dev)
 884 {
 885         struct fe_priv *np = get_nvpriv(dev);
 886
 887         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 888                 if(np->rx_ring.orig)
 889                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 890                                             np->rx_ring.orig, np->ring_addr);
 891         } else {
 892                 if (np->rx_ring.ex)
 893                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 894                                             np->rx_ring.ex, np->ring_addr);
 895         }
 896         if (np->rx_skbuff)
 897                 kfree(np->rx_skbuff);
 898         if (np->rx_dma)
 899                 kfree(np->rx_dma);
 900         if (np->tx_skbuff)
 901                 kfree(np->tx_skbuff);
 902         if (np->tx_dma)
 903                 kfree(np->tx_dma);
 904         if (np->tx_dma_len)
 905                 kfree(np->tx_dma_len);
 906 }
 907
 908 static int using_multi_irqs(struct net_device *dev)
 909 {
 910         struct fe_priv *np = get_nvpriv(dev);
 911
 912         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 913             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 914              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 915                 return 0;
 916         else
 917                 return 1;
 918 }
 919
 920 static void nv_enable_irq(struct net_device *dev)
 921 {
 922         struct fe_priv *np = get_nvpriv(dev);
 923
 924         if (!using_multi_irqs(dev)) {
 925                 if (np->msi_flags & NV_MSI_X_ENABLED)
 926                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 927                 else
 928                         enable_irq(dev->irq);
 929         } else {
 930                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 931                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 932                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 933         }
 934 }
 935
 936 static void nv_disable_irq(struct net_device *dev)
 937 {
 938         struct fe_priv *np = get_nvpriv(dev);
 939
 940         if (!using_multi_irqs(dev)) {
 941                 if (np->msi_flags & NV_MSI_X_ENABLED)
 942                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 943                 else
 944                         disable_irq(dev->irq);
 945         } else {
 946                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 947                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 948                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 949         }
 950 }
 951
 952 /* In MSIX mode, a write to irqmask behaves as XOR */
 953 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 954 {
 955         u8 __iomem *base = get_hwbase(dev);
 956
 957         writel(mask, base + NvRegIrqMask);
 958 }
 959
 960 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 961 {
 962         struct fe_priv *np = get_nvpriv(dev);
 963         u8 __iomem *base = get_hwbase(dev);
 964
 965         if (np->msi_flags & NV_MSI_X_ENABLED) {
 966                 writel(mask, base + NvRegIrqMask);
 967         } else {
 968                 if (np->msi_flags & NV_MSI_ENABLED)
 969                         writel(0, base + NvRegMSIIrqMask);
 970                 writel(0, base + NvRegIrqMask);
 971         }
 972 }
 973
 974 #define MII_READ        (-1)
 975 /* mii_rw: read/write a register on the PHY.
 976  *
 977  * Caller must guarantee serialization
 978  */
 979 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 980 {
 981         u8 __iomem *base = get_hwbase(dev);
 982         u32 reg;
 983         int retval;
 984
 985         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 986
 987         reg = readl(base + NvRegMIIControl);
 988         if (reg & NVREG_MIICTL_INUSE) {
 989                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 990                 udelay(NV_MIIBUSY_DELAY);
 991         }
 992
 993         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 994         if (value != MII_READ) {
 995                 writel(value, base + NvRegMIIData);
 996                 reg |= NVREG_MIICTL_WRITE;
 997         }
 998         writel(reg, base + NvRegMIIControl);
 999
1000         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1001                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1002                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1003                                 dev->name, miireg, addr);
1004                 retval = -1;
1005         } else if (value != MII_READ) {
1006                 /* it was a write operation - fewer failures are detectable */
1007                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1008                                 dev->name, value, miireg, addr);
1009                 retval = 0;
1010         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1011                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1012                                 dev->name, miireg, addr);
1013                 retval = -1;
1014         } else {
1015                 retval = readl(base + NvRegMIIData);
1016                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1017                                 dev->name, miireg, addr, retval);
1018         }
1019
1020         return retval;
1021 }
1022
1023 static int phy_reset(struct net_device *dev)
1024 {
1025         struct fe_priv *np = netdev_priv(dev);
1026         u32 miicontrol;
1027         unsigned int tries = 0;
1028
1029         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1030         miicontrol |= BMCR_RESET;
1031         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1032                 return -1;
1033         }
1034
1035         /* wait for 500ms */
1036         msleep(500);
1037
1038         /* must wait till reset is deasserted */
1039         while (miicontrol & BMCR_RESET) {
1040                 msleep(10);
1041                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1042                 /* FIXME: 100 tries seem excessive */
1043                 if (tries++ > 100)
1044                         return -1;
1045         }
1046         return 0;
1047 }
1048
1049 static int phy_init(struct net_device *dev)
1050 {
1051         struct fe_priv *np = get_nvpriv(dev);
1052         u8 __iomem *base = get_hwbase(dev);
1053         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1054
1055         /* set advertise register */
1056         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1057         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1058         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1059                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1060                 return PHY_ERROR;
1061         }
1062
1063         /* get phy interface type */
1064         phyinterface = readl(base + NvRegPhyInterface);
1065
1066         /* see if gigabit phy */
1067         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1068         if (mii_status & PHY_GIGABIT) {
1069                 np->gigabit = PHY_GIGABIT;
1070                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1071                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1072                 if (phyinterface & PHY_RGMII)
1073                         mii_control_1000 |= ADVERTISE_1000FULL;
1074                 else
1075                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1076
1077                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1078                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1079                         return PHY_ERROR;
1080                 }
1081         }
1082         else
1083                 np->gigabit = 0;
1084
1085         /* reset the phy */
1086         if (phy_reset(dev)) {
1087                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1088                 return PHY_ERROR;
1089         }
1090
1091         /* phy vendor specific configuration */
1092         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1093                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1094                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1095                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1096                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1097                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1098                         return PHY_ERROR;
1099                 }
1100                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1101                 phy_reserved |= PHY_INIT5;
1102                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1103                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1104                         return PHY_ERROR;
1105                 }
1106         }
1107         if (np->phy_oui == PHY_OUI_CICADA) {
1108                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1109                 phy_reserved |= PHY_INIT6;
1110                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1111                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1112                         return PHY_ERROR;
1113                 }
1114         }
1115         /* some phys clear out pause advertisment on reset, set it back */
1116         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1117
1118         /* restart auto negotiation */
1119         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1120         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1121         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1122                 return PHY_ERROR;
1123         }
1124
1125         return 0;
1126 }
1127
1128 static void nv_start_rx(struct net_device *dev)
1129 {
1130         struct fe_priv *np = netdev_priv(dev);
1131         u8 __iomem *base = get_hwbase(dev);
1132
1133         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1134         /* Already running? Stop it. */
1135         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1136                 writel(0, base + NvRegReceiverControl);
1137                 pci_push(base);
1138         }
1139         writel(np->linkspeed, base + NvRegLinkSpeed);
1140         pci_push(base);
1141         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1142         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1143                                 dev->name, np->duplex, np->linkspeed);
1144         pci_push(base);
1145 }
1146
1147 static void nv_stop_rx(struct net_device *dev)
1148 {
1149         u8 __iomem *base = get_hwbase(dev);
1150
1151         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1152         writel(0, base + NvRegReceiverControl);
1153         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1154                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1155                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1156
1157         udelay(NV_RXSTOP_DELAY2);
1158         writel(0, base + NvRegLinkSpeed);
1159 }
1160
1161 static void nv_start_tx(struct net_device *dev)
1162 {
1163         u8 __iomem *base = get_hwbase(dev);
1164
1165         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1166         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1167         pci_push(base);
1168 }
1169
1170 static void nv_stop_tx(struct net_device *dev)
1171 {
1172         u8 __iomem *base = get_hwbase(dev);
1173
1174         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1175         writel(0, base + NvRegTransmitterControl);
1176         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1177                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1178                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1179
1180         udelay(NV_TXSTOP_DELAY2);
1181         writel(0, base + NvRegUnknownTransmitterReg);
1182 }
1183
1184 static void nv_txrx_reset(struct net_device *dev)
1185 {
1186         struct fe_priv *np = netdev_priv(dev);
1187         u8 __iomem *base = get_hwbase(dev);
1188
1189         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1190         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1191         pci_push(base);
1192         udelay(NV_TXRX_RESET_DELAY);
1193         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1194         pci_push(base);
1195 }
1196
1197 static void nv_mac_reset(struct net_device *dev)
1198 {
1199         struct fe_priv *np = netdev_priv(dev);
1200         u8 __iomem *base = get_hwbase(dev);
1201
1202         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1203         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1204         pci_push(base);
1205         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1206         pci_push(base);
1207         udelay(NV_MAC_RESET_DELAY);
1208         writel(0, base + NvRegMacReset);
1209         pci_push(base);
1210         udelay(NV_MAC_RESET_DELAY);
1211         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1212         pci_push(base);
1213 }
1214
1215 /*
1216  * nv_get_stats: dev->get_stats function
1217  * Get latest stats value from the nic.
1218  * Called with read_lock(&dev_base_lock) held for read -
1219  * only synchronized against unregister_netdevice.
1220  */
1221 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1222 {
1223         struct fe_priv *np = netdev_priv(dev);
1224
1225         /* It seems that the nic always generates interrupts and doesn't
1226          * accumulate errors internally. Thus the current values in np->stats
1227          * are already up to date.
1228          */
1229         return &np->stats;
1230 }
1231
1232 /*
1233  * nv_alloc_rx: fill rx ring entries.
1234  * Return 1 if the allocations for the skbs failed and the
1235  * rx engine is without Available descriptors
1236  */
1237 static int nv_alloc_rx(struct net_device *dev)
1238 {
1239         struct fe_priv *np = netdev_priv(dev);
1240         unsigned int refill_rx = np->refill_rx;
1241         int nr;
1242
1243         while (np->cur_rx != refill_rx) {
1244                 struct sk_buff *skb;
1245
1246                 nr = refill_rx % np->rx_ring_size;
1247                 if (np->rx_skbuff[nr] == NULL) {
1248
1249                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1250                         if (!skb)
1251                                 break;
1252
1253                         skb->dev = dev;
1254                         np->rx_skbuff[nr] = skb;
1255                 } else {
1256                         skb = np->rx_skbuff[nr];
1257                 }
1258                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1259                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1260                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1261                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1262                         wmb();
1263                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1264                 } else {
1265                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1266                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1267                         wmb();
1268                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1269                 }
1270                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1271                                         dev->name, refill_rx);
1272                 refill_rx++;
1273         }
1274         np->refill_rx = refill_rx;
1275         if (np->cur_rx - refill_rx == np->rx_ring_size)
1276                 return 1;
1277         return 0;
1278 }
1279
1280 static void nv_do_rx_refill(unsigned long data)
1281 {
1282         struct net_device *dev = (struct net_device *) data;
1283         struct fe_priv *np = netdev_priv(dev);
1284
1285         if (!using_multi_irqs(dev)) {
1286                 if (np->msi_flags & NV_MSI_X_ENABLED)
1287                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1288                 else
1289                         disable_irq(dev->irq);
1290         } else {
1291                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1292         }
1293         if (nv_alloc_rx(dev)) {
1294                 spin_lock_irq(&np->lock);
1295                 if (!np->in_shutdown)
1296                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1297                 spin_unlock_irq(&np->lock);
1298         }
1299         if (!using_multi_irqs(dev)) {
1300                 if (np->msi_flags & NV_MSI_X_ENABLED)
1301                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1302                 else
1303                         enable_irq(dev->irq);
1304         } else {
1305                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1306         }
1307 }
1308
1309 static void nv_init_rx(struct net_device *dev)
1310 {
1311         struct fe_priv *np = netdev_priv(dev);
1312         int i;
1313
1314         np->cur_rx = np->rx_ring_size;
1315         np->refill_rx = 0;
1316         for (i = 0; i < np->rx_ring_size; i++)
1317                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1318                         np->rx_ring.orig[i].FlagLen = 0;
1319                 else
1320                         np->rx_ring.ex[i].FlagLen = 0;
1321 }
1322
1323 static void nv_init_tx(struct net_device *dev)
1324 {
1325         struct fe_priv *np = netdev_priv(dev);
1326         int i;
1327
1328         np->next_tx = np->nic_tx = 0;
1329         for (i = 0; i < np->tx_ring_size; i++) {
1330                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1331                         np->tx_ring.orig[i].FlagLen = 0;
1332                 else
1333                         np->tx_ring.ex[i].FlagLen = 0;
1334                 np->tx_skbuff[i] = NULL;
1335                 np->tx_dma[i] = 0;
1336         }
1337 }
1338
1339 static int nv_init_ring(struct net_device *dev)
1340 {
1341         nv_init_tx(dev);
1342         nv_init_rx(dev);
1343         return nv_alloc_rx(dev);
1344 }
1345
1346 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1347 {
1348         struct fe_priv *np = netdev_priv(dev);
1349
1350         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1351                 dev->name, skbnr);
1352
1353         if (np->tx_dma[skbnr]) {
1354                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1355                                np->tx_dma_len[skbnr],
1356                                PCI_DMA_TODEVICE);
1357                 np->tx_dma[skbnr] = 0;
1358         }
1359
1360         if (np->tx_skbuff[skbnr]) {
1361                 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1362                 np->tx_skbuff[skbnr] = NULL;
1363                 return 1;
1364         } else {
1365                 return 0;
1366         }
1367 }
1368
1369 static void nv_drain_tx(struct net_device *dev)
1370 {
1371         struct fe_priv *np = netdev_priv(dev);
1372         unsigned int i;
1373
1374         for (i = 0; i < np->tx_ring_size; i++) {
1375                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1376                         np->tx_ring.orig[i].FlagLen = 0;
1377                 else
1378                         np->tx_ring.ex[i].FlagLen = 0;
1379                 if (nv_release_txskb(dev, i))
1380                         np->stats.tx_dropped++;
1381         }
1382 }
1383
1384 static void nv_drain_rx(struct net_device *dev)
1385 {
1386         struct fe_priv *np = netdev_priv(dev);
1387         int i;
1388         for (i = 0; i < np->rx_ring_size; i++) {
1389                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1390                         np->rx_ring.orig[i].FlagLen = 0;
1391                 else
1392                         np->rx_ring.ex[i].FlagLen = 0;
1393                 wmb();
1394                 if (np->rx_skbuff[i]) {
1395                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1396                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1397                                                 PCI_DMA_FROMDEVICE);
1398                         dev_kfree_skb(np->rx_skbuff[i]);
1399                         np->rx_skbuff[i] = NULL;
1400                 }
1401         }
1402 }
1403
1404 static void drain_ring(struct net_device *dev)
1405 {
1406         nv_drain_tx(dev);
1407         nv_drain_rx(dev);
1408 }
1409
1410 /*
1411  * nv_start_xmit: dev->hard_start_xmit function
1412  * Called with netif_tx_lock held.
1413  */
1414 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1415 {
1416         struct fe_priv *np = netdev_priv(dev);
1417         u32 tx_flags = 0;
1418         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1419         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1420         unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1421         unsigned int start_nr = np->next_tx % np->tx_ring_size;
1422         unsigned int i;
1423         u32 offset = 0;
1424         u32 bcnt;
1425         u32 size = skb->len-skb->data_len;
1426         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1427         u32 tx_flags_vlan = 0;
1428
1429         /* add fragments to entries count */
1430         for (i = 0; i < fragments; i++) {
1431                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1432                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1433         }
1434
1435         spin_lock_irq(&np->lock);
1436
1437         if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1438                 spin_unlock_irq(&np->lock);
1439                 netif_stop_queue(dev);
1440                 return NETDEV_TX_BUSY;
1441         }
1442
1443         /* setup the header buffer */
1444         do {
1445                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1446                 nr = (nr + 1) % np->tx_ring_size;
1447
1448                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1449                                                 PCI_DMA_TODEVICE);
1450                 np->tx_dma_len[nr] = bcnt;
1451
1452                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1453                         np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1454                         np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1455                 } else {
1456                         np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1457                         np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1458                         np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1459                 }
1460                 tx_flags = np->tx_flags;
1461                 offset += bcnt;
1462                 size -= bcnt;
1463         } while(size);
1464
1465         /* setup the fragments */
1466         for (i = 0; i < fragments; i++) {
1467                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1468                 u32 size = frag->size;
1469                 offset = 0;
1470
1471                 do {
1472                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1473                         nr = (nr + 1) % np->tx_ring_size;
1474
1475                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1476                                                       PCI_DMA_TODEVICE);
1477                         np->tx_dma_len[nr] = bcnt;
1478
1479                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1480                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1481                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1482                         } else {
1483                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1484                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1485                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1486                         }
1487                         offset += bcnt;
1488                         size -= bcnt;
1489                 } while (size);
1490         }
1491
1492         /* set last fragment flag  */
1493         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1494                 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1495         } else {
1496                 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1497         }
1498
1499         np->tx_skbuff[nr] = skb;
1500
1501 #ifdef NETIF_F_TSO
1502         if (skb_is_gso(skb))
1503                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1504         else
1505 #endif
1506         tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1507                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1508
1509         /* vlan tag */
1510         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1511                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1512         }
1513
1514         /* set tx flags */
1515         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1516                 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1517         } else {
1518                 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1519                 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1520         }
1521
1522         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1523                 dev->name, np->next_tx, entries, tx_flags_extra);
1524         {
1525                 int j;
1526                 for (j=0; j<64; j++) {
1527                         if ((j%16) == 0)
1528                                 dprintk("\n%03x:", j);
1529                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1530                 }
1531                 dprintk("\n");
1532         }
1533
1534         np->next_tx += entries;
1535
1536         dev->trans_start = jiffies;
1537         spin_unlock_irq(&np->lock);
1538         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1539         pci_push(get_hwbase(dev));
1540         return NETDEV_TX_OK;
1541 }
1542
1543 /*
1544  * nv_tx_done: check for completed packets, release the skbs.
1545  *
1546  * Caller must own np->lock.
1547  */
1548 static void nv_tx_done(struct net_device *dev)
1549 {
1550         struct fe_priv *np = netdev_priv(dev);
1551         u32 Flags;
1552         unsigned int i;
1553         struct sk_buff *skb;
1554
1555         while (np->nic_tx != np->next_tx) {
1556                 i = np->nic_tx % np->tx_ring_size;
1557
1558                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1559                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1560                 else
1561                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1562
1563                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1564                                         dev->name, np->nic_tx, Flags);
1565                 if (Flags & NV_TX_VALID)
1566                         break;
1567                 if (np->desc_ver == DESC_VER_1) {
1568                         if (Flags & NV_TX_LASTPACKET) {
1569                                 skb = np->tx_skbuff[i];
1570                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1571                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1572                                         if (Flags & NV_TX_UNDERFLOW)
1573                                                 np->stats.tx_fifo_errors++;
1574                                         if (Flags & NV_TX_CARRIERLOST)
1575                                                 np->stats.tx_carrier_errors++;
1576                                         np->stats.tx_errors++;
1577                                 } else {
1578                                         np->stats.tx_packets++;
1579                                         np->stats.tx_bytes += skb->len;
1580                                 }
1581                         }
1582                 } else {
1583                         if (Flags & NV_TX2_LASTPACKET) {
1584                                 skb = np->tx_skbuff[i];
1585                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1586                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1587                                         if (Flags & NV_TX2_UNDERFLOW)
1588                                                 np->stats.tx_fifo_errors++;
1589                                         if (Flags & NV_TX2_CARRIERLOST)
1590                                                 np->stats.tx_carrier_errors++;
1591                                         np->stats.tx_errors++;
1592                                 } else {
1593                                         np->stats.tx_packets++;
1594                                         np->stats.tx_bytes += skb->len;
1595                                 }
1596                         }
1597                 }
1598                 nv_release_txskb(dev, i);
1599                 np->nic_tx++;
1600         }
1601         if (np->next_tx - np->nic_tx < np->tx_limit_start)
1602                 netif_wake_queue(dev);
1603 }
1604
1605 /*
1606  * nv_tx_timeout: dev->tx_timeout function
1607  * Called with netif_tx_lock held.
1608  */
1609 static void nv_tx_timeout(struct net_device *dev)
1610 {
1611         struct fe_priv *np = netdev_priv(dev);
1612         u8 __iomem *base = get_hwbase(dev);
1613         u32 status;
1614
1615         if (np->msi_flags & NV_MSI_X_ENABLED)
1616                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1617         else
1618                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1619
1620         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1621
1622         {
1623                 int i;
1624
1625                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1626                                 dev->name, (unsigned long)np->ring_addr,
1627                                 np->next_tx, np->nic_tx);
1628                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1629                 for (i=0;i<=np->register_size;i+= 32) {
1630                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1631                                         i,
1632                                         readl(base + i + 0), readl(base + i + 4),
1633                                         readl(base + i + 8), readl(base + i + 12),
1634                                         readl(base + i + 16), readl(base + i + 20),
1635                                         readl(base + i + 24), readl(base + i + 28));
1636                 }
1637                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1638                 for (i=0;i<np->tx_ring_size;i+= 4) {
1639                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1640                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1641                                        i,
1642                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1643                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1644                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1645                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1646                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1647                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1648                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1649                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1650                         } else {
1651                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1652                                        i,
1653                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1654                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1655                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1656                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1657                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1658                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1659                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1660                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1661                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1662                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1663                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1664                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1665                         }
1666                 }
1667         }
1668
1669         spin_lock_irq(&np->lock);
1670
1671         /* 1) stop tx engine */
1672         nv_stop_tx(dev);
1673
1674         /* 2) check that the packets were not sent already: */
1675         nv_tx_done(dev);
1676
1677         /* 3) if there are dead entries: clear everything */
1678         if (np->next_tx != np->nic_tx) {
1679                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1680                 nv_drain_tx(dev);
1681                 np->next_tx = np->nic_tx = 0;
1682                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1683                 netif_wake_queue(dev);
1684         }
1685
1686         /* 4) restart tx engine */
1687         nv_start_tx(dev);
1688         spin_unlock_irq(&np->lock);
1689 }
1690
1691 /*
1692  * Called when the nic notices a mismatch between the actual data len on the
1693  * wire and the len indicated in the 802 header
1694  */
1695 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1696 {
1697         int hdrlen;     /* length of the 802 header */
1698         int protolen;   /* length as stored in the proto field */
1699
1700         /* 1) calculate len according to header */
1701         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1702                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1703                 hdrlen = VLAN_HLEN;
1704         } else {
1705                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1706                 hdrlen = ETH_HLEN;
1707         }
1708         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1709                                 dev->name, datalen, protolen, hdrlen);
1710         if (protolen > ETH_DATA_LEN)
1711                 return datalen; /* Value in proto field not a len, no checks possible */
1712
1713         protolen += hdrlen;
1714         /* consistency checks: */
1715         if (datalen > ETH_ZLEN) {
1716                 if (datalen >= protolen) {
1717                         /* more data on wire than in 802 header, trim of
1718                          * additional data.
1719                          */
1720                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1721                                         dev->name, protolen);
1722                         return protolen;
1723                 } else {
1724                         /* less data on wire than mentioned in header.
1725                          * Discard the packet.
1726                          */
1727                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1728                                         dev->name);
1729                         return -1;
1730                 }
1731         } else {
1732                 /* short packet. Accept only if 802 values are also short */
1733                 if (protolen > ETH_ZLEN) {
1734                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1735                                         dev->name);
1736                         return -1;
1737                 }
1738                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1739                                 dev->name, datalen);
1740                 return datalen;
1741         }
1742 }
1743
1744 static void nv_rx_process(struct net_device *dev)
1745 {
1746         struct fe_priv *np = netdev_priv(dev);
1747         u32 Flags;
1748         u32 vlanflags = 0;
1749
1750         for (;;) {
1751                 struct sk_buff *skb;
1752                 int len;
1753                 int i;
1754                 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1755                         break;  /* we scanned the whole ring - do not continue */
1756
1757                 i = np->cur_rx % np->rx_ring_size;
1758                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1759                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1760                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1761                 } else {
1762                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1763                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1764                         vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1765                 }
1766
1767                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1768                                         dev->name, np->cur_rx, Flags);
1769
1770                 if (Flags & NV_RX_AVAIL)
1771                         break;  /* still owned by hardware, */
1772
1773                 /*
1774                  * the packet is for us - immediately tear down the pci mapping.
1775                  * TODO: check if a prefetch of the first cacheline improves
1776                  * the performance.
1777                  */
1778                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1779                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1780                                 PCI_DMA_FROMDEVICE);
1781
1782                 {
1783                         int j;
1784                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1785                         for (j=0; j<64; j++) {
1786                                 if ((j%16) == 0)
1787                                         dprintk("\n%03x:", j);
1788                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1789                         }
1790                         dprintk("\n");
1791                 }
1792                 /* look at what we actually got: */
1793                 if (np->desc_ver == DESC_VER_1) {
1794                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1795                                 goto next_pkt;
1796
1797                         if (Flags & NV_RX_ERROR) {
1798                                 if (Flags & NV_RX_MISSEDFRAME) {
1799                                         np->stats.rx_missed_errors++;
1800                                         np->stats.rx_errors++;
1801                                         goto next_pkt;
1802                                 }
1803                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1804                                         np->stats.rx_errors++;
1805                                         goto next_pkt;
1806                                 }
1807                                 if (Flags & NV_RX_CRCERR) {
1808                                         np->stats.rx_crc_errors++;
1809                                         np->stats.rx_errors++;
1810                                         goto next_pkt;
1811                                 }
1812                                 if (Flags & NV_RX_OVERFLOW) {
1813                                         np->stats.rx_over_errors++;
1814                                         np->stats.rx_errors++;
1815                                         goto next_pkt;
1816                                 }
1817                                 if (Flags & NV_RX_ERROR4) {
1818                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1819                                         if (len < 0) {
1820                                                 np->stats.rx_errors++;
1821                                                 goto next_pkt;
1822                                         }
1823                                 }
1824                                 /* framing errors are soft errors. */
1825                                 if (Flags & NV_RX_FRAMINGERR) {
1826                                         if (Flags & NV_RX_SUBSTRACT1) {
1827                                                 len--;
1828                                         }
1829                                 }
1830                         }
1831                 } else {
1832                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1833                                 goto next_pkt;
1834
1835                         if (Flags & NV_RX2_ERROR) {
1836                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1837                                         np->stats.rx_errors++;
1838                                         goto next_pkt;
1839                                 }
1840                                 if (Flags & NV_RX2_CRCERR) {
1841                                         np->stats.rx_crc_errors++;
1842                                         np->stats.rx_errors++;
1843                                         goto next_pkt;
1844                                 }
1845                                 if (Flags & NV_RX2_OVERFLOW) {
1846                                         np->stats.rx_over_errors++;
1847                                         np->stats.rx_errors++;
1848                                         goto next_pkt;
1849                                 }
1850                                 if (Flags & NV_RX2_ERROR4) {
1851                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1852                                         if (len < 0) {
1853                                                 np->stats.rx_errors++;
1854                                                 goto next_pkt;
1855                                         }
1856                                 }
1857                                 /* framing errors are soft errors */
1858                                 if (Flags & NV_RX2_FRAMINGERR) {
1859                                         if (Flags & NV_RX2_SUBSTRACT1) {
1860                                                 len--;
1861                                         }
1862                                 }
1863                         }
1864                         if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1865                                 Flags &= NV_RX2_CHECKSUMMASK;
1866                                 if (Flags == NV_RX2_CHECKSUMOK1 ||
1867                                     Flags == NV_RX2_CHECKSUMOK2 ||
1868                                     Flags == NV_RX2_CHECKSUMOK3) {
1869                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1870                                         np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1871                                 } else {
1872                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1873                                 }
1874                         }
1875                 }
1876                 /* got a valid packet - forward it to the network core */
1877                 skb = np->rx_skbuff[i];
1878                 np->rx_skbuff[i] = NULL;
1879
1880                 skb_put(skb, len);
1881                 skb->protocol = eth_type_trans(skb, dev);
1882                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1883                                         dev->name, np->cur_rx, len, skb->protocol);
1884                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1885                         vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1886                 } else {
1887                         netif_rx(skb);
1888                 }
1889                 dev->last_rx = jiffies;
1890                 np->stats.rx_packets++;
1891                 np->stats.rx_bytes += len;
1892 next_pkt:
1893                 np->cur_rx++;
1894         }
1895 }
1896
1897 static void set_bufsize(struct net_device *dev)
1898 {
1899         struct fe_priv *np = netdev_priv(dev);
1900
1901         if (dev->mtu <= ETH_DATA_LEN)
1902                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1903         else
1904                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1905 }
1906
1907 /*
1908  * nv_change_mtu: dev->change_mtu function
1909  * Called with dev_base_lock held for read.
1910  */
1911 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1912 {
1913         struct fe_priv *np = netdev_priv(dev);
1914         int old_mtu;
1915
1916         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1917                 return -EINVAL;
1918
1919         old_mtu = dev->mtu;
1920         dev->mtu = new_mtu;
1921
1922         /* return early if the buffer sizes will not change */
1923         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1924                 return 0;
1925         if (old_mtu == new_mtu)
1926                 return 0;
1927
1928         /* synchronized against open : rtnl_lock() held by caller */
1929         if (netif_running(dev)) {
1930                 u8 __iomem *base = get_hwbase(dev);
1931                 /*
1932                  * It seems that the nic preloads valid ring entries into an
1933                  * internal buffer. The procedure for flushing everything is
1934                  * guessed, there is probably a simpler approach.
1935                  * Changing the MTU is a rare event, it shouldn't matter.
1936                  */
1937                 nv_disable_irq(dev);
1938                 netif_tx_lock_bh(dev);
1939                 spin_lock(&np->lock);
1940                 /* stop engines */
1941                 nv_stop_rx(dev);
1942                 nv_stop_tx(dev);
1943                 nv_txrx_reset(dev);
1944                 /* drain rx queue */
1945                 nv_drain_rx(dev);
1946                 nv_drain_tx(dev);
1947                 /* reinit driver view of the rx queue */
1948                 set_bufsize(dev);
1949                 if (nv_init_ring(dev)) {
1950                         if (!np->in_shutdown)
1951                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1952                 }
1953                 /* reinit nic view of the rx queue */
1954                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1955                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1956                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1957                         base + NvRegRingSizes);
1958                 pci_push(base);
1959                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1960                 pci_push(base);
1961
1962                 /* restart rx engine */
1963                 nv_start_rx(dev);
1964                 nv_start_tx(dev);
1965                 spin_unlock(&np->lock);
1966                 netif_tx_unlock_bh(dev);
1967                 nv_enable_irq(dev);
1968         }
1969         return 0;
1970 }
1971
1972 static void nv_copy_mac_to_hw(struct net_device *dev)
1973 {
1974         u8 __iomem *base = get_hwbase(dev);
1975         u32 mac[2];
1976
1977         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1978                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1979         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1980
1981         writel(mac[0], base + NvRegMacAddrA);
1982         writel(mac[1], base + NvRegMacAddrB);
1983 }
1984
1985 /*
1986  * nv_set_mac_address: dev->set_mac_address function
1987  * Called with rtnl_lock() held.
1988  */
1989 static int nv_set_mac_address(struct net_device *dev, void *addr)
1990 {
1991         struct fe_priv *np = netdev_priv(dev);
1992         struct sockaddr *macaddr = (struct sockaddr*)addr;
1993
1994         if(!is_valid_ether_addr(macaddr->sa_data))
1995                 return -EADDRNOTAVAIL;
1996
1997         /* synchronized against open : rtnl_lock() held by caller */
1998         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1999
2000         if (netif_running(dev)) {
2001                 netif_tx_lock_bh(dev);
2002                 spin_lock_irq(&np->lock);
2003
2004                 /* stop rx engine */
2005                 nv_stop_rx(dev);
2006
2007                 /* set mac address */
2008                 nv_copy_mac_to_hw(dev);
2009
2010                 /* restart rx engine */
2011                 nv_start_rx(dev);
2012                 spin_unlock_irq(&np->lock);
2013                 netif_tx_unlock_bh(dev);
2014         } else {
2015                 nv_copy_mac_to_hw(dev);
2016         }
2017         return 0;
2018 }
2019
2020 /*
2021  * nv_set_multicast: dev->set_multicast function
2022  * Called with netif_tx_lock held.
2023  */
2024 static void nv_set_multicast(struct net_device *dev)
2025 {
2026         struct fe_priv *np = netdev_priv(dev);
2027         u8 __iomem *base = get_hwbase(dev);
2028         u32 addr[2];
2029         u32 mask[2];
2030         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2031
2032         memset(addr, 0, sizeof(addr));
2033         memset(mask, 0, sizeof(mask));
2034
2035         if (dev->flags & IFF_PROMISC) {
2036                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2037                 pff |= NVREG_PFF_PROMISC;
2038         } else {
2039                 pff |= NVREG_PFF_MYADDR;
2040
2041                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2042                         u32 alwaysOff[2];
2043                         u32 alwaysOn[2];
2044
2045                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2046                         if (dev->flags & IFF_ALLMULTI) {
2047                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2048                         } else {
2049                                 struct dev_mc_list *walk;
2050
2051                                 walk = dev->mc_list;
2052                                 while (walk != NULL) {
2053                                         u32 a, b;
2054                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2055                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2056                                         alwaysOn[0] &= a;
2057                                         alwaysOff[0] &= ~a;
2058                                         alwaysOn[1] &= b;
2059                                         alwaysOff[1] &= ~b;
2060                                         walk = walk->next;
2061                                 }
2062                         }
2063                         addr[0] = alwaysOn[0];
2064                         addr[1] = alwaysOn[1];
2065                         mask[0] = alwaysOn[0] | alwaysOff[0];
2066                         mask[1] = alwaysOn[1] | alwaysOff[1];
2067                 }
2068         }
2069         addr[0] |= NVREG_MCASTADDRA_FORCE;
2070         pff |= NVREG_PFF_ALWAYS;
2071         spin_lock_irq(&np->lock);
2072         nv_stop_rx(dev);
2073         writel(addr[0], base + NvRegMulticastAddrA);
2074         writel(addr[1], base + NvRegMulticastAddrB);
2075         writel(mask[0], base + NvRegMulticastMaskA);
2076         writel(mask[1], base + NvRegMulticastMaskB);
2077         writel(pff, base + NvRegPacketFilterFlags);
2078         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2079                 dev->name);
2080         nv_start_rx(dev);
2081         spin_unlock_irq(&np->lock);
2082 }
2083
2084 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2085 {
2086         struct fe_priv *np = netdev_priv(dev);
2087         u8 __iomem *base = get_hwbase(dev);
2088
2089         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2090
2091         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2092                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2093                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2094                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2095                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2096                 } else {
2097                         writel(pff, base + NvRegPacketFilterFlags);
2098                 }
2099         }
2100         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2101                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2102                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2103                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2104                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2105                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2106                 } else {
2107                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2108                         writel(regmisc, base + NvRegMisc1);
2109                 }
2110         }
2111 }
2112
2113 /**
2114  * nv_update_linkspeed: Setup the MAC according to the link partner
2115  * @dev: Network device to be configured
2116  *
2117  * The function queries the PHY and checks if there is a link partner.
2118  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2119  * set to 10 MBit HD.
2120  *
2121  * The function returns 0 if there is no link partner and 1 if there is
2122  * a good link partner.
2123  */
2124 static int nv_update_linkspeed(struct net_device *dev)
2125 {
2126         struct fe_priv *np = netdev_priv(dev);
2127         u8 __iomem *base = get_hwbase(dev);
2128         int adv = 0;
2129         int lpa = 0;
2130         int adv_lpa, adv_pause, lpa_pause;
2131         int newls = np->linkspeed;
2132         int newdup = np->duplex;
2133         int mii_status;
2134         int retval = 0;
2135         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2136
2137         /* BMSR_LSTATUS is latched, read it twice:
2138          * we want the current value.
2139          */
2140         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2141         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2142
2143         if (!(mii_status & BMSR_LSTATUS)) {
2144                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2145                                 dev->name);
2146                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2147                 newdup = 0;
2148                 retval = 0;
2149                 goto set_speed;
2150         }
2151
2152         if (np->autoneg == 0) {
2153                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2154                                 dev->name, np->fixed_mode);
2155                 if (np->fixed_mode & LPA_100FULL) {
2156                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2157                         newdup = 1;
2158                 } else if (np->fixed_mode & LPA_100HALF) {
2159                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2160                         newdup = 0;
2161                 } else if (np->fixed_mode & LPA_10FULL) {
2162                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2163                         newdup = 1;
2164                 } else {
2165                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2166                         newdup = 0;
2167                 }
2168                 retval = 1;
2169                 goto set_speed;
2170         }
2171         /* check auto negotiation is complete */
2172         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2173                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2174                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2175                 newdup = 0;
2176                 retval = 0;
2177                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2178                 goto set_speed;
2179         }
2180
2181         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2182         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2183         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2184                                 dev->name, adv, lpa);
2185
2186         retval = 1;
2187         if (np->gigabit == PHY_GIGABIT) {
2188                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2189                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2190
2191                 if ((control_1000 & ADVERTISE_1000FULL) &&
2192                         (status_1000 & LPA_1000FULL)) {
2193                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2194                                 dev->name);
2195                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2196                         newdup = 1;
2197                         goto set_speed;
2198                 }
2199         }
2200
2201         /* FIXME: handle parallel detection properly */
2202         adv_lpa = lpa & adv;
2203         if (adv_lpa & LPA_100FULL) {
2204                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2205                 newdup = 1;
2206         } else if (adv_lpa & LPA_100HALF) {
2207                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2208                 newdup = 0;
2209         } else if (adv_lpa & LPA_10FULL) {
2210                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2211                 newdup = 1;
2212         } else if (adv_lpa & LPA_10HALF) {
2213                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2214                 newdup = 0;
2215         } else {
2216                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2217                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2218                 newdup = 0;
2219         }
2220
2221 set_speed:
2222         if (np->duplex == newdup && np->linkspeed == newls)
2223                 return retval;
2224
2225         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2226                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2227
2228         np->duplex = newdup;
2229         np->linkspeed = newls;
2230
2231         if (np->gigabit == PHY_GIGABIT) {
2232                 phyreg = readl(base + NvRegRandomSeed);
2233                 phyreg &= ~(0x3FF00);
2234                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2235                         phyreg |= NVREG_RNDSEED_FORCE3;
2236                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2237                         phyreg |= NVREG_RNDSEED_FORCE2;
2238                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2239                         phyreg |= NVREG_RNDSEED_FORCE;
2240                 writel(phyreg, base + NvRegRandomSeed);
2241         }
2242
2243         phyreg = readl(base + NvRegPhyInterface);
2244         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2245         if (np->duplex == 0)
2246                 phyreg |= PHY_HALF;
2247         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2248                 phyreg |= PHY_100;
2249         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2250                 phyreg |= PHY_1000;
2251         writel(phyreg, base + NvRegPhyInterface);
2252
2253         if (phyreg & PHY_RGMII) {
2254                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2255                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2256                 else
2257                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2258         } else {
2259                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2260         }
2261         writel(txreg, base + NvRegTxDeferral);
2262
2263         if (np->desc_ver == DESC_VER_1) {
2264                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2265         } else {
2266                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2267                         txreg = NVREG_TX_WM_DESC2_3_1000;
2268                 else
2269                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2270         }
2271         writel(txreg, base + NvRegTxWatermark);
2272
2273         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2274                 base + NvRegMisc1);
2275         pci_push(base);
2276         writel(np->linkspeed, base + NvRegLinkSpeed);
2277         pci_push(base);
2278
2279         pause_flags = 0;
2280         /* setup pause frame */
2281         if (np->duplex != 0) {
2282                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2283                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2284                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2285
2286                         switch (adv_pause) {
2287                         case (ADVERTISE_PAUSE_CAP):
2288                                 if (lpa_pause & LPA_PAUSE_CAP) {
2289                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2290                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2291                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2292                                 }
2293                                 break;
2294                         case (ADVERTISE_PAUSE_ASYM):
2295                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2296                                 {
2297                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2298                                 }
2299                                 break;
2300                         case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2301                                 if (lpa_pause & LPA_PAUSE_CAP)
2302                                 {
2303                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2304                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2305                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2306                                 }
2307                                 if (lpa_pause == LPA_PAUSE_ASYM)
2308                                 {
2309                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2310                                 }
2311                                 break;
2312                         }
2313                 } else {
2314                         pause_flags = np->pause_flags;
2315                 }
2316         }
2317         nv_update_pause(dev, pause_flags);
2318
2319         return retval;
2320 }
2321
2322 static void nv_linkchange(struct net_device *dev)
2323 {
2324         if (nv_update_linkspeed(dev)) {
2325                 if (!netif_carrier_ok(dev)) {
2326                         netif_carrier_on(dev);
2327                         printk(KERN_INFO "%s: link up.\n", dev->name);
2328                         nv_start_rx(dev);
2329                 }
2330         } else {
2331                 if (netif_carrier_ok(dev)) {
2332                         netif_carrier_off(dev);
2333                         printk(KERN_INFO "%s: link down.\n", dev->name);
2334                         nv_stop_rx(dev);
2335                 }
2336         }
2337 }
2338
2339 static void nv_link_irq(struct net_device *dev)
2340 {
2341         u8 __iomem *base = get_hwbase(dev);
2342         u32 miistat;
2343
2344         miistat = readl(base + NvRegMIIStatus);
2345         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2346         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2347
2348         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2349                 nv_linkchange(dev);
2350         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2351 }
2352
2353 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2354 {
2355         struct net_device *dev = (struct net_device *) data;
2356         struct fe_priv *np = netdev_priv(dev);
2357         u8 __iomem *base = get_hwbase(dev);
2358         u32 events;
2359         int i;
2360
2361         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2362
2363         for (i=0; ; i++) {
2364                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2365                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2366                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2367                 } else {
2368                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2369                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2370                 }
2371                 pci_push(base);
2372                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2373                 if (!(events & np->irqmask))
2374                         break;
2375
2376                 spin_lock(&np->lock);
2377                 nv_tx_done(dev);
2378                 spin_unlock(&np->lock);
2379
2380                 nv_rx_process(dev);
2381                 if (nv_alloc_rx(dev)) {
2382                         spin_lock(&np->lock);
2383                         if (!np->in_shutdown)
2384                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2385                         spin_unlock(&np->lock);
2386                 }
2387
2388                 if (events & NVREG_IRQ_LINK) {
2389                         spin_lock(&np->lock);
2390                         nv_link_irq(dev);
2391                         spin_unlock(&np->lock);
2392                 }
2393                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2394                         spin_lock(&np->lock);
2395                         nv_linkchange(dev);
2396                         spin_unlock(&np->lock);
2397                         np->link_timeout = jiffies + LINK_TIMEOUT;
2398                 }
2399                 if (events & (NVREG_IRQ_TX_ERR)) {
2400                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2401                                                 dev->name, events);
2402                 }
2403                 if (events & (NVREG_IRQ_UNKNOWN)) {
2404                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2405                                                 dev->name, events);
2406                 }
2407                 if (i > max_interrupt_work) {
2408                         spin_lock(&np->lock);
2409                         /* disable interrupts on the nic */
2410                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2411                                 writel(0, base + NvRegIrqMask);
2412                         else
2413                                 writel(np->irqmask, base + NvRegIrqMask);
2414                         pci_push(base);
2415
2416                         if (!np->in_shutdown) {
2417                                 np->nic_poll_irq = np->irqmask;
2418                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2419                         }
2420                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2421                         spin_unlock(&np->lock);
2422                         break;
2423                 }
2424
2425         }
2426         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2427
2428         return IRQ_RETVAL(i);
2429 }
2430
2431 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2432 {
2433         struct net_device *dev = (struct net_device *) data;
2434         struct fe_priv *np = netdev_priv(dev);
2435         u8 __iomem *base = get_hwbase(dev);
2436         u32 events;
2437         int i;
2438
2439         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2440
2441         for (i=0; ; i++) {
2442                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2443                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2444                 pci_push(base);
2445                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2446                 if (!(events & np->irqmask))
2447                         break;
2448
2449                 spin_lock_irq(&np->lock);
2450                 nv_tx_done(dev);
2451                 spin_unlock_irq(&np->lock);
2452
2453                 if (events & (NVREG_IRQ_TX_ERR)) {
2454                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2455                                                 dev->name, events);
2456                 }
2457                 if (i > max_interrupt_work) {
2458                         spin_lock_irq(&np->lock);
2459                         /* disable interrupts on the nic */
2460                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2461                         pci_push(base);
2462
2463                         if (!np->in_shutdown) {
2464                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2465                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2466                         }
2467                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2468                         spin_unlock_irq(&np->lock);
2469                         break;
2470                 }
2471
2472         }
2473         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2474
2475         return IRQ_RETVAL(i);
2476 }
2477
2478 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2479 {
2480         struct net_device *dev = (struct net_device *) data;
2481         struct fe_priv *np = netdev_priv(dev);
2482         u8 __iomem *base = get_hwbase(dev);
2483         u32 events;
2484         int i;
2485
2486         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2487
2488         for (i=0; ; i++) {
2489                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2490                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2491                 pci_push(base);
2492                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2493                 if (!(events & np->irqmask))
2494                         break;
2495
2496                 nv_rx_process(dev);
2497                 if (nv_alloc_rx(dev)) {
2498                         spin_lock_irq(&np->lock);
2499                         if (!np->in_shutdown)
2500                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2501                         spin_unlock_irq(&np->lock);
2502                 }
2503
2504                 if (i > max_interrupt_work) {
2505                         spin_lock_irq(&np->lock);
2506                         /* disable interrupts on the nic */
2507                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2508                         pci_push(base);
2509
2510                         if (!np->in_shutdown) {
2511                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2512                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2513                         }
2514                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2515                         spin_unlock_irq(&np->lock);
2516                         break;
2517                 }
2518
2519         }
2520         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2521
2522         return IRQ_RETVAL(i);
2523 }
2524
2525 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2526 {
2527         struct net_device *dev = (struct net_device *) data;
2528         struct fe_priv *np = netdev_priv(dev);
2529         u8 __iomem *base = get_hwbase(dev);
2530         u32 events;
2531         int i;
2532
2533         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2534
2535         for (i=0; ; i++) {
2536                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2537                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2538                 pci_push(base);
2539                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2540                 if (!(events & np->irqmask))
2541                         break;
2542
2543                 if (events & NVREG_IRQ_LINK) {
2544                         spin_lock_irq(&np->lock);
2545                         nv_link_irq(dev);
2546                         spin_unlock_irq(&np->lock);
2547                 }
2548                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2549                         spin_lock_irq(&np->lock);
2550                         nv_linkchange(dev);
2551                         spin_unlock_irq(&np->lock);
2552                         np->link_timeout = jiffies + LINK_TIMEOUT;
2553                 }
2554                 if (events & (NVREG_IRQ_UNKNOWN)) {
2555                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2556                                                 dev->name, events);
2557                 }
2558                 if (i > max_interrupt_work) {
2559                         spin_lock_irq(&np->lock);
2560                         /* disable interrupts on the nic */
2561                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2562                         pci_push(base);
2563
2564                         if (!np->in_shutdown) {
2565                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2566                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2567                         }
2568                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2569                         spin_unlock_irq(&np->lock);
2570                         break;
2571                 }
2572
2573         }
2574         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2575
2576         return IRQ_RETVAL(i);
2577 }
2578
2579 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2580 {
2581         struct net_device *dev = (struct net_device *) data;
2582         struct fe_priv *np = netdev_priv(dev);
2583         u8 __iomem *base = get_hwbase(dev);
2584         u32 events;
2585
2586         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2587
2588         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2589                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2590                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2591         } else {
2592                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2593                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2594         }
2595         pci_push(base);
2596         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2597         if (!(events & NVREG_IRQ_TIMER))
2598                 return IRQ_RETVAL(0);
2599
2600         spin_lock(&np->lock);
2601         np->intr_test = 1;
2602         spin_unlock(&np->lock);
2603
2604         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2605
2606         return IRQ_RETVAL(1);
2607 }
2608
2609 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2610 {
2611         u8 __iomem *base = get_hwbase(dev);
2612         int i;
2613         u32 msixmap = 0;
2614
2615         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2616          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2617          * the remaining 8 interrupts.
2618          */
2619         for (i = 0; i < 8; i++) {
2620                 if ((irqmask >> i) & 0x1) {
2621                         msixmap |= vector << (i << 2);
2622                 }
2623         }
2624         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2625
2626         msixmap = 0;
2627         for (i = 0; i < 8; i++) {
2628                 if ((irqmask >> (i + 8)) & 0x1) {
2629                         msixmap |= vector << (i << 2);
2630                 }
2631         }
2632         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2633 }
2634
2635 static int nv_request_irq(struct net_device *dev, int intr_test)
2636 {
2637         struct fe_priv *np = get_nvpriv(dev);
2638         u8 __iomem *base = get_hwbase(dev);
2639         int ret = 1;
2640         int i;
2641
2642         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2643                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2644                         np->msi_x_entry[i].entry = i;
2645                 }
2646                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2647                         np->msi_flags |= NV_MSI_X_ENABLED;
2648                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2649                                 /* Request irq for rx handling */
2650                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2651                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2652                                         pci_disable_msix(np->pci_dev);
2653                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2654                                         goto out_err;
2655                                 }
2656                                 /* Request irq for tx handling */
2657                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2658                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2659                                         pci_disable_msix(np->pci_dev);
2660                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2661                                         goto out_free_rx;
2662                                 }
2663                                 /* Request irq for link and timer handling */
2664                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2665                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2666                                         pci_disable_msix(np->pci_dev);
2667                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2668                                         goto out_free_tx;
2669                                 }
2670                                 /* map interrupts to their respective vector */
2671                                 writel(0, base + NvRegMSIXMap0);
2672                                 writel(0, base + NvRegMSIXMap1);
2673                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2674                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2675                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2676                         } else {
2677                                 /* Request irq for all interrupts */
2678                                 if ((!intr_test &&
2679                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2680                                     (intr_test &&
2681                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2682                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2683                                         pci_disable_msix(np->pci_dev);
2684                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2685                                         goto out_err;
2686                                 }
2687
2688                                 /* map interrupts to vector 0 */
2689                                 writel(0, base + NvRegMSIXMap0);
2690                                 writel(0, base + NvRegMSIXMap1);
2691                         }
2692                 }
2693         }
2694         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2695                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2696                         np->msi_flags |= NV_MSI_ENABLED;
2697                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2698                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2699                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2700                                 pci_disable_msi(np->pci_dev);
2701                                 np->msi_flags &= ~NV_MSI_ENABLED;
2702                                 goto out_err;
2703                         }
2704
2705                         /* map interrupts to vector 0 */
2706                         writel(0, base + NvRegMSIMap0);
2707                         writel(0, base + NvRegMSIMap1);
2708                         /* enable msi vector 0 */
2709                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2710                 }
2711         }
2712         if (ret != 0) {
2713                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2714                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2715                         goto out_err;
2716
2717         }
2718
2719         return 0;
2720 out_free_tx:
2721         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2722 out_free_rx:
2723         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2724 out_err:
2725         return 1;
2726 }
2727
2728 static void nv_free_irq(struct net_device *dev)
2729 {
2730         struct fe_priv *np = get_nvpriv(dev);
2731         int i;
2732
2733         if (np->msi_flags & NV_MSI_X_ENABLED) {
2734                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2735                         free_irq(np->msi_x_entry[i].vector, dev);
2736                 }
2737                 pci_disable_msix(np->pci_dev);
2738                 np->msi_flags &= ~NV_MSI_X_ENABLED;
2739         } else {
2740                 free_irq(np->pci_dev->irq, dev);
2741                 if (np->msi_flags & NV_MSI_ENABLED) {
2742                         pci_disable_msi(np->pci_dev);
2743                         np->msi_flags &= ~NV_MSI_ENABLED;
2744                 }
2745         }
2746 }
2747
2748 static void nv_do_nic_poll(unsigned long data)
2749 {
2750         struct net_device *dev = (struct net_device *) data;
2751         struct fe_priv *np = netdev_priv(dev);
2752         u8 __iomem *base = get_hwbase(dev);
2753         u32 mask = 0;
2754
2755         /*
2756          * First disable irq(s) and then
2757          * reenable interrupts on the nic, we have to do this before calling
2758          * nv_nic_irq because that may decide to do otherwise
2759          */
2760
2761         if (!using_multi_irqs(dev)) {
2762                 if (np->msi_flags & NV_MSI_X_ENABLED)
2763                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2764                 else
2765                         disable_irq_lockdep(dev->irq);
2766                 mask = np->irqmask;
2767         } else {
2768                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2769                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2770                         mask |= NVREG_IRQ_RX_ALL;
2771                 }
2772                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2773                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2774                         mask |= NVREG_IRQ_TX_ALL;
2775                 }
2776                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2777                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2778                         mask |= NVREG_IRQ_OTHER;
2779                 }
2780         }
2781         np->nic_poll_irq = 0;
2782
2783         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2784
2785         writel(mask, base + NvRegIrqMask);
2786         pci_push(base);
2787
2788         if (!using_multi_irqs(dev)) {
2789                 nv_nic_irq(0, dev, NULL);
2790                 if (np->msi_flags & NV_MSI_X_ENABLED)
2791                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2792                 else
2793                         enable_irq_lockdep(dev->irq);
2794         } else {
2795                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2796                         nv_nic_irq_rx(0, dev, NULL);
2797                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2798                 }
2799                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2800                         nv_nic_irq_tx(0, dev, NULL);
2801                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2802                 }
2803                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2804                         nv_nic_irq_other(0, dev, NULL);
2805                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2806                 }
2807         }
2808 }
2809
2810 #ifdef CONFIG_NET_POLL_CONTROLLER
2811 static void nv_poll_controller(struct net_device *dev)
2812 {
2813         nv_do_nic_poll((unsigned long) dev);
2814 }
2815 #endif
2816
2817 static void nv_do_stats_poll(unsigned long data)
2818 {
2819         struct net_device *dev = (struct net_device *) data;
2820         struct fe_priv *np = netdev_priv(dev);
2821         u8 __iomem *base = get_hwbase(dev);
2822
2823         np->estats.tx_bytes += readl(base + NvRegTxCnt);
2824         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2825         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2826         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2827         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2828         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2829         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2830         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2831         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2832         np->estats.tx_deferral += readl(base + NvRegTxDef);
2833         np->estats.tx_packets += readl(base + NvRegTxFrame);
2834         np->estats.tx_pause += readl(base + NvRegTxPause);
2835         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2836         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2837         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2838         np->estats.rx_runt += readl(base + NvRegRxRunt);
2839         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2840         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2841         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2842         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2843         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2844         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2845         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2846         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2847         np->estats.rx_bytes += readl(base + NvRegRxCnt);
2848         np->estats.rx_pause += readl(base + NvRegRxPause);
2849         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2850         np->estats.rx_packets =
2851                 np->estats.rx_unicast +
2852                 np->estats.rx_multicast +
2853                 np->estats.rx_broadcast;
2854         np->estats.rx_errors_total =
2855                 np->estats.rx_crc_errors +
2856                 np->estats.rx_over_errors +
2857                 np->estats.rx_frame_error +
2858                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2859                 np->estats.rx_late_collision +
2860                 np->estats.rx_runt +
2861                 np->estats.rx_frame_too_long;
2862
2863         if (!np->in_shutdown)
2864                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2865 }
2866
2867 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2868 {
2869         struct fe_priv *np = netdev_priv(dev);
2870         strcpy(info->driver, "forcedeth");
2871         strcpy(info->version, FORCEDETH_VERSION);
2872         strcpy(info->bus_info, pci_name(np->pci_dev));
2873 }
2874
2875 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2876 {
2877         struct fe_priv *np = netdev_priv(dev);
2878         wolinfo->supported = WAKE_MAGIC;
2879
2880         spin_lock_irq(&np->lock);
2881         if (np->wolenabled)
2882                 wolinfo->wolopts = WAKE_MAGIC;
2883         spin_unlock_irq(&np->lock);
2884 }
2885
2886 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2887 {
2888         struct fe_priv *np = netdev_priv(dev);
2889         u8 __iomem *base = get_hwbase(dev);
2890         u32 flags = 0;
2891
2892         if (wolinfo->wolopts == 0) {
2893                 np->wolenabled = 0;
2894         } else if (wolinfo->wolopts & WAKE_MAGIC) {
2895                 np->wolenabled = 1;
2896                 flags = NVREG_WAKEUPFLAGS_ENABLE;
2897         }
2898         if (netif_running(dev)) {
2899                 spin_lock_irq(&np->lock);
2900                 writel(flags, base + NvRegWakeUpFlags);
2901                 spin_unlock_irq(&np->lock);
2902         }
2903         return 0;
2904 }
2905
2906 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2907 {
2908         struct fe_priv *np = netdev_priv(dev);
2909         int adv;
2910
2911         spin_lock_irq(&np->lock);
2912         ecmd->port = PORT_MII;
2913         if (!netif_running(dev)) {
2914                 /* We do not track link speed / duplex setting if the
2915                  * interface is disabled. Force a link check */
2916                 if (nv_update_linkspeed(dev)) {
2917                         if (!netif_carrier_ok(dev))
2918                                 netif_carrier_on(dev);
2919                 } else {
2920                         if (netif_carrier_ok(dev))
2921                                 netif_carrier_off(dev);
2922                 }
2923         }
2924
2925         if (netif_carrier_ok(dev)) {
2926                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2927                 case NVREG_LINKSPEED_10:
2928                         ecmd->speed = SPEED_10;
2929                         break;
2930                 case NVREG_LINKSPEED_100:
2931                         ecmd->speed = SPEED_100;
2932                         break;
2933                 case NVREG_LINKSPEED_1000:
2934                         ecmd->speed = SPEED_1000;
2935                         break;
2936                 }
2937                 ecmd->duplex = DUPLEX_HALF;
2938                 if (np->duplex)
2939                         ecmd->duplex = DUPLEX_FULL;
2940         } else {
2941                 ecmd->speed = -1;
2942                 ecmd->duplex = -1;
2943         }
2944
2945         ecmd->autoneg = np->autoneg;
2946
2947         ecmd->advertising = ADVERTISED_MII;
2948         if (np->autoneg) {
2949                 ecmd->advertising |= ADVERTISED_Autoneg;
2950                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2951                 if (adv & ADVERTISE_10HALF)
2952                         ecmd->advertising |= ADVERTISED_10baseT_Half;
2953                 if (adv & ADVERTISE_10FULL)
2954                         ecmd->advertising |= ADVERTISED_10baseT_Full;
2955                 if (adv & ADVERTISE_100HALF)
2956                         ecmd->advertising |= ADVERTISED_100baseT_Half;
2957                 if (adv & ADVERTISE_100FULL)
2958                         ecmd->advertising |= ADVERTISED_100baseT_Full;
2959                 if (np->gigabit == PHY_GIGABIT) {
2960                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2961                         if (adv & ADVERTISE_1000FULL)
2962                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2963                 }
2964         }
2965         ecmd->supported = (SUPPORTED_Autoneg |
2966                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2967                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2968                 SUPPORTED_MII);
2969         if (np->gigabit == PHY_GIGABIT)
2970                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2971
2972         ecmd->phy_address = np->phyaddr;
2973         ecmd->transceiver = XCVR_EXTERNAL;
2974
2975         /* ignore maxtxpkt, maxrxpkt for now */
2976         spin_unlock_irq(&np->lock);
2977         return 0;
2978 }
2979
2980 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2981 {
2982         struct fe_priv *np = netdev_priv(dev);
2983
2984         if (ecmd->port != PORT_MII)
2985                 return -EINVAL;
2986         if (ecmd->transceiver != XCVR_EXTERNAL)
2987                 return -EINVAL;
2988         if (ecmd->phy_address != np->phyaddr) {
2989                 /* TODO: support switching between multiple phys. Should be
2990                  * trivial, but not enabled due to lack of test hardware. */
2991                 return -EINVAL;
2992         }
2993         if (ecmd->autoneg == AUTONEG_ENABLE) {
2994                 u32 mask;
2995
2996                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2997                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2998                 if (np->gigabit == PHY_GIGABIT)
2999                         mask |= ADVERTISED_1000baseT_Full;
3000
3001                 if ((ecmd->advertising & mask) == 0)
3002                         return -EINVAL;
3003
3004         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3005                 /* Note: autonegotiation disable, speed 1000 intentionally
3006                  * forbidden - noone should need that. */
3007
3008                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3009                         return -EINVAL;
3010                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3011                         return -EINVAL;
3012         } else {
3013                 return -EINVAL;
3014         }
3015
3016         netif_carrier_off(dev);
3017         if (netif_running(dev)) {
3018                 nv_disable_irq(dev);
3019                 netif_tx_lock_bh(dev);
3020                 spin_lock(&np->lock);
3021                 /* stop engines */
3022                 nv_stop_rx(dev);
3023                 nv_stop_tx(dev);
3024                 spin_unlock(&np->lock);
3025                 netif_tx_unlock_bh(dev);
3026         }
3027
3028         if (ecmd->autoneg == AUTONEG_ENABLE) {
3029                 int adv, bmcr;
3030
3031                 np->autoneg = 1;
3032
3033                 /* advertise only what has been requested */
3034                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3035                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3036                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3037                         adv |= ADVERTISE_10HALF;
3038                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3039                         adv |= ADVERTISE_10FULL;
3040                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3041                         adv |= ADVERTISE_100HALF;
3042                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3043                         adv |= ADVERTISE_100FULL;
3044                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3045                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3046                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3047                         adv |=  ADVERTISE_PAUSE_ASYM;
3048                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3049
3050                 if (np->gigabit == PHY_GIGABIT) {
3051                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3052                         adv &= ~ADVERTISE_1000FULL;
3053                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3054                                 adv |= ADVERTISE_1000FULL;
3055                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3056                 }
3057
3058                 if (netif_running(dev))
3059                         printk(KERN_INFO "%s: link down.\n", dev->name);
3060                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3061                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3062                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3063
3064         } else {
3065                 int adv, bmcr;
3066
3067                 np->autoneg = 0;
3068
3069                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3070                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3071                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3072                         adv |= ADVERTISE_10HALF;
3073                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3074                         adv |= ADVERTISE_10FULL;
3075                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3076                         adv |= ADVERTISE_100HALF;
3077                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3078                         adv |= ADVERTISE_100FULL;
3079                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3080                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3081                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3082                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3083                 }
3084                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3085                         adv |=  ADVERTISE_PAUSE_ASYM;
3086                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3087                 }
3088                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3089                 np->fixed_mode = adv;
3090
3091                 if (np->gigabit == PHY_GIGABIT) {
3092                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3093                         adv &= ~ADVERTISE_1000FULL;
3094                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3095                 }
3096
3097                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3098                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3099                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3100                         bmcr |= BMCR_FULLDPLX;
3101                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3102                         bmcr |= BMCR_SPEED100;
3103                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3104                 if (np->phy_oui == PHY_OUI_MARVELL) {
3105                         /* reset the phy */
3106                         if (phy_reset(dev)) {
3107                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3108                                 return -EINVAL;
3109                         }
3110                 } else if (netif_running(dev)) {
3111                         /* Wait a bit and then reconfigure the nic. */
3112                         udelay(10);
3113                         nv_linkchange(dev);
3114                 }
3115         }
3116
3117         if (netif_running(dev)) {
3118                 nv_start_rx(dev);
3119                 nv_start_tx(dev);
3120                 nv_enable_irq(dev);
3121         }
3122
3123         return 0;
3124 }
3125
3126 #define FORCEDETH_REGS_VER      1
3127
3128 static int nv_get_regs_len(struct net_device *dev)
3129 {
3130         struct fe_priv *np = netdev_priv(dev);
3131         return np->register_size;
3132 }
3133
3134 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3135 {
3136         struct fe_priv *np = netdev_priv(dev);
3137         u8 __iomem *base = get_hwbase(dev);
3138         u32 *rbuf = buf;
3139         int i;
3140
3141         regs->version = FORCEDETH_REGS_VER;
3142         spin_lock_irq(&np->lock);
3143         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3144                 rbuf[i] = readl(base + i*sizeof(u32));
3145         spin_unlock_irq(&np->lock);
3146 }
3147
3148 static int nv_nway_reset(struct net_device *dev)
3149 {
3150         struct fe_priv *np = netdev_priv(dev);
3151         int ret;
3152
3153         if (np->autoneg) {
3154                 int bmcr;
3155
3156                 netif_carrier_off(dev);
3157                 if (netif_running(dev)) {
3158                         nv_disable_irq(dev);
3159                         netif_tx_lock_bh(dev);
3160                         spin_lock(&np->lock);
3161                         /* stop engines */
3162                         nv_stop_rx(dev);
3163                         nv_stop_tx(dev);
3164                         spin_unlock(&np->lock);
3165                         netif_tx_unlock_bh(dev);
3166                         printk(KERN_INFO "%s: link down.\n", dev->name);
3167                 }
3168
3169                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3170                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3171                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3172
3173                 if (netif_running(dev)) {
3174                         nv_start_rx(dev);
3175                         nv_start_tx(dev);
3176                         nv_enable_irq(dev);
3177                 }
3178                 ret = 0;
3179         } else {
3180                 ret = -EINVAL;
3181         }
3182
3183         return ret;
3184 }
3185
3186 static int nv_set_tso(struct net_device *dev, u32 value)
3187 {
3188         struct fe_priv *np = netdev_priv(dev);
3189
3190         if ((np->driver_data & DEV_HAS_CHECKSUM))
3191                 return ethtool_op_set_tso(dev, value);
3192         else
3193                 return -EOPNOTSUPP;
3194 }
3195
3196 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3197 {
3198         struct fe_priv *np = netdev_priv(dev);
3199
3200         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3201         ring->rx_mini_max_pending = 0;
3202         ring->rx_jumbo_max_pending = 0;
3203         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3204
3205         ring->rx_pending = np->rx_ring_size;
3206         ring->rx_mini_pending = 0;
3207         ring->rx_jumbo_pending = 0;
3208         ring->tx_pending = np->tx_ring_size;
3209 }
3210
3211 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3212 {
3213         struct fe_priv *np = netdev_priv(dev);
3214         u8 __iomem *base = get_hwbase(dev);
3215         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3216         dma_addr_t ring_addr;
3217
3218         if (ring->rx_pending < RX_RING_MIN ||
3219             ring->tx_pending < TX_RING_MIN ||
3220             ring->rx_mini_pending != 0 ||
3221             ring->rx_jumbo_pending != 0 ||
3222             (np->desc_ver == DESC_VER_1 &&
3223              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3224               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3225             (np->desc_ver != DESC_VER_1 &&
3226              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3227               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3228                 return -EINVAL;
3229         }
3230
3231         /* allocate new rings */
3232         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3233                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3234                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3235                                             &ring_addr);
3236         } else {
3237                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3238                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3239                                             &ring_addr);
3240         }
3241         rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3242         rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3243         tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3244         tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3245         tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3246         if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3247                 /* fall back to old rings */
3248                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3249                         if(rxtx_ring)
3250                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3251                                                     rxtx_ring, ring_addr);
3252                 } else {
3253                         if (rxtx_ring)
3254                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3255                                                     rxtx_ring, ring_addr);
3256                 }
3257                 if (rx_skbuff)
3258                         kfree(rx_skbuff);
3259                 if (rx_dma)
3260                         kfree(rx_dma);
3261                 if (tx_skbuff)
3262                         kfree(tx_skbuff);
3263                 if (tx_dma)
3264                         kfree(tx_dma);
3265                 if (tx_dma_len)
3266                         kfree(tx_dma_len);
3267                 goto exit;
3268         }
3269
3270         if (netif_running(dev)) {
3271                 nv_disable_irq(dev);
3272                 netif_tx_lock_bh(dev);
3273                 spin_lock(&np->lock);
3274                 /* stop engines */
3275                 nv_stop_rx(dev);
3276                 nv_stop_tx(dev);
3277                 nv_txrx_reset(dev);
3278                 /* drain queues */
3279                 nv_drain_rx(dev);
3280                 nv_drain_tx(dev);
3281                 /* delete queues */
3282                 free_rings(dev);
3283         }
3284
3285         /* set new values */
3286         np->rx_ring_size = ring->rx_pending;
3287         np->tx_ring_size = ring->tx_pending;
3288         np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3289         np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3290         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3291                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3292                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3293         } else {
3294                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3295                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3296         }
3297         np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3298         np->rx_dma = (dma_addr_t*)rx_dma;
3299         np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3300         np->tx_dma = (dma_addr_t*)tx_dma;
3301         np->tx_dma_len = (unsigned int*)tx_dma_len;
3302         np->ring_addr = ring_addr;
3303
3304         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3305         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3306         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3307         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3308         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3309
3310         if (netif_running(dev)) {
3311                 /* reinit driver view of the queues */
3312                 set_bufsize(dev);
3313                 if (nv_init_ring(dev)) {
3314                         if (!np->in_shutdown)
3315                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3316                 }
3317
3318                 /* reinit nic view of the queues */
3319                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3320                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3321                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3322                         base + NvRegRingSizes);
3323                 pci_push(base);
3324                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3325                 pci_push(base);
3326
3327                 /* restart engines */
3328                 nv_start_rx(dev);
3329                 nv_start_tx(dev);
3330                 spin_unlock(&np->lock);
3331                 netif_tx_unlock_bh(dev);
3332                 nv_enable_irq(dev);
3333         }
3334         return 0;
3335 exit:
3336         return -ENOMEM;
3337 }
3338
3339 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3340 {
3341         struct fe_priv *np = netdev_priv(dev);
3342
3343         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3344         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3345         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3346 }
3347
3348 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3349 {
3350         struct fe_priv *np = netdev_priv(dev);
3351         int adv, bmcr;
3352
3353         if ((!np->autoneg && np->duplex == 0) ||
3354             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3355                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3356                        dev->name);
3357                 return -EINVAL;
3358         }
3359         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3360                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3361                 return -EINVAL;
3362         }
3363
3364         netif_carrier_off(dev);
3365         if (netif_running(dev)) {
3366                 nv_disable_irq(dev);
3367                 netif_tx_lock_bh(dev);
3368                 spin_lock(&np->lock);
3369                 /* stop engines */
3370                 nv_stop_rx(dev);
3371                 nv_stop_tx(dev);
3372                 spin_unlock(&np->lock);
3373                 netif_tx_unlock_bh(dev);
3374         }
3375
3376         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3377         if (pause->rx_pause)
3378                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3379         if (pause->tx_pause)
3380                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3381
3382         if (np->autoneg && pause->autoneg) {
3383                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3384
3385                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3386                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3387                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3388                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3389                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3390                         adv |=  ADVERTISE_PAUSE_ASYM;
3391                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3392
3393                 if (netif_running(dev))
3394                         printk(KERN_INFO "%s: link down.\n", dev->name);
3395                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3396                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3397                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3398         } else {
3399                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3400                 if (pause->rx_pause)
3401                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3402                 if (pause->tx_pause)
3403                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3404
3405                 if (!netif_running(dev))
3406                         nv_update_linkspeed(dev);
3407                 else
3408                         nv_update_pause(dev, np->pause_flags);
3409         }
3410
3411         if (netif_running(dev)) {
3412                 nv_start_rx(dev);
3413                 nv_start_tx(dev);
3414                 nv_enable_irq(dev);
3415         }
3416         return 0;
3417 }
3418
3419 static u32 nv_get_rx_csum(struct net_device *dev)
3420 {
3421         struct fe_priv *np = netdev_priv(dev);
3422         return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3423 }
3424
3425 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3426 {
3427         struct fe_priv *np = netdev_priv(dev);
3428         u8 __iomem *base = get_hwbase(dev);
3429         int retcode = 0;
3430
3431         if (np->driver_data & DEV_HAS_CHECKSUM) {
3432
3433                 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3434                     (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3435                         /* already set or unset */
3436                         return 0;
3437                 }
3438
3439                 if (data) {
3440                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3441                 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3442                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3443                 } else {
3444                         printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3445                         return -EINVAL;
3446                 }
3447
3448                 if (netif_running(dev)) {
3449                         spin_lock_irq(&np->lock);
3450                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3451                         spin_unlock_irq(&np->lock);
3452                 }
3453         } else {
3454                 return -EINVAL;
3455         }
3456
3457         return retcode;
3458 }
3459
3460 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3461 {
3462         struct fe_priv *np = netdev_priv(dev);
3463
3464         if (np->driver_data & DEV_HAS_CHECKSUM)
3465                 return ethtool_op_set_tx_hw_csum(dev, data);
3466         else
3467                 return -EOPNOTSUPP;
3468 }
3469
3470 static int nv_set_sg(struct net_device *dev, u32 data)
3471 {
3472         struct fe_priv *np = netdev_priv(dev);
3473
3474         if (np->driver_data & DEV_HAS_CHECKSUM)
3475                 return ethtool_op_set_sg(dev, data);
3476         else
3477                 return -EOPNOTSUPP;
3478 }
3479
3480 static int nv_get_stats_count(struct net_device *dev)
3481 {
3482         struct fe_priv *np = netdev_priv(dev);
3483
3484         if (np->driver_data & DEV_HAS_STATISTICS)
3485                 return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3486         else
3487                 return 0;
3488 }
3489
3490 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3491 {
3492         struct fe_priv *np = netdev_priv(dev);
3493
3494         /* update stats */
3495         nv_do_stats_poll((unsigned long)dev);
3496
3497         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3498 }
3499
3500 static int nv_self_test_count(struct net_device *dev)
3501 {
3502         struct fe_priv *np = netdev_priv(dev);
3503
3504         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3505                 return NV_TEST_COUNT_EXTENDED;
3506         else
3507                 return NV_TEST_COUNT_BASE;
3508 }
3509
3510 static int nv_link_test(struct net_device *dev)
3511 {
3512         struct fe_priv *np = netdev_priv(dev);
3513         int mii_status;
3514
3515         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3516         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3517
3518         /* check phy link status */
3519         if (!(mii_status & BMSR_LSTATUS))
3520                 return 0;
3521         else
3522                 return 1;
3523 }
3524
3525 static int nv_register_test(struct net_device *dev)
3526 {
3527         u8 __iomem *base = get_hwbase(dev);
3528         int i = 0;
3529         u32 orig_read, new_read;
3530
3531         do {
3532                 orig_read = readl(base + nv_registers_test[i].reg);
3533
3534                 /* xor with mask to toggle bits */
3535                 orig_read ^= nv_registers_test[i].mask;
3536
3537                 writel(orig_read, base + nv_registers_test[i].reg);
3538
3539                 new_read = readl(base + nv_registers_test[i].reg);
3540
3541                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3542                         return 0;
3543
3544                 /* restore original value */
3545                 orig_read ^= nv_registers_test[i].mask;
3546                 writel(orig_read, base + nv_registers_test[i].reg);
3547
3548         } while (nv_registers_test[++i].reg != 0);
3549
3550         return 1;
3551 }
3552
3553 static int nv_interrupt_test(struct net_device *dev)
3554 {
3555         struct fe_priv *np = netdev_priv(dev);
3556         u8 __iomem *base = get_hwbase(dev);
3557         int ret = 1;
3558         int testcnt;
3559         u32 save_msi_flags, save_poll_interval = 0;
3560
3561         if (netif_running(dev)) {
3562                 /* free current irq */
3563                 nv_free_irq(dev);
3564                 save_poll_interval = readl(base+NvRegPollingInterval);
3565         }
3566
3567         /* flag to test interrupt handler */
3568         np->intr_test = 0;
3569
3570         /* setup test irq */
3571         save_msi_flags = np->msi_flags;
3572         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3573         np->msi_flags |= 0x001; /* setup 1 vector */
3574         if (nv_request_irq(dev, 1))
3575                 return 0;
3576
3577         /* setup timer interrupt */
3578         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3579         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3580
3581         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3582
3583         /* wait for at least one interrupt */
3584         msleep(100);
3585
3586         spin_lock_irq(&np->lock);
3587
3588         /* flag should be set within ISR */
3589         testcnt = np->intr_test;
3590         if (!testcnt)
3591                 ret = 2;
3592
3593         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3594         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3595                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3596         else
3597                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3598
3599         spin_unlock_irq(&np->lock);
3600
3601         nv_free_irq(dev);
3602
3603         np->msi_flags = save_msi_flags;
3604
3605         if (netif_running(dev)) {
3606                 writel(save_poll_interval, base + NvRegPollingInterval);
3607                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3608                 /* restore original irq */
3609                 if (nv_request_irq(dev, 0))
3610                         return 0;
3611         }
3612
3613         return ret;
3614 }
3615
3616 static int nv_loopback_test(struct net_device *dev)
3617 {
3618         struct fe_priv *np = netdev_priv(dev);
3619         u8 __iomem *base = get_hwbase(dev);
3620         struct sk_buff *tx_skb, *rx_skb;
3621         dma_addr_t test_dma_addr;
3622         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3623         u32 Flags;
3624         int len, i, pkt_len;
3625         u8 *pkt_data;
3626         u32 filter_flags = 0;
3627         u32 misc1_flags = 0;
3628         int ret = 1;
3629
3630         if (netif_running(dev)) {
3631                 nv_disable_irq(dev);
3632                 filter_flags = readl(base + NvRegPacketFilterFlags);
3633                 misc1_flags = readl(base + NvRegMisc1);
3634         } else {
3635                 nv_txrx_reset(dev);
3636         }
3637
3638         /* reinit driver view of the rx queue */
3639         set_bufsize(dev);
3640         nv_init_ring(dev);
3641
3642         /* setup hardware for loopback */
3643         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3644         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3645
3646         /* reinit nic view of the rx queue */
3647         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3648         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3649         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3650                 base + NvRegRingSizes);
3651         pci_push(base);
3652
3653         /* restart rx engine */
3654         nv_start_rx(dev);
3655         nv_start_tx(dev);
3656
3657         /* setup packet for tx */
3658         pkt_len = ETH_DATA_LEN;
3659         tx_skb = dev_alloc_skb(pkt_len);
3660         pkt_data = skb_put(tx_skb, pkt_len);
3661         for (i = 0; i < pkt_len; i++)
3662                 pkt_data[i] = (u8)(i & 0xff);
3663         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3664                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3665
3666         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3667                 np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr);
3668                 np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3669         } else {
3670                 np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32;
3671                 np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3672                 np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3673         }
3674         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3675         pci_push(get_hwbase(dev));
3676
3677         msleep(500);
3678
3679         /* check for rx of the packet */
3680         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3681                 Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
3682                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3683
3684         } else {
3685                 Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
3686                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3687         }
3688
3689         if (Flags & NV_RX_AVAIL) {
3690                 ret = 0;
3691         } else if (np->desc_ver == DESC_VER_1) {
3692                 if (Flags & NV_RX_ERROR)
3693                         ret = 0;
3694         } else {
3695                 if (Flags & NV_RX2_ERROR) {
3696                         ret = 0;
3697                 }
3698         }
3699
3700         if (ret) {
3701                 if (len != pkt_len) {
3702                         ret = 0;
3703                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3704                                 dev->name, len, pkt_len);
3705                 } else {
3706                         rx_skb = np->rx_skbuff[0];
3707                         for (i = 0; i < pkt_len; i++) {
3708                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3709                                         ret = 0;
3710                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3711                                                 dev->name, i);
3712                                         break;
3713                                 }
3714                         }
3715                 }
3716         } else {
3717                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3718         }
3719
3720         pci_unmap_page(np->pci_dev, test_dma_addr,
3721                        tx_skb->end-tx_skb->data,
3722                        PCI_DMA_TODEVICE);
3723         dev_kfree_skb_any(tx_skb);
3724
3725         /* stop engines */
3726         nv_stop_rx(dev);
3727         nv_stop_tx(dev);
3728         nv_txrx_reset(dev);
3729         /* drain rx queue */
3730         nv_drain_rx(dev);
3731         nv_drain_tx(dev);
3732
3733         if (netif_running(dev)) {
3734                 writel(misc1_flags, base + NvRegMisc1);
3735                 writel(filter_flags, base + NvRegPacketFilterFlags);
3736                 nv_enable_irq(dev);
3737         }
3738
3739         return ret;
3740 }
3741
3742 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3743 {
3744         struct fe_priv *np = netdev_priv(dev);
3745         u8 __iomem *base = get_hwbase(dev);
3746         int result;
3747         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3748
3749         if (!nv_link_test(dev)) {
3750                 test->flags |= ETH_TEST_FL_FAILED;
3751                 buffer[0] = 1;
3752         }
3753
3754         if (test->flags & ETH_TEST_FL_OFFLINE) {
3755                 if (netif_running(dev)) {
3756                         netif_stop_queue(dev);
3757                         netif_tx_lock_bh(dev);
3758                         spin_lock_irq(&np->lock);
3759                         nv_disable_hw_interrupts(dev, np->irqmask);
3760                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3761                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3762                         } else {
3763                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3764                         }
3765                         /* stop engines */
3766                         nv_stop_rx(dev);
3767                         nv_stop_tx(dev);
3768                         nv_txrx_reset(dev);
3769                         /* drain rx queue */
3770                         nv_drain_rx(dev);
3771                         nv_drain_tx(dev);
3772                         spin_unlock_irq(&np->lock);
3773                         netif_tx_unlock_bh(dev);
3774                 }
3775
3776                 if (!nv_register_test(dev)) {
3777                         test->flags |= ETH_TEST_FL_FAILED;
3778                         buffer[1] = 1;
3779                 }
3780
3781                 result = nv_interrupt_test(dev);
3782                 if (result != 1) {
3783                         test->flags |= ETH_TEST_FL_FAILED;
3784                         buffer[2] = 1;
3785                 }
3786                 if (result == 0) {
3787                         /* bail out */
3788                         return;
3789                 }
3790
3791                 if (!nv_loopback_test(dev)) {
3792                         test->flags |= ETH_TEST_FL_FAILED;
3793                         buffer[3] = 1;
3794                 }
3795
3796                 if (netif_running(dev)) {
3797                         /* reinit driver view of the rx queue */
3798                         set_bufsize(dev);
3799                         if (nv_init_ring(dev)) {
3800                                 if (!np->in_shutdown)
3801                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3802                         }
3803                         /* reinit nic view of the rx queue */
3804                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3805                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3806                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3807                                 base + NvRegRingSizes);
3808                         pci_push(base);
3809                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3810                         pci_push(base);
3811                         /* restart rx engine */
3812                         nv_start_rx(dev);
3813                         nv_start_tx(dev);
3814                         netif_start_queue(dev);
3815                         nv_enable_hw_interrupts(dev, np->irqmask);
3816                 }
3817         }
3818 }
3819
3820 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3821 {
3822         switch (stringset) {
3823         case ETH_SS_STATS:
3824                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3825                 break;
3826         case ETH_SS_TEST:
3827                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3828                 break;
3829         }
3830 }
3831
3832 static struct ethtool_ops ops = {
3833         .get_drvinfo = nv_get_drvinfo,
3834         .get_link = ethtool_op_get_link,
3835         .get_wol = nv_get_wol,
3836         .set_wol = nv_set_wol,
3837         .get_settings = nv_get_settings,
3838         .set_settings = nv_set_settings,
3839         .get_regs_len = nv_get_regs_len,
3840         .get_regs = nv_get_regs,
3841         .nway_reset = nv_nway_reset,
3842         .get_perm_addr = ethtool_op_get_perm_addr,
3843         .get_tso = ethtool_op_get_tso,
3844         .set_tso = nv_set_tso,
3845         .get_ringparam = nv_get_ringparam,
3846         .set_ringparam = nv_set_ringparam,
3847         .get_pauseparam = nv_get_pauseparam,
3848         .set_pauseparam = nv_set_pauseparam,
3849         .get_rx_csum = nv_get_rx_csum,
3850         .set_rx_csum = nv_set_rx_csum,
3851         .get_tx_csum = ethtool_op_get_tx_csum,
3852         .set_tx_csum = nv_set_tx_csum,
3853         .get_sg = ethtool_op_get_sg,
3854         .set_sg = nv_set_sg,
3855         .get_strings = nv_get_strings,
3856         .get_stats_count = nv_get_stats_count,
3857         .get_ethtool_stats = nv_get_ethtool_stats,
3858         .self_test_count = nv_self_test_count,
3859         .self_test = nv_self_test,
3860 };
3861
3862 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3863 {
3864         struct fe_priv *np = get_nvpriv(dev);
3865
3866         spin_lock_irq(&np->lock);
3867
3868         /* save vlan group */
3869         np->vlangrp = grp;
3870
3871         if (grp) {
3872                 /* enable vlan on MAC */
3873                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3874         } else {
3875                 /* disable vlan on MAC */
3876                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3877                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3878         }
3879
3880         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3881
3882         spin_unlock_irq(&np->lock);
3883 };
3884
3885 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3886 {
3887         /* nothing to do */
3888 };
3889
3890 static int nv_open(struct net_device *dev)
3891 {
3892         struct fe_priv *np = netdev_priv(dev);
3893         u8 __iomem *base = get_hwbase(dev);
3894         int ret = 1;
3895         int oom, i;
3896
3897         dprintk(KERN_DEBUG "nv_open: begin\n");
3898
3899         /* 1) erase previous misconfiguration */
3900         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3901                 nv_mac_reset(dev);
3902         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3903         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3904         writel(0, base + NvRegMulticastAddrB);
3905         writel(0, base + NvRegMulticastMaskA);
3906         writel(0, base + NvRegMulticastMaskB);
3907         writel(0, base + NvRegPacketFilterFlags);
3908
3909         writel(0, base + NvRegTransmitterControl);
3910         writel(0, base + NvRegReceiverControl);
3911
3912         writel(0, base + NvRegAdapterControl);
3913
3914         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3915                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3916
3917         /* 2) initialize descriptor rings */
3918         set_bufsize(dev);
3919         oom = nv_init_ring(dev);
3920
3921         writel(0, base + NvRegLinkSpeed);
3922         writel(0, base + NvRegUnknownTransmitterReg);
3923         nv_txrx_reset(dev);
3924         writel(0, base + NvRegUnknownSetupReg6);
3925
3926         np->in_shutdown = 0;
3927
3928         /* 3) set mac address */
3929         nv_copy_mac_to_hw(dev);
3930
3931         /* 4) give hw rings */
3932         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3933         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3934                 base + NvRegRingSizes);
3935
3936         /* 5) continue setup */
3937         writel(np->linkspeed, base + NvRegLinkSpeed);
3938         if (np->desc_ver == DESC_VER_1)
3939                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
3940         else
3941                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
3942         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3943         writel(np->vlanctl_bits, base + NvRegVlanControl);
3944         pci_push(base);
3945         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3946         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3947                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3948                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3949
3950         writel(0, base + NvRegUnknownSetupReg4);
3951         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3952         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3953
3954         /* 6) continue setup */
3955         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3956         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3957         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3958         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3959
3960         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3961         get_random_bytes(&i, sizeof(i));
3962         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3963         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
3964         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
3965         if (poll_interval == -1) {
3966                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3967                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3968                 else
3969                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3970         }
3971         else
3972                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3973         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3974         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3975                         base + NvRegAdapterControl);
3976         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3977         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3978         if (np->wolenabled)
3979                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3980
3981         i = readl(base + NvRegPowerState);
3982         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3983                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3984
3985         pci_push(base);
3986         udelay(10);
3987         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3988
3989         nv_disable_hw_interrupts(dev, np->irqmask);
3990         pci_push(base);
3991         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3992         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3993         pci_push(base);
3994
3995         if (nv_request_irq(dev, 0)) {
3996                 goto out_drain;
3997         }
3998
3999         /* ask for interrupts */
4000         nv_enable_hw_interrupts(dev, np->irqmask);
4001
4002         spin_lock_irq(&np->lock);
4003         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4004         writel(0, base + NvRegMulticastAddrB);
4005         writel(0, base + NvRegMulticastMaskA);
4006         writel(0, base + NvRegMulticastMaskB);
4007         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4008         /* One manual link speed update: Interrupts are enabled, future link
4009          * speed changes cause interrupts and are handled by nv_link_irq().
4010          */
4011         {
4012                 u32 miistat;
4013                 miistat = readl(base + NvRegMIIStatus);
4014                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4015                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4016         }
4017         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4018          * to init hw */
4019         np->linkspeed = 0;
4020         ret = nv_update_linkspeed(dev);
4021         nv_start_rx(dev);
4022         nv_start_tx(dev);
4023         netif_start_queue(dev);
4024         if (ret) {
4025                 netif_carrier_on(dev);
4026         } else {
4027                 printk("%s: no link during initialization.\n", dev->name);
4028                 netif_carrier_off(dev);
4029         }
4030         if (oom)
4031                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4032
4033         /* start statistics timer */
4034         if (np->driver_data & DEV_HAS_STATISTICS)
4035                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4036
4037         spin_unlock_irq(&np->lock);
4038
4039         return 0;
4040 out_drain:
4041         drain_ring(dev);
4042         return ret;
4043 }
4044
4045 static int nv_close(struct net_device *dev)
4046 {
4047         struct fe_priv *np = netdev_priv(dev);
4048         u8 __iomem *base;
4049
4050         spin_lock_irq(&np->lock);
4051         np->in_shutdown = 1;
4052         spin_unlock_irq(&np->lock);
4053         synchronize_irq(dev->irq);
4054
4055         del_timer_sync(&np->oom_kick);
4056         del_timer_sync(&np->nic_poll);
4057         del_timer_sync(&np->stats_poll);
4058
4059         netif_stop_queue(dev);
4060         spin_lock_irq(&np->lock);
4061         nv_stop_tx(dev);
4062         nv_stop_rx(dev);
4063         nv_txrx_reset(dev);
4064
4065         /* disable interrupts on the nic or we will lock up */
4066         base = get_hwbase(dev);
4067         nv_disable_hw_interrupts(dev, np->irqmask);
4068         pci_push(base);
4069         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4070
4071         spin_unlock_irq(&np->lock);
4072
4073         nv_free_irq(dev);
4074
4075         drain_ring(dev);
4076
4077         if (np->wolenabled)
4078                 nv_start_rx(dev);
4079
4080         /* special op: write back the misordered MAC address - otherwise
4081          * the next nv_probe would see a wrong address.
4082          */
4083         writel(np->orig_mac[0], base + NvRegMacAddrA);
4084         writel(np->orig_mac[1], base + NvRegMacAddrB);
4085
4086         /* FIXME: power down nic */
4087
4088         return 0;
4089 }
4090
4091 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4092 {
4093         struct net_device *dev;
4094         struct fe_priv *np;
4095         unsigned long addr;
4096         u8 __iomem *base;
4097         int err, i;
4098         u32 powerstate;
4099
4100         dev = alloc_etherdev(sizeof(struct fe_priv));
4101         err = -ENOMEM;
4102         if (!dev)
4103                 goto out;
4104
4105         np = netdev_priv(dev);
4106         np->pci_dev = pci_dev;
4107         spin_lock_init(&np->lock);
4108         SET_MODULE_OWNER(dev);
4109         SET_NETDEV_DEV(dev, &pci_dev->dev);
4110
4111         init_timer(&np->oom_kick);
4112         np->oom_kick.data = (unsigned long) dev;
4113         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4114         init_timer(&np->nic_poll);
4115         np->nic_poll.data = (unsigned long) dev;
4116         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4117         init_timer(&np->stats_poll);
4118         np->stats_poll.data = (unsigned long) dev;
4119         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4120
4121         err = pci_enable_device(pci_dev);
4122         if (err) {
4123                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4124                                 err, pci_name(pci_dev));
4125                 goto out_free;
4126         }
4127
4128         pci_set_master(pci_dev);
4129
4130         err = pci_request_regions(pci_dev, DRV_NAME);
4131         if (err < 0)
4132                 goto out_disable;
4133
4134         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4135                 np->register_size = NV_PCI_REGSZ_VER2;
4136         else
4137                 np->register_size = NV_PCI_REGSZ_VER1;
4138
4139         err = -EINVAL;
4140         addr = 0;
4141         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4142                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4143                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4144                                 pci_resource_len(pci_dev, i),
4145                                 pci_resource_flags(pci_dev, i));
4146                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4147                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4148                         addr = pci_resource_start(pci_dev, i);
4149                         break;
4150                 }
4151         }
4152         if (i == DEVICE_COUNT_RESOURCE) {
4153                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4154                                         pci_name(pci_dev));
4155                 goto out_relreg;
4156         }
4157
4158         /* copy of driver data */
4159         np->driver_data = id->driver_data;
4160
4161         /* handle different descriptor versions */
4162         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4163                 /* packet format 3: supports 40-bit addressing */
4164                 np->desc_ver = DESC_VER_3;
4165                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4166                 if (dma_64bit) {
4167                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4168                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4169                                        pci_name(pci_dev));
4170                         } else {
4171                                 dev->features |= NETIF_F_HIGHDMA;
4172                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4173                         }
4174                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4175                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4176                                        pci_name(pci_dev));
4177                         }
4178                 }
4179         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4180                 /* packet format 2: supports jumbo frames */
4181                 np->desc_ver = DESC_VER_2;
4182                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4183         } else {
4184                 /* original packet format */
4185                 np->desc_ver = DESC_VER_1;
4186                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4187         }
4188
4189         np->pkt_limit = NV_PKTLIMIT_1;
4190         if (id->driver_data & DEV_HAS_LARGEDESC)
4191                 np->pkt_limit = NV_PKTLIMIT_2;
4192
4193         if (id->driver_data & DEV_HAS_CHECKSUM) {
4194                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4195                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4196 #ifdef NETIF_F_TSO
4197                 dev->features |= NETIF_F_TSO;
4198 #endif
4199         }
4200
4201         np->vlanctl_bits = 0;
4202         if (id->driver_data & DEV_HAS_VLAN) {
4203                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4204                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4205                 dev->vlan_rx_register = nv_vlan_rx_register;
4206                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4207         }
4208
4209         np->msi_flags = 0;
4210         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4211                 np->msi_flags |= NV_MSI_CAPABLE;
4212         }
4213         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4214                 np->msi_flags |= NV_MSI_X_CAPABLE;
4215         }
4216
4217         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4218         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4219                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4220         }
4221
4222
4223         err = -ENOMEM;
4224         np->base = ioremap(addr, np->register_size);
4225         if (!np->base)
4226                 goto out_relreg;
4227         dev->base_addr = (unsigned long)np->base;
4228
4229         dev->irq = pci_dev->irq;
4230
4231         np->rx_ring_size = RX_RING_DEFAULT;
4232         np->tx_ring_size = TX_RING_DEFAULT;
4233         np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4234         np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4235
4236         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4237                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4238                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4239                                         &np->ring_addr);
4240                 if (!np->rx_ring.orig)
4241                         goto out_unmap;
4242                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4243         } else {
4244                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4245                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4246                                         &np->ring_addr);
4247                 if (!np->rx_ring.ex)
4248                         goto out_unmap;
4249                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4250         }
4251         np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4252         np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4253         np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4254         np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4255         np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4256         if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4257                 goto out_freering;
4258         memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4259         memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4260         memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4261         memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4262         memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4263
4264         dev->open = nv_open;
4265         dev->stop = nv_close;
4266         dev->hard_start_xmit = nv_start_xmit;
4267         dev->get_stats = nv_get_stats;
4268         dev->change_mtu = nv_change_mtu;
4269         dev->set_mac_address = nv_set_mac_address;
4270         dev->set_multicast_list = nv_set_multicast;
4271 #ifdef CONFIG_NET_POLL_CONTROLLER
4272         dev->poll_controller = nv_poll_controller;
4273 #endif
4274         SET_ETHTOOL_OPS(dev, &ops);
4275         dev->tx_timeout = nv_tx_timeout;
4276         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4277
4278         pci_set_drvdata(pci_dev, dev);
4279
4280         /* read the mac address */
4281         base = get_hwbase(dev);
4282         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4283         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4284
4285         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4286         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4287         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4288         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4289         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4290         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4291         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4292
4293         if (!is_valid_ether_addr(dev->perm_addr)) {
4294                 /*
4295                  * Bad mac address. At least one bios sets the mac address
4296                  * to 01:23:45:67:89:ab
4297                  */
4298                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4299                         pci_name(pci_dev),
4300                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4301                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4302                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4303                 dev->dev_addr[0] = 0x00;
4304                 dev->dev_addr[1] = 0x00;
4305                 dev->dev_addr[2] = 0x6c;
4306                 get_random_bytes(&dev->dev_addr[3], 3);
4307         }
4308
4309         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4310                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4311                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4312
4313         /* disable WOL */
4314         writel(0, base + NvRegWakeUpFlags);
4315         np->wolenabled = 0;
4316
4317         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4318                 u8 revision_id;
4319                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4320
4321                 /* take phy and nic out of low power mode */
4322                 powerstate = readl(base + NvRegPowerState2);
4323                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4324                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4325                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4326                     revision_id >= 0xA3)
4327                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4328                 writel(powerstate, base + NvRegPowerState2);
4329         }
4330
4331         if (np->desc_ver == DESC_VER_1) {
4332                 np->tx_flags = NV_TX_VALID;
4333         } else {
4334                 np->tx_flags = NV_TX2_VALID;
4335         }
4336         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4337                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4338                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4339                         np->msi_flags |= 0x0003;
4340         } else {
4341                 np->irqmask = NVREG_IRQMASK_CPU;
4342                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4343                         np->msi_flags |= 0x0001;
4344         }
4345
4346         if (id->driver_data & DEV_NEED_TIMERIRQ)
4347                 np->irqmask |= NVREG_IRQ_TIMER;
4348         if (id->driver_data & DEV_NEED_LINKTIMER) {
4349                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4350                 np->need_linktimer = 1;
4351                 np->link_timeout = jiffies + LINK_TIMEOUT;
4352         } else {
4353                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4354                 np->need_linktimer = 0;
4355         }
4356
4357         /* find a suitable phy */
4358         for (i = 1; i <= 32; i++) {
4359                 int id1, id2;
4360                 int phyaddr = i & 0x1F;
4361
4362                 spin_lock_irq(&np->lock);
4363                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4364                 spin_unlock_irq(&np->lock);
4365                 if (id1 < 0 || id1 == 0xffff)
4366                         continue;
4367                 spin_lock_irq(&np->lock);
4368                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4369                 spin_unlock_irq(&np->lock);
4370                 if (id2 < 0 || id2 == 0xffff)
4371                         continue;
4372
4373                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4374                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4375                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4376                         pci_name(pci_dev), id1, id2, phyaddr);
4377                 np->phyaddr = phyaddr;
4378                 np->phy_oui = id1 | id2;
4379                 break;
4380         }
4381         if (i == 33) {
4382                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4383                        pci_name(pci_dev));
4384                 goto out_error;
4385         }
4386
4387         /* reset it */
4388         phy_init(dev);
4389
4390         /* set default link speed settings */
4391         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4392         np->duplex = 0;
4393         np->autoneg = 1;
4394
4395         err = register_netdev(dev);
4396         if (err) {
4397                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4398                 goto out_error;
4399         }
4400         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4401                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4402                         pci_name(pci_dev));
4403
4404         return 0;
4405
4406 out_error:
4407         pci_set_drvdata(pci_dev, NULL);
4408 out_freering:
4409         free_rings(dev);
4410 out_unmap:
4411         iounmap(get_hwbase(dev));
4412 out_relreg:
4413         pci_release_regions(pci_dev);
4414 out_disable:
4415         pci_disable_device(pci_dev);
4416 out_free:
4417         free_netdev(dev);
4418 out:
4419         return err;
4420 }
4421
4422 static void __devexit nv_remove(struct pci_dev *pci_dev)
4423 {
4424         struct net_device *dev = pci_get_drvdata(pci_dev);
4425
4426         unregister_netdev(dev);
4427
4428         /* free all structures */
4429         free_rings(dev);
4430         iounmap(get_hwbase(dev));
4431         pci_release_regions(pci_dev);
4432         pci_disable_device(pci_dev);
4433         free_netdev(dev);
4434         pci_set_drvdata(pci_dev, NULL);
4435 }
4436
4437 static struct pci_device_id pci_tbl[] = {
4438         {       /* nForce Ethernet Controller */
4439                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4440                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4441         },
4442         {       /* nForce2 Ethernet Controller */
4443                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4444                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4445         },
4446         {       /* nForce3 Ethernet Controller */
4447                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4448                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4449         },
4450         {       /* nForce3 Ethernet Controller */
4451                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4452                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4453         },
4454         {       /* nForce3 Ethernet Controller */
4455                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4456                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4457         },
4458         {       /* nForce3 Ethernet Controller */
4459                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4460                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4461         },
4462         {       /* nForce3 Ethernet Controller */
4463                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4464                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4465         },
4466         {       /* CK804 Ethernet Controller */
4467                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4468                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4469         },
4470         {       /* CK804 Ethernet Controller */
4471                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4472                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4473         },
4474         {       /* MCP04 Ethernet Controller */
4475                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4476                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4477         },
4478         {       /* MCP04 Ethernet Controller */
4479                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4480                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4481         },
4482         {       /* MCP51 Ethernet Controller */
4483                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4484                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4485         },
4486         {       /* MCP51 Ethernet Controller */
4487                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4488                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4489         },
4490         {       /* MCP55 Ethernet Controller */
4491                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4492                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4493         },
4494         {       /* MCP55 Ethernet Controller */
4495                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4496                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4497         },
4498         {       /* MCP61 Ethernet Controller */
4499                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4500                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4501         },
4502         {       /* MCP61 Ethernet Controller */
4503                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4504                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4505         },
4506         {       /* MCP61 Ethernet Controller */
4507                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4508                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4509         },
4510         {       /* MCP61 Ethernet Controller */
4511                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4512                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4513         },
4514         {       /* MCP65 Ethernet Controller */
4515                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4516                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4517         },
4518         {       /* MCP65 Ethernet Controller */
4519                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4520                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4521         },
4522         {       /* MCP65 Ethernet Controller */
4523                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4524                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4525         },
4526         {       /* MCP65 Ethernet Controller */
4527                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4528                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4529         },
4530         {0,},
4531 };
4532
4533 static struct pci_driver driver = {
4534         .name = "forcedeth",
4535         .id_table = pci_tbl,
4536         .probe = nv_probe,
4537         .remove = __devexit_p(nv_remove),
4538 };
4539
4540
4541 static int __init init_nic(void)
4542 {
4543         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4544         return pci_module_init(&driver);
4545 }
4546
4547 static void __exit exit_nic(void)
4548 {
4549         pci_unregister_driver(&driver);
4550 }
4551
4552 module_param(max_interrupt_work, int, 0);
4553 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4554 module_param(optimization_mode, int, 0);
4555 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4556 module_param(poll_interval, int, 0);
4557 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4558 module_param(msi, int, 0);
4559 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4560 module_param(msix, int, 0);
4561 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4562 module_param(dma_64bit, int, 0);
4563 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4564
4565 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4566 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4567 MODULE_LICENSE("GPL");
4568
4569 MODULE_DEVICE_TABLE(pci, pci_tbl);
4570
4571 module_init(init_nic);
4572 module_exit(exit_nic);