drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x01234567
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(cpsw, priv)                            \
 144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 145                 cpsw->data.active_slave)
 146 #define IRQ_NUM                 2
 147 #define CPSW_MAX_QUEUES         8
 148 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 149
 150 static int debug_level;
 151 module_param(debug_level, int, 0);
 152 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 153
 154 static int ale_ageout = 10;
 155 module_param(ale_ageout, int, 0);
 156 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 157
 158 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 159 module_param(rx_packet_max, int, 0);
 160 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 161
 162 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 163 module_param(descs_pool_size, int, 0444);
 164 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 165
 166 struct cpsw_wr_regs {
 167         u32     id_ver;
 168         u32     soft_reset;
 169         u32     control;
 170         u32     int_control;
 171         u32     rx_thresh_en;
 172         u32     rx_en;
 173         u32     tx_en;
 174         u32     misc_en;
 175         u32     mem_allign1[8];
 176         u32     rx_thresh_stat;
 177         u32     rx_stat;
 178         u32     tx_stat;
 179         u32     misc_stat;
 180         u32     mem_allign2[8];
 181         u32     rx_imax;
 182         u32     tx_imax;
 183
 184 };
 185
 186 struct cpsw_ss_regs {
 187         u32     id_ver;
 188         u32     control;
 189         u32     soft_reset;
 190         u32     stat_port_en;
 191         u32     ptype;
 192         u32     soft_idle;
 193         u32     thru_rate;
 194         u32     gap_thresh;
 195         u32     tx_start_wds;
 196         u32     flow_control;
 197         u32     vlan_ltype;
 198         u32     ts_ltype;
 199         u32     dlr_ltype;
 200 };
 201
 202 /* CPSW_PORT_V1 */
 203 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 204 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 205 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 206 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 207 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 208 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 209 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 210 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 211
 212 /* CPSW_PORT_V2 */
 213 #define CPSW2_CONTROL       0x00 /* Control Register */
 214 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 215 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 216 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 217 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 218 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 219 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 220
 221 /* CPSW_PORT_V1 and V2 */
 222 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 223 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 224 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 225
 226 /* CPSW_PORT_V2 only */
 227 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 235
 236 /* Bit definitions for the CPSW2_CONTROL register */
 237 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 238 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 239 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 240 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 241 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 242 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 243 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 244 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 245 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 246 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 247 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 248 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 249 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 250 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 251 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 252 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 253 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 254
 255 #define CTRL_V2_TS_BITS \
 256         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 257          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 258
 259 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 260 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 261 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 262
 263
 264 #define CTRL_V3_TS_BITS \
 265         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 266          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 267          TS_LTYPE1_EN)
 268
 269 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 270 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 271 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 272
 273 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 274 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 275 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 276 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 277 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 278
 279 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 280 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 281
 282 /* Bit definitions for the CPSW1_TS_CTL register */
 283 #define CPSW_V1_TS_RX_EN                BIT(0)
 284 #define CPSW_V1_TS_TX_EN                BIT(4)
 285 #define CPSW_V1_MSG_TYPE_OFS            16
 286
 287 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 288 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 289
 290 struct cpsw_host_regs {
 291         u32     max_blks;
 292         u32     blk_cnt;
 293         u32     tx_in_ctl;
 294         u32     port_vlan;
 295         u32     tx_pri_map;
 296         u32     cpdma_tx_pri_map;
 297         u32     cpdma_rx_chan_map;
 298 };
 299
 300 struct cpsw_sliver_regs {
 301         u32     id_ver;
 302         u32     mac_control;
 303         u32     mac_status;
 304         u32     soft_reset;
 305         u32     rx_maxlen;
 306         u32     __reserved_0;
 307         u32     rx_pause;
 308         u32     tx_pause;
 309         u32     __reserved_1;
 310         u32     rx_pri_map;
 311 };
 312
 313 struct cpsw_hw_stats {
 314         u32     rxgoodframes;
 315         u32     rxbroadcastframes;
 316         u32     rxmulticastframes;
 317         u32     rxpauseframes;
 318         u32     rxcrcerrors;
 319         u32     rxaligncodeerrors;
 320         u32     rxoversizedframes;
 321         u32     rxjabberframes;
 322         u32     rxundersizedframes;
 323         u32     rxfragments;
 324         u32     __pad_0[2];
 325         u32     rxoctets;
 326         u32     txgoodframes;
 327         u32     txbroadcastframes;
 328         u32     txmulticastframes;
 329         u32     txpauseframes;
 330         u32     txdeferredframes;
 331         u32     txcollisionframes;
 332         u32     txsinglecollframes;
 333         u32     txmultcollframes;
 334         u32     txexcessivecollisions;
 335         u32     txlatecollisions;
 336         u32     txunderrun;
 337         u32     txcarriersenseerrors;
 338         u32     txoctets;
 339         u32     octetframes64;
 340         u32     octetframes65t127;
 341         u32     octetframes128t255;
 342         u32     octetframes256t511;
 343         u32     octetframes512t1023;
 344         u32     octetframes1024tup;
 345         u32     netoctets;
 346         u32     rxsofoverruns;
 347         u32     rxmofoverruns;
 348         u32     rxdmaoverruns;
 349 };
 350
 351 struct cpsw_slave {
 352         void __iomem                    *regs;
 353         struct cpsw_sliver_regs __iomem *sliver;
 354         int                             slave_num;
 355         u32                             mac_control;
 356         struct cpsw_slave_data          *data;
 357         struct phy_device               *phy;
 358         struct net_device               *ndev;
 359         u32                             port_vlan;
 360 };
 361
 362 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 363 {
 364         return __raw_readl(slave->regs + offset);
 365 }
 366
 367 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 368 {
 369         __raw_writel(val, slave->regs + offset);
 370 }
 371
 372 struct cpsw_vector {
 373         struct cpdma_chan *ch;
 374         int budget;
 375 };
 376
 377 struct cpsw_common {
 378         struct device                   *dev;
 379         struct cpsw_platform_data       data;
 380         struct napi_struct              napi_rx;
 381         struct napi_struct              napi_tx;
 382         struct cpsw_ss_regs __iomem     *regs;
 383         struct cpsw_wr_regs __iomem     *wr_regs;
 384         u8 __iomem                      *hw_stats;
 385         struct cpsw_host_regs __iomem   *host_port_regs;
 386         u32                             version;
 387         u32                             coal_intvl;
 388         u32                             bus_freq_mhz;
 389         int                             rx_packet_max;
 390         struct cpsw_slave               *slaves;
 391         struct cpdma_ctlr               *dma;
 392         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 393         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 394         struct cpsw_ale                 *ale;
 395         bool                            quirk_irq;
 396         bool                            rx_irq_disabled;
 397         bool                            tx_irq_disabled;
 398         u32 irqs_table[IRQ_NUM];
 399         struct cpts                     *cpts;
 400         int                             rx_ch_num, tx_ch_num;
 401         int                             speed;
 402         int                             usage_count;
 403 };
 404
 405 struct cpsw_priv {
 406         struct net_device               *ndev;
 407         struct device                   *dev;
 408         u32                             msg_enable;
 409         u8                              mac_addr[ETH_ALEN];
 410         bool                            rx_pause;
 411         bool                            tx_pause;
 412         u32 emac_port;
 413         struct cpsw_common *cpsw;
 414 };
 415
 416 struct cpsw_stats {
 417         char stat_string[ETH_GSTRING_LEN];
 418         int type;
 419         int sizeof_stat;
 420         int stat_offset;
 421 };
 422
 423 enum {
 424         CPSW_STATS,
 425         CPDMA_RX_STATS,
 426         CPDMA_TX_STATS,
 427 };
 428
 429 #define CPSW_STAT(m)            CPSW_STATS,                             \
 430                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 431                                 offsetof(struct cpsw_hw_stats, m)
 432 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 433                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 434                                 offsetof(struct cpdma_chan_stats, m)
 435 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 436                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 437                                 offsetof(struct cpdma_chan_stats, m)
 438
 439 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 440         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 441         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 442         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 443         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 444         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 445         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 446         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 447         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 448         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 449         { "Rx Fragments", CPSW_STAT(rxfragments) },
 450         { "Rx Octets", CPSW_STAT(rxoctets) },
 451         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 452         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 453         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 454         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 455         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 456         { "Collisions", CPSW_STAT(txcollisionframes) },
 457         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 458         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 459         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 460         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 461         { "Tx Underrun", CPSW_STAT(txunderrun) },
 462         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 463         { "Tx Octets", CPSW_STAT(txoctets) },
 464         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 465         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 466         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 467         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 468         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 469         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 470         { "Net Octets", CPSW_STAT(netoctets) },
 471         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 472         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 473         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 474 };
 475
 476 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 477         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 478         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 479         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 480         { "misqueued", CPDMA_RX_STAT(misqueued) },
 481         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 482         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 483         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 484         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 485         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 486         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 487         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 488         { "requeue", CPDMA_RX_STAT(requeue) },
 489         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 490 };
 491
 492 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 493 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 494
 495 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 496 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 497 #define for_each_slave(priv, func, arg...)                              \
 498         do {                                                            \
 499                 struct cpsw_slave *slave;                               \
 500                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 501                 int n;                                                  \
 502                 if (cpsw->data.dual_emac)                               \
 503                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 504                 else                                                    \
 505                         for (n = cpsw->data.slaves,                     \
 506                                         slave = cpsw->slaves;           \
 507                                         n; n--)                         \
 508                                 (func)(slave++, ##arg);                 \
 509         } while (0)
 510
 511 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 512         do {                                                            \
 513                 if (!cpsw->data.dual_emac)                              \
 514                         break;                                          \
 515                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 516                         ndev = cpsw->slaves[0].ndev;                    \
 517                         skb->dev = ndev;                                \
 518                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 519                         ndev = cpsw->slaves[1].ndev;                    \
 520                         skb->dev = ndev;                                \
 521                 }                                                       \
 522         } while (0)
 523 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 524         do {                                                            \
 525                 if (cpsw->data.dual_emac) {                             \
 526                         struct cpsw_slave *slave = cpsw->slaves +       \
 527                                                 priv->emac_port;        \
 528                         int slave_port = cpsw_get_slave_port(           \
 529                                                 slave->slave_num);      \
 530                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 531                                 1 << slave_port | ALE_PORT_HOST,        \
 532                                 ALE_VLAN, slave->port_vlan, 0);         \
 533                 } else {                                                \
 534                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 535                                 ALE_ALL_PORTS,                          \
 536                                 0, 0, 0);                               \
 537                 }                                                       \
 538         } while (0)
 539
 540 static inline int cpsw_get_slave_port(u32 slave_num)
 541 {
 542         return slave_num + 1;
 543 }
 544
 545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 546 {
 547         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 548         struct cpsw_ale *ale = cpsw->ale;
 549         int i;
 550
 551         if (cpsw->data.dual_emac) {
 552                 bool flag = false;
 553
 554                 /* Enabling promiscuous mode for one interface will be
 555                  * common for both the interface as the interface shares
 556                  * the same hardware resource.
 557                  */
 558                 for (i = 0; i < cpsw->data.slaves; i++)
 559                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 560                                 flag = true;
 561
 562                 if (!enable && flag) {
 563                         enable = true;
 564                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 565                 }
 566
 567                 if (enable) {
 568                         /* Enable Bypass */
 569                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 570
 571                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 572                 } else {
 573                         /* Disable Bypass */
 574                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 575                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 576                 }
 577         } else {
 578                 if (enable) {
 579                         unsigned long timeout = jiffies + HZ;
 580
 581                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 582                         for (i = 0; i <= cpsw->data.slaves; i++) {
 583                                 cpsw_ale_control_set(ale, i,
 584                                                      ALE_PORT_NOLEARN, 1);
 585                                 cpsw_ale_control_set(ale, i,
 586                                                      ALE_PORT_NO_SA_UPDATE, 1);
 587                         }
 588
 589                         /* Clear All Untouched entries */
 590                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 591                         do {
 592                                 cpu_relax();
 593                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 594                                         break;
 595                         } while (time_after(timeout, jiffies));
 596                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 597
 598                         /* Clear all mcast from ALE */
 599                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 600
 601                         /* Flood All Unicast Packets to Host port */
 602                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 603                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 604                 } else {
 605                         /* Don't Flood All Unicast Packets to Host port */
 606                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 607
 608                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 609                         for (i = 0; i <= cpsw->data.slaves; i++) {
 610                                 cpsw_ale_control_set(ale, i,
 611                                                      ALE_PORT_NOLEARN, 0);
 612                                 cpsw_ale_control_set(ale, i,
 613                                                      ALE_PORT_NO_SA_UPDATE, 0);
 614                         }
 615                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 616                 }
 617         }
 618 }
 619
 620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 621 {
 622         struct cpsw_priv *priv = netdev_priv(ndev);
 623         struct cpsw_common *cpsw = priv->cpsw;
 624         int vid;
 625
 626         if (cpsw->data.dual_emac)
 627                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 628         else
 629                 vid = cpsw->data.default_vlan;
 630
 631         if (ndev->flags & IFF_PROMISC) {
 632                 /* Enable promiscuous mode */
 633                 cpsw_set_promiscious(ndev, true);
 634                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 635                 return;
 636         } else {
 637                 /* Disable promiscuous mode */
 638                 cpsw_set_promiscious(ndev, false);
 639         }
 640
 641         /* Restore allmulti on vlans if necessary */
 642         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 643
 644         /* Clear all mcast from ALE */
 645         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 646
 647         if (!netdev_mc_empty(ndev)) {
 648                 struct netdev_hw_addr *ha;
 649
 650                 /* program multicast address list into ALE register */
 651                 netdev_for_each_mc_addr(ha, ndev) {
 652                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 653                 }
 654         }
 655 }
 656
 657 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 658 {
 659         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
 660         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
 661
 662         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 663         return;
 664 }
 665
 666 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 667 {
 668         __raw_writel(0, &cpsw->wr_regs->tx_en);
 669         __raw_writel(0, &cpsw->wr_regs->rx_en);
 670
 671         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 672         return;
 673 }
 674
 675 static void cpsw_tx_handler(void *token, int len, int status)
 676 {
 677         struct netdev_queue     *txq;
 678         struct sk_buff          *skb = token;
 679         struct net_device       *ndev = skb->dev;
 680         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 681
 682         /* Check whether the queue is stopped due to stalled tx dma, if the
 683          * queue is stopped then start the queue as we have free desc for tx
 684          */
 685         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 686         if (unlikely(netif_tx_queue_stopped(txq)))
 687                 netif_tx_wake_queue(txq);
 688
 689         cpts_tx_timestamp(cpsw->cpts, skb);
 690         ndev->stats.tx_packets++;
 691         ndev->stats.tx_bytes += len;
 692         dev_kfree_skb_any(skb);
 693 }
 694
 695 static void cpsw_rx_handler(void *token, int len, int status)
 696 {
 697         struct cpdma_chan       *ch;
 698         struct sk_buff          *skb = token;
 699         struct sk_buff          *new_skb;
 700         struct net_device       *ndev = skb->dev;
 701         int                     ret = 0;
 702         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 703
 704         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 705
 706         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 707                 /* In dual emac mode check for all interfaces */
 708                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 709                     (status >= 0)) {
 710                         /* The packet received is for the interface which
 711                          * is already down and the other interface is up
 712                          * and running, instead of freeing which results
 713                          * in reducing of the number of rx descriptor in
 714                          * DMA engine, requeue skb back to cpdma.
 715                          */
 716                         new_skb = skb;
 717                         goto requeue;
 718                 }
 719
 720                 /* the interface is going down, skbs are purged */
 721                 dev_kfree_skb_any(skb);
 722                 return;
 723         }
 724
 725         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 726         if (new_skb) {
 727                 skb_copy_queue_mapping(new_skb, skb);
 728                 skb_put(skb, len);
 729                 cpts_rx_timestamp(cpsw->cpts, skb);
 730                 skb->protocol = eth_type_trans(skb, ndev);
 731                 netif_receive_skb(skb);
 732                 ndev->stats.rx_bytes += len;
 733                 ndev->stats.rx_packets++;
 734                 kmemleak_not_leak(new_skb);
 735         } else {
 736                 ndev->stats.rx_dropped++;
 737                 new_skb = skb;
 738         }
 739
 740 requeue:
 741         if (netif_dormant(ndev)) {
 742                 dev_kfree_skb_any(new_skb);
 743                 return;
 744         }
 745
 746         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 747         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 748                                 skb_tailroom(new_skb), 0);
 749         if (WARN_ON(ret < 0))
 750                 dev_kfree_skb_any(new_skb);
 751 }
 752
 753 static void cpsw_split_res(struct net_device *ndev)
 754 {
 755         struct cpsw_priv *priv = netdev_priv(ndev);
 756         u32 consumed_rate = 0, bigest_rate = 0;
 757         struct cpsw_common *cpsw = priv->cpsw;
 758         struct cpsw_vector *txv = cpsw->txv;
 759         int i, ch_weight, rlim_ch_num = 0;
 760         int budget, bigest_rate_ch = 0;
 761         u32 ch_rate, max_rate;
 762         int ch_budget = 0;
 763
 764         for (i = 0; i < cpsw->tx_ch_num; i++) {
 765                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 766                 if (!ch_rate)
 767                         continue;
 768
 769                 rlim_ch_num++;
 770                 consumed_rate += ch_rate;
 771         }
 772
 773         if (cpsw->tx_ch_num == rlim_ch_num) {
 774                 max_rate = consumed_rate;
 775         } else if (!rlim_ch_num) {
 776                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 777                 bigest_rate = 0;
 778                 max_rate = consumed_rate;
 779         } else {
 780                 max_rate = cpsw->speed * 1000;
 781
 782                 /* if max_rate is less then expected due to reduced link speed,
 783                  * split proportionally according next potential max speed
 784                  */
 785                 if (max_rate < consumed_rate)
 786                         max_rate *= 10;
 787
 788                 if (max_rate < consumed_rate)
 789                         max_rate *= 10;
 790
 791                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 792                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 793                             (cpsw->tx_ch_num - rlim_ch_num);
 794                 bigest_rate = (max_rate - consumed_rate) /
 795                               (cpsw->tx_ch_num - rlim_ch_num);
 796         }
 797
 798         /* split tx weight/budget */
 799         budget = CPSW_POLL_WEIGHT;
 800         for (i = 0; i < cpsw->tx_ch_num; i++) {
 801                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 802                 if (ch_rate) {
 803                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 804                         if (!txv[i].budget)
 805                                 txv[i].budget++;
 806                         if (ch_rate > bigest_rate) {
 807                                 bigest_rate_ch = i;
 808                                 bigest_rate = ch_rate;
 809                         }
 810
 811                         ch_weight = (ch_rate * 100) / max_rate;
 812                         if (!ch_weight)
 813                                 ch_weight++;
 814                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 815                 } else {
 816                         txv[i].budget = ch_budget;
 817                         if (!bigest_rate_ch)
 818                                 bigest_rate_ch = i;
 819                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 820                 }
 821
 822                 budget -= txv[i].budget;
 823         }
 824
 825         if (budget)
 826                 txv[bigest_rate_ch].budget += budget;
 827
 828         /* split rx budget */
 829         budget = CPSW_POLL_WEIGHT;
 830         ch_budget = budget / cpsw->rx_ch_num;
 831         for (i = 0; i < cpsw->rx_ch_num; i++) {
 832                 cpsw->rxv[i].budget = ch_budget;
 833                 budget -= ch_budget;
 834         }
 835
 836         if (budget)
 837                 cpsw->rxv[0].budget += budget;
 838 }
 839
 840 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 841 {
 842         struct cpsw_common *cpsw = dev_id;
 843
 844         writel(0, &cpsw->wr_regs->tx_en);
 845         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 846
 847         if (cpsw->quirk_irq) {
 848                 disable_irq_nosync(cpsw->irqs_table[1]);
 849                 cpsw->tx_irq_disabled = true;
 850         }
 851
 852         napi_schedule(&cpsw->napi_tx);
 853         return IRQ_HANDLED;
 854 }
 855
 856 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 857 {
 858         struct cpsw_common *cpsw = dev_id;
 859
 860         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 861         writel(0, &cpsw->wr_regs->rx_en);
 862
 863         if (cpsw->quirk_irq) {
 864                 disable_irq_nosync(cpsw->irqs_table[0]);
 865                 cpsw->rx_irq_disabled = true;
 866         }
 867
 868         napi_schedule(&cpsw->napi_rx);
 869         return IRQ_HANDLED;
 870 }
 871
 872 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 873 {
 874         u32                     ch_map;
 875         int                     num_tx, cur_budget, ch;
 876         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 877         struct cpsw_vector      *txv;
 878
 879         /* process every unprocessed channel */
 880         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 881         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 882                 if (!(ch_map & 0x01))
 883                         continue;
 884
 885                 txv = &cpsw->txv[ch];
 886                 if (unlikely(txv->budget > budget - num_tx))
 887                         cur_budget = budget - num_tx;
 888                 else
 889                         cur_budget = txv->budget;
 890
 891                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 892                 if (num_tx >= budget)
 893                         break;
 894         }
 895
 896         if (num_tx < budget) {
 897                 napi_complete(napi_tx);
 898                 writel(0xff, &cpsw->wr_regs->tx_en);
 899                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 900                         cpsw->tx_irq_disabled = false;
 901                         enable_irq(cpsw->irqs_table[1]);
 902                 }
 903         }
 904
 905         return num_tx;
 906 }
 907
 908 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 909 {
 910         u32                     ch_map;
 911         int                     num_rx, cur_budget, ch;
 912         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 913         struct cpsw_vector      *rxv;
 914
 915         /* process every unprocessed channel */
 916         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 917         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
 918                 if (!(ch_map & 0x01))
 919                         continue;
 920
 921                 rxv = &cpsw->rxv[ch];
 922                 if (unlikely(rxv->budget > budget - num_rx))
 923                         cur_budget = budget - num_rx;
 924                 else
 925                         cur_budget = rxv->budget;
 926
 927                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
 928                 if (num_rx >= budget)
 929                         break;
 930         }
 931
 932         if (num_rx < budget) {
 933                 napi_complete_done(napi_rx, num_rx);
 934                 writel(0xff, &cpsw->wr_regs->rx_en);
 935                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 936                         cpsw->rx_irq_disabled = false;
 937                         enable_irq(cpsw->irqs_table[0]);
 938                 }
 939         }
 940
 941         return num_rx;
 942 }
 943
 944 static inline void soft_reset(const char *module, void __iomem *reg)
 945 {
 946         unsigned long timeout = jiffies + HZ;
 947
 948         __raw_writel(1, reg);
 949         do {
 950                 cpu_relax();
 951         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 952
 953         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 954 }
 955
 956 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 957                          ((mac)[2] << 16) | ((mac)[3] << 24))
 958 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 959
 960 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 961                                struct cpsw_priv *priv)
 962 {
 963         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 964         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 965 }
 966
 967 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 968                               struct cpsw_priv *priv, bool *link)
 969 {
 970         struct phy_device       *phy = slave->phy;
 971         u32                     mac_control = 0;
 972         u32                     slave_port;
 973         struct cpsw_common *cpsw = priv->cpsw;
 974
 975         if (!phy)
 976                 return;
 977
 978         slave_port = cpsw_get_slave_port(slave->slave_num);
 979
 980         if (phy->link) {
 981                 mac_control = cpsw->data.mac_control;
 982
 983                 /* enable forwarding */
 984                 cpsw_ale_control_set(cpsw->ale, slave_port,
 985                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 986
 987                 if (phy->speed == 1000)
 988                         mac_control |= BIT(7);  /* GIGABITEN    */
 989                 if (phy->duplex)
 990                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 991
 992                 /* set speed_in input in case RMII mode is used in 100Mbps */
 993                 if (phy->speed == 100)
 994                         mac_control |= BIT(15);
 995                 else if (phy->speed == 10)
 996                         mac_control |= BIT(18); /* In Band mode */
 997
 998                 if (priv->rx_pause)
 999                         mac_control |= BIT(3);
1000
1001                 if (priv->tx_pause)
1002                         mac_control |= BIT(4);
1003
1004                 *link = true;
1005         } else {
1006                 mac_control = 0;
1007                 /* disable forwarding */
1008                 cpsw_ale_control_set(cpsw->ale, slave_port,
1009                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1010         }
1011
1012         if (mac_control != slave->mac_control) {
1013                 phy_print_status(phy);
1014                 __raw_writel(mac_control, &slave->sliver->mac_control);
1015         }
1016
1017         slave->mac_control = mac_control;
1018 }
1019
1020 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1021 {
1022         int i, speed;
1023
1024         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1025                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1026                         speed += cpsw->slaves[i].phy->speed;
1027
1028         return speed;
1029 }
1030
1031 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1032 {
1033         int i, rlim_ch_num;
1034         int speed, ch_rate;
1035
1036         /* re-split resources only in case speed was changed */
1037         speed = cpsw_get_common_speed(cpsw);
1038         if (speed == cpsw->speed || !speed)
1039                 return 0;
1040
1041         cpsw->speed = speed;
1042
1043         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1044                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1045                 if (!ch_rate)
1046                         break;
1047
1048                 rlim_ch_num++;
1049         }
1050
1051         /* cases not dependent on speed */
1052         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1053                 return 0;
1054
1055         return 1;
1056 }
1057
1058 static void cpsw_adjust_link(struct net_device *ndev)
1059 {
1060         struct cpsw_priv        *priv = netdev_priv(ndev);
1061         struct cpsw_common      *cpsw = priv->cpsw;
1062         bool                    link = false;
1063
1064         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1065
1066         if (link) {
1067                 if (cpsw_need_resplit(cpsw))
1068                         cpsw_split_res(ndev);
1069
1070                 netif_carrier_on(ndev);
1071                 if (netif_running(ndev))
1072                         netif_tx_wake_all_queues(ndev);
1073         } else {
1074                 netif_carrier_off(ndev);
1075                 netif_tx_stop_all_queues(ndev);
1076         }
1077 }
1078
1079 static int cpsw_get_coalesce(struct net_device *ndev,
1080                                 struct ethtool_coalesce *coal)
1081 {
1082         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1083
1084         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1085         return 0;
1086 }
1087
1088 static int cpsw_set_coalesce(struct net_device *ndev,
1089                                 struct ethtool_coalesce *coal)
1090 {
1091         struct cpsw_priv *priv = netdev_priv(ndev);
1092         u32 int_ctrl;
1093         u32 num_interrupts = 0;
1094         u32 prescale = 0;
1095         u32 addnl_dvdr = 1;
1096         u32 coal_intvl = 0;
1097         struct cpsw_common *cpsw = priv->cpsw;
1098
1099         coal_intvl = coal->rx_coalesce_usecs;
1100
1101         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1102         prescale = cpsw->bus_freq_mhz * 4;
1103
1104         if (!coal->rx_coalesce_usecs) {
1105                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1106                 goto update_return;
1107         }
1108
1109         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1110                 coal_intvl = CPSW_CMINTMIN_INTVL;
1111
1112         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1113                 /* Interrupt pacer works with 4us Pulse, we can
1114                  * throttle further by dilating the 4us pulse.
1115                  */
1116                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1117
1118                 if (addnl_dvdr > 1) {
1119                         prescale *= addnl_dvdr;
1120                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1121                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1122                                                 * addnl_dvdr);
1123                 } else {
1124                         addnl_dvdr = 1;
1125                         coal_intvl = CPSW_CMINTMAX_INTVL;
1126                 }
1127         }
1128
1129         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1130         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1131         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1132
1133         int_ctrl |= CPSW_INTPACEEN;
1134         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1135         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1136
1137 update_return:
1138         writel(int_ctrl, &cpsw->wr_regs->int_control);
1139
1140         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1141         cpsw->coal_intvl = coal_intvl;
1142
1143         return 0;
1144 }
1145
1146 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1147 {
1148         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1149
1150         switch (sset) {
1151         case ETH_SS_STATS:
1152                 return (CPSW_STATS_COMMON_LEN +
1153                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1154                        CPSW_STATS_CH_LEN);
1155         default:
1156                 return -EOPNOTSUPP;
1157         }
1158 }
1159
1160 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1161 {
1162         int ch_stats_len;
1163         int line;
1164         int i;
1165
1166         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1167         for (i = 0; i < ch_stats_len; i++) {
1168                 line = i % CPSW_STATS_CH_LEN;
1169                 snprintf(*p, ETH_GSTRING_LEN,
1170                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1171                          i / CPSW_STATS_CH_LEN,
1172                          cpsw_gstrings_ch_stats[line].stat_string);
1173                 *p += ETH_GSTRING_LEN;
1174         }
1175 }
1176
1177 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1178 {
1179         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1180         u8 *p = data;
1181         int i;
1182
1183         switch (stringset) {
1184         case ETH_SS_STATS:
1185                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1186                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1187                                ETH_GSTRING_LEN);
1188                         p += ETH_GSTRING_LEN;
1189                 }
1190
1191                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1192                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1193                 break;
1194         }
1195 }
1196
1197 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1198                                     struct ethtool_stats *stats, u64 *data)
1199 {
1200         u8 *p;
1201         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1202         struct cpdma_chan_stats ch_stats;
1203         int i, l, ch;
1204
1205         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1206         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1207                 data[l] = readl(cpsw->hw_stats +
1208                                 cpsw_gstrings_stats[l].stat_offset);
1209
1210         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1211                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1212                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1213                         p = (u8 *)&ch_stats +
1214                                 cpsw_gstrings_ch_stats[i].stat_offset;
1215                         data[l] = *(u32 *)p;
1216                 }
1217         }
1218
1219         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1220                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1221                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1222                         p = (u8 *)&ch_stats +
1223                                 cpsw_gstrings_ch_stats[i].stat_offset;
1224                         data[l] = *(u32 *)p;
1225                 }
1226         }
1227 }
1228
1229 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1230                                         struct sk_buff *skb,
1231                                         struct cpdma_chan *txch)
1232 {
1233         struct cpsw_common *cpsw = priv->cpsw;
1234
1235         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1236                                  priv->emac_port + cpsw->data.dual_emac);
1237 }
1238
1239 static inline void cpsw_add_dual_emac_def_ale_entries(
1240                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1241                 u32 slave_port)
1242 {
1243         struct cpsw_common *cpsw = priv->cpsw;
1244         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1245
1246         if (cpsw->version == CPSW_VERSION_1)
1247                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1248         else
1249                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1250         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1251                           port_mask, port_mask, 0);
1252         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1253                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1254         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1255                            HOST_PORT_NUM, ALE_VLAN |
1256                            ALE_SECURE, slave->port_vlan);
1257 }
1258
1259 static void soft_reset_slave(struct cpsw_slave *slave)
1260 {
1261         char name[32];
1262
1263         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1264         soft_reset(name, &slave->sliver->soft_reset);
1265 }
1266
1267 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1268 {
1269         u32 slave_port;
1270         struct phy_device *phy;
1271         struct cpsw_common *cpsw = priv->cpsw;
1272
1273         soft_reset_slave(slave);
1274
1275         /* setup priority mapping */
1276         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1277
1278         switch (cpsw->version) {
1279         case CPSW_VERSION_1:
1280                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1281                 break;
1282         case CPSW_VERSION_2:
1283         case CPSW_VERSION_3:
1284         case CPSW_VERSION_4:
1285                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1286                 break;
1287         }
1288
1289         /* setup max packet size, and mac address */
1290         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1291         cpsw_set_slave_mac(slave, priv);
1292
1293         slave->mac_control = 0; /* no link yet */
1294
1295         slave_port = cpsw_get_slave_port(slave->slave_num);
1296
1297         if (cpsw->data.dual_emac)
1298                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1299         else
1300                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1301                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1302
1303         if (slave->data->phy_node) {
1304                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1305                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1306                 if (!phy) {
1307                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1308                                 slave->data->phy_node->full_name,
1309                                 slave->slave_num);
1310                         return;
1311                 }
1312         } else {
1313                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1314                                  &cpsw_adjust_link, slave->data->phy_if);
1315                 if (IS_ERR(phy)) {
1316                         dev_err(priv->dev,
1317                                 "phy \"%s\" not found on slave %d, err %ld\n",
1318                                 slave->data->phy_id, slave->slave_num,
1319                                 PTR_ERR(phy));
1320                         return;
1321                 }
1322         }
1323
1324         slave->phy = phy;
1325
1326         phy_attached_info(slave->phy);
1327
1328         phy_start(slave->phy);
1329
1330         /* Configure GMII_SEL register */
1331         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1332 }
1333
1334 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1335 {
1336         struct cpsw_common *cpsw = priv->cpsw;
1337         const int vlan = cpsw->data.default_vlan;
1338         u32 reg;
1339         int i;
1340         int unreg_mcast_mask;
1341
1342         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1343                CPSW2_PORT_VLAN;
1344
1345         writel(vlan, &cpsw->host_port_regs->port_vlan);
1346
1347         for (i = 0; i < cpsw->data.slaves; i++)
1348                 slave_write(cpsw->slaves + i, vlan, reg);
1349
1350         if (priv->ndev->flags & IFF_ALLMULTI)
1351                 unreg_mcast_mask = ALE_ALL_PORTS;
1352         else
1353                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1354
1355         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1356                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1357                           unreg_mcast_mask);
1358 }
1359
1360 static void cpsw_init_host_port(struct cpsw_priv *priv)
1361 {
1362         u32 fifo_mode;
1363         u32 control_reg;
1364         struct cpsw_common *cpsw = priv->cpsw;
1365
1366         /* soft reset the controller and initialize ale */
1367         soft_reset("cpsw", &cpsw->regs->soft_reset);
1368         cpsw_ale_start(cpsw->ale);
1369
1370         /* switch to vlan unaware mode */
1371         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1372                              CPSW_ALE_VLAN_AWARE);
1373         control_reg = readl(&cpsw->regs->control);
1374         control_reg |= CPSW_VLAN_AWARE;
1375         writel(control_reg, &cpsw->regs->control);
1376         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1377                      CPSW_FIFO_NORMAL_MODE;
1378         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1379
1380         /* setup host port priority mapping */
1381         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1382                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1383         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1384
1385         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1386                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1387
1388         if (!cpsw->data.dual_emac) {
1389                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1390                                    0, 0);
1391                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1392                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1393         }
1394 }
1395
1396 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1397 {
1398         struct cpsw_common *cpsw = priv->cpsw;
1399         struct sk_buff *skb;
1400         int ch_buf_num;
1401         int ch, i, ret;
1402
1403         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1404                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1405                 for (i = 0; i < ch_buf_num; i++) {
1406                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1407                                                           cpsw->rx_packet_max,
1408                                                           GFP_KERNEL);
1409                         if (!skb) {
1410                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1411                                 return -ENOMEM;
1412                         }
1413
1414                         skb_set_queue_mapping(skb, ch);
1415                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1416                                                 skb->data, skb_tailroom(skb),
1417                                                 0);
1418                         if (ret < 0) {
1419                                 cpsw_err(priv, ifup,
1420                                          "cannot submit skb to channel %d rx, error %d\n",
1421                                          ch, ret);
1422                                 kfree_skb(skb);
1423                                 return ret;
1424                         }
1425                         kmemleak_not_leak(skb);
1426                 }
1427
1428                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1429                           ch, ch_buf_num);
1430         }
1431
1432         return 0;
1433 }
1434
1435 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1436 {
1437         u32 slave_port;
1438
1439         slave_port = cpsw_get_slave_port(slave->slave_num);
1440
1441         if (!slave->phy)
1442                 return;
1443         phy_stop(slave->phy);
1444         phy_disconnect(slave->phy);
1445         slave->phy = NULL;
1446         cpsw_ale_control_set(cpsw->ale, slave_port,
1447                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1448         soft_reset_slave(slave);
1449 }
1450
1451 static int cpsw_ndo_open(struct net_device *ndev)
1452 {
1453         struct cpsw_priv *priv = netdev_priv(ndev);
1454         struct cpsw_common *cpsw = priv->cpsw;
1455         int ret;
1456         u32 reg;
1457
1458         ret = pm_runtime_get_sync(cpsw->dev);
1459         if (ret < 0) {
1460                 pm_runtime_put_noidle(cpsw->dev);
1461                 return ret;
1462         }
1463
1464         netif_carrier_off(ndev);
1465
1466         /* Notify the stack of the actual queue counts. */
1467         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1468         if (ret) {
1469                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1470                 goto err_cleanup;
1471         }
1472
1473         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1474         if (ret) {
1475                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1476                 goto err_cleanup;
1477         }
1478
1479         reg = cpsw->version;
1480
1481         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1482                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1483                  CPSW_RTL_VERSION(reg));
1484
1485         /* Initialize host and slave ports */
1486         if (!cpsw->usage_count)
1487                 cpsw_init_host_port(priv);
1488         for_each_slave(priv, cpsw_slave_open, priv);
1489
1490         /* Add default VLAN */
1491         if (!cpsw->data.dual_emac)
1492                 cpsw_add_default_vlan(priv);
1493         else
1494                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1495                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1496
1497         /* initialize shared resources for every ndev */
1498         if (!cpsw->usage_count) {
1499                 /* disable priority elevation */
1500                 __raw_writel(0, &cpsw->regs->ptype);
1501
1502                 /* enable statistics collection only on all ports */
1503                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1504
1505                 /* Enable internal fifo flow control */
1506                 writel(0x7, &cpsw->regs->flow_control);
1507
1508                 napi_enable(&cpsw->napi_rx);
1509                 napi_enable(&cpsw->napi_tx);
1510
1511                 if (cpsw->tx_irq_disabled) {
1512                         cpsw->tx_irq_disabled = false;
1513                         enable_irq(cpsw->irqs_table[1]);
1514                 }
1515
1516                 if (cpsw->rx_irq_disabled) {
1517                         cpsw->rx_irq_disabled = false;
1518                         enable_irq(cpsw->irqs_table[0]);
1519                 }
1520
1521                 ret = cpsw_fill_rx_channels(priv);
1522                 if (ret < 0)
1523                         goto err_cleanup;
1524
1525                 if (cpts_register(cpsw->cpts))
1526                         dev_err(priv->dev, "error registering cpts device\n");
1527
1528         }
1529
1530         /* Enable Interrupt pacing if configured */
1531         if (cpsw->coal_intvl != 0) {
1532                 struct ethtool_coalesce coal;
1533
1534                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1535                 cpsw_set_coalesce(ndev, &coal);
1536         }
1537
1538         cpdma_ctlr_start(cpsw->dma);
1539         cpsw_intr_enable(cpsw);
1540         cpsw->usage_count++;
1541
1542         return 0;
1543
1544 err_cleanup:
1545         cpdma_ctlr_stop(cpsw->dma);
1546         for_each_slave(priv, cpsw_slave_stop, cpsw);
1547         pm_runtime_put_sync(cpsw->dev);
1548         netif_carrier_off(priv->ndev);
1549         return ret;
1550 }
1551
1552 static int cpsw_ndo_stop(struct net_device *ndev)
1553 {
1554         struct cpsw_priv *priv = netdev_priv(ndev);
1555         struct cpsw_common *cpsw = priv->cpsw;
1556
1557         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1558         netif_tx_stop_all_queues(priv->ndev);
1559         netif_carrier_off(priv->ndev);
1560
1561         if (cpsw->usage_count <= 1) {
1562                 napi_disable(&cpsw->napi_rx);
1563                 napi_disable(&cpsw->napi_tx);
1564                 cpts_unregister(cpsw->cpts);
1565                 cpsw_intr_disable(cpsw);
1566                 cpdma_ctlr_stop(cpsw->dma);
1567                 cpsw_ale_stop(cpsw->ale);
1568         }
1569         for_each_slave(priv, cpsw_slave_stop, cpsw);
1570
1571         if (cpsw_need_resplit(cpsw))
1572                 cpsw_split_res(ndev);
1573
1574         cpsw->usage_count--;
1575         pm_runtime_put_sync(cpsw->dev);
1576         return 0;
1577 }
1578
1579 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1580                                        struct net_device *ndev)
1581 {
1582         struct cpsw_priv *priv = netdev_priv(ndev);
1583         struct cpsw_common *cpsw = priv->cpsw;
1584         struct netdev_queue *txq;
1585         struct cpdma_chan *txch;
1586         int ret, q_idx;
1587
1588         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1589                 cpsw_err(priv, tx_err, "packet pad failed\n");
1590                 ndev->stats.tx_dropped++;
1591                 return NET_XMIT_DROP;
1592         }
1593
1594         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1595             cpts_is_tx_enabled(cpsw->cpts))
1596                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1597
1598         skb_tx_timestamp(skb);
1599
1600         q_idx = skb_get_queue_mapping(skb);
1601         if (q_idx >= cpsw->tx_ch_num)
1602                 q_idx = q_idx % cpsw->tx_ch_num;
1603
1604         txch = cpsw->txv[q_idx].ch;
1605         ret = cpsw_tx_packet_submit(priv, skb, txch);
1606         if (unlikely(ret != 0)) {
1607                 cpsw_err(priv, tx_err, "desc submit failed\n");
1608                 goto fail;
1609         }
1610
1611         /* If there is no more tx desc left free then we need to
1612          * tell the kernel to stop sending us tx frames.
1613          */
1614         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1615                 txq = netdev_get_tx_queue(ndev, q_idx);
1616                 netif_tx_stop_queue(txq);
1617         }
1618
1619         return NETDEV_TX_OK;
1620 fail:
1621         ndev->stats.tx_dropped++;
1622         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1623         netif_tx_stop_queue(txq);
1624         return NETDEV_TX_BUSY;
1625 }
1626
1627 #if IS_ENABLED(CONFIG_TI_CPTS)
1628
1629 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1630 {
1631         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1632         u32 ts_en, seq_id;
1633
1634         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1635             !cpts_is_rx_enabled(cpsw->cpts)) {
1636                 slave_write(slave, 0, CPSW1_TS_CTL);
1637                 return;
1638         }
1639
1640         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1641         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1642
1643         if (cpts_is_tx_enabled(cpsw->cpts))
1644                 ts_en |= CPSW_V1_TS_TX_EN;
1645
1646         if (cpts_is_rx_enabled(cpsw->cpts))
1647                 ts_en |= CPSW_V1_TS_RX_EN;
1648
1649         slave_write(slave, ts_en, CPSW1_TS_CTL);
1650         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1651 }
1652
1653 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1654 {
1655         struct cpsw_slave *slave;
1656         struct cpsw_common *cpsw = priv->cpsw;
1657         u32 ctrl, mtype;
1658
1659         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1660
1661         ctrl = slave_read(slave, CPSW2_CONTROL);
1662         switch (cpsw->version) {
1663         case CPSW_VERSION_2:
1664                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1665
1666                 if (cpts_is_tx_enabled(cpsw->cpts))
1667                         ctrl |= CTRL_V2_TX_TS_BITS;
1668
1669                 if (cpts_is_rx_enabled(cpsw->cpts))
1670                         ctrl |= CTRL_V2_RX_TS_BITS;
1671                 break;
1672         case CPSW_VERSION_3:
1673         default:
1674                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1675
1676                 if (cpts_is_tx_enabled(cpsw->cpts))
1677                         ctrl |= CTRL_V3_TX_TS_BITS;
1678
1679                 if (cpts_is_rx_enabled(cpsw->cpts))
1680                         ctrl |= CTRL_V3_RX_TS_BITS;
1681                 break;
1682         }
1683
1684         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1685
1686         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1687         slave_write(slave, ctrl, CPSW2_CONTROL);
1688         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1689 }
1690
1691 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1692 {
1693         struct cpsw_priv *priv = netdev_priv(dev);
1694         struct hwtstamp_config cfg;
1695         struct cpsw_common *cpsw = priv->cpsw;
1696         struct cpts *cpts = cpsw->cpts;
1697
1698         if (cpsw->version != CPSW_VERSION_1 &&
1699             cpsw->version != CPSW_VERSION_2 &&
1700             cpsw->version != CPSW_VERSION_3)
1701                 return -EOPNOTSUPP;
1702
1703         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1704                 return -EFAULT;
1705
1706         /* reserved for future extensions */
1707         if (cfg.flags)
1708                 return -EINVAL;
1709
1710         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1711                 return -ERANGE;
1712
1713         switch (cfg.rx_filter) {
1714         case HWTSTAMP_FILTER_NONE:
1715                 cpts_rx_enable(cpts, 0);
1716                 break;
1717         case HWTSTAMP_FILTER_ALL:
1718         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1719         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1720         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1721                 return -ERANGE;
1722         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1723         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1724         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1725         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1726         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1727         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1728         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1729         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1730         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1731                 cpts_rx_enable(cpts, 1);
1732                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1733                 break;
1734         default:
1735                 return -ERANGE;
1736         }
1737
1738         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1739
1740         switch (cpsw->version) {
1741         case CPSW_VERSION_1:
1742                 cpsw_hwtstamp_v1(cpsw);
1743                 break;
1744         case CPSW_VERSION_2:
1745         case CPSW_VERSION_3:
1746                 cpsw_hwtstamp_v2(priv);
1747                 break;
1748         default:
1749                 WARN_ON(1);
1750         }
1751
1752         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1753 }
1754
1755 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1756 {
1757         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1758         struct cpts *cpts = cpsw->cpts;
1759         struct hwtstamp_config cfg;
1760
1761         if (cpsw->version != CPSW_VERSION_1 &&
1762             cpsw->version != CPSW_VERSION_2 &&
1763             cpsw->version != CPSW_VERSION_3)
1764                 return -EOPNOTSUPP;
1765
1766         cfg.flags = 0;
1767         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1768                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1769         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1770                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1771
1772         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1773 }
1774 #else
1775 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1776 {
1777         return -EOPNOTSUPP;
1778 }
1779
1780 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1781 {
1782         return -EOPNOTSUPP;
1783 }
1784 #endif /*CONFIG_TI_CPTS*/
1785
1786 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1787 {
1788         struct cpsw_priv *priv = netdev_priv(dev);
1789         struct cpsw_common *cpsw = priv->cpsw;
1790         int slave_no = cpsw_slave_index(cpsw, priv);
1791
1792         if (!netif_running(dev))
1793                 return -EINVAL;
1794
1795         switch (cmd) {
1796         case SIOCSHWTSTAMP:
1797                 return cpsw_hwtstamp_set(dev, req);
1798         case SIOCGHWTSTAMP:
1799                 return cpsw_hwtstamp_get(dev, req);
1800         }
1801
1802         if (!cpsw->slaves[slave_no].phy)
1803                 return -EOPNOTSUPP;
1804         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1805 }
1806
1807 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1808 {
1809         struct cpsw_priv *priv = netdev_priv(ndev);
1810         struct cpsw_common *cpsw = priv->cpsw;
1811         int ch;
1812
1813         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1814         ndev->stats.tx_errors++;
1815         cpsw_intr_disable(cpsw);
1816         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1817                 cpdma_chan_stop(cpsw->txv[ch].ch);
1818                 cpdma_chan_start(cpsw->txv[ch].ch);
1819         }
1820
1821         cpsw_intr_enable(cpsw);
1822         netif_trans_update(ndev);
1823         netif_tx_wake_all_queues(ndev);
1824 }
1825
1826 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1827 {
1828         struct cpsw_priv *priv = netdev_priv(ndev);
1829         struct sockaddr *addr = (struct sockaddr *)p;
1830         struct cpsw_common *cpsw = priv->cpsw;
1831         int flags = 0;
1832         u16 vid = 0;
1833         int ret;
1834
1835         if (!is_valid_ether_addr(addr->sa_data))
1836                 return -EADDRNOTAVAIL;
1837
1838         ret = pm_runtime_get_sync(cpsw->dev);
1839         if (ret < 0) {
1840                 pm_runtime_put_noidle(cpsw->dev);
1841                 return ret;
1842         }
1843
1844         if (cpsw->data.dual_emac) {
1845                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1846                 flags = ALE_VLAN;
1847         }
1848
1849         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1850                            flags, vid);
1851         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1852                            flags, vid);
1853
1854         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1855         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1856         for_each_slave(priv, cpsw_set_slave_mac, priv);
1857
1858         pm_runtime_put(cpsw->dev);
1859
1860         return 0;
1861 }
1862
1863 #ifdef CONFIG_NET_POLL_CONTROLLER
1864 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1865 {
1866         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1867
1868         cpsw_intr_disable(cpsw);
1869         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1870         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1871         cpsw_intr_enable(cpsw);
1872 }
1873 #endif
1874
1875 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1876                                 unsigned short vid)
1877 {
1878         int ret;
1879         int unreg_mcast_mask = 0;
1880         u32 port_mask;
1881         struct cpsw_common *cpsw = priv->cpsw;
1882
1883         if (cpsw->data.dual_emac) {
1884                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1885
1886                 if (priv->ndev->flags & IFF_ALLMULTI)
1887                         unreg_mcast_mask = port_mask;
1888         } else {
1889                 port_mask = ALE_ALL_PORTS;
1890
1891                 if (priv->ndev->flags & IFF_ALLMULTI)
1892                         unreg_mcast_mask = ALE_ALL_PORTS;
1893                 else
1894                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1895         }
1896
1897         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1898                                 unreg_mcast_mask);
1899         if (ret != 0)
1900                 return ret;
1901
1902         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1903                                  HOST_PORT_NUM, ALE_VLAN, vid);
1904         if (ret != 0)
1905                 goto clean_vid;
1906
1907         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1908                                  port_mask, ALE_VLAN, vid, 0);
1909         if (ret != 0)
1910                 goto clean_vlan_ucast;
1911         return 0;
1912
1913 clean_vlan_ucast:
1914         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1915                            HOST_PORT_NUM, ALE_VLAN, vid);
1916 clean_vid:
1917         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1918         return ret;
1919 }
1920
1921 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1922                                     __be16 proto, u16 vid)
1923 {
1924         struct cpsw_priv *priv = netdev_priv(ndev);
1925         struct cpsw_common *cpsw = priv->cpsw;
1926         int ret;
1927
1928         if (vid == cpsw->data.default_vlan)
1929                 return 0;
1930
1931         ret = pm_runtime_get_sync(cpsw->dev);
1932         if (ret < 0) {
1933                 pm_runtime_put_noidle(cpsw->dev);
1934                 return ret;
1935         }
1936
1937         if (cpsw->data.dual_emac) {
1938                 /* In dual EMAC, reserved VLAN id should not be used for
1939                  * creating VLAN interfaces as this can break the dual
1940                  * EMAC port separation
1941                  */
1942                 int i;
1943
1944                 for (i = 0; i < cpsw->data.slaves; i++) {
1945                         if (vid == cpsw->slaves[i].port_vlan)
1946                                 return -EINVAL;
1947                 }
1948         }
1949
1950         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1951         ret = cpsw_add_vlan_ale_entry(priv, vid);
1952
1953         pm_runtime_put(cpsw->dev);
1954         return ret;
1955 }
1956
1957 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1958                                      __be16 proto, u16 vid)
1959 {
1960         struct cpsw_priv *priv = netdev_priv(ndev);
1961         struct cpsw_common *cpsw = priv->cpsw;
1962         int ret;
1963
1964         if (vid == cpsw->data.default_vlan)
1965                 return 0;
1966
1967         ret = pm_runtime_get_sync(cpsw->dev);
1968         if (ret < 0) {
1969                 pm_runtime_put_noidle(cpsw->dev);
1970                 return ret;
1971         }
1972
1973         if (cpsw->data.dual_emac) {
1974                 int i;
1975
1976                 for (i = 0; i < cpsw->data.slaves; i++) {
1977                         if (vid == cpsw->slaves[i].port_vlan)
1978                                 return -EINVAL;
1979                 }
1980         }
1981
1982         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1983         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1984         if (ret != 0)
1985                 return ret;
1986
1987         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1988                                  HOST_PORT_NUM, ALE_VLAN, vid);
1989         if (ret != 0)
1990                 return ret;
1991
1992         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
1993                                  0, ALE_VLAN, vid);
1994         pm_runtime_put(cpsw->dev);
1995         return ret;
1996 }
1997
1998 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
1999 {
2000         struct cpsw_priv *priv = netdev_priv(ndev);
2001         struct cpsw_common *cpsw = priv->cpsw;
2002         struct cpsw_slave *slave;
2003         u32 min_rate;
2004         u32 ch_rate;
2005         int i, ret;
2006
2007         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2008         if (ch_rate == rate)
2009                 return 0;
2010
2011         ch_rate = rate * 1000;
2012         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2013         if ((ch_rate < min_rate && ch_rate)) {
2014                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2015                         min_rate);
2016                 return -EINVAL;
2017         }
2018
2019         if (rate > cpsw->speed) {
2020                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2021                 return -EINVAL;
2022         }
2023
2024         ret = pm_runtime_get_sync(cpsw->dev);
2025         if (ret < 0) {
2026                 pm_runtime_put_noidle(cpsw->dev);
2027                 return ret;
2028         }
2029
2030         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2031         pm_runtime_put(cpsw->dev);
2032
2033         if (ret)
2034                 return ret;
2035
2036         /* update rates for slaves tx queues */
2037         for (i = 0; i < cpsw->data.slaves; i++) {
2038                 slave = &cpsw->slaves[i];
2039                 if (!slave->ndev)
2040                         continue;
2041
2042                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2043         }
2044
2045         cpsw_split_res(ndev);
2046         return ret;
2047 }
2048
2049 static const struct net_device_ops cpsw_netdev_ops = {
2050         .ndo_open               = cpsw_ndo_open,
2051         .ndo_stop               = cpsw_ndo_stop,
2052         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2053         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2054         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2055         .ndo_validate_addr      = eth_validate_addr,
2056         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2057         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2058         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2059 #ifdef CONFIG_NET_POLL_CONTROLLER
2060         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2061 #endif
2062         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2063         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2064 };
2065
2066 static int cpsw_get_regs_len(struct net_device *ndev)
2067 {
2068         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2069
2070         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2071 }
2072
2073 static void cpsw_get_regs(struct net_device *ndev,
2074                           struct ethtool_regs *regs, void *p)
2075 {
2076         u32 *reg = p;
2077         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2078
2079         /* update CPSW IP version */
2080         regs->version = cpsw->version;
2081
2082         cpsw_ale_dump(cpsw->ale, reg);
2083 }
2084
2085 static void cpsw_get_drvinfo(struct net_device *ndev,
2086                              struct ethtool_drvinfo *info)
2087 {
2088         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2089         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2090
2091         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2092         strlcpy(info->version, "1.0", sizeof(info->version));
2093         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2094 }
2095
2096 static u32 cpsw_get_msglevel(struct net_device *ndev)
2097 {
2098         struct cpsw_priv *priv = netdev_priv(ndev);
2099         return priv->msg_enable;
2100 }
2101
2102 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2103 {
2104         struct cpsw_priv *priv = netdev_priv(ndev);
2105         priv->msg_enable = value;
2106 }
2107
2108 #if IS_ENABLED(CONFIG_TI_CPTS)
2109 static int cpsw_get_ts_info(struct net_device *ndev,
2110                             struct ethtool_ts_info *info)
2111 {
2112         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2113
2114         info->so_timestamping =
2115                 SOF_TIMESTAMPING_TX_HARDWARE |
2116                 SOF_TIMESTAMPING_TX_SOFTWARE |
2117                 SOF_TIMESTAMPING_RX_HARDWARE |
2118                 SOF_TIMESTAMPING_RX_SOFTWARE |
2119                 SOF_TIMESTAMPING_SOFTWARE |
2120                 SOF_TIMESTAMPING_RAW_HARDWARE;
2121         info->phc_index = cpsw->cpts->phc_index;
2122         info->tx_types =
2123                 (1 << HWTSTAMP_TX_OFF) |
2124                 (1 << HWTSTAMP_TX_ON);
2125         info->rx_filters =
2126                 (1 << HWTSTAMP_FILTER_NONE) |
2127                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2128         return 0;
2129 }
2130 #else
2131 static int cpsw_get_ts_info(struct net_device *ndev,
2132                             struct ethtool_ts_info *info)
2133 {
2134         info->so_timestamping =
2135                 SOF_TIMESTAMPING_TX_SOFTWARE |
2136                 SOF_TIMESTAMPING_RX_SOFTWARE |
2137                 SOF_TIMESTAMPING_SOFTWARE;
2138         info->phc_index = -1;
2139         info->tx_types = 0;
2140         info->rx_filters = 0;
2141         return 0;
2142 }
2143 #endif
2144
2145 static int cpsw_get_link_ksettings(struct net_device *ndev,
2146                                    struct ethtool_link_ksettings *ecmd)
2147 {
2148         struct cpsw_priv *priv = netdev_priv(ndev);
2149         struct cpsw_common *cpsw = priv->cpsw;
2150         int slave_no = cpsw_slave_index(cpsw, priv);
2151
2152         if (cpsw->slaves[slave_no].phy)
2153                 return phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy,
2154                                                  ecmd);
2155         else
2156                 return -EOPNOTSUPP;
2157 }
2158
2159 static int cpsw_set_link_ksettings(struct net_device *ndev,
2160                                    const struct ethtool_link_ksettings *ecmd)
2161 {
2162         struct cpsw_priv *priv = netdev_priv(ndev);
2163         struct cpsw_common *cpsw = priv->cpsw;
2164         int slave_no = cpsw_slave_index(cpsw, priv);
2165
2166         if (cpsw->slaves[slave_no].phy)
2167                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2168                                                  ecmd);
2169         else
2170                 return -EOPNOTSUPP;
2171 }
2172
2173 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2174 {
2175         struct cpsw_priv *priv = netdev_priv(ndev);
2176         struct cpsw_common *cpsw = priv->cpsw;
2177         int slave_no = cpsw_slave_index(cpsw, priv);
2178
2179         wol->supported = 0;
2180         wol->wolopts = 0;
2181
2182         if (cpsw->slaves[slave_no].phy)
2183                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2184 }
2185
2186 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2187 {
2188         struct cpsw_priv *priv = netdev_priv(ndev);
2189         struct cpsw_common *cpsw = priv->cpsw;
2190         int slave_no = cpsw_slave_index(cpsw, priv);
2191
2192         if (cpsw->slaves[slave_no].phy)
2193                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2194         else
2195                 return -EOPNOTSUPP;
2196 }
2197
2198 static void cpsw_get_pauseparam(struct net_device *ndev,
2199                                 struct ethtool_pauseparam *pause)
2200 {
2201         struct cpsw_priv *priv = netdev_priv(ndev);
2202
2203         pause->autoneg = AUTONEG_DISABLE;
2204         pause->rx_pause = priv->rx_pause ? true : false;
2205         pause->tx_pause = priv->tx_pause ? true : false;
2206 }
2207
2208 static int cpsw_set_pauseparam(struct net_device *ndev,
2209                                struct ethtool_pauseparam *pause)
2210 {
2211         struct cpsw_priv *priv = netdev_priv(ndev);
2212         bool link;
2213
2214         priv->rx_pause = pause->rx_pause ? true : false;
2215         priv->tx_pause = pause->tx_pause ? true : false;
2216
2217         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2218         return 0;
2219 }
2220
2221 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2222 {
2223         struct cpsw_priv *priv = netdev_priv(ndev);
2224         struct cpsw_common *cpsw = priv->cpsw;
2225         int ret;
2226
2227         ret = pm_runtime_get_sync(cpsw->dev);
2228         if (ret < 0) {
2229                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2230                 pm_runtime_put_noidle(cpsw->dev);
2231         }
2232
2233         return ret;
2234 }
2235
2236 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2237 {
2238         struct cpsw_priv *priv = netdev_priv(ndev);
2239         int ret;
2240
2241         ret = pm_runtime_put(priv->cpsw->dev);
2242         if (ret < 0)
2243                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2244 }
2245
2246 static void cpsw_get_channels(struct net_device *ndev,
2247                               struct ethtool_channels *ch)
2248 {
2249         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2250
2251         ch->max_combined = 0;
2252         ch->max_rx = CPSW_MAX_QUEUES;
2253         ch->max_tx = CPSW_MAX_QUEUES;
2254         ch->max_other = 0;
2255         ch->other_count = 0;
2256         ch->rx_count = cpsw->rx_ch_num;
2257         ch->tx_count = cpsw->tx_ch_num;
2258         ch->combined_count = 0;
2259 }
2260
2261 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2262                                   struct ethtool_channels *ch)
2263 {
2264         if (ch->combined_count)
2265                 return -EINVAL;
2266
2267         /* verify we have at least one channel in each direction */
2268         if (!ch->rx_count || !ch->tx_count)
2269                 return -EINVAL;
2270
2271         if (ch->rx_count > cpsw->data.channels ||
2272             ch->tx_count > cpsw->data.channels)
2273                 return -EINVAL;
2274
2275         return 0;
2276 }
2277
2278 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2279 {
2280         int (*poll)(struct napi_struct *, int);
2281         struct cpsw_common *cpsw = priv->cpsw;
2282         void (*handler)(void *, int, int);
2283         struct netdev_queue *queue;
2284         struct cpsw_vector *vec;
2285         int ret, *ch;
2286
2287         if (rx) {
2288                 ch = &cpsw->rx_ch_num;
2289                 vec = cpsw->rxv;
2290                 handler = cpsw_rx_handler;
2291                 poll = cpsw_rx_poll;
2292         } else {
2293                 ch = &cpsw->tx_ch_num;
2294                 vec = cpsw->txv;
2295                 handler = cpsw_tx_handler;
2296                 poll = cpsw_tx_poll;
2297         }
2298
2299         while (*ch < ch_num) {
2300                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2301                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2302                 queue->tx_maxrate = 0;
2303
2304                 if (IS_ERR(vec[*ch].ch))
2305                         return PTR_ERR(vec[*ch].ch);
2306
2307                 if (!vec[*ch].ch)
2308                         return -EINVAL;
2309
2310                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2311                           (rx ? "rx" : "tx"));
2312                 (*ch)++;
2313         }
2314
2315         while (*ch > ch_num) {
2316                 (*ch)--;
2317
2318                 ret = cpdma_chan_destroy(vec[*ch].ch);
2319                 if (ret)
2320                         return ret;
2321
2322                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2323                           (rx ? "rx" : "tx"));
2324         }
2325
2326         return 0;
2327 }
2328
2329 static int cpsw_update_channels(struct cpsw_priv *priv,
2330                                 struct ethtool_channels *ch)
2331 {
2332         int ret;
2333
2334         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2335         if (ret)
2336                 return ret;
2337
2338         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2339         if (ret)
2340                 return ret;
2341
2342         return 0;
2343 }
2344
2345 static void cpsw_suspend_data_pass(struct net_device *ndev)
2346 {
2347         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2348         struct cpsw_slave *slave;
2349         int i;
2350
2351         /* Disable NAPI scheduling */
2352         cpsw_intr_disable(cpsw);
2353
2354         /* Stop all transmit queues for every network device.
2355          * Disable re-using rx descriptors with dormant_on.
2356          */
2357         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2358                 if (!(slave->ndev && netif_running(slave->ndev)))
2359                         continue;
2360
2361                 netif_tx_stop_all_queues(slave->ndev);
2362                 netif_dormant_on(slave->ndev);
2363         }
2364
2365         /* Handle rest of tx packets and stop cpdma channels */
2366         cpdma_ctlr_stop(cpsw->dma);
2367 }
2368
2369 static int cpsw_resume_data_pass(struct net_device *ndev)
2370 {
2371         struct cpsw_priv *priv = netdev_priv(ndev);
2372         struct cpsw_common *cpsw = priv->cpsw;
2373         struct cpsw_slave *slave;
2374         int i, ret;
2375
2376         /* Allow rx packets handling */
2377         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2378                 if (slave->ndev && netif_running(slave->ndev))
2379                         netif_dormant_off(slave->ndev);
2380
2381         /* After this receive is started */
2382         if (cpsw->usage_count) {
2383                 ret = cpsw_fill_rx_channels(priv);
2384                 if (ret)
2385                         return ret;
2386
2387                 cpdma_ctlr_start(cpsw->dma);
2388                 cpsw_intr_enable(cpsw);
2389         }
2390
2391         /* Resume transmit for every affected interface */
2392         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2393                 if (slave->ndev && netif_running(slave->ndev))
2394                         netif_tx_start_all_queues(slave->ndev);
2395
2396         return 0;
2397 }
2398
2399 static int cpsw_set_channels(struct net_device *ndev,
2400                              struct ethtool_channels *chs)
2401 {
2402         struct cpsw_priv *priv = netdev_priv(ndev);
2403         struct cpsw_common *cpsw = priv->cpsw;
2404         struct cpsw_slave *slave;
2405         int i, ret;
2406
2407         ret = cpsw_check_ch_settings(cpsw, chs);
2408         if (ret < 0)
2409                 return ret;
2410
2411         cpsw_suspend_data_pass(ndev);
2412         ret = cpsw_update_channels(priv, chs);
2413         if (ret)
2414                 goto err;
2415
2416         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2417                 if (!(slave->ndev && netif_running(slave->ndev)))
2418                         continue;
2419
2420                 /* Inform stack about new count of queues */
2421                 ret = netif_set_real_num_tx_queues(slave->ndev,
2422                                                    cpsw->tx_ch_num);
2423                 if (ret) {
2424                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2425                         goto err;
2426                 }
2427
2428                 ret = netif_set_real_num_rx_queues(slave->ndev,
2429                                                    cpsw->rx_ch_num);
2430                 if (ret) {
2431                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2432                         goto err;
2433                 }
2434         }
2435
2436         if (cpsw->usage_count)
2437                 cpsw_split_res(ndev);
2438
2439         ret = cpsw_resume_data_pass(ndev);
2440         if (!ret)
2441                 return 0;
2442 err:
2443         dev_err(priv->dev, "cannot update channels number, closing device\n");
2444         dev_close(ndev);
2445         return ret;
2446 }
2447
2448 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2449 {
2450         struct cpsw_priv *priv = netdev_priv(ndev);
2451         struct cpsw_common *cpsw = priv->cpsw;
2452         int slave_no = cpsw_slave_index(cpsw, priv);
2453
2454         if (cpsw->slaves[slave_no].phy)
2455                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2456         else
2457                 return -EOPNOTSUPP;
2458 }
2459
2460 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2461 {
2462         struct cpsw_priv *priv = netdev_priv(ndev);
2463         struct cpsw_common *cpsw = priv->cpsw;
2464         int slave_no = cpsw_slave_index(cpsw, priv);
2465
2466         if (cpsw->slaves[slave_no].phy)
2467                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2468         else
2469                 return -EOPNOTSUPP;
2470 }
2471
2472 static int cpsw_nway_reset(struct net_device *ndev)
2473 {
2474         struct cpsw_priv *priv = netdev_priv(ndev);
2475         struct cpsw_common *cpsw = priv->cpsw;
2476         int slave_no = cpsw_slave_index(cpsw, priv);
2477
2478         if (cpsw->slaves[slave_no].phy)
2479                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2480         else
2481                 return -EOPNOTSUPP;
2482 }
2483
2484 static void cpsw_get_ringparam(struct net_device *ndev,
2485                                struct ethtool_ringparam *ering)
2486 {
2487         struct cpsw_priv *priv = netdev_priv(ndev);
2488         struct cpsw_common *cpsw = priv->cpsw;
2489
2490         /* not supported */
2491         ering->tx_max_pending = 0;
2492         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2493         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2494         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2495 }
2496
2497 static int cpsw_set_ringparam(struct net_device *ndev,
2498                               struct ethtool_ringparam *ering)
2499 {
2500         struct cpsw_priv *priv = netdev_priv(ndev);
2501         struct cpsw_common *cpsw = priv->cpsw;
2502         int ret;
2503
2504         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2505
2506         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2507             ering->rx_pending < CPSW_MAX_QUEUES ||
2508             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2509                 return -EINVAL;
2510
2511         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2512                 return 0;
2513
2514         cpsw_suspend_data_pass(ndev);
2515
2516         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2517
2518         if (cpsw->usage_count)
2519                 cpdma_chan_split_pool(cpsw->dma);
2520
2521         ret = cpsw_resume_data_pass(ndev);
2522         if (!ret)
2523                 return 0;
2524
2525         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2526         dev_close(ndev);
2527         return ret;
2528 }
2529
2530 static const struct ethtool_ops cpsw_ethtool_ops = {
2531         .get_drvinfo    = cpsw_get_drvinfo,
2532         .get_msglevel   = cpsw_get_msglevel,
2533         .set_msglevel   = cpsw_set_msglevel,
2534         .get_link       = ethtool_op_get_link,
2535         .get_ts_info    = cpsw_get_ts_info,
2536         .get_coalesce   = cpsw_get_coalesce,
2537         .set_coalesce   = cpsw_set_coalesce,
2538         .get_sset_count         = cpsw_get_sset_count,
2539         .get_strings            = cpsw_get_strings,
2540         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2541         .get_pauseparam         = cpsw_get_pauseparam,
2542         .set_pauseparam         = cpsw_set_pauseparam,
2543         .get_wol        = cpsw_get_wol,
2544         .set_wol        = cpsw_set_wol,
2545         .get_regs_len   = cpsw_get_regs_len,
2546         .get_regs       = cpsw_get_regs,
2547         .begin          = cpsw_ethtool_op_begin,
2548         .complete       = cpsw_ethtool_op_complete,
2549         .get_channels   = cpsw_get_channels,
2550         .set_channels   = cpsw_set_channels,
2551         .get_link_ksettings     = cpsw_get_link_ksettings,
2552         .set_link_ksettings     = cpsw_set_link_ksettings,
2553         .get_eee        = cpsw_get_eee,
2554         .set_eee        = cpsw_set_eee,
2555         .nway_reset     = cpsw_nway_reset,
2556         .get_ringparam = cpsw_get_ringparam,
2557         .set_ringparam = cpsw_set_ringparam,
2558 };
2559
2560 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2561                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2562 {
2563         void __iomem            *regs = cpsw->regs;
2564         int                     slave_num = slave->slave_num;
2565         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2566
2567         slave->data     = data;
2568         slave->regs     = regs + slave_reg_ofs;
2569         slave->sliver   = regs + sliver_reg_ofs;
2570         slave->port_vlan = data->dual_emac_res_vlan;
2571 }
2572
2573 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2574                          struct platform_device *pdev)
2575 {
2576         struct device_node *node = pdev->dev.of_node;
2577         struct device_node *slave_node;
2578         int i = 0, ret;
2579         u32 prop;
2580
2581         if (!node)
2582                 return -EINVAL;
2583
2584         if (of_property_read_u32(node, "slaves", &prop)) {
2585                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2586                 return -EINVAL;
2587         }
2588         data->slaves = prop;
2589
2590         if (of_property_read_u32(node, "active_slave", &prop)) {
2591                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2592                 return -EINVAL;
2593         }
2594         data->active_slave = prop;
2595
2596         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2597                                         * sizeof(struct cpsw_slave_data),
2598                                         GFP_KERNEL);
2599         if (!data->slave_data)
2600                 return -ENOMEM;
2601
2602         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2603                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2604                 return -EINVAL;
2605         }
2606         data->channels = prop;
2607
2608         if (of_property_read_u32(node, "ale_entries", &prop)) {
2609                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2610                 return -EINVAL;
2611         }
2612         data->ale_entries = prop;
2613
2614         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2615                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2616                 return -EINVAL;
2617         }
2618         data->bd_ram_size = prop;
2619
2620         if (of_property_read_u32(node, "mac_control", &prop)) {
2621                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2622                 return -EINVAL;
2623         }
2624         data->mac_control = prop;
2625
2626         if (of_property_read_bool(node, "dual_emac"))
2627                 data->dual_emac = 1;
2628
2629         /*
2630          * Populate all the child nodes here...
2631          */
2632         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2633         /* We do not want to force this, as in some cases may not have child */
2634         if (ret)
2635                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2636
2637         for_each_available_child_of_node(node, slave_node) {
2638                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2639                 const void *mac_addr = NULL;
2640                 int lenp;
2641                 const __be32 *parp;
2642
2643                 /* This is no slave child node, continue */
2644                 if (strcmp(slave_node->name, "slave"))
2645                         continue;
2646
2647                 slave_data->phy_node = of_parse_phandle(slave_node,
2648                                                         "phy-handle", 0);
2649                 parp = of_get_property(slave_node, "phy_id", &lenp);
2650                 if (slave_data->phy_node) {
2651                         dev_dbg(&pdev->dev,
2652                                 "slave[%d] using phy-handle=\"%s\"\n",
2653                                 i, slave_data->phy_node->full_name);
2654                 } else if (of_phy_is_fixed_link(slave_node)) {
2655                         /* In the case of a fixed PHY, the DT node associated
2656                          * to the PHY is the Ethernet MAC DT node.
2657                          */
2658                         ret = of_phy_register_fixed_link(slave_node);
2659                         if (ret) {
2660                                 if (ret != -EPROBE_DEFER)
2661                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2662                                 return ret;
2663                         }
2664                         slave_data->phy_node = of_node_get(slave_node);
2665                 } else if (parp) {
2666                         u32 phyid;
2667                         struct device_node *mdio_node;
2668                         struct platform_device *mdio;
2669
2670                         if (lenp != (sizeof(__be32) * 2)) {
2671                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2672                                 goto no_phy_slave;
2673                         }
2674                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2675                         phyid = be32_to_cpup(parp+1);
2676                         mdio = of_find_device_by_node(mdio_node);
2677                         of_node_put(mdio_node);
2678                         if (!mdio) {
2679                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2680                                 return -EINVAL;
2681                         }
2682                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2683                                  PHY_ID_FMT, mdio->name, phyid);
2684                         put_device(&mdio->dev);
2685                 } else {
2686                         dev_err(&pdev->dev,
2687                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2688                                 i);
2689                         goto no_phy_slave;
2690                 }
2691                 slave_data->phy_if = of_get_phy_mode(slave_node);
2692                 if (slave_data->phy_if < 0) {
2693                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2694                                 i);
2695                         return slave_data->phy_if;
2696                 }
2697
2698 no_phy_slave:
2699                 mac_addr = of_get_mac_address(slave_node);
2700                 if (mac_addr) {
2701                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2702                 } else {
2703                         ret = ti_cm_get_macid(&pdev->dev, i,
2704                                               slave_data->mac_addr);
2705                         if (ret)
2706                                 return ret;
2707                 }
2708                 if (data->dual_emac) {
2709                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2710                                                  &prop)) {
2711                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2712                                 slave_data->dual_emac_res_vlan = i+1;
2713                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2714                                         slave_data->dual_emac_res_vlan, i);
2715                         } else {
2716                                 slave_data->dual_emac_res_vlan = prop;
2717                         }
2718                 }
2719
2720                 i++;
2721                 if (i == data->slaves)
2722                         break;
2723         }
2724
2725         return 0;
2726 }
2727
2728 static void cpsw_remove_dt(struct platform_device *pdev)
2729 {
2730         struct net_device *ndev = platform_get_drvdata(pdev);
2731         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2732         struct cpsw_platform_data *data = &cpsw->data;
2733         struct device_node *node = pdev->dev.of_node;
2734         struct device_node *slave_node;
2735         int i = 0;
2736
2737         for_each_available_child_of_node(node, slave_node) {
2738                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2739
2740                 if (strcmp(slave_node->name, "slave"))
2741                         continue;
2742
2743                 if (of_phy_is_fixed_link(slave_node))
2744                         of_phy_deregister_fixed_link(slave_node);
2745
2746                 of_node_put(slave_data->phy_node);
2747
2748                 i++;
2749                 if (i == data->slaves)
2750                         break;
2751         }
2752
2753         of_platform_depopulate(&pdev->dev);
2754 }
2755
2756 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2757 {
2758         struct cpsw_common              *cpsw = priv->cpsw;
2759         struct cpsw_platform_data       *data = &cpsw->data;
2760         struct net_device               *ndev;
2761         struct cpsw_priv                *priv_sl2;
2762         int ret = 0;
2763
2764         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2765         if (!ndev) {
2766                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2767                 return -ENOMEM;
2768         }
2769
2770         priv_sl2 = netdev_priv(ndev);
2771         priv_sl2->cpsw = cpsw;
2772         priv_sl2->ndev = ndev;
2773         priv_sl2->dev  = &ndev->dev;
2774         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2775
2776         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2777                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2778                         ETH_ALEN);
2779                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2780                          priv_sl2->mac_addr);
2781         } else {
2782                 random_ether_addr(priv_sl2->mac_addr);
2783                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2784                          priv_sl2->mac_addr);
2785         }
2786         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2787
2788         priv_sl2->emac_port = 1;
2789         cpsw->slaves[1].ndev = ndev;
2790         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2791
2792         ndev->netdev_ops = &cpsw_netdev_ops;
2793         ndev->ethtool_ops = &cpsw_ethtool_ops;
2794
2795         /* register the network device */
2796         SET_NETDEV_DEV(ndev, cpsw->dev);
2797         ret = register_netdev(ndev);
2798         if (ret) {
2799                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2800                 free_netdev(ndev);
2801                 ret = -ENODEV;
2802         }
2803
2804         return ret;
2805 }
2806
2807 #define CPSW_QUIRK_IRQ          BIT(0)
2808
2809 static struct platform_device_id cpsw_devtype[] = {
2810         {
2811                 /* keep it for existing comaptibles */
2812                 .name = "cpsw",
2813                 .driver_data = CPSW_QUIRK_IRQ,
2814         }, {
2815                 .name = "am335x-cpsw",
2816                 .driver_data = CPSW_QUIRK_IRQ,
2817         }, {
2818                 .name = "am4372-cpsw",
2819                 .driver_data = 0,
2820         }, {
2821                 .name = "dra7-cpsw",
2822                 .driver_data = 0,
2823         }, {
2824                 /* sentinel */
2825         }
2826 };
2827 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2828
2829 enum ti_cpsw_type {
2830         CPSW = 0,
2831         AM335X_CPSW,
2832         AM4372_CPSW,
2833         DRA7_CPSW,
2834 };
2835
2836 static const struct of_device_id cpsw_of_mtable[] = {
2837         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2838         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2839         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2840         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2841         { /* sentinel */ },
2842 };
2843 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2844
2845 static int cpsw_probe(struct platform_device *pdev)
2846 {
2847         struct clk                      *clk;
2848         struct cpsw_platform_data       *data;
2849         struct net_device               *ndev;
2850         struct cpsw_priv                *priv;
2851         struct cpdma_params             dma_params;
2852         struct cpsw_ale_params          ale_params;
2853         void __iomem                    *ss_regs;
2854         void __iomem                    *cpts_regs;
2855         struct resource                 *res, *ss_res;
2856         const struct of_device_id       *of_id;
2857         struct gpio_descs               *mode;
2858         u32 slave_offset, sliver_offset, slave_size;
2859         struct cpsw_common              *cpsw;
2860         int ret = 0, i;
2861         int irq;
2862
2863         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2864         if (!cpsw)
2865                 return -ENOMEM;
2866
2867         cpsw->dev = &pdev->dev;
2868
2869         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2870         if (!ndev) {
2871                 dev_err(&pdev->dev, "error allocating net_device\n");
2872                 return -ENOMEM;
2873         }
2874
2875         platform_set_drvdata(pdev, ndev);
2876         priv = netdev_priv(ndev);
2877         priv->cpsw = cpsw;
2878         priv->ndev = ndev;
2879         priv->dev  = &ndev->dev;
2880         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2881         cpsw->rx_packet_max = max(rx_packet_max, 128);
2882
2883         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2884         if (IS_ERR(mode)) {
2885                 ret = PTR_ERR(mode);
2886                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2887                 goto clean_ndev_ret;
2888         }
2889
2890         /*
2891          * This may be required here for child devices.
2892          */
2893         pm_runtime_enable(&pdev->dev);
2894
2895         /* Select default pin state */
2896         pinctrl_pm_select_default_state(&pdev->dev);
2897
2898         /* Need to enable clocks with runtime PM api to access module
2899          * registers
2900          */
2901         ret = pm_runtime_get_sync(&pdev->dev);
2902         if (ret < 0) {
2903                 pm_runtime_put_noidle(&pdev->dev);
2904                 goto clean_runtime_disable_ret;
2905         }
2906
2907         ret = cpsw_probe_dt(&cpsw->data, pdev);
2908         if (ret)
2909                 goto clean_dt_ret;
2910
2911         data = &cpsw->data;
2912         cpsw->rx_ch_num = 1;
2913         cpsw->tx_ch_num = 1;
2914
2915         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2916                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2917                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2918         } else {
2919                 eth_random_addr(priv->mac_addr);
2920                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2921         }
2922
2923         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2924
2925         cpsw->slaves = devm_kzalloc(&pdev->dev,
2926                                     sizeof(struct cpsw_slave) * data->slaves,
2927                                     GFP_KERNEL);
2928         if (!cpsw->slaves) {
2929                 ret = -ENOMEM;
2930                 goto clean_dt_ret;
2931         }
2932         for (i = 0; i < data->slaves; i++)
2933                 cpsw->slaves[i].slave_num = i;
2934
2935         cpsw->slaves[0].ndev = ndev;
2936         priv->emac_port = 0;
2937
2938         clk = devm_clk_get(&pdev->dev, "fck");
2939         if (IS_ERR(clk)) {
2940                 dev_err(priv->dev, "fck is not found\n");
2941                 ret = -ENODEV;
2942                 goto clean_dt_ret;
2943         }
2944         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2945
2946         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2947         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2948         if (IS_ERR(ss_regs)) {
2949                 ret = PTR_ERR(ss_regs);
2950                 goto clean_dt_ret;
2951         }
2952         cpsw->regs = ss_regs;
2953
2954         cpsw->version = readl(&cpsw->regs->id_ver);
2955
2956         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2957         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2958         if (IS_ERR(cpsw->wr_regs)) {
2959                 ret = PTR_ERR(cpsw->wr_regs);
2960                 goto clean_dt_ret;
2961         }
2962
2963         memset(&dma_params, 0, sizeof(dma_params));
2964         memset(&ale_params, 0, sizeof(ale_params));
2965
2966         switch (cpsw->version) {
2967         case CPSW_VERSION_1:
2968                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2969                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
2970                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
2971                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2972                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2973                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2974                 slave_offset         = CPSW1_SLAVE_OFFSET;
2975                 slave_size           = CPSW1_SLAVE_SIZE;
2976                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2977                 dma_params.desc_mem_phys = 0;
2978                 break;
2979         case CPSW_VERSION_2:
2980         case CPSW_VERSION_3:
2981         case CPSW_VERSION_4:
2982                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2983                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
2984                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
2985                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2986                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2987                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2988                 slave_offset         = CPSW2_SLAVE_OFFSET;
2989                 slave_size           = CPSW2_SLAVE_SIZE;
2990                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2991                 dma_params.desc_mem_phys =
2992                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2993                 break;
2994         default:
2995                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2996                 ret = -ENODEV;
2997                 goto clean_dt_ret;
2998         }
2999         for (i = 0; i < cpsw->data.slaves; i++) {
3000                 struct cpsw_slave *slave = &cpsw->slaves[i];
3001
3002                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3003                 slave_offset  += slave_size;
3004                 sliver_offset += SLIVER_SIZE;
3005         }
3006
3007         dma_params.dev          = &pdev->dev;
3008         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3009         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3010         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3011         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3012         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3013
3014         dma_params.num_chan             = data->channels;
3015         dma_params.has_soft_reset       = true;
3016         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3017         dma_params.desc_mem_size        = data->bd_ram_size;
3018         dma_params.desc_align           = 16;
3019         dma_params.has_ext_regs         = true;
3020         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3021         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3022         dma_params.descs_pool_size      = descs_pool_size;
3023
3024         cpsw->dma = cpdma_ctlr_create(&dma_params);
3025         if (!cpsw->dma) {
3026                 dev_err(priv->dev, "error initializing dma\n");
3027                 ret = -ENOMEM;
3028                 goto clean_dt_ret;
3029         }
3030
3031         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3032         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3033         if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
3034                 dev_err(priv->dev, "error initializing dma channels\n");
3035                 ret = -ENOMEM;
3036                 goto clean_dma_ret;
3037         }
3038
3039         ale_params.dev                  = &pdev->dev;
3040         ale_params.ale_ageout           = ale_ageout;
3041         ale_params.ale_entries          = data->ale_entries;
3042         ale_params.ale_ports            = data->slaves;
3043
3044         cpsw->ale = cpsw_ale_create(&ale_params);
3045         if (!cpsw->ale) {
3046                 dev_err(priv->dev, "error initializing ale engine\n");
3047                 ret = -ENODEV;
3048                 goto clean_dma_ret;
3049         }
3050
3051         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3052         if (IS_ERR(cpsw->cpts)) {
3053                 ret = PTR_ERR(cpsw->cpts);
3054                 goto clean_ale_ret;
3055         }
3056
3057         ndev->irq = platform_get_irq(pdev, 1);
3058         if (ndev->irq < 0) {
3059                 dev_err(priv->dev, "error getting irq resource\n");
3060                 ret = ndev->irq;
3061                 goto clean_ale_ret;
3062         }
3063
3064         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3065         if (of_id) {
3066                 pdev->id_entry = of_id->data;
3067                 if (pdev->id_entry->driver_data)
3068                         cpsw->quirk_irq = true;
3069         }
3070
3071         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3072          * MISC IRQs which are always kept disabled with this driver so
3073          * we will not request them.
3074          *
3075          * If anyone wants to implement support for those, make sure to
3076          * first request and append them to irqs_table array.
3077          */
3078
3079         /* RX IRQ */
3080         irq = platform_get_irq(pdev, 1);
3081         if (irq < 0) {
3082                 ret = irq;
3083                 goto clean_ale_ret;
3084         }
3085
3086         cpsw->irqs_table[0] = irq;
3087         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3088                                0, dev_name(&pdev->dev), cpsw);
3089         if (ret < 0) {
3090                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3091                 goto clean_ale_ret;
3092         }
3093
3094         /* TX IRQ */
3095         irq = platform_get_irq(pdev, 2);
3096         if (irq < 0) {
3097                 ret = irq;
3098                 goto clean_ale_ret;
3099         }
3100
3101         cpsw->irqs_table[1] = irq;
3102         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3103                                0, dev_name(&pdev->dev), cpsw);
3104         if (ret < 0) {
3105                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3106                 goto clean_ale_ret;
3107         }
3108
3109         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3110
3111         ndev->netdev_ops = &cpsw_netdev_ops;
3112         ndev->ethtool_ops = &cpsw_ethtool_ops;
3113         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3114         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3115         cpsw_split_res(ndev);
3116
3117         /* register the network device */
3118         SET_NETDEV_DEV(ndev, &pdev->dev);
3119         ret = register_netdev(ndev);
3120         if (ret) {
3121                 dev_err(priv->dev, "error registering net device\n");
3122                 ret = -ENODEV;
3123                 goto clean_ale_ret;
3124         }
3125
3126         cpsw_notice(priv, probe,
3127                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3128                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3129         if (cpsw->data.dual_emac) {
3130                 ret = cpsw_probe_dual_emac(priv);
3131                 if (ret) {
3132                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3133                         goto clean_unregister_netdev_ret;
3134                 }
3135         }
3136
3137         pm_runtime_put(&pdev->dev);
3138
3139         return 0;
3140
3141 clean_unregister_netdev_ret:
3142         unregister_netdev(ndev);
3143 clean_ale_ret:
3144         cpsw_ale_destroy(cpsw->ale);
3145 clean_dma_ret:
3146         cpdma_ctlr_destroy(cpsw->dma);
3147 clean_dt_ret:
3148         cpsw_remove_dt(pdev);
3149         pm_runtime_put_sync(&pdev->dev);
3150 clean_runtime_disable_ret:
3151         pm_runtime_disable(&pdev->dev);
3152 clean_ndev_ret:
3153         free_netdev(priv->ndev);
3154         return ret;
3155 }
3156
3157 static int cpsw_remove(struct platform_device *pdev)
3158 {
3159         struct net_device *ndev = platform_get_drvdata(pdev);
3160         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3161         int ret;
3162
3163         ret = pm_runtime_get_sync(&pdev->dev);
3164         if (ret < 0) {
3165                 pm_runtime_put_noidle(&pdev->dev);
3166                 return ret;
3167         }
3168
3169         if (cpsw->data.dual_emac)
3170                 unregister_netdev(cpsw->slaves[1].ndev);
3171         unregister_netdev(ndev);
3172
3173         cpts_release(cpsw->cpts);
3174         cpsw_ale_destroy(cpsw->ale);
3175         cpdma_ctlr_destroy(cpsw->dma);
3176         cpsw_remove_dt(pdev);
3177         pm_runtime_put_sync(&pdev->dev);
3178         pm_runtime_disable(&pdev->dev);
3179         if (cpsw->data.dual_emac)
3180                 free_netdev(cpsw->slaves[1].ndev);
3181         free_netdev(ndev);
3182         return 0;
3183 }
3184
3185 #ifdef CONFIG_PM_SLEEP
3186 static int cpsw_suspend(struct device *dev)
3187 {
3188         struct platform_device  *pdev = to_platform_device(dev);
3189         struct net_device       *ndev = platform_get_drvdata(pdev);
3190         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3191
3192         if (cpsw->data.dual_emac) {
3193                 int i;
3194
3195                 for (i = 0; i < cpsw->data.slaves; i++) {
3196                         if (netif_running(cpsw->slaves[i].ndev))
3197                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3198                 }
3199         } else {
3200                 if (netif_running(ndev))
3201                         cpsw_ndo_stop(ndev);
3202         }
3203
3204         /* Select sleep pin state */
3205         pinctrl_pm_select_sleep_state(dev);
3206
3207         return 0;
3208 }
3209
3210 static int cpsw_resume(struct device *dev)
3211 {
3212         struct platform_device  *pdev = to_platform_device(dev);
3213         struct net_device       *ndev = platform_get_drvdata(pdev);
3214         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3215
3216         /* Select default pin state */
3217         pinctrl_pm_select_default_state(dev);
3218
3219         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3220         rtnl_lock();
3221         if (cpsw->data.dual_emac) {
3222                 int i;
3223
3224                 for (i = 0; i < cpsw->data.slaves; i++) {
3225                         if (netif_running(cpsw->slaves[i].ndev))
3226                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3227                 }
3228         } else {
3229                 if (netif_running(ndev))
3230                         cpsw_ndo_open(ndev);
3231         }
3232         rtnl_unlock();
3233
3234         return 0;
3235 }
3236 #endif
3237
3238 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3239
3240 static struct platform_driver cpsw_driver = {
3241         .driver = {
3242                 .name    = "cpsw",
3243                 .pm      = &cpsw_pm_ops,
3244                 .of_match_table = cpsw_of_mtable,
3245         },
3246         .probe = cpsw_probe,
3247         .remove = cpsw_remove,
3248 };
3249
3250 module_platform_driver(cpsw_driver);
3251
3252 MODULE_LICENSE("GPL");
3253 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3254 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3255 MODULE_DESCRIPTION("TI CPSW Ethernet driver");