drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio/consumer.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/kmemleak.h>
  39 #include <linux/sys_soc.h>
  40
  41 #include <linux/pinctrl/consumer.h>
  42
  43 #include "cpsw.h"
  44 #include "cpsw_ale.h"
  45 #include "cpts.h"
  46 #include "davinci_cpdma.h"
  47
  48 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  49                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  50                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  51                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  52                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  53                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  54                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  55                          NETIF_MSG_RX_STATUS)
  56
  57 #define cpsw_info(priv, type, format, ...)              \
  58 do {                                                            \
  59         if (netif_msg_##type(priv) && net_ratelimit())          \
  60                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  61 } while (0)
  62
  63 #define cpsw_err(priv, type, format, ...)               \
  64 do {                                                            \
  65         if (netif_msg_##type(priv) && net_ratelimit())          \
  66                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  67 } while (0)
  68
  69 #define cpsw_dbg(priv, type, format, ...)               \
  70 do {                                                            \
  71         if (netif_msg_##type(priv) && net_ratelimit())          \
  72                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  73 } while (0)
  74
  75 #define cpsw_notice(priv, type, format, ...)            \
  76 do {                                                            \
  77         if (netif_msg_##type(priv) && net_ratelimit())          \
  78                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  79 } while (0)
  80
  81 #define ALE_ALL_PORTS           0x7
  82
  83 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  84 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  85 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  86
  87 #define CPSW_VERSION_1          0x19010a
  88 #define CPSW_VERSION_2          0x19010c
  89 #define CPSW_VERSION_3          0x19010f
  90 #define CPSW_VERSION_4          0x190112
  91
  92 #define HOST_PORT_NUM           0
  93 #define CPSW_ALE_PORTS_NUM      3
  94 #define SLIVER_SIZE             0x40
  95
  96 #define CPSW1_HOST_PORT_OFFSET  0x028
  97 #define CPSW1_SLAVE_OFFSET      0x050
  98 #define CPSW1_SLAVE_SIZE        0x040
  99 #define CPSW1_CPDMA_OFFSET      0x100
 100 #define CPSW1_STATERAM_OFFSET   0x200
 101 #define CPSW1_HW_STATS          0x400
 102 #define CPSW1_CPTS_OFFSET       0x500
 103 #define CPSW1_ALE_OFFSET        0x600
 104 #define CPSW1_SLIVER_OFFSET     0x700
 105
 106 #define CPSW2_HOST_PORT_OFFSET  0x108
 107 #define CPSW2_SLAVE_OFFSET      0x200
 108 #define CPSW2_SLAVE_SIZE        0x100
 109 #define CPSW2_CPDMA_OFFSET      0x800
 110 #define CPSW2_HW_STATS          0x900
 111 #define CPSW2_STATERAM_OFFSET   0xa00
 112 #define CPSW2_CPTS_OFFSET       0xc00
 113 #define CPSW2_ALE_OFFSET        0xd00
 114 #define CPSW2_SLIVER_OFFSET     0xd80
 115 #define CPSW2_BD_OFFSET         0x2000
 116
 117 #define CPDMA_RXTHRESH          0x0c0
 118 #define CPDMA_RXFREE            0x0e0
 119 #define CPDMA_TXHDP             0x00
 120 #define CPDMA_RXHDP             0x20
 121 #define CPDMA_TXCP              0x40
 122 #define CPDMA_RXCP              0x60
 123
 124 #define CPSW_POLL_WEIGHT        64
 125 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE             4
 126 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
 127 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN +\
 128                                  ETH_FCS_LEN +\
 129                                  CPSW_RX_VLAN_ENCAP_HDR_SIZE)
 130
 131 #define RX_PRIORITY_MAPPING     0x76543210
 132 #define TX_PRIORITY_MAPPING     0x33221100
 133 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 134
 135 #define CPSW_VLAN_AWARE         BIT(1)
 136 #define CPSW_RX_VLAN_ENCAP      BIT(2)
 137 #define CPSW_ALE_VLAN_AWARE     1
 138
 139 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 140 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 141 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 142
 143 #define CPSW_INTPACEEN          (0x3f << 16)
 144 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 145 #define CPSW_CMINTMAX_CNT       63
 146 #define CPSW_CMINTMIN_CNT       2
 147 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 148 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 149
 150 #define cpsw_slave_index(cpsw, priv)                            \
 151                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 152                 cpsw->data.active_slave)
 153 #define IRQ_NUM                 2
 154 #define CPSW_MAX_QUEUES         8
 155 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 156
 157 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT       29
 158 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK         GENMASK(2, 0)
 159 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT        16
 160 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT   8
 161 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK     GENMASK(1, 0)
 162 enum {
 163         CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
 164         CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
 165         CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
 166         CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
 167 };
 168
 169 static int debug_level;
 170 module_param(debug_level, int, 0);
 171 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 172
 173 static int ale_ageout = 10;
 174 module_param(ale_ageout, int, 0);
 175 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 176
 177 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 178 module_param(rx_packet_max, int, 0);
 179 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 180
 181 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 182 module_param(descs_pool_size, int, 0444);
 183 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 184
 185 struct cpsw_wr_regs {
 186         u32     id_ver;
 187         u32     soft_reset;
 188         u32     control;
 189         u32     int_control;
 190         u32     rx_thresh_en;
 191         u32     rx_en;
 192         u32     tx_en;
 193         u32     misc_en;
 194         u32     mem_allign1[8];
 195         u32     rx_thresh_stat;
 196         u32     rx_stat;
 197         u32     tx_stat;
 198         u32     misc_stat;
 199         u32     mem_allign2[8];
 200         u32     rx_imax;
 201         u32     tx_imax;
 202
 203 };
 204
 205 struct cpsw_ss_regs {
 206         u32     id_ver;
 207         u32     control;
 208         u32     soft_reset;
 209         u32     stat_port_en;
 210         u32     ptype;
 211         u32     soft_idle;
 212         u32     thru_rate;
 213         u32     gap_thresh;
 214         u32     tx_start_wds;
 215         u32     flow_control;
 216         u32     vlan_ltype;
 217         u32     ts_ltype;
 218         u32     dlr_ltype;
 219 };
 220
 221 /* CPSW_PORT_V1 */
 222 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 223 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 224 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 225 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 226 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 227 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 228 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 229 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 230
 231 /* CPSW_PORT_V2 */
 232 #define CPSW2_CONTROL       0x00 /* Control Register */
 233 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 234 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 235 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 236 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 237 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 238 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 239
 240 /* CPSW_PORT_V1 and V2 */
 241 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 242 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 243 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 244
 245 /* CPSW_PORT_V2 only */
 246 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 247 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 248 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 249 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 250 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 251 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 252 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 253 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 254
 255 /* Bit definitions for the CPSW2_CONTROL register */
 256 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 257 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 258 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 259 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 260 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 261 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 262 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 263 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 264 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 265 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 266 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 267 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 268 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 269 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 270 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 271 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 272 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 273
 274 #define CTRL_V2_TS_BITS \
 275         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 276          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 277
 278 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 279 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 280 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 281
 282
 283 #define CTRL_V3_TS_BITS \
 284         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 285          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 286          TS_LTYPE1_EN)
 287
 288 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 289 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 290 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 291
 292 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 293 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 294 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 295 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 296 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 297
 298 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 299 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 300
 301 /* Bit definitions for the CPSW1_TS_CTL register */
 302 #define CPSW_V1_TS_RX_EN                BIT(0)
 303 #define CPSW_V1_TS_TX_EN                BIT(4)
 304 #define CPSW_V1_MSG_TYPE_OFS            16
 305
 306 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 307 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 308
 309 #define CPSW_MAX_BLKS_TX                15
 310 #define CPSW_MAX_BLKS_TX_SHIFT          4
 311 #define CPSW_MAX_BLKS_RX                5
 312
 313 struct cpsw_host_regs {
 314         u32     max_blks;
 315         u32     blk_cnt;
 316         u32     tx_in_ctl;
 317         u32     port_vlan;
 318         u32     tx_pri_map;
 319         u32     cpdma_tx_pri_map;
 320         u32     cpdma_rx_chan_map;
 321 };
 322
 323 struct cpsw_sliver_regs {
 324         u32     id_ver;
 325         u32     mac_control;
 326         u32     mac_status;
 327         u32     soft_reset;
 328         u32     rx_maxlen;
 329         u32     __reserved_0;
 330         u32     rx_pause;
 331         u32     tx_pause;
 332         u32     __reserved_1;
 333         u32     rx_pri_map;
 334 };
 335
 336 struct cpsw_hw_stats {
 337         u32     rxgoodframes;
 338         u32     rxbroadcastframes;
 339         u32     rxmulticastframes;
 340         u32     rxpauseframes;
 341         u32     rxcrcerrors;
 342         u32     rxaligncodeerrors;
 343         u32     rxoversizedframes;
 344         u32     rxjabberframes;
 345         u32     rxundersizedframes;
 346         u32     rxfragments;
 347         u32     __pad_0[2];
 348         u32     rxoctets;
 349         u32     txgoodframes;
 350         u32     txbroadcastframes;
 351         u32     txmulticastframes;
 352         u32     txpauseframes;
 353         u32     txdeferredframes;
 354         u32     txcollisionframes;
 355         u32     txsinglecollframes;
 356         u32     txmultcollframes;
 357         u32     txexcessivecollisions;
 358         u32     txlatecollisions;
 359         u32     txunderrun;
 360         u32     txcarriersenseerrors;
 361         u32     txoctets;
 362         u32     octetframes64;
 363         u32     octetframes65t127;
 364         u32     octetframes128t255;
 365         u32     octetframes256t511;
 366         u32     octetframes512t1023;
 367         u32     octetframes1024tup;
 368         u32     netoctets;
 369         u32     rxsofoverruns;
 370         u32     rxmofoverruns;
 371         u32     rxdmaoverruns;
 372 };
 373
 374 struct cpsw_slave_data {
 375         struct device_node *phy_node;
 376         char            phy_id[MII_BUS_ID_SIZE];
 377         int             phy_if;
 378         u8              mac_addr[ETH_ALEN];
 379         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
 380 };
 381
 382 struct cpsw_platform_data {
 383         struct cpsw_slave_data  *slave_data;
 384         u32     ss_reg_ofs;     /* Subsystem control register offset */
 385         u32     channels;       /* number of cpdma channels (symmetric) */
 386         u32     slaves;         /* number of slave cpgmac ports */
 387         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
 388         u32     ale_entries;    /* ale table size */
 389         u32     bd_ram_size;  /*buffer descriptor ram size */
 390         u32     mac_control;    /* Mac control register */
 391         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
 392         bool    dual_emac;      /* Enable Dual EMAC mode */
 393 };
 394
 395 struct cpsw_slave {
 396         void __iomem                    *regs;
 397         struct cpsw_sliver_regs __iomem *sliver;
 398         int                             slave_num;
 399         u32                             mac_control;
 400         struct cpsw_slave_data          *data;
 401         struct phy_device               *phy;
 402         struct net_device               *ndev;
 403         u32                             port_vlan;
 404 };
 405
 406 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 407 {
 408         return readl_relaxed(slave->regs + offset);
 409 }
 410
 411 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 412 {
 413         writel_relaxed(val, slave->regs + offset);
 414 }
 415
 416 struct cpsw_vector {
 417         struct cpdma_chan *ch;
 418         int budget;
 419 };
 420
 421 struct cpsw_common {
 422         struct device                   *dev;
 423         struct cpsw_platform_data       data;
 424         struct napi_struct              napi_rx;
 425         struct napi_struct              napi_tx;
 426         struct cpsw_ss_regs __iomem     *regs;
 427         struct cpsw_wr_regs __iomem     *wr_regs;
 428         u8 __iomem                      *hw_stats;
 429         struct cpsw_host_regs __iomem   *host_port_regs;
 430         u32                             version;
 431         u32                             coal_intvl;
 432         u32                             bus_freq_mhz;
 433         int                             rx_packet_max;
 434         struct cpsw_slave               *slaves;
 435         struct cpdma_ctlr               *dma;
 436         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 437         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 438         struct cpsw_ale                 *ale;
 439         bool                            quirk_irq;
 440         bool                            rx_irq_disabled;
 441         bool                            tx_irq_disabled;
 442         u32 irqs_table[IRQ_NUM];
 443         struct cpts                     *cpts;
 444         int                             rx_ch_num, tx_ch_num;
 445         int                             speed;
 446         int                             usage_count;
 447 };
 448
 449 struct cpsw_priv {
 450         struct net_device               *ndev;
 451         struct device                   *dev;
 452         u32                             msg_enable;
 453         u8                              mac_addr[ETH_ALEN];
 454         bool                            rx_pause;
 455         bool                            tx_pause;
 456         u32 emac_port;
 457         struct cpsw_common *cpsw;
 458 };
 459
 460 struct cpsw_stats {
 461         char stat_string[ETH_GSTRING_LEN];
 462         int type;
 463         int sizeof_stat;
 464         int stat_offset;
 465 };
 466
 467 enum {
 468         CPSW_STATS,
 469         CPDMA_RX_STATS,
 470         CPDMA_TX_STATS,
 471 };
 472
 473 #define CPSW_STAT(m)            CPSW_STATS,                             \
 474                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 475                                 offsetof(struct cpsw_hw_stats, m)
 476 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 477                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 478                                 offsetof(struct cpdma_chan_stats, m)
 479 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 480                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 481                                 offsetof(struct cpdma_chan_stats, m)
 482
 483 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 484         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 485         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 486         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 487         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 488         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 489         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 490         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 491         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 492         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 493         { "Rx Fragments", CPSW_STAT(rxfragments) },
 494         { "Rx Octets", CPSW_STAT(rxoctets) },
 495         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 496         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 497         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 498         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 499         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 500         { "Collisions", CPSW_STAT(txcollisionframes) },
 501         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 502         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 503         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 504         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 505         { "Tx Underrun", CPSW_STAT(txunderrun) },
 506         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 507         { "Tx Octets", CPSW_STAT(txoctets) },
 508         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 509         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 510         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 511         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 512         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 513         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 514         { "Net Octets", CPSW_STAT(netoctets) },
 515         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 516         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 517         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 518 };
 519
 520 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 521         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 522         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 523         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 524         { "misqueued", CPDMA_RX_STAT(misqueued) },
 525         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 526         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 527         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 528         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 529         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 530         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 531         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 532         { "requeue", CPDMA_RX_STAT(requeue) },
 533         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 534 };
 535
 536 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 537 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 538
 539 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 540 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 541 #define for_each_slave(priv, func, arg...)                              \
 542         do {                                                            \
 543                 struct cpsw_slave *slave;                               \
 544                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 545                 int n;                                                  \
 546                 if (cpsw->data.dual_emac)                               \
 547                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 548                 else                                                    \
 549                         for (n = cpsw->data.slaves,                     \
 550                                         slave = cpsw->slaves;           \
 551                                         n; n--)                         \
 552                                 (func)(slave++, ##arg);                 \
 553         } while (0)
 554
 555 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 556         do {                                                            \
 557                 if (!cpsw->data.dual_emac)                              \
 558                         break;                                          \
 559                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 560                         ndev = cpsw->slaves[0].ndev;                    \
 561                         skb->dev = ndev;                                \
 562                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 563                         ndev = cpsw->slaves[1].ndev;                    \
 564                         skb->dev = ndev;                                \
 565                 }                                                       \
 566         } while (0)
 567 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 568         do {                                                            \
 569                 if (cpsw->data.dual_emac) {                             \
 570                         struct cpsw_slave *slave = cpsw->slaves +       \
 571                                                 priv->emac_port;        \
 572                         int slave_port = cpsw_get_slave_port(           \
 573                                                 slave->slave_num);      \
 574                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 575                                 1 << slave_port | ALE_PORT_HOST,        \
 576                                 ALE_VLAN, slave->port_vlan, 0);         \
 577                 } else {                                                \
 578                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 579                                 ALE_ALL_PORTS,                          \
 580                                 0, 0, 0);                               \
 581                 }                                                       \
 582         } while (0)
 583
 584 static inline int cpsw_get_slave_port(u32 slave_num)
 585 {
 586         return slave_num + 1;
 587 }
 588
 589 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 590 {
 591         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 592         struct cpsw_ale *ale = cpsw->ale;
 593         int i;
 594
 595         if (cpsw->data.dual_emac) {
 596                 bool flag = false;
 597
 598                 /* Enabling promiscuous mode for one interface will be
 599                  * common for both the interface as the interface shares
 600                  * the same hardware resource.
 601                  */
 602                 for (i = 0; i < cpsw->data.slaves; i++)
 603                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 604                                 flag = true;
 605
 606                 if (!enable && flag) {
 607                         enable = true;
 608                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 609                 }
 610
 611                 if (enable) {
 612                         /* Enable Bypass */
 613                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 614
 615                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 616                 } else {
 617                         /* Disable Bypass */
 618                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 619                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 620                 }
 621         } else {
 622                 if (enable) {
 623                         unsigned long timeout = jiffies + HZ;
 624
 625                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 626                         for (i = 0; i <= cpsw->data.slaves; i++) {
 627                                 cpsw_ale_control_set(ale, i,
 628                                                      ALE_PORT_NOLEARN, 1);
 629                                 cpsw_ale_control_set(ale, i,
 630                                                      ALE_PORT_NO_SA_UPDATE, 1);
 631                         }
 632
 633                         /* Clear All Untouched entries */
 634                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 635                         do {
 636                                 cpu_relax();
 637                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 638                                         break;
 639                         } while (time_after(timeout, jiffies));
 640                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 641
 642                         /* Clear all mcast from ALE */
 643                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 644
 645                         /* Flood All Unicast Packets to Host port */
 646                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 647                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 648                 } else {
 649                         /* Don't Flood All Unicast Packets to Host port */
 650                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 651
 652                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 653                         for (i = 0; i <= cpsw->data.slaves; i++) {
 654                                 cpsw_ale_control_set(ale, i,
 655                                                      ALE_PORT_NOLEARN, 0);
 656                                 cpsw_ale_control_set(ale, i,
 657                                                      ALE_PORT_NO_SA_UPDATE, 0);
 658                         }
 659                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 660                 }
 661         }
 662 }
 663
 664 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 665 {
 666         struct cpsw_priv *priv = netdev_priv(ndev);
 667         struct cpsw_common *cpsw = priv->cpsw;
 668         int vid;
 669
 670         if (cpsw->data.dual_emac)
 671                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 672         else
 673                 vid = cpsw->data.default_vlan;
 674
 675         if (ndev->flags & IFF_PROMISC) {
 676                 /* Enable promiscuous mode */
 677                 cpsw_set_promiscious(ndev, true);
 678                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 679                 return;
 680         } else {
 681                 /* Disable promiscuous mode */
 682                 cpsw_set_promiscious(ndev, false);
 683         }
 684
 685         /* Restore allmulti on vlans if necessary */
 686         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 687
 688         /* Clear all mcast from ALE */
 689         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 690
 691         if (!netdev_mc_empty(ndev)) {
 692                 struct netdev_hw_addr *ha;
 693
 694                 /* program multicast address list into ALE register */
 695                 netdev_for_each_mc_addr(ha, ndev) {
 696                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 697                 }
 698         }
 699 }
 700
 701 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 702 {
 703         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
 704         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
 705
 706         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 707         return;
 708 }
 709
 710 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 711 {
 712         writel_relaxed(0, &cpsw->wr_regs->tx_en);
 713         writel_relaxed(0, &cpsw->wr_regs->rx_en);
 714
 715         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 716         return;
 717 }
 718
 719 static void cpsw_tx_handler(void *token, int len, int status)
 720 {
 721         struct netdev_queue     *txq;
 722         struct sk_buff          *skb = token;
 723         struct net_device       *ndev = skb->dev;
 724         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 725
 726         /* Check whether the queue is stopped due to stalled tx dma, if the
 727          * queue is stopped then start the queue as we have free desc for tx
 728          */
 729         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 730         if (unlikely(netif_tx_queue_stopped(txq)))
 731                 netif_tx_wake_queue(txq);
 732
 733         cpts_tx_timestamp(cpsw->cpts, skb);
 734         ndev->stats.tx_packets++;
 735         ndev->stats.tx_bytes += len;
 736         dev_kfree_skb_any(skb);
 737 }
 738
 739 static void cpsw_rx_vlan_encap(struct sk_buff *skb)
 740 {
 741         struct cpsw_priv *priv = netdev_priv(skb->dev);
 742         struct cpsw_common *cpsw = priv->cpsw;
 743         u32 rx_vlan_encap_hdr = *((u32 *)skb->data);
 744         u16 vtag, vid, prio, pkt_type;
 745
 746         /* Remove VLAN header encapsulation word */
 747         skb_pull(skb, CPSW_RX_VLAN_ENCAP_HDR_SIZE);
 748
 749         pkt_type = (rx_vlan_encap_hdr >>
 750                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT) &
 751                     CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK;
 752         /* Ignore unknown & Priority-tagged packets*/
 753         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV ||
 754             pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG)
 755                 return;
 756
 757         vid = (rx_vlan_encap_hdr >>
 758                CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT) &
 759                VLAN_VID_MASK;
 760         /* Ignore vid 0 and pass packet as is */
 761         if (!vid)
 762                 return;
 763         /* Ignore default vlans in dual mac mode */
 764         if (cpsw->data.dual_emac &&
 765             vid == cpsw->slaves[priv->emac_port].port_vlan)
 766                 return;
 767
 768         prio = (rx_vlan_encap_hdr >>
 769                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT) &
 770                 CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK;
 771
 772         vtag = (prio << VLAN_PRIO_SHIFT) | vid;
 773         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
 774
 775         /* strip vlan tag for VLAN-tagged packet */
 776         if (pkt_type == CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG) {
 777                 memmove(skb->data + VLAN_HLEN, skb->data, 2 * ETH_ALEN);
 778                 skb_pull(skb, VLAN_HLEN);
 779         }
 780 }
 781
 782 static void cpsw_rx_handler(void *token, int len, int status)
 783 {
 784         struct cpdma_chan       *ch;
 785         struct sk_buff          *skb = token;
 786         struct sk_buff          *new_skb;
 787         struct net_device       *ndev = skb->dev;
 788         int                     ret = 0;
 789         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 790
 791         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 792
 793         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 794                 /* In dual emac mode check for all interfaces */
 795                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 796                     (status >= 0)) {
 797                         /* The packet received is for the interface which
 798                          * is already down and the other interface is up
 799                          * and running, instead of freeing which results
 800                          * in reducing of the number of rx descriptor in
 801                          * DMA engine, requeue skb back to cpdma.
 802                          */
 803                         new_skb = skb;
 804                         goto requeue;
 805                 }
 806
 807                 /* the interface is going down, skbs are purged */
 808                 dev_kfree_skb_any(skb);
 809                 return;
 810         }
 811
 812         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 813         if (new_skb) {
 814                 skb_copy_queue_mapping(new_skb, skb);
 815                 skb_put(skb, len);
 816                 if (status & CPDMA_RX_VLAN_ENCAP)
 817                         cpsw_rx_vlan_encap(skb);
 818                 cpts_rx_timestamp(cpsw->cpts, skb);
 819                 skb->protocol = eth_type_trans(skb, ndev);
 820                 netif_receive_skb(skb);
 821                 ndev->stats.rx_bytes += len;
 822                 ndev->stats.rx_packets++;
 823                 kmemleak_not_leak(new_skb);
 824         } else {
 825                 ndev->stats.rx_dropped++;
 826                 new_skb = skb;
 827         }
 828
 829 requeue:
 830         if (netif_dormant(ndev)) {
 831                 dev_kfree_skb_any(new_skb);
 832                 return;
 833         }
 834
 835         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 836         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 837                                 skb_tailroom(new_skb), 0);
 838         if (WARN_ON(ret < 0))
 839                 dev_kfree_skb_any(new_skb);
 840 }
 841
 842 static void cpsw_split_res(struct net_device *ndev)
 843 {
 844         struct cpsw_priv *priv = netdev_priv(ndev);
 845         u32 consumed_rate = 0, bigest_rate = 0;
 846         struct cpsw_common *cpsw = priv->cpsw;
 847         struct cpsw_vector *txv = cpsw->txv;
 848         int i, ch_weight, rlim_ch_num = 0;
 849         int budget, bigest_rate_ch = 0;
 850         u32 ch_rate, max_rate;
 851         int ch_budget = 0;
 852
 853         for (i = 0; i < cpsw->tx_ch_num; i++) {
 854                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 855                 if (!ch_rate)
 856                         continue;
 857
 858                 rlim_ch_num++;
 859                 consumed_rate += ch_rate;
 860         }
 861
 862         if (cpsw->tx_ch_num == rlim_ch_num) {
 863                 max_rate = consumed_rate;
 864         } else if (!rlim_ch_num) {
 865                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 866                 bigest_rate = 0;
 867                 max_rate = consumed_rate;
 868         } else {
 869                 max_rate = cpsw->speed * 1000;
 870
 871                 /* if max_rate is less then expected due to reduced link speed,
 872                  * split proportionally according next potential max speed
 873                  */
 874                 if (max_rate < consumed_rate)
 875                         max_rate *= 10;
 876
 877                 if (max_rate < consumed_rate)
 878                         max_rate *= 10;
 879
 880                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 881                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 882                             (cpsw->tx_ch_num - rlim_ch_num);
 883                 bigest_rate = (max_rate - consumed_rate) /
 884                               (cpsw->tx_ch_num - rlim_ch_num);
 885         }
 886
 887         /* split tx weight/budget */
 888         budget = CPSW_POLL_WEIGHT;
 889         for (i = 0; i < cpsw->tx_ch_num; i++) {
 890                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 891                 if (ch_rate) {
 892                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 893                         if (!txv[i].budget)
 894                                 txv[i].budget++;
 895                         if (ch_rate > bigest_rate) {
 896                                 bigest_rate_ch = i;
 897                                 bigest_rate = ch_rate;
 898                         }
 899
 900                         ch_weight = (ch_rate * 100) / max_rate;
 901                         if (!ch_weight)
 902                                 ch_weight++;
 903                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 904                 } else {
 905                         txv[i].budget = ch_budget;
 906                         if (!bigest_rate_ch)
 907                                 bigest_rate_ch = i;
 908                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 909                 }
 910
 911                 budget -= txv[i].budget;
 912         }
 913
 914         if (budget)
 915                 txv[bigest_rate_ch].budget += budget;
 916
 917         /* split rx budget */
 918         budget = CPSW_POLL_WEIGHT;
 919         ch_budget = budget / cpsw->rx_ch_num;
 920         for (i = 0; i < cpsw->rx_ch_num; i++) {
 921                 cpsw->rxv[i].budget = ch_budget;
 922                 budget -= ch_budget;
 923         }
 924
 925         if (budget)
 926                 cpsw->rxv[0].budget += budget;
 927 }
 928
 929 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 930 {
 931         struct cpsw_common *cpsw = dev_id;
 932
 933         writel(0, &cpsw->wr_regs->tx_en);
 934         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 935
 936         if (cpsw->quirk_irq) {
 937                 disable_irq_nosync(cpsw->irqs_table[1]);
 938                 cpsw->tx_irq_disabled = true;
 939         }
 940
 941         napi_schedule(&cpsw->napi_tx);
 942         return IRQ_HANDLED;
 943 }
 944
 945 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 946 {
 947         struct cpsw_common *cpsw = dev_id;
 948
 949         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 950         writel(0, &cpsw->wr_regs->rx_en);
 951
 952         if (cpsw->quirk_irq) {
 953                 disable_irq_nosync(cpsw->irqs_table[0]);
 954                 cpsw->rx_irq_disabled = true;
 955         }
 956
 957         napi_schedule(&cpsw->napi_rx);
 958         return IRQ_HANDLED;
 959 }
 960
 961 static int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget)
 962 {
 963         u32                     ch_map;
 964         int                     num_tx, cur_budget, ch;
 965         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 966         struct cpsw_vector      *txv;
 967
 968         /* process every unprocessed channel */
 969         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 970         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 971                 if (!(ch_map & 0x01))
 972                         continue;
 973
 974                 txv = &cpsw->txv[ch];
 975                 if (unlikely(txv->budget > budget - num_tx))
 976                         cur_budget = budget - num_tx;
 977                 else
 978                         cur_budget = txv->budget;
 979
 980                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 981                 if (num_tx >= budget)
 982                         break;
 983         }
 984
 985         if (num_tx < budget) {
 986                 napi_complete(napi_tx);
 987                 writel(0xff, &cpsw->wr_regs->tx_en);
 988         }
 989
 990         return num_tx;
 991 }
 992
 993 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 994 {
 995         struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
 996         int num_tx;
 997
 998         num_tx = cpdma_chan_process(cpsw->txv[0].ch, budget);
 999         if (num_tx < budget) {
1000                 napi_complete(napi_tx);
1001                 writel(0xff, &cpsw->wr_regs->tx_en);
1002                 if (cpsw->tx_irq_disabled) {
1003                         cpsw->tx_irq_disabled = false;
1004                         enable_irq(cpsw->irqs_table[1]);
1005                 }
1006         }
1007
1008         return num_tx;
1009 }
1010
1011 static int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget)
1012 {
1013         u32                     ch_map;
1014         int                     num_rx, cur_budget, ch;
1015         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
1016         struct cpsw_vector      *rxv;
1017
1018         /* process every unprocessed channel */
1019         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
1020         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
1021                 if (!(ch_map & 0x01))
1022                         continue;
1023
1024                 rxv = &cpsw->rxv[ch];
1025                 if (unlikely(rxv->budget > budget - num_rx))
1026                         cur_budget = budget - num_rx;
1027                 else
1028                         cur_budget = rxv->budget;
1029
1030                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
1031                 if (num_rx >= budget)
1032                         break;
1033         }
1034
1035         if (num_rx < budget) {
1036                 napi_complete_done(napi_rx, num_rx);
1037                 writel(0xff, &cpsw->wr_regs->rx_en);
1038         }
1039
1040         return num_rx;
1041 }
1042
1043 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
1044 {
1045         struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
1046         int num_rx;
1047
1048         num_rx = cpdma_chan_process(cpsw->rxv[0].ch, budget);
1049         if (num_rx < budget) {
1050                 napi_complete_done(napi_rx, num_rx);
1051                 writel(0xff, &cpsw->wr_regs->rx_en);
1052                 if (cpsw->rx_irq_disabled) {
1053                         cpsw->rx_irq_disabled = false;
1054                         enable_irq(cpsw->irqs_table[0]);
1055                 }
1056         }
1057
1058         return num_rx;
1059 }
1060
1061 static inline void soft_reset(const char *module, void __iomem *reg)
1062 {
1063         unsigned long timeout = jiffies + HZ;
1064
1065         writel_relaxed(1, reg);
1066         do {
1067                 cpu_relax();
1068         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
1069
1070         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
1071 }
1072
1073 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
1074                                struct cpsw_priv *priv)
1075 {
1076         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
1077         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
1078 }
1079
1080 static void _cpsw_adjust_link(struct cpsw_slave *slave,
1081                               struct cpsw_priv *priv, bool *link)
1082 {
1083         struct phy_device       *phy = slave->phy;
1084         u32                     mac_control = 0;
1085         u32                     slave_port;
1086         struct cpsw_common *cpsw = priv->cpsw;
1087
1088         if (!phy)
1089                 return;
1090
1091         slave_port = cpsw_get_slave_port(slave->slave_num);
1092
1093         if (phy->link) {
1094                 mac_control = cpsw->data.mac_control;
1095
1096                 /* enable forwarding */
1097                 cpsw_ale_control_set(cpsw->ale, slave_port,
1098                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1099
1100                 if (phy->speed == 1000)
1101                         mac_control |= BIT(7);  /* GIGABITEN    */
1102                 if (phy->duplex)
1103                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1104
1105                 /* set speed_in input in case RMII mode is used in 100Mbps */
1106                 if (phy->speed == 100)
1107                         mac_control |= BIT(15);
1108                 /* in band mode only works in 10Mbps RGMII mode */
1109                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1110                         mac_control |= BIT(18); /* In Band mode */
1111
1112                 if (priv->rx_pause)
1113                         mac_control |= BIT(3);
1114
1115                 if (priv->tx_pause)
1116                         mac_control |= BIT(4);
1117
1118                 *link = true;
1119         } else {
1120                 mac_control = 0;
1121                 /* disable forwarding */
1122                 cpsw_ale_control_set(cpsw->ale, slave_port,
1123                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1124         }
1125
1126         if (mac_control != slave->mac_control) {
1127                 phy_print_status(phy);
1128                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1129         }
1130
1131         slave->mac_control = mac_control;
1132 }
1133
1134 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1135 {
1136         int i, speed;
1137
1138         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1139                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1140                         speed += cpsw->slaves[i].phy->speed;
1141
1142         return speed;
1143 }
1144
1145 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1146 {
1147         int i, rlim_ch_num;
1148         int speed, ch_rate;
1149
1150         /* re-split resources only in case speed was changed */
1151         speed = cpsw_get_common_speed(cpsw);
1152         if (speed == cpsw->speed || !speed)
1153                 return 0;
1154
1155         cpsw->speed = speed;
1156
1157         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1158                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1159                 if (!ch_rate)
1160                         break;
1161
1162                 rlim_ch_num++;
1163         }
1164
1165         /* cases not dependent on speed */
1166         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1167                 return 0;
1168
1169         return 1;
1170 }
1171
1172 static void cpsw_adjust_link(struct net_device *ndev)
1173 {
1174         struct cpsw_priv        *priv = netdev_priv(ndev);
1175         struct cpsw_common      *cpsw = priv->cpsw;
1176         bool                    link = false;
1177
1178         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1179
1180         if (link) {
1181                 if (cpsw_need_resplit(cpsw))
1182                         cpsw_split_res(ndev);
1183
1184                 netif_carrier_on(ndev);
1185                 if (netif_running(ndev))
1186                         netif_tx_wake_all_queues(ndev);
1187         } else {
1188                 netif_carrier_off(ndev);
1189                 netif_tx_stop_all_queues(ndev);
1190         }
1191 }
1192
1193 static int cpsw_get_coalesce(struct net_device *ndev,
1194                                 struct ethtool_coalesce *coal)
1195 {
1196         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1197
1198         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1199         return 0;
1200 }
1201
1202 static int cpsw_set_coalesce(struct net_device *ndev,
1203                                 struct ethtool_coalesce *coal)
1204 {
1205         struct cpsw_priv *priv = netdev_priv(ndev);
1206         u32 int_ctrl;
1207         u32 num_interrupts = 0;
1208         u32 prescale = 0;
1209         u32 addnl_dvdr = 1;
1210         u32 coal_intvl = 0;
1211         struct cpsw_common *cpsw = priv->cpsw;
1212
1213         coal_intvl = coal->rx_coalesce_usecs;
1214
1215         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1216         prescale = cpsw->bus_freq_mhz * 4;
1217
1218         if (!coal->rx_coalesce_usecs) {
1219                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1220                 goto update_return;
1221         }
1222
1223         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1224                 coal_intvl = CPSW_CMINTMIN_INTVL;
1225
1226         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1227                 /* Interrupt pacer works with 4us Pulse, we can
1228                  * throttle further by dilating the 4us pulse.
1229                  */
1230                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1231
1232                 if (addnl_dvdr > 1) {
1233                         prescale *= addnl_dvdr;
1234                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1235                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1236                                                 * addnl_dvdr);
1237                 } else {
1238                         addnl_dvdr = 1;
1239                         coal_intvl = CPSW_CMINTMAX_INTVL;
1240                 }
1241         }
1242
1243         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1244         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1245         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1246
1247         int_ctrl |= CPSW_INTPACEEN;
1248         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1249         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1250
1251 update_return:
1252         writel(int_ctrl, &cpsw->wr_regs->int_control);
1253
1254         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1255         cpsw->coal_intvl = coal_intvl;
1256
1257         return 0;
1258 }
1259
1260 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1261 {
1262         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1263
1264         switch (sset) {
1265         case ETH_SS_STATS:
1266                 return (CPSW_STATS_COMMON_LEN +
1267                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1268                        CPSW_STATS_CH_LEN);
1269         default:
1270                 return -EOPNOTSUPP;
1271         }
1272 }
1273
1274 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1275 {
1276         int ch_stats_len;
1277         int line;
1278         int i;
1279
1280         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1281         for (i = 0; i < ch_stats_len; i++) {
1282                 line = i % CPSW_STATS_CH_LEN;
1283                 snprintf(*p, ETH_GSTRING_LEN,
1284                          "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1285                          (long)(i / CPSW_STATS_CH_LEN),
1286                          cpsw_gstrings_ch_stats[line].stat_string);
1287                 *p += ETH_GSTRING_LEN;
1288         }
1289 }
1290
1291 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1292 {
1293         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1294         u8 *p = data;
1295         int i;
1296
1297         switch (stringset) {
1298         case ETH_SS_STATS:
1299                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1300                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1301                                ETH_GSTRING_LEN);
1302                         p += ETH_GSTRING_LEN;
1303                 }
1304
1305                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1306                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1307                 break;
1308         }
1309 }
1310
1311 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1312                                     struct ethtool_stats *stats, u64 *data)
1313 {
1314         u8 *p;
1315         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1316         struct cpdma_chan_stats ch_stats;
1317         int i, l, ch;
1318
1319         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1320         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1321                 data[l] = readl(cpsw->hw_stats +
1322                                 cpsw_gstrings_stats[l].stat_offset);
1323
1324         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1325                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1326                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1327                         p = (u8 *)&ch_stats +
1328                                 cpsw_gstrings_ch_stats[i].stat_offset;
1329                         data[l] = *(u32 *)p;
1330                 }
1331         }
1332
1333         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1334                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1335                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1336                         p = (u8 *)&ch_stats +
1337                                 cpsw_gstrings_ch_stats[i].stat_offset;
1338                         data[l] = *(u32 *)p;
1339                 }
1340         }
1341 }
1342
1343 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1344                                         struct sk_buff *skb,
1345                                         struct cpdma_chan *txch)
1346 {
1347         struct cpsw_common *cpsw = priv->cpsw;
1348
1349         skb_tx_timestamp(skb);
1350         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1351                                  priv->emac_port + cpsw->data.dual_emac);
1352 }
1353
1354 static inline void cpsw_add_dual_emac_def_ale_entries(
1355                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1356                 u32 slave_port)
1357 {
1358         struct cpsw_common *cpsw = priv->cpsw;
1359         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1360
1361         if (cpsw->version == CPSW_VERSION_1)
1362                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1363         else
1364                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1365         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1366                           port_mask, port_mask, 0);
1367         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1368                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1369         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1370                            HOST_PORT_NUM, ALE_VLAN |
1371                            ALE_SECURE, slave->port_vlan);
1372         cpsw_ale_control_set(cpsw->ale, slave_port,
1373                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1374 }
1375
1376 static void soft_reset_slave(struct cpsw_slave *slave)
1377 {
1378         char name[32];
1379
1380         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1381         soft_reset(name, &slave->sliver->soft_reset);
1382 }
1383
1384 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1385 {
1386         u32 slave_port;
1387         struct phy_device *phy;
1388         struct cpsw_common *cpsw = priv->cpsw;
1389
1390         soft_reset_slave(slave);
1391
1392         /* setup priority mapping */
1393         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1394
1395         switch (cpsw->version) {
1396         case CPSW_VERSION_1:
1397                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1398                 /* Increase RX FIFO size to 5 for supporting fullduplex
1399                  * flow control mode
1400                  */
1401                 slave_write(slave,
1402                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1403                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1404                 break;
1405         case CPSW_VERSION_2:
1406         case CPSW_VERSION_3:
1407         case CPSW_VERSION_4:
1408                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1409                 /* Increase RX FIFO size to 5 for supporting fullduplex
1410                  * flow control mode
1411                  */
1412                 slave_write(slave,
1413                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1414                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1415                 break;
1416         }
1417
1418         /* setup max packet size, and mac address */
1419         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1420         cpsw_set_slave_mac(slave, priv);
1421
1422         slave->mac_control = 0; /* no link yet */
1423
1424         slave_port = cpsw_get_slave_port(slave->slave_num);
1425
1426         if (cpsw->data.dual_emac)
1427                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1428         else
1429                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1430                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1431
1432         if (slave->data->phy_node) {
1433                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1434                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1435                 if (!phy) {
1436                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1437                                 slave->data->phy_node,
1438                                 slave->slave_num);
1439                         return;
1440                 }
1441         } else {
1442                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1443                                  &cpsw_adjust_link, slave->data->phy_if);
1444                 if (IS_ERR(phy)) {
1445                         dev_err(priv->dev,
1446                                 "phy \"%s\" not found on slave %d, err %ld\n",
1447                                 slave->data->phy_id, slave->slave_num,
1448                                 PTR_ERR(phy));
1449                         return;
1450                 }
1451         }
1452
1453         slave->phy = phy;
1454
1455         phy_attached_info(slave->phy);
1456
1457         phy_start(slave->phy);
1458
1459         /* Configure GMII_SEL register */
1460         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1461 }
1462
1463 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1464 {
1465         struct cpsw_common *cpsw = priv->cpsw;
1466         const int vlan = cpsw->data.default_vlan;
1467         u32 reg;
1468         int i;
1469         int unreg_mcast_mask;
1470
1471         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1472                CPSW2_PORT_VLAN;
1473
1474         writel(vlan, &cpsw->host_port_regs->port_vlan);
1475
1476         for (i = 0; i < cpsw->data.slaves; i++)
1477                 slave_write(cpsw->slaves + i, vlan, reg);
1478
1479         if (priv->ndev->flags & IFF_ALLMULTI)
1480                 unreg_mcast_mask = ALE_ALL_PORTS;
1481         else
1482                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1483
1484         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1485                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1486                           unreg_mcast_mask);
1487 }
1488
1489 static void cpsw_init_host_port(struct cpsw_priv *priv)
1490 {
1491         u32 fifo_mode;
1492         u32 control_reg;
1493         struct cpsw_common *cpsw = priv->cpsw;
1494
1495         /* soft reset the controller and initialize ale */
1496         soft_reset("cpsw", &cpsw->regs->soft_reset);
1497         cpsw_ale_start(cpsw->ale);
1498
1499         /* switch to vlan unaware mode */
1500         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1501                              CPSW_ALE_VLAN_AWARE);
1502         control_reg = readl(&cpsw->regs->control);
1503         control_reg |= CPSW_VLAN_AWARE | CPSW_RX_VLAN_ENCAP;
1504         writel(control_reg, &cpsw->regs->control);
1505         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1506                      CPSW_FIFO_NORMAL_MODE;
1507         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1508
1509         /* setup host port priority mapping */
1510         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1511                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1512         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1513
1514         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1515                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1516
1517         if (!cpsw->data.dual_emac) {
1518                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1519                                    0, 0);
1520                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1521                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1522         }
1523 }
1524
1525 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1526 {
1527         struct cpsw_common *cpsw = priv->cpsw;
1528         struct sk_buff *skb;
1529         int ch_buf_num;
1530         int ch, i, ret;
1531
1532         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1533                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1534                 for (i = 0; i < ch_buf_num; i++) {
1535                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1536                                                           cpsw->rx_packet_max,
1537                                                           GFP_KERNEL);
1538                         if (!skb) {
1539                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1540                                 return -ENOMEM;
1541                         }
1542
1543                         skb_set_queue_mapping(skb, ch);
1544                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1545                                                 skb->data, skb_tailroom(skb),
1546                                                 0);
1547                         if (ret < 0) {
1548                                 cpsw_err(priv, ifup,
1549                                          "cannot submit skb to channel %d rx, error %d\n",
1550                                          ch, ret);
1551                                 kfree_skb(skb);
1552                                 return ret;
1553                         }
1554                         kmemleak_not_leak(skb);
1555                 }
1556
1557                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1558                           ch, ch_buf_num);
1559         }
1560
1561         return 0;
1562 }
1563
1564 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1565 {
1566         u32 slave_port;
1567
1568         slave_port = cpsw_get_slave_port(slave->slave_num);
1569
1570         if (!slave->phy)
1571                 return;
1572         phy_stop(slave->phy);
1573         phy_disconnect(slave->phy);
1574         slave->phy = NULL;
1575         cpsw_ale_control_set(cpsw->ale, slave_port,
1576                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1577         soft_reset_slave(slave);
1578 }
1579
1580 static int cpsw_ndo_open(struct net_device *ndev)
1581 {
1582         struct cpsw_priv *priv = netdev_priv(ndev);
1583         struct cpsw_common *cpsw = priv->cpsw;
1584         int ret;
1585         u32 reg;
1586
1587         ret = pm_runtime_get_sync(cpsw->dev);
1588         if (ret < 0) {
1589                 pm_runtime_put_noidle(cpsw->dev);
1590                 return ret;
1591         }
1592
1593         netif_carrier_off(ndev);
1594
1595         /* Notify the stack of the actual queue counts. */
1596         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1597         if (ret) {
1598                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1599                 goto err_cleanup;
1600         }
1601
1602         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1603         if (ret) {
1604                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1605                 goto err_cleanup;
1606         }
1607
1608         reg = cpsw->version;
1609
1610         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1611                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1612                  CPSW_RTL_VERSION(reg));
1613
1614         /* Initialize host and slave ports */
1615         if (!cpsw->usage_count)
1616                 cpsw_init_host_port(priv);
1617         for_each_slave(priv, cpsw_slave_open, priv);
1618
1619         /* Add default VLAN */
1620         if (!cpsw->data.dual_emac)
1621                 cpsw_add_default_vlan(priv);
1622         else
1623                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1624                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1625
1626         /* initialize shared resources for every ndev */
1627         if (!cpsw->usage_count) {
1628                 /* disable priority elevation */
1629                 writel_relaxed(0, &cpsw->regs->ptype);
1630
1631                 /* enable statistics collection only on all ports */
1632                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1633
1634                 /* Enable internal fifo flow control */
1635                 writel(0x7, &cpsw->regs->flow_control);
1636
1637                 napi_enable(&cpsw->napi_rx);
1638                 napi_enable(&cpsw->napi_tx);
1639
1640                 if (cpsw->tx_irq_disabled) {
1641                         cpsw->tx_irq_disabled = false;
1642                         enable_irq(cpsw->irqs_table[1]);
1643                 }
1644
1645                 if (cpsw->rx_irq_disabled) {
1646                         cpsw->rx_irq_disabled = false;
1647                         enable_irq(cpsw->irqs_table[0]);
1648                 }
1649
1650                 ret = cpsw_fill_rx_channels(priv);
1651                 if (ret < 0)
1652                         goto err_cleanup;
1653
1654                 if (cpts_register(cpsw->cpts))
1655                         dev_err(priv->dev, "error registering cpts device\n");
1656
1657         }
1658
1659         /* Enable Interrupt pacing if configured */
1660         if (cpsw->coal_intvl != 0) {
1661                 struct ethtool_coalesce coal;
1662
1663                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1664                 cpsw_set_coalesce(ndev, &coal);
1665         }
1666
1667         cpdma_ctlr_start(cpsw->dma);
1668         cpsw_intr_enable(cpsw);
1669         cpsw->usage_count++;
1670
1671         return 0;
1672
1673 err_cleanup:
1674         cpdma_ctlr_stop(cpsw->dma);
1675         for_each_slave(priv, cpsw_slave_stop, cpsw);
1676         pm_runtime_put_sync(cpsw->dev);
1677         netif_carrier_off(priv->ndev);
1678         return ret;
1679 }
1680
1681 static int cpsw_ndo_stop(struct net_device *ndev)
1682 {
1683         struct cpsw_priv *priv = netdev_priv(ndev);
1684         struct cpsw_common *cpsw = priv->cpsw;
1685
1686         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1687         netif_tx_stop_all_queues(priv->ndev);
1688         netif_carrier_off(priv->ndev);
1689
1690         if (cpsw->usage_count <= 1) {
1691                 napi_disable(&cpsw->napi_rx);
1692                 napi_disable(&cpsw->napi_tx);
1693                 cpts_unregister(cpsw->cpts);
1694                 cpsw_intr_disable(cpsw);
1695                 cpdma_ctlr_stop(cpsw->dma);
1696                 cpsw_ale_stop(cpsw->ale);
1697         }
1698         for_each_slave(priv, cpsw_slave_stop, cpsw);
1699
1700         if (cpsw_need_resplit(cpsw))
1701                 cpsw_split_res(ndev);
1702
1703         cpsw->usage_count--;
1704         pm_runtime_put_sync(cpsw->dev);
1705         return 0;
1706 }
1707
1708 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1709                                        struct net_device *ndev)
1710 {
1711         struct cpsw_priv *priv = netdev_priv(ndev);
1712         struct cpsw_common *cpsw = priv->cpsw;
1713         struct cpts *cpts = cpsw->cpts;
1714         struct netdev_queue *txq;
1715         struct cpdma_chan *txch;
1716         int ret, q_idx;
1717
1718         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1719                 cpsw_err(priv, tx_err, "packet pad failed\n");
1720                 ndev->stats.tx_dropped++;
1721                 return NET_XMIT_DROP;
1722         }
1723
1724         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1725             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1726                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1727
1728         q_idx = skb_get_queue_mapping(skb);
1729         if (q_idx >= cpsw->tx_ch_num)
1730                 q_idx = q_idx % cpsw->tx_ch_num;
1731
1732         txch = cpsw->txv[q_idx].ch;
1733         txq = netdev_get_tx_queue(ndev, q_idx);
1734         ret = cpsw_tx_packet_submit(priv, skb, txch);
1735         if (unlikely(ret != 0)) {
1736                 cpsw_err(priv, tx_err, "desc submit failed\n");
1737                 goto fail;
1738         }
1739
1740         /* If there is no more tx desc left free then we need to
1741          * tell the kernel to stop sending us tx frames.
1742          */
1743         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1744                 netif_tx_stop_queue(txq);
1745
1746                 /* Barrier, so that stop_queue visible to other cpus */
1747                 smp_mb__after_atomic();
1748
1749                 if (cpdma_check_free_tx_desc(txch))
1750                         netif_tx_wake_queue(txq);
1751         }
1752
1753         return NETDEV_TX_OK;
1754 fail:
1755         ndev->stats.tx_dropped++;
1756         netif_tx_stop_queue(txq);
1757
1758         /* Barrier, so that stop_queue visible to other cpus */
1759         smp_mb__after_atomic();
1760
1761         if (cpdma_check_free_tx_desc(txch))
1762                 netif_tx_wake_queue(txq);
1763
1764         return NETDEV_TX_BUSY;
1765 }
1766
1767 #if IS_ENABLED(CONFIG_TI_CPTS)
1768
1769 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1770 {
1771         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1772         u32 ts_en, seq_id;
1773
1774         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1775             !cpts_is_rx_enabled(cpsw->cpts)) {
1776                 slave_write(slave, 0, CPSW1_TS_CTL);
1777                 return;
1778         }
1779
1780         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1781         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1782
1783         if (cpts_is_tx_enabled(cpsw->cpts))
1784                 ts_en |= CPSW_V1_TS_TX_EN;
1785
1786         if (cpts_is_rx_enabled(cpsw->cpts))
1787                 ts_en |= CPSW_V1_TS_RX_EN;
1788
1789         slave_write(slave, ts_en, CPSW1_TS_CTL);
1790         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1791 }
1792
1793 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1794 {
1795         struct cpsw_slave *slave;
1796         struct cpsw_common *cpsw = priv->cpsw;
1797         u32 ctrl, mtype;
1798
1799         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1800
1801         ctrl = slave_read(slave, CPSW2_CONTROL);
1802         switch (cpsw->version) {
1803         case CPSW_VERSION_2:
1804                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1805
1806                 if (cpts_is_tx_enabled(cpsw->cpts))
1807                         ctrl |= CTRL_V2_TX_TS_BITS;
1808
1809                 if (cpts_is_rx_enabled(cpsw->cpts))
1810                         ctrl |= CTRL_V2_RX_TS_BITS;
1811                 break;
1812         case CPSW_VERSION_3:
1813         default:
1814                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1815
1816                 if (cpts_is_tx_enabled(cpsw->cpts))
1817                         ctrl |= CTRL_V3_TX_TS_BITS;
1818
1819                 if (cpts_is_rx_enabled(cpsw->cpts))
1820                         ctrl |= CTRL_V3_RX_TS_BITS;
1821                 break;
1822         }
1823
1824         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1825
1826         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1827         slave_write(slave, ctrl, CPSW2_CONTROL);
1828         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
1829 }
1830
1831 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1832 {
1833         struct cpsw_priv *priv = netdev_priv(dev);
1834         struct hwtstamp_config cfg;
1835         struct cpsw_common *cpsw = priv->cpsw;
1836         struct cpts *cpts = cpsw->cpts;
1837
1838         if (cpsw->version != CPSW_VERSION_1 &&
1839             cpsw->version != CPSW_VERSION_2 &&
1840             cpsw->version != CPSW_VERSION_3)
1841                 return -EOPNOTSUPP;
1842
1843         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1844                 return -EFAULT;
1845
1846         /* reserved for future extensions */
1847         if (cfg.flags)
1848                 return -EINVAL;
1849
1850         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1851                 return -ERANGE;
1852
1853         switch (cfg.rx_filter) {
1854         case HWTSTAMP_FILTER_NONE:
1855                 cpts_rx_enable(cpts, 0);
1856                 break;
1857         case HWTSTAMP_FILTER_ALL:
1858         case HWTSTAMP_FILTER_NTP_ALL:
1859                 return -ERANGE;
1860         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1861         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1862         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1863                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1864                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1865                 break;
1866         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1867         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1868         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1869         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1870         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1871         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1872         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1873         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1874         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1875                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1876                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1877                 break;
1878         default:
1879                 return -ERANGE;
1880         }
1881
1882         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1883
1884         switch (cpsw->version) {
1885         case CPSW_VERSION_1:
1886                 cpsw_hwtstamp_v1(cpsw);
1887                 break;
1888         case CPSW_VERSION_2:
1889         case CPSW_VERSION_3:
1890                 cpsw_hwtstamp_v2(priv);
1891                 break;
1892         default:
1893                 WARN_ON(1);
1894         }
1895
1896         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1897 }
1898
1899 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1900 {
1901         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1902         struct cpts *cpts = cpsw->cpts;
1903         struct hwtstamp_config cfg;
1904
1905         if (cpsw->version != CPSW_VERSION_1 &&
1906             cpsw->version != CPSW_VERSION_2 &&
1907             cpsw->version != CPSW_VERSION_3)
1908                 return -EOPNOTSUPP;
1909
1910         cfg.flags = 0;
1911         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1912                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1913         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1914                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1915
1916         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1917 }
1918 #else
1919 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1920 {
1921         return -EOPNOTSUPP;
1922 }
1923
1924 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1925 {
1926         return -EOPNOTSUPP;
1927 }
1928 #endif /*CONFIG_TI_CPTS*/
1929
1930 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1931 {
1932         struct cpsw_priv *priv = netdev_priv(dev);
1933         struct cpsw_common *cpsw = priv->cpsw;
1934         int slave_no = cpsw_slave_index(cpsw, priv);
1935
1936         if (!netif_running(dev))
1937                 return -EINVAL;
1938
1939         switch (cmd) {
1940         case SIOCSHWTSTAMP:
1941                 return cpsw_hwtstamp_set(dev, req);
1942         case SIOCGHWTSTAMP:
1943                 return cpsw_hwtstamp_get(dev, req);
1944         }
1945
1946         if (!cpsw->slaves[slave_no].phy)
1947                 return -EOPNOTSUPP;
1948         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1949 }
1950
1951 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1952 {
1953         struct cpsw_priv *priv = netdev_priv(ndev);
1954         struct cpsw_common *cpsw = priv->cpsw;
1955         int ch;
1956
1957         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1958         ndev->stats.tx_errors++;
1959         cpsw_intr_disable(cpsw);
1960         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1961                 cpdma_chan_stop(cpsw->txv[ch].ch);
1962                 cpdma_chan_start(cpsw->txv[ch].ch);
1963         }
1964
1965         cpsw_intr_enable(cpsw);
1966         netif_trans_update(ndev);
1967         netif_tx_wake_all_queues(ndev);
1968 }
1969
1970 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1971 {
1972         struct cpsw_priv *priv = netdev_priv(ndev);
1973         struct sockaddr *addr = (struct sockaddr *)p;
1974         struct cpsw_common *cpsw = priv->cpsw;
1975         int flags = 0;
1976         u16 vid = 0;
1977         int ret;
1978
1979         if (!is_valid_ether_addr(addr->sa_data))
1980                 return -EADDRNOTAVAIL;
1981
1982         ret = pm_runtime_get_sync(cpsw->dev);
1983         if (ret < 0) {
1984                 pm_runtime_put_noidle(cpsw->dev);
1985                 return ret;
1986         }
1987
1988         if (cpsw->data.dual_emac) {
1989                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1990                 flags = ALE_VLAN;
1991         }
1992
1993         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1994                            flags, vid);
1995         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1996                            flags, vid);
1997
1998         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1999         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2000         for_each_slave(priv, cpsw_set_slave_mac, priv);
2001
2002         pm_runtime_put(cpsw->dev);
2003
2004         return 0;
2005 }
2006
2007 #ifdef CONFIG_NET_POLL_CONTROLLER
2008 static void cpsw_ndo_poll_controller(struct net_device *ndev)
2009 {
2010         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2011
2012         cpsw_intr_disable(cpsw);
2013         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2014         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2015         cpsw_intr_enable(cpsw);
2016 }
2017 #endif
2018
2019 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2020                                 unsigned short vid)
2021 {
2022         int ret;
2023         int unreg_mcast_mask = 0;
2024         u32 port_mask;
2025         struct cpsw_common *cpsw = priv->cpsw;
2026
2027         if (cpsw->data.dual_emac) {
2028                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
2029
2030                 if (priv->ndev->flags & IFF_ALLMULTI)
2031                         unreg_mcast_mask = port_mask;
2032         } else {
2033                 port_mask = ALE_ALL_PORTS;
2034
2035                 if (priv->ndev->flags & IFF_ALLMULTI)
2036                         unreg_mcast_mask = ALE_ALL_PORTS;
2037                 else
2038                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
2039         }
2040
2041         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
2042                                 unreg_mcast_mask);
2043         if (ret != 0)
2044                 return ret;
2045
2046         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
2047                                  HOST_PORT_NUM, ALE_VLAN, vid);
2048         if (ret != 0)
2049                 goto clean_vid;
2050
2051         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
2052                                  port_mask, ALE_VLAN, vid, 0);
2053         if (ret != 0)
2054                 goto clean_vlan_ucast;
2055         return 0;
2056
2057 clean_vlan_ucast:
2058         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2059                            HOST_PORT_NUM, ALE_VLAN, vid);
2060 clean_vid:
2061         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2062         return ret;
2063 }
2064
2065 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
2066                                     __be16 proto, u16 vid)
2067 {
2068         struct cpsw_priv *priv = netdev_priv(ndev);
2069         struct cpsw_common *cpsw = priv->cpsw;
2070         int ret;
2071
2072         if (vid == cpsw->data.default_vlan)
2073                 return 0;
2074
2075         ret = pm_runtime_get_sync(cpsw->dev);
2076         if (ret < 0) {
2077                 pm_runtime_put_noidle(cpsw->dev);
2078                 return ret;
2079         }
2080
2081         if (cpsw->data.dual_emac) {
2082                 /* In dual EMAC, reserved VLAN id should not be used for
2083                  * creating VLAN interfaces as this can break the dual
2084                  * EMAC port separation
2085                  */
2086                 int i;
2087
2088                 for (i = 0; i < cpsw->data.slaves; i++) {
2089                         if (vid == cpsw->slaves[i].port_vlan) {
2090                                 ret = -EINVAL;
2091                                 goto err;
2092                         }
2093                 }
2094         }
2095
2096         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2097         ret = cpsw_add_vlan_ale_entry(priv, vid);
2098 err:
2099         pm_runtime_put(cpsw->dev);
2100         return ret;
2101 }
2102
2103 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2104                                      __be16 proto, u16 vid)
2105 {
2106         struct cpsw_priv *priv = netdev_priv(ndev);
2107         struct cpsw_common *cpsw = priv->cpsw;
2108         int ret;
2109
2110         if (vid == cpsw->data.default_vlan)
2111                 return 0;
2112
2113         ret = pm_runtime_get_sync(cpsw->dev);
2114         if (ret < 0) {
2115                 pm_runtime_put_noidle(cpsw->dev);
2116                 return ret;
2117         }
2118
2119         if (cpsw->data.dual_emac) {
2120                 int i;
2121
2122                 for (i = 0; i < cpsw->data.slaves; i++) {
2123                         if (vid == cpsw->slaves[i].port_vlan)
2124                                 goto err;
2125                 }
2126         }
2127
2128         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2129         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2130         ret |= cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2131                                   HOST_PORT_NUM, ALE_VLAN, vid);
2132         ret |= cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2133                                   0, ALE_VLAN, vid);
2134 err:
2135         pm_runtime_put(cpsw->dev);
2136         return ret;
2137 }
2138
2139 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2140 {
2141         struct cpsw_priv *priv = netdev_priv(ndev);
2142         struct cpsw_common *cpsw = priv->cpsw;
2143         struct cpsw_slave *slave;
2144         u32 min_rate;
2145         u32 ch_rate;
2146         int i, ret;
2147
2148         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2149         if (ch_rate == rate)
2150                 return 0;
2151
2152         ch_rate = rate * 1000;
2153         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2154         if ((ch_rate < min_rate && ch_rate)) {
2155                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2156                         min_rate);
2157                 return -EINVAL;
2158         }
2159
2160         if (rate > cpsw->speed) {
2161                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2162                 return -EINVAL;
2163         }
2164
2165         ret = pm_runtime_get_sync(cpsw->dev);
2166         if (ret < 0) {
2167                 pm_runtime_put_noidle(cpsw->dev);
2168                 return ret;
2169         }
2170
2171         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2172         pm_runtime_put(cpsw->dev);
2173
2174         if (ret)
2175                 return ret;
2176
2177         /* update rates for slaves tx queues */
2178         for (i = 0; i < cpsw->data.slaves; i++) {
2179                 slave = &cpsw->slaves[i];
2180                 if (!slave->ndev)
2181                         continue;
2182
2183                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2184         }
2185
2186         cpsw_split_res(ndev);
2187         return ret;
2188 }
2189
2190 static const struct net_device_ops cpsw_netdev_ops = {
2191         .ndo_open               = cpsw_ndo_open,
2192         .ndo_stop               = cpsw_ndo_stop,
2193         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2194         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2195         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2196         .ndo_validate_addr      = eth_validate_addr,
2197         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2198         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2199         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2200 #ifdef CONFIG_NET_POLL_CONTROLLER
2201         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2202 #endif
2203         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2204         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2205 };
2206
2207 static int cpsw_get_regs_len(struct net_device *ndev)
2208 {
2209         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2210
2211         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2212 }
2213
2214 static void cpsw_get_regs(struct net_device *ndev,
2215                           struct ethtool_regs *regs, void *p)
2216 {
2217         u32 *reg = p;
2218         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2219
2220         /* update CPSW IP version */
2221         regs->version = cpsw->version;
2222
2223         cpsw_ale_dump(cpsw->ale, reg);
2224 }
2225
2226 static void cpsw_get_drvinfo(struct net_device *ndev,
2227                              struct ethtool_drvinfo *info)
2228 {
2229         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2230         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2231
2232         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2233         strlcpy(info->version, "1.0", sizeof(info->version));
2234         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2235 }
2236
2237 static u32 cpsw_get_msglevel(struct net_device *ndev)
2238 {
2239         struct cpsw_priv *priv = netdev_priv(ndev);
2240         return priv->msg_enable;
2241 }
2242
2243 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2244 {
2245         struct cpsw_priv *priv = netdev_priv(ndev);
2246         priv->msg_enable = value;
2247 }
2248
2249 #if IS_ENABLED(CONFIG_TI_CPTS)
2250 static int cpsw_get_ts_info(struct net_device *ndev,
2251                             struct ethtool_ts_info *info)
2252 {
2253         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2254
2255         info->so_timestamping =
2256                 SOF_TIMESTAMPING_TX_HARDWARE |
2257                 SOF_TIMESTAMPING_TX_SOFTWARE |
2258                 SOF_TIMESTAMPING_RX_HARDWARE |
2259                 SOF_TIMESTAMPING_RX_SOFTWARE |
2260                 SOF_TIMESTAMPING_SOFTWARE |
2261                 SOF_TIMESTAMPING_RAW_HARDWARE;
2262         info->phc_index = cpsw->cpts->phc_index;
2263         info->tx_types =
2264                 (1 << HWTSTAMP_TX_OFF) |
2265                 (1 << HWTSTAMP_TX_ON);
2266         info->rx_filters =
2267                 (1 << HWTSTAMP_FILTER_NONE) |
2268                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2269                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2270         return 0;
2271 }
2272 #else
2273 static int cpsw_get_ts_info(struct net_device *ndev,
2274                             struct ethtool_ts_info *info)
2275 {
2276         info->so_timestamping =
2277                 SOF_TIMESTAMPING_TX_SOFTWARE |
2278                 SOF_TIMESTAMPING_RX_SOFTWARE |
2279                 SOF_TIMESTAMPING_SOFTWARE;
2280         info->phc_index = -1;
2281         info->tx_types = 0;
2282         info->rx_filters = 0;
2283         return 0;
2284 }
2285 #endif
2286
2287 static int cpsw_get_link_ksettings(struct net_device *ndev,
2288                                    struct ethtool_link_ksettings *ecmd)
2289 {
2290         struct cpsw_priv *priv = netdev_priv(ndev);
2291         struct cpsw_common *cpsw = priv->cpsw;
2292         int slave_no = cpsw_slave_index(cpsw, priv);
2293
2294         if (!cpsw->slaves[slave_no].phy)
2295                 return -EOPNOTSUPP;
2296
2297         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2298         return 0;
2299 }
2300
2301 static int cpsw_set_link_ksettings(struct net_device *ndev,
2302                                    const struct ethtool_link_ksettings *ecmd)
2303 {
2304         struct cpsw_priv *priv = netdev_priv(ndev);
2305         struct cpsw_common *cpsw = priv->cpsw;
2306         int slave_no = cpsw_slave_index(cpsw, priv);
2307
2308         if (cpsw->slaves[slave_no].phy)
2309                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2310                                                  ecmd);
2311         else
2312                 return -EOPNOTSUPP;
2313 }
2314
2315 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2316 {
2317         struct cpsw_priv *priv = netdev_priv(ndev);
2318         struct cpsw_common *cpsw = priv->cpsw;
2319         int slave_no = cpsw_slave_index(cpsw, priv);
2320
2321         wol->supported = 0;
2322         wol->wolopts = 0;
2323
2324         if (cpsw->slaves[slave_no].phy)
2325                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2326 }
2327
2328 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2329 {
2330         struct cpsw_priv *priv = netdev_priv(ndev);
2331         struct cpsw_common *cpsw = priv->cpsw;
2332         int slave_no = cpsw_slave_index(cpsw, priv);
2333
2334         if (cpsw->slaves[slave_no].phy)
2335                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2336         else
2337                 return -EOPNOTSUPP;
2338 }
2339
2340 static void cpsw_get_pauseparam(struct net_device *ndev,
2341                                 struct ethtool_pauseparam *pause)
2342 {
2343         struct cpsw_priv *priv = netdev_priv(ndev);
2344
2345         pause->autoneg = AUTONEG_DISABLE;
2346         pause->rx_pause = priv->rx_pause ? true : false;
2347         pause->tx_pause = priv->tx_pause ? true : false;
2348 }
2349
2350 static int cpsw_set_pauseparam(struct net_device *ndev,
2351                                struct ethtool_pauseparam *pause)
2352 {
2353         struct cpsw_priv *priv = netdev_priv(ndev);
2354         bool link;
2355
2356         priv->rx_pause = pause->rx_pause ? true : false;
2357         priv->tx_pause = pause->tx_pause ? true : false;
2358
2359         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2360         return 0;
2361 }
2362
2363 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2364 {
2365         struct cpsw_priv *priv = netdev_priv(ndev);
2366         struct cpsw_common *cpsw = priv->cpsw;
2367         int ret;
2368
2369         ret = pm_runtime_get_sync(cpsw->dev);
2370         if (ret < 0) {
2371                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2372                 pm_runtime_put_noidle(cpsw->dev);
2373         }
2374
2375         return ret;
2376 }
2377
2378 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2379 {
2380         struct cpsw_priv *priv = netdev_priv(ndev);
2381         int ret;
2382
2383         ret = pm_runtime_put(priv->cpsw->dev);
2384         if (ret < 0)
2385                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2386 }
2387
2388 static void cpsw_get_channels(struct net_device *ndev,
2389                               struct ethtool_channels *ch)
2390 {
2391         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2392
2393         ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2394         ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2395         ch->max_combined = 0;
2396         ch->max_other = 0;
2397         ch->other_count = 0;
2398         ch->rx_count = cpsw->rx_ch_num;
2399         ch->tx_count = cpsw->tx_ch_num;
2400         ch->combined_count = 0;
2401 }
2402
2403 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2404                                   struct ethtool_channels *ch)
2405 {
2406         if (cpsw->quirk_irq) {
2407                 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2408                 return -EOPNOTSUPP;
2409         }
2410
2411         if (ch->combined_count)
2412                 return -EINVAL;
2413
2414         /* verify we have at least one channel in each direction */
2415         if (!ch->rx_count || !ch->tx_count)
2416                 return -EINVAL;
2417
2418         if (ch->rx_count > cpsw->data.channels ||
2419             ch->tx_count > cpsw->data.channels)
2420                 return -EINVAL;
2421
2422         return 0;
2423 }
2424
2425 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2426 {
2427         struct cpsw_common *cpsw = priv->cpsw;
2428         void (*handler)(void *, int, int);
2429         struct netdev_queue *queue;
2430         struct cpsw_vector *vec;
2431         int ret, *ch;
2432
2433         if (rx) {
2434                 ch = &cpsw->rx_ch_num;
2435                 vec = cpsw->rxv;
2436                 handler = cpsw_rx_handler;
2437         } else {
2438                 ch = &cpsw->tx_ch_num;
2439                 vec = cpsw->txv;
2440                 handler = cpsw_tx_handler;
2441         }
2442
2443         while (*ch < ch_num) {
2444                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2445                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2446                 queue->tx_maxrate = 0;
2447
2448                 if (IS_ERR(vec[*ch].ch))
2449                         return PTR_ERR(vec[*ch].ch);
2450
2451                 if (!vec[*ch].ch)
2452                         return -EINVAL;
2453
2454                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2455                           (rx ? "rx" : "tx"));
2456                 (*ch)++;
2457         }
2458
2459         while (*ch > ch_num) {
2460                 (*ch)--;
2461
2462                 ret = cpdma_chan_destroy(vec[*ch].ch);
2463                 if (ret)
2464                         return ret;
2465
2466                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2467                           (rx ? "rx" : "tx"));
2468         }
2469
2470         return 0;
2471 }
2472
2473 static int cpsw_update_channels(struct cpsw_priv *priv,
2474                                 struct ethtool_channels *ch)
2475 {
2476         int ret;
2477
2478         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2479         if (ret)
2480                 return ret;
2481
2482         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2483         if (ret)
2484                 return ret;
2485
2486         return 0;
2487 }
2488
2489 static void cpsw_suspend_data_pass(struct net_device *ndev)
2490 {
2491         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2492         struct cpsw_slave *slave;
2493         int i;
2494
2495         /* Disable NAPI scheduling */
2496         cpsw_intr_disable(cpsw);
2497
2498         /* Stop all transmit queues for every network device.
2499          * Disable re-using rx descriptors with dormant_on.
2500          */
2501         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2502                 if (!(slave->ndev && netif_running(slave->ndev)))
2503                         continue;
2504
2505                 netif_tx_stop_all_queues(slave->ndev);
2506                 netif_dormant_on(slave->ndev);
2507         }
2508
2509         /* Handle rest of tx packets and stop cpdma channels */
2510         cpdma_ctlr_stop(cpsw->dma);
2511 }
2512
2513 static int cpsw_resume_data_pass(struct net_device *ndev)
2514 {
2515         struct cpsw_priv *priv = netdev_priv(ndev);
2516         struct cpsw_common *cpsw = priv->cpsw;
2517         struct cpsw_slave *slave;
2518         int i, ret;
2519
2520         /* Allow rx packets handling */
2521         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2522                 if (slave->ndev && netif_running(slave->ndev))
2523                         netif_dormant_off(slave->ndev);
2524
2525         /* After this receive is started */
2526         if (cpsw->usage_count) {
2527                 ret = cpsw_fill_rx_channels(priv);
2528                 if (ret)
2529                         return ret;
2530
2531                 cpdma_ctlr_start(cpsw->dma);
2532                 cpsw_intr_enable(cpsw);
2533         }
2534
2535         /* Resume transmit for every affected interface */
2536         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2537                 if (slave->ndev && netif_running(slave->ndev))
2538                         netif_tx_start_all_queues(slave->ndev);
2539
2540         return 0;
2541 }
2542
2543 static int cpsw_set_channels(struct net_device *ndev,
2544                              struct ethtool_channels *chs)
2545 {
2546         struct cpsw_priv *priv = netdev_priv(ndev);
2547         struct cpsw_common *cpsw = priv->cpsw;
2548         struct cpsw_slave *slave;
2549         int i, ret;
2550
2551         ret = cpsw_check_ch_settings(cpsw, chs);
2552         if (ret < 0)
2553                 return ret;
2554
2555         cpsw_suspend_data_pass(ndev);
2556         ret = cpsw_update_channels(priv, chs);
2557         if (ret)
2558                 goto err;
2559
2560         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2561                 if (!(slave->ndev && netif_running(slave->ndev)))
2562                         continue;
2563
2564                 /* Inform stack about new count of queues */
2565                 ret = netif_set_real_num_tx_queues(slave->ndev,
2566                                                    cpsw->tx_ch_num);
2567                 if (ret) {
2568                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2569                         goto err;
2570                 }
2571
2572                 ret = netif_set_real_num_rx_queues(slave->ndev,
2573                                                    cpsw->rx_ch_num);
2574                 if (ret) {
2575                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2576                         goto err;
2577                 }
2578         }
2579
2580         if (cpsw->usage_count)
2581                 cpsw_split_res(ndev);
2582
2583         ret = cpsw_resume_data_pass(ndev);
2584         if (!ret)
2585                 return 0;
2586 err:
2587         dev_err(priv->dev, "cannot update channels number, closing device\n");
2588         dev_close(ndev);
2589         return ret;
2590 }
2591
2592 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2593 {
2594         struct cpsw_priv *priv = netdev_priv(ndev);
2595         struct cpsw_common *cpsw = priv->cpsw;
2596         int slave_no = cpsw_slave_index(cpsw, priv);
2597
2598         if (cpsw->slaves[slave_no].phy)
2599                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2600         else
2601                 return -EOPNOTSUPP;
2602 }
2603
2604 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2605 {
2606         struct cpsw_priv *priv = netdev_priv(ndev);
2607         struct cpsw_common *cpsw = priv->cpsw;
2608         int slave_no = cpsw_slave_index(cpsw, priv);
2609
2610         if (cpsw->slaves[slave_no].phy)
2611                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2612         else
2613                 return -EOPNOTSUPP;
2614 }
2615
2616 static int cpsw_nway_reset(struct net_device *ndev)
2617 {
2618         struct cpsw_priv *priv = netdev_priv(ndev);
2619         struct cpsw_common *cpsw = priv->cpsw;
2620         int slave_no = cpsw_slave_index(cpsw, priv);
2621
2622         if (cpsw->slaves[slave_no].phy)
2623                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2624         else
2625                 return -EOPNOTSUPP;
2626 }
2627
2628 static void cpsw_get_ringparam(struct net_device *ndev,
2629                                struct ethtool_ringparam *ering)
2630 {
2631         struct cpsw_priv *priv = netdev_priv(ndev);
2632         struct cpsw_common *cpsw = priv->cpsw;
2633
2634         /* not supported */
2635         ering->tx_max_pending = 0;
2636         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2637         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2638         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2639 }
2640
2641 static int cpsw_set_ringparam(struct net_device *ndev,
2642                               struct ethtool_ringparam *ering)
2643 {
2644         struct cpsw_priv *priv = netdev_priv(ndev);
2645         struct cpsw_common *cpsw = priv->cpsw;
2646         int ret;
2647
2648         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2649
2650         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2651             ering->rx_pending < CPSW_MAX_QUEUES ||
2652             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2653                 return -EINVAL;
2654
2655         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2656                 return 0;
2657
2658         cpsw_suspend_data_pass(ndev);
2659
2660         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2661
2662         if (cpsw->usage_count)
2663                 cpdma_chan_split_pool(cpsw->dma);
2664
2665         ret = cpsw_resume_data_pass(ndev);
2666         if (!ret)
2667                 return 0;
2668
2669         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2670         dev_close(ndev);
2671         return ret;
2672 }
2673
2674 static const struct ethtool_ops cpsw_ethtool_ops = {
2675         .get_drvinfo    = cpsw_get_drvinfo,
2676         .get_msglevel   = cpsw_get_msglevel,
2677         .set_msglevel   = cpsw_set_msglevel,
2678         .get_link       = ethtool_op_get_link,
2679         .get_ts_info    = cpsw_get_ts_info,
2680         .get_coalesce   = cpsw_get_coalesce,
2681         .set_coalesce   = cpsw_set_coalesce,
2682         .get_sset_count         = cpsw_get_sset_count,
2683         .get_strings            = cpsw_get_strings,
2684         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2685         .get_pauseparam         = cpsw_get_pauseparam,
2686         .set_pauseparam         = cpsw_set_pauseparam,
2687         .get_wol        = cpsw_get_wol,
2688         .set_wol        = cpsw_set_wol,
2689         .get_regs_len   = cpsw_get_regs_len,
2690         .get_regs       = cpsw_get_regs,
2691         .begin          = cpsw_ethtool_op_begin,
2692         .complete       = cpsw_ethtool_op_complete,
2693         .get_channels   = cpsw_get_channels,
2694         .set_channels   = cpsw_set_channels,
2695         .get_link_ksettings     = cpsw_get_link_ksettings,
2696         .set_link_ksettings     = cpsw_set_link_ksettings,
2697         .get_eee        = cpsw_get_eee,
2698         .set_eee        = cpsw_set_eee,
2699         .nway_reset     = cpsw_nway_reset,
2700         .get_ringparam = cpsw_get_ringparam,
2701         .set_ringparam = cpsw_set_ringparam,
2702 };
2703
2704 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2705                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2706 {
2707         void __iomem            *regs = cpsw->regs;
2708         int                     slave_num = slave->slave_num;
2709         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2710
2711         slave->data     = data;
2712         slave->regs     = regs + slave_reg_ofs;
2713         slave->sliver   = regs + sliver_reg_ofs;
2714         slave->port_vlan = data->dual_emac_res_vlan;
2715 }
2716
2717 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2718                          struct platform_device *pdev)
2719 {
2720         struct device_node *node = pdev->dev.of_node;
2721         struct device_node *slave_node;
2722         int i = 0, ret;
2723         u32 prop;
2724
2725         if (!node)
2726                 return -EINVAL;
2727
2728         if (of_property_read_u32(node, "slaves", &prop)) {
2729                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2730                 return -EINVAL;
2731         }
2732         data->slaves = prop;
2733
2734         if (of_property_read_u32(node, "active_slave", &prop)) {
2735                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2736                 return -EINVAL;
2737         }
2738         data->active_slave = prop;
2739
2740         data->slave_data = devm_kcalloc(&pdev->dev,
2741                                         data->slaves,
2742                                         sizeof(struct cpsw_slave_data),
2743                                         GFP_KERNEL);
2744         if (!data->slave_data)
2745                 return -ENOMEM;
2746
2747         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2748                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2749                 return -EINVAL;
2750         }
2751         data->channels = prop;
2752
2753         if (of_property_read_u32(node, "ale_entries", &prop)) {
2754                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2755                 return -EINVAL;
2756         }
2757         data->ale_entries = prop;
2758
2759         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2760                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2761                 return -EINVAL;
2762         }
2763         data->bd_ram_size = prop;
2764
2765         if (of_property_read_u32(node, "mac_control", &prop)) {
2766                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2767                 return -EINVAL;
2768         }
2769         data->mac_control = prop;
2770
2771         if (of_property_read_bool(node, "dual_emac"))
2772                 data->dual_emac = 1;
2773
2774         /*
2775          * Populate all the child nodes here...
2776          */
2777         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2778         /* We do not want to force this, as in some cases may not have child */
2779         if (ret)
2780                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2781
2782         for_each_available_child_of_node(node, slave_node) {
2783                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2784                 const void *mac_addr = NULL;
2785                 int lenp;
2786                 const __be32 *parp;
2787
2788                 /* This is no slave child node, continue */
2789                 if (strcmp(slave_node->name, "slave"))
2790                         continue;
2791
2792                 slave_data->phy_node = of_parse_phandle(slave_node,
2793                                                         "phy-handle", 0);
2794                 parp = of_get_property(slave_node, "phy_id", &lenp);
2795                 if (slave_data->phy_node) {
2796                         dev_dbg(&pdev->dev,
2797                                 "slave[%d] using phy-handle=\"%pOF\"\n",
2798                                 i, slave_data->phy_node);
2799                 } else if (of_phy_is_fixed_link(slave_node)) {
2800                         /* In the case of a fixed PHY, the DT node associated
2801                          * to the PHY is the Ethernet MAC DT node.
2802                          */
2803                         ret = of_phy_register_fixed_link(slave_node);
2804                         if (ret) {
2805                                 if (ret != -EPROBE_DEFER)
2806                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2807                                 return ret;
2808                         }
2809                         slave_data->phy_node = of_node_get(slave_node);
2810                 } else if (parp) {
2811                         u32 phyid;
2812                         struct device_node *mdio_node;
2813                         struct platform_device *mdio;
2814
2815                         if (lenp != (sizeof(__be32) * 2)) {
2816                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2817                                 goto no_phy_slave;
2818                         }
2819                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2820                         phyid = be32_to_cpup(parp+1);
2821                         mdio = of_find_device_by_node(mdio_node);
2822                         of_node_put(mdio_node);
2823                         if (!mdio) {
2824                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2825                                 return -EINVAL;
2826                         }
2827                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2828                                  PHY_ID_FMT, mdio->name, phyid);
2829                         put_device(&mdio->dev);
2830                 } else {
2831                         dev_err(&pdev->dev,
2832                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2833                                 i);
2834                         goto no_phy_slave;
2835                 }
2836                 slave_data->phy_if = of_get_phy_mode(slave_node);
2837                 if (slave_data->phy_if < 0) {
2838                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2839                                 i);
2840                         return slave_data->phy_if;
2841                 }
2842
2843 no_phy_slave:
2844                 mac_addr = of_get_mac_address(slave_node);
2845                 if (mac_addr) {
2846                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2847                 } else {
2848                         ret = ti_cm_get_macid(&pdev->dev, i,
2849                                               slave_data->mac_addr);
2850                         if (ret)
2851                                 return ret;
2852                 }
2853                 if (data->dual_emac) {
2854                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2855                                                  &prop)) {
2856                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2857                                 slave_data->dual_emac_res_vlan = i+1;
2858                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2859                                         slave_data->dual_emac_res_vlan, i);
2860                         } else {
2861                                 slave_data->dual_emac_res_vlan = prop;
2862                         }
2863                 }
2864
2865                 i++;
2866                 if (i == data->slaves)
2867                         break;
2868         }
2869
2870         return 0;
2871 }
2872
2873 static void cpsw_remove_dt(struct platform_device *pdev)
2874 {
2875         struct net_device *ndev = platform_get_drvdata(pdev);
2876         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2877         struct cpsw_platform_data *data = &cpsw->data;
2878         struct device_node *node = pdev->dev.of_node;
2879         struct device_node *slave_node;
2880         int i = 0;
2881
2882         for_each_available_child_of_node(node, slave_node) {
2883                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2884
2885                 if (strcmp(slave_node->name, "slave"))
2886                         continue;
2887
2888                 if (of_phy_is_fixed_link(slave_node))
2889                         of_phy_deregister_fixed_link(slave_node);
2890
2891                 of_node_put(slave_data->phy_node);
2892
2893                 i++;
2894                 if (i == data->slaves)
2895                         break;
2896         }
2897
2898         of_platform_depopulate(&pdev->dev);
2899 }
2900
2901 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2902 {
2903         struct cpsw_common              *cpsw = priv->cpsw;
2904         struct cpsw_platform_data       *data = &cpsw->data;
2905         struct net_device               *ndev;
2906         struct cpsw_priv                *priv_sl2;
2907         int ret = 0;
2908
2909         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2910         if (!ndev) {
2911                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2912                 return -ENOMEM;
2913         }
2914
2915         priv_sl2 = netdev_priv(ndev);
2916         priv_sl2->cpsw = cpsw;
2917         priv_sl2->ndev = ndev;
2918         priv_sl2->dev  = &ndev->dev;
2919         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2920
2921         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2922                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2923                         ETH_ALEN);
2924                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2925                          priv_sl2->mac_addr);
2926         } else {
2927                 random_ether_addr(priv_sl2->mac_addr);
2928                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2929                          priv_sl2->mac_addr);
2930         }
2931         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2932
2933         priv_sl2->emac_port = 1;
2934         cpsw->slaves[1].ndev = ndev;
2935         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2936
2937         ndev->netdev_ops = &cpsw_netdev_ops;
2938         ndev->ethtool_ops = &cpsw_ethtool_ops;
2939
2940         /* register the network device */
2941         SET_NETDEV_DEV(ndev, cpsw->dev);
2942         ret = register_netdev(ndev);
2943         if (ret) {
2944                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2945                 free_netdev(ndev);
2946                 ret = -ENODEV;
2947         }
2948
2949         return ret;
2950 }
2951
2952 static const struct of_device_id cpsw_of_mtable[] = {
2953         { .compatible = "ti,cpsw"},
2954         { .compatible = "ti,am335x-cpsw"},
2955         { .compatible = "ti,am4372-cpsw"},
2956         { .compatible = "ti,dra7-cpsw"},
2957         { /* sentinel */ },
2958 };
2959 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2960
2961 static const struct soc_device_attribute cpsw_soc_devices[] = {
2962         { .family = "AM33xx", .revision = "ES1.0"},
2963         { /* sentinel */ }
2964 };
2965
2966 static int cpsw_probe(struct platform_device *pdev)
2967 {
2968         struct clk                      *clk;
2969         struct cpsw_platform_data       *data;
2970         struct net_device               *ndev;
2971         struct cpsw_priv                *priv;
2972         struct cpdma_params             dma_params;
2973         struct cpsw_ale_params          ale_params;
2974         void __iomem                    *ss_regs;
2975         void __iomem                    *cpts_regs;
2976         struct resource                 *res, *ss_res;
2977         struct gpio_descs               *mode;
2978         u32 slave_offset, sliver_offset, slave_size;
2979         const struct soc_device_attribute *soc;
2980         struct cpsw_common              *cpsw;
2981         int ret = 0, i;
2982         int irq;
2983
2984         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2985         if (!cpsw)
2986                 return -ENOMEM;
2987
2988         cpsw->dev = &pdev->dev;
2989
2990         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2991         if (!ndev) {
2992                 dev_err(&pdev->dev, "error allocating net_device\n");
2993                 return -ENOMEM;
2994         }
2995
2996         platform_set_drvdata(pdev, ndev);
2997         priv = netdev_priv(ndev);
2998         priv->cpsw = cpsw;
2999         priv->ndev = ndev;
3000         priv->dev  = &ndev->dev;
3001         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3002         cpsw->rx_packet_max = max(rx_packet_max, 128);
3003
3004         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
3005         if (IS_ERR(mode)) {
3006                 ret = PTR_ERR(mode);
3007                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
3008                 goto clean_ndev_ret;
3009         }
3010
3011         /*
3012          * This may be required here for child devices.
3013          */
3014         pm_runtime_enable(&pdev->dev);
3015
3016         /* Select default pin state */
3017         pinctrl_pm_select_default_state(&pdev->dev);
3018
3019         /* Need to enable clocks with runtime PM api to access module
3020          * registers
3021          */
3022         ret = pm_runtime_get_sync(&pdev->dev);
3023         if (ret < 0) {
3024                 pm_runtime_put_noidle(&pdev->dev);
3025                 goto clean_runtime_disable_ret;
3026         }
3027
3028         ret = cpsw_probe_dt(&cpsw->data, pdev);
3029         if (ret)
3030                 goto clean_dt_ret;
3031
3032         data = &cpsw->data;
3033         cpsw->rx_ch_num = 1;
3034         cpsw->tx_ch_num = 1;
3035
3036         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3037                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3038                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
3039         } else {
3040                 eth_random_addr(priv->mac_addr);
3041                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
3042         }
3043
3044         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3045
3046         cpsw->slaves = devm_kcalloc(&pdev->dev,
3047                                     data->slaves, sizeof(struct cpsw_slave),
3048                                     GFP_KERNEL);
3049         if (!cpsw->slaves) {
3050                 ret = -ENOMEM;
3051                 goto clean_dt_ret;
3052         }
3053         for (i = 0; i < data->slaves; i++)
3054                 cpsw->slaves[i].slave_num = i;
3055
3056         cpsw->slaves[0].ndev = ndev;
3057         priv->emac_port = 0;
3058
3059         clk = devm_clk_get(&pdev->dev, "fck");
3060         if (IS_ERR(clk)) {
3061                 dev_err(priv->dev, "fck is not found\n");
3062                 ret = -ENODEV;
3063                 goto clean_dt_ret;
3064         }
3065         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3066
3067         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3068         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
3069         if (IS_ERR(ss_regs)) {
3070                 ret = PTR_ERR(ss_regs);
3071                 goto clean_dt_ret;
3072         }
3073         cpsw->regs = ss_regs;
3074
3075         cpsw->version = readl(&cpsw->regs->id_ver);
3076
3077         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3078         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3079         if (IS_ERR(cpsw->wr_regs)) {
3080                 ret = PTR_ERR(cpsw->wr_regs);
3081                 goto clean_dt_ret;
3082         }
3083
3084         memset(&dma_params, 0, sizeof(dma_params));
3085         memset(&ale_params, 0, sizeof(ale_params));
3086
3087         switch (cpsw->version) {
3088         case CPSW_VERSION_1:
3089                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3090                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3091                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3092                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3093                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3094                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3095                 slave_offset         = CPSW1_SLAVE_OFFSET;
3096                 slave_size           = CPSW1_SLAVE_SIZE;
3097                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3098                 dma_params.desc_mem_phys = 0;
3099                 break;
3100         case CPSW_VERSION_2:
3101         case CPSW_VERSION_3:
3102         case CPSW_VERSION_4:
3103                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3104                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3105                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3106                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3107                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3108                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3109                 slave_offset         = CPSW2_SLAVE_OFFSET;
3110                 slave_size           = CPSW2_SLAVE_SIZE;
3111                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3112                 dma_params.desc_mem_phys =
3113                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3114                 break;
3115         default:
3116                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3117                 ret = -ENODEV;
3118                 goto clean_dt_ret;
3119         }
3120         for (i = 0; i < cpsw->data.slaves; i++) {
3121                 struct cpsw_slave *slave = &cpsw->slaves[i];
3122
3123                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3124                 slave_offset  += slave_size;
3125                 sliver_offset += SLIVER_SIZE;
3126         }
3127
3128         dma_params.dev          = &pdev->dev;
3129         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3130         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3131         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3132         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3133         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3134
3135         dma_params.num_chan             = data->channels;
3136         dma_params.has_soft_reset       = true;
3137         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3138         dma_params.desc_mem_size        = data->bd_ram_size;
3139         dma_params.desc_align           = 16;
3140         dma_params.has_ext_regs         = true;
3141         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3142         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3143         dma_params.descs_pool_size      = descs_pool_size;
3144
3145         cpsw->dma = cpdma_ctlr_create(&dma_params);
3146         if (!cpsw->dma) {
3147                 dev_err(priv->dev, "error initializing dma\n");
3148                 ret = -ENOMEM;
3149                 goto clean_dt_ret;
3150         }
3151
3152         soc = soc_device_match(cpsw_soc_devices);
3153         if (soc)
3154                 cpsw->quirk_irq = 1;
3155
3156         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3157         if (IS_ERR(cpsw->txv[0].ch)) {
3158                 dev_err(priv->dev, "error initializing tx dma channel\n");
3159                 ret = PTR_ERR(cpsw->txv[0].ch);
3160                 goto clean_dma_ret;
3161         }
3162
3163         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3164         if (IS_ERR(cpsw->rxv[0].ch)) {
3165                 dev_err(priv->dev, "error initializing rx dma channel\n");
3166                 ret = PTR_ERR(cpsw->rxv[0].ch);
3167                 goto clean_dma_ret;
3168         }
3169
3170         ale_params.dev                  = &pdev->dev;
3171         ale_params.ale_ageout           = ale_ageout;
3172         ale_params.ale_entries          = data->ale_entries;
3173         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
3174
3175         cpsw->ale = cpsw_ale_create(&ale_params);
3176         if (!cpsw->ale) {
3177                 dev_err(priv->dev, "error initializing ale engine\n");
3178                 ret = -ENODEV;
3179                 goto clean_dma_ret;
3180         }
3181
3182         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3183         if (IS_ERR(cpsw->cpts)) {
3184                 ret = PTR_ERR(cpsw->cpts);
3185                 goto clean_dma_ret;
3186         }
3187
3188         ndev->irq = platform_get_irq(pdev, 1);
3189         if (ndev->irq < 0) {
3190                 dev_err(priv->dev, "error getting irq resource\n");
3191                 ret = ndev->irq;
3192                 goto clean_dma_ret;
3193         }
3194
3195         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3196
3197         ndev->netdev_ops = &cpsw_netdev_ops;
3198         ndev->ethtool_ops = &cpsw_ethtool_ops;
3199         netif_napi_add(ndev, &cpsw->napi_rx,
3200                        cpsw->quirk_irq ? cpsw_rx_poll : cpsw_rx_mq_poll,
3201                        CPSW_POLL_WEIGHT);
3202         netif_tx_napi_add(ndev, &cpsw->napi_tx,
3203                           cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3204                           CPSW_POLL_WEIGHT);
3205         cpsw_split_res(ndev);
3206
3207         /* register the network device */
3208         SET_NETDEV_DEV(ndev, &pdev->dev);
3209         ret = register_netdev(ndev);
3210         if (ret) {
3211                 dev_err(priv->dev, "error registering net device\n");
3212                 ret = -ENODEV;
3213                 goto clean_dma_ret;
3214         }
3215
3216         if (cpsw->data.dual_emac) {
3217                 ret = cpsw_probe_dual_emac(priv);
3218                 if (ret) {
3219                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3220                         goto clean_unregister_netdev_ret;
3221                 }
3222         }
3223
3224         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3225          * MISC IRQs which are always kept disabled with this driver so
3226          * we will not request them.
3227          *
3228          * If anyone wants to implement support for those, make sure to
3229          * first request and append them to irqs_table array.
3230          */
3231
3232         /* RX IRQ */
3233         irq = platform_get_irq(pdev, 1);
3234         if (irq < 0) {
3235                 ret = irq;
3236                 goto clean_dma_ret;
3237         }
3238
3239         cpsw->irqs_table[0] = irq;
3240         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3241                                0, dev_name(&pdev->dev), cpsw);
3242         if (ret < 0) {
3243                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3244                 goto clean_dma_ret;
3245         }
3246
3247         /* TX IRQ */
3248         irq = platform_get_irq(pdev, 2);
3249         if (irq < 0) {
3250                 ret = irq;
3251                 goto clean_dma_ret;
3252         }
3253
3254         cpsw->irqs_table[1] = irq;
3255         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3256                                0, dev_name(&pdev->dev), cpsw);
3257         if (ret < 0) {
3258                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3259                 goto clean_dma_ret;
3260         }
3261
3262         cpsw_notice(priv, probe,
3263                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3264                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3265
3266         pm_runtime_put(&pdev->dev);
3267
3268         return 0;
3269
3270 clean_unregister_netdev_ret:
3271         unregister_netdev(ndev);
3272 clean_dma_ret:
3273         cpdma_ctlr_destroy(cpsw->dma);
3274 clean_dt_ret:
3275         cpsw_remove_dt(pdev);
3276         pm_runtime_put_sync(&pdev->dev);
3277 clean_runtime_disable_ret:
3278         pm_runtime_disable(&pdev->dev);
3279 clean_ndev_ret:
3280         free_netdev(priv->ndev);
3281         return ret;
3282 }
3283
3284 static int cpsw_remove(struct platform_device *pdev)
3285 {
3286         struct net_device *ndev = platform_get_drvdata(pdev);
3287         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3288         int ret;
3289
3290         ret = pm_runtime_get_sync(&pdev->dev);
3291         if (ret < 0) {
3292                 pm_runtime_put_noidle(&pdev->dev);
3293                 return ret;
3294         }
3295
3296         if (cpsw->data.dual_emac)
3297                 unregister_netdev(cpsw->slaves[1].ndev);
3298         unregister_netdev(ndev);
3299
3300         cpts_release(cpsw->cpts);
3301         cpdma_ctlr_destroy(cpsw->dma);
3302         cpsw_remove_dt(pdev);
3303         pm_runtime_put_sync(&pdev->dev);
3304         pm_runtime_disable(&pdev->dev);
3305         if (cpsw->data.dual_emac)
3306                 free_netdev(cpsw->slaves[1].ndev);
3307         free_netdev(ndev);
3308         return 0;
3309 }
3310
3311 #ifdef CONFIG_PM_SLEEP
3312 static int cpsw_suspend(struct device *dev)
3313 {
3314         struct platform_device  *pdev = to_platform_device(dev);
3315         struct net_device       *ndev = platform_get_drvdata(pdev);
3316         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3317
3318         if (cpsw->data.dual_emac) {
3319                 int i;
3320
3321                 for (i = 0; i < cpsw->data.slaves; i++) {
3322                         if (netif_running(cpsw->slaves[i].ndev))
3323                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3324                 }
3325         } else {
3326                 if (netif_running(ndev))
3327                         cpsw_ndo_stop(ndev);
3328         }
3329
3330         /* Select sleep pin state */
3331         pinctrl_pm_select_sleep_state(dev);
3332
3333         return 0;
3334 }
3335
3336 static int cpsw_resume(struct device *dev)
3337 {
3338         struct platform_device  *pdev = to_platform_device(dev);
3339         struct net_device       *ndev = platform_get_drvdata(pdev);
3340         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3341
3342         /* Select default pin state */
3343         pinctrl_pm_select_default_state(dev);
3344
3345         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3346         rtnl_lock();
3347         if (cpsw->data.dual_emac) {
3348                 int i;
3349
3350                 for (i = 0; i < cpsw->data.slaves; i++) {
3351                         if (netif_running(cpsw->slaves[i].ndev))
3352                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3353                 }
3354         } else {
3355                 if (netif_running(ndev))
3356                         cpsw_ndo_open(ndev);
3357         }
3358         rtnl_unlock();
3359
3360         return 0;
3361 }
3362 #endif
3363
3364 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3365
3366 static struct platform_driver cpsw_driver = {
3367         .driver = {
3368                 .name    = "cpsw",
3369                 .pm      = &cpsw_pm_ops,
3370                 .of_match_table = cpsw_of_mtable,
3371         },
3372         .probe = cpsw_probe,
3373         .remove = cpsw_remove,
3374 };
3375
3376 module_platform_driver(cpsw_driver);
3377
3378 MODULE_LICENSE("GPL");
3379 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3380 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3381 MODULE_DESCRIPTION("TI CPSW Ethernet driver");