1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 Documentation available at:
22 http://www.stlinux.com
24 https://bugzilla.stlinux.com/
25 *******************************************************************************/
27 #include <linux/clk.h>
28 #include <linux/kernel.h>
29 #include <linux/interrupt.h>
31 #include <linux/tcp.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/if_ether.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/prefetch.h>
42 #include <linux/pinctrl/consumer.h>
43 #ifdef CONFIG_DEBUG_FS
44 #include <linux/debugfs.h>
45 #include <linux/seq_file.h>
46 #endif /* CONFIG_DEBUG_FS */
47 #include <linux/net_tstamp.h>
48 #include <net/pkt_cls.h>
49 #include "stmmac_ptp.h"
51 #include <linux/reset.h>
52 #include <linux/of_mdio.h>
53 #include "dwmac1000.h"
57 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
58 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
60 /* Module parameters */
62 static int watchdog = TX_TIMEO;
63 module_param(watchdog, int, 0644);
64 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
66 static int debug = -1;
67 module_param(debug, int, 0644);
68 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
70 static int phyaddr = -1;
71 module_param(phyaddr, int, 0444);
72 MODULE_PARM_DESC(phyaddr, "Physical device address");
74 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
75 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
77 static int flow_ctrl = FLOW_OFF;
78 module_param(flow_ctrl, int, 0644);
79 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
81 static int pause = PAUSE_TIME;
82 module_param(pause, int, 0644);
83 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
86 static int tc = TC_DEFAULT;
87 module_param(tc, int, 0644);
88 MODULE_PARM_DESC(tc, "DMA threshold control value");
90 #define DEFAULT_BUFSIZE 1536
91 static int buf_sz = DEFAULT_BUFSIZE;
92 module_param(buf_sz, int, 0644);
93 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
95 #define STMMAC_RX_COPYBREAK 256
97 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
98 NETIF_MSG_LINK | NETIF_MSG_IFUP |
99 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
101 #define STMMAC_DEFAULT_LPI_TIMER 1000
102 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
103 module_param(eee_timer, int, 0644);
104 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
105 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
107 /* By default the driver will use the ring mode to manage tx and rx descriptors,
108 * but allow user to force to use the chain instead of the ring
110 static unsigned int chain_mode;
111 module_param(chain_mode, int, 0444);
112 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
114 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
116 #ifdef CONFIG_DEBUG_FS
117 static int stmmac_init_fs(struct net_device *dev);
118 static void stmmac_exit_fs(struct net_device *dev);
121 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
124 * stmmac_verify_args - verify the driver parameters.
125 * Description: it checks the driver parameters and set a default in case of
128 static void stmmac_verify_args(void)
130 if (unlikely(watchdog < 0))
132 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
133 buf_sz = DEFAULT_BUFSIZE;
134 if (unlikely(flow_ctrl > 1))
135 flow_ctrl = FLOW_AUTO;
136 else if (likely(flow_ctrl < 0))
137 flow_ctrl = FLOW_OFF;
138 if (unlikely((pause < 0) || (pause > 0xffff)))
141 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
145 * stmmac_disable_all_queues - Disable all queues
146 * @priv: driver private structure
148 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
150 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
151 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
152 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
155 for (queue = 0; queue < maxq; queue++) {
156 struct stmmac_channel *ch = &priv->channel[queue];
158 if (queue < rx_queues_cnt)
159 napi_disable(&ch->rx_napi);
160 if (queue < tx_queues_cnt)
161 napi_disable(&ch->tx_napi);
166 * stmmac_enable_all_queues - Enable all queues
167 * @priv: driver private structure
169 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
171 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
172 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
173 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
176 for (queue = 0; queue < maxq; queue++) {
177 struct stmmac_channel *ch = &priv->channel[queue];
179 if (queue < rx_queues_cnt)
180 napi_enable(&ch->rx_napi);
181 if (queue < tx_queues_cnt)
182 napi_enable(&ch->tx_napi);
187 * stmmac_stop_all_queues - Stop all queues
188 * @priv: driver private structure
190 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
192 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
195 for (queue = 0; queue < tx_queues_cnt; queue++)
196 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
200 * stmmac_start_all_queues - Start all queues
201 * @priv: driver private structure
203 static void stmmac_start_all_queues(struct stmmac_priv *priv)
205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
208 for (queue = 0; queue < tx_queues_cnt; queue++)
209 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
212 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
214 if (!test_bit(STMMAC_DOWN, &priv->state) &&
215 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
216 queue_work(priv->wq, &priv->service_task);
219 static void stmmac_global_err(struct stmmac_priv *priv)
221 netif_carrier_off(priv->dev);
222 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
223 stmmac_service_event_schedule(priv);
227 * stmmac_clk_csr_set - dynamically set the MDC clock
228 * @priv: driver private structure
229 * Description: this is to dynamically set the MDC clock according to the csr
232 * If a specific clk_csr value is passed from the platform
233 * this means that the CSR Clock Range selection cannot be
234 * changed at run-time and it is fixed (as reported in the driver
235 * documentation). Viceversa the driver will try to set the MDC
236 * clock dynamically according to the actual clock input.
238 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
242 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
244 /* Platform provided default clk_csr would be assumed valid
245 * for all other cases except for the below mentioned ones.
246 * For values higher than the IEEE 802.3 specified frequency
247 * we can not estimate the proper divider as it is not known
248 * the frequency of clk_csr_i. So we do not change the default
251 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
252 if (clk_rate < CSR_F_35M)
253 priv->clk_csr = STMMAC_CSR_20_35M;
254 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
255 priv->clk_csr = STMMAC_CSR_35_60M;
256 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
257 priv->clk_csr = STMMAC_CSR_60_100M;
258 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
259 priv->clk_csr = STMMAC_CSR_100_150M;
260 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
261 priv->clk_csr = STMMAC_CSR_150_250M;
262 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
263 priv->clk_csr = STMMAC_CSR_250_300M;
266 if (priv->plat->has_sun8i) {
267 if (clk_rate > 160000000)
268 priv->clk_csr = 0x03;
269 else if (clk_rate > 80000000)
270 priv->clk_csr = 0x02;
271 else if (clk_rate > 40000000)
272 priv->clk_csr = 0x01;
277 if (priv->plat->has_xgmac) {
278 if (clk_rate > 400000000)
280 else if (clk_rate > 350000000)
282 else if (clk_rate > 300000000)
284 else if (clk_rate > 250000000)
286 else if (clk_rate > 150000000)
293 static void print_pkt(unsigned char *buf, int len)
295 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
296 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
299 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
301 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
304 if (tx_q->dirty_tx > tx_q->cur_tx)
305 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
307 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
313 * stmmac_rx_dirty - Get RX queue dirty
314 * @priv: driver private structure
315 * @queue: RX queue index
317 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
319 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
322 if (rx_q->dirty_rx <= rx_q->cur_rx)
323 dirty = rx_q->cur_rx - rx_q->dirty_rx;
325 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
331 * stmmac_hw_fix_mac_speed - callback for speed selection
332 * @priv: driver private structure
333 * Description: on some platforms (e.g. ST), some HW system configuration
334 * registers have to be set according to the link speed negotiated.
336 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
338 struct net_device *ndev = priv->dev;
339 struct phy_device *phydev = ndev->phydev;
341 if (likely(priv->plat->fix_mac_speed))
342 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
346 * stmmac_enable_eee_mode - check and enter in LPI mode
347 * @priv: driver private structure
348 * Description: this function is to verify and enter in LPI mode in case of
351 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
353 u32 tx_cnt = priv->plat->tx_queues_to_use;
356 /* check if all TX queues have the work finished */
357 for (queue = 0; queue < tx_cnt; queue++) {
358 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
360 if (tx_q->dirty_tx != tx_q->cur_tx)
361 return; /* still unfinished work */
364 /* Check and enter in LPI mode */
365 if (!priv->tx_path_in_lpi_mode)
366 stmmac_set_eee_mode(priv, priv->hw,
367 priv->plat->en_tx_lpi_clockgating);
371 * stmmac_disable_eee_mode - disable and exit from LPI mode
372 * @priv: driver private structure
373 * Description: this function is to exit and disable EEE in case of
374 * LPI state is true. This is called by the xmit.
376 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
378 stmmac_reset_eee_mode(priv, priv->hw);
379 del_timer_sync(&priv->eee_ctrl_timer);
380 priv->tx_path_in_lpi_mode = false;
384 * stmmac_eee_ctrl_timer - EEE TX SW timer.
387 * if there is no data transfer and if we are not in LPI state,
388 * then MAC Transmitter can be moved to LPI state.
390 static void stmmac_eee_ctrl_timer(struct timer_list *t)
392 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
394 stmmac_enable_eee_mode(priv);
395 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
399 * stmmac_eee_init - init EEE
400 * @priv: driver private structure
402 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
403 * can also manage EEE, this function enable the LPI state and start related
406 bool stmmac_eee_init(struct stmmac_priv *priv)
408 struct net_device *ndev = priv->dev;
409 int interface = priv->plat->interface;
412 if ((interface != PHY_INTERFACE_MODE_MII) &&
413 (interface != PHY_INTERFACE_MODE_GMII) &&
414 !phy_interface_mode_is_rgmii(interface))
417 /* Using PCS we cannot dial with the phy registers at this stage
418 * so we do not support extra feature like EEE.
420 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
421 (priv->hw->pcs == STMMAC_PCS_TBI) ||
422 (priv->hw->pcs == STMMAC_PCS_RTBI))
425 /* MAC core supports the EEE feature. */
426 if (priv->dma_cap.eee) {
427 int tx_lpi_timer = priv->tx_lpi_timer;
429 /* Check if the PHY supports EEE */
430 if (phy_init_eee(ndev->phydev, 1)) {
431 /* To manage at run-time if the EEE cannot be supported
432 * anymore (for example because the lp caps have been
434 * In that case the driver disable own timers.
436 mutex_lock(&priv->lock);
437 if (priv->eee_active) {
438 netdev_dbg(priv->dev, "disable EEE\n");
439 del_timer_sync(&priv->eee_ctrl_timer);
440 stmmac_set_eee_timer(priv, priv->hw, 0,
443 priv->eee_active = 0;
444 mutex_unlock(&priv->lock);
447 /* Activate the EEE and start timers */
448 mutex_lock(&priv->lock);
449 if (!priv->eee_active) {
450 priv->eee_active = 1;
451 timer_setup(&priv->eee_ctrl_timer,
452 stmmac_eee_ctrl_timer, 0);
453 mod_timer(&priv->eee_ctrl_timer,
454 STMMAC_LPI_T(eee_timer));
456 stmmac_set_eee_timer(priv, priv->hw,
457 STMMAC_DEFAULT_LIT_LS, tx_lpi_timer);
459 /* Set HW EEE according to the speed */
460 stmmac_set_eee_pls(priv, priv->hw, ndev->phydev->link);
463 mutex_unlock(&priv->lock);
465 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
471 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
472 * @priv: driver private structure
473 * @p : descriptor pointer
474 * @skb : the socket buffer
476 * This function will read timestamp from the descriptor & pass it to stack.
477 * and also perform some sanity checks.
479 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
480 struct dma_desc *p, struct sk_buff *skb)
482 struct skb_shared_hwtstamps shhwtstamp;
485 if (!priv->hwts_tx_en)
488 /* exit if skb doesn't support hw tstamp */
489 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
492 /* check tx tstamp status */
493 if (stmmac_get_tx_timestamp_status(priv, p)) {
494 /* get the valid tstamp */
495 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
497 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
498 shhwtstamp.hwtstamp = ns_to_ktime(ns);
500 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
501 /* pass tstamp to stack */
502 skb_tstamp_tx(skb, &shhwtstamp);
508 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
509 * @priv: driver private structure
510 * @p : descriptor pointer
511 * @np : next descriptor pointer
512 * @skb : the socket buffer
514 * This function will read received packet's timestamp from the descriptor
515 * and pass it to stack. It also perform some sanity checks.
517 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
518 struct dma_desc *np, struct sk_buff *skb)
520 struct skb_shared_hwtstamps *shhwtstamp = NULL;
521 struct dma_desc *desc = p;
524 if (!priv->hwts_rx_en)
526 /* For GMAC4, the valid timestamp is from CTX next desc. */
527 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
530 /* Check if timestamp is available */
531 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
532 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
533 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
534 shhwtstamp = skb_hwtstamps(skb);
535 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
536 shhwtstamp->hwtstamp = ns_to_ktime(ns);
538 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
543 * stmmac_hwtstamp_set - control hardware timestamping.
544 * @dev: device pointer.
545 * @ifr: An IOCTL specific structure, that can contain a pointer to
546 * a proprietary structure used to pass information to the driver.
548 * This function configures the MAC to enable/disable both outgoing(TX)
549 * and incoming(RX) packets time stamping based on user input.
551 * 0 on success and an appropriate -ve integer on failure.
553 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
555 struct stmmac_priv *priv = netdev_priv(dev);
556 struct hwtstamp_config config;
557 struct timespec64 now;
561 u32 ptp_over_ipv4_udp = 0;
562 u32 ptp_over_ipv6_udp = 0;
563 u32 ptp_over_ethernet = 0;
564 u32 snap_type_sel = 0;
565 u32 ts_master_en = 0;
571 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
573 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
574 netdev_alert(priv->dev, "No support for HW time stamping\n");
575 priv->hwts_tx_en = 0;
576 priv->hwts_rx_en = 0;
581 if (copy_from_user(&config, ifr->ifr_data,
585 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
586 __func__, config.flags, config.tx_type, config.rx_filter);
588 /* reserved for future extensions */
592 if (config.tx_type != HWTSTAMP_TX_OFF &&
593 config.tx_type != HWTSTAMP_TX_ON)
597 switch (config.rx_filter) {
598 case HWTSTAMP_FILTER_NONE:
599 /* time stamp no incoming packet at all */
600 config.rx_filter = HWTSTAMP_FILTER_NONE;
603 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
604 /* PTP v1, UDP, any kind of event packet */
605 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
606 /* 'xmac' hardware can support Sync, Pdelay_Req and
607 * Pdelay_resp by setting bit14 and bits17/16 to 01
608 * This leaves Delay_Req timestamps out.
609 * Enable all events *and* general purpose message
612 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
613 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
614 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
617 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
618 /* PTP v1, UDP, Sync packet */
619 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
620 /* take time stamp for SYNC messages only */
621 ts_event_en = PTP_TCR_TSEVNTENA;
623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
627 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
628 /* PTP v1, UDP, Delay_req packet */
629 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
630 /* take time stamp for Delay_Req messages only */
631 ts_master_en = PTP_TCR_TSMSTRENA;
632 ts_event_en = PTP_TCR_TSEVNTENA;
634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
638 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
639 /* PTP v2, UDP, any kind of event packet */
640 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
641 ptp_v2 = PTP_TCR_TSVER2ENA;
642 /* take time stamp for all event messages */
643 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
645 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
646 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
649 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
650 /* PTP v2, UDP, Sync packet */
651 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
652 ptp_v2 = PTP_TCR_TSVER2ENA;
653 /* take time stamp for SYNC messages only */
654 ts_event_en = PTP_TCR_TSEVNTENA;
656 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
657 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
660 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
661 /* PTP v2, UDP, Delay_req packet */
662 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
663 ptp_v2 = PTP_TCR_TSVER2ENA;
664 /* take time stamp for Delay_Req messages only */
665 ts_master_en = PTP_TCR_TSMSTRENA;
666 ts_event_en = PTP_TCR_TSEVNTENA;
668 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
669 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
672 case HWTSTAMP_FILTER_PTP_V2_EVENT:
673 /* PTP v2/802.AS1 any layer, any kind of event packet */
674 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
675 ptp_v2 = PTP_TCR_TSVER2ENA;
676 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
679 ptp_over_ethernet = PTP_TCR_TSIPENA;
682 case HWTSTAMP_FILTER_PTP_V2_SYNC:
683 /* PTP v2/802.AS1, any layer, Sync packet */
684 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
685 ptp_v2 = PTP_TCR_TSVER2ENA;
686 /* take time stamp for SYNC messages only */
687 ts_event_en = PTP_TCR_TSEVNTENA;
689 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
690 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
691 ptp_over_ethernet = PTP_TCR_TSIPENA;
694 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
695 /* PTP v2/802.AS1, any layer, Delay_req packet */
696 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
697 ptp_v2 = PTP_TCR_TSVER2ENA;
698 /* take time stamp for Delay_Req messages only */
699 ts_master_en = PTP_TCR_TSMSTRENA;
700 ts_event_en = PTP_TCR_TSEVNTENA;
702 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
703 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
704 ptp_over_ethernet = PTP_TCR_TSIPENA;
707 case HWTSTAMP_FILTER_NTP_ALL:
708 case HWTSTAMP_FILTER_ALL:
709 /* time stamp any incoming packet */
710 config.rx_filter = HWTSTAMP_FILTER_ALL;
711 tstamp_all = PTP_TCR_TSENALL;
718 switch (config.rx_filter) {
719 case HWTSTAMP_FILTER_NONE:
720 config.rx_filter = HWTSTAMP_FILTER_NONE;
723 /* PTP v1, UDP, any kind of event packet */
724 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
728 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
729 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
731 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
732 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
734 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
735 tstamp_all | ptp_v2 | ptp_over_ethernet |
736 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
737 ts_master_en | snap_type_sel);
738 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
740 /* program Sub Second Increment reg */
741 stmmac_config_sub_second_increment(priv,
742 priv->ptpaddr, priv->plat->clk_ptp_rate,
744 temp = div_u64(1000000000ULL, sec_inc);
746 /* Store sub second increment and flags for later use */
747 priv->sub_second_inc = sec_inc;
748 priv->systime_flags = value;
750 /* calculate default added value:
752 * addend = (2^32)/freq_div_ratio;
753 * where, freq_div_ratio = 1e9ns/sec_inc
755 temp = (u64)(temp << 32);
756 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
757 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
759 /* initialize system time */
760 ktime_get_real_ts64(&now);
762 /* lower 32 bits of tv_sec are safe until y2106 */
763 stmmac_init_systime(priv, priv->ptpaddr,
764 (u32)now.tv_sec, now.tv_nsec);
767 memcpy(&priv->tstamp_config, &config, sizeof(config));
769 return copy_to_user(ifr->ifr_data, &config,
770 sizeof(config)) ? -EFAULT : 0;
774 * stmmac_hwtstamp_get - read hardware timestamping.
775 * @dev: device pointer.
776 * @ifr: An IOCTL specific structure, that can contain a pointer to
777 * a proprietary structure used to pass information to the driver.
779 * This function obtain the current hardware timestamping settings
782 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
784 struct stmmac_priv *priv = netdev_priv(dev);
785 struct hwtstamp_config *config = &priv->tstamp_config;
787 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
790 return copy_to_user(ifr->ifr_data, config,
791 sizeof(*config)) ? -EFAULT : 0;
795 * stmmac_init_ptp - init PTP
796 * @priv: driver private structure
797 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
798 * This is done by looking at the HW cap. register.
799 * This function also registers the ptp driver.
801 static int stmmac_init_ptp(struct stmmac_priv *priv)
803 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
805 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
809 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
810 if (xmac && priv->dma_cap.atime_stamp)
812 /* Dwmac 3.x core with extend_desc can support adv_ts */
813 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
816 if (priv->dma_cap.time_stamp)
817 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
820 netdev_info(priv->dev,
821 "IEEE 1588-2008 Advanced Timestamp supported\n");
823 priv->hwts_tx_en = 0;
824 priv->hwts_rx_en = 0;
826 stmmac_ptp_register(priv);
831 static void stmmac_release_ptp(struct stmmac_priv *priv)
833 if (priv->plat->clk_ptp_ref)
834 clk_disable_unprepare(priv->plat->clk_ptp_ref);
835 stmmac_ptp_unregister(priv);
839 * stmmac_mac_flow_ctrl - Configure flow control in all queues
840 * @priv: driver private structure
841 * Description: It is used for configuring the flow control in all queues
843 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
845 u32 tx_cnt = priv->plat->tx_queues_to_use;
847 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
848 priv->pause, tx_cnt);
852 * stmmac_adjust_link - adjusts the link parameters
853 * @dev: net device structure
854 * Description: this is the helper called by the physical abstraction layer
855 * drivers to communicate the phy link status. According the speed and duplex
856 * this driver can invoke registered glue-logic as well.
857 * It also invoke the eee initialization because it could happen when switch
858 * on different networks (that are eee capable).
860 static void stmmac_adjust_link(struct net_device *dev)
862 struct stmmac_priv *priv = netdev_priv(dev);
863 struct phy_device *phydev = dev->phydev;
864 bool new_state = false;
869 mutex_lock(&priv->lock);
872 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
874 /* Now we make sure that we can be in full duplex mode.
875 * If not, we operate in half-duplex mode. */
876 if (phydev->duplex != priv->oldduplex) {
879 ctrl &= ~priv->hw->link.duplex;
881 ctrl |= priv->hw->link.duplex;
882 priv->oldduplex = phydev->duplex;
884 /* Flow Control operation */
886 stmmac_mac_flow_ctrl(priv, phydev->duplex);
888 if (phydev->speed != priv->speed) {
890 ctrl &= ~priv->hw->link.speed_mask;
891 switch (phydev->speed) {
893 ctrl |= priv->hw->link.speed1000;
896 ctrl |= priv->hw->link.speed100;
899 ctrl |= priv->hw->link.speed10;
902 netif_warn(priv, link, priv->dev,
903 "broken speed: %d\n", phydev->speed);
904 phydev->speed = SPEED_UNKNOWN;
907 if (phydev->speed != SPEED_UNKNOWN)
908 stmmac_hw_fix_mac_speed(priv);
909 priv->speed = phydev->speed;
912 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
914 if (!priv->oldlink) {
916 priv->oldlink = true;
918 } else if (priv->oldlink) {
920 priv->oldlink = false;
921 priv->speed = SPEED_UNKNOWN;
922 priv->oldduplex = DUPLEX_UNKNOWN;
925 if (new_state && netif_msg_link(priv))
926 phy_print_status(phydev);
928 mutex_unlock(&priv->lock);
930 if (phydev->is_pseudo_fixed_link)
931 /* Stop PHY layer to call the hook to adjust the link in case
932 * of a switch is attached to the stmmac driver.
934 phydev->irq = PHY_IGNORE_INTERRUPT;
936 /* At this stage, init the EEE if supported.
937 * Never called in case of fixed_link.
939 priv->eee_enabled = stmmac_eee_init(priv);
943 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
944 * @priv: driver private structure
945 * Description: this is to verify if the HW supports the PCS.
946 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
947 * configured for the TBI, RTBI, or SGMII PHY interface.
949 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
951 int interface = priv->plat->interface;
953 if (priv->dma_cap.pcs) {
954 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
955 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
956 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
957 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
958 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
959 priv->hw->pcs = STMMAC_PCS_RGMII;
960 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
961 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
962 priv->hw->pcs = STMMAC_PCS_SGMII;
968 * stmmac_init_phy - PHY initialization
969 * @dev: net device structure
970 * Description: it initializes the driver's PHY state, and attaches the PHY
975 static int stmmac_init_phy(struct net_device *dev)
977 struct stmmac_priv *priv = netdev_priv(dev);
978 u32 tx_cnt = priv->plat->tx_queues_to_use;
979 struct phy_device *phydev;
980 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
981 char bus_id[MII_BUS_ID_SIZE];
982 int interface = priv->plat->interface;
983 int max_speed = priv->plat->max_speed;
984 priv->oldlink = false;
985 priv->speed = SPEED_UNKNOWN;
986 priv->oldduplex = DUPLEX_UNKNOWN;
988 if (priv->plat->phy_node) {
989 phydev = of_phy_connect(dev, priv->plat->phy_node,
990 &stmmac_adjust_link, 0, interface);
992 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
995 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
996 priv->plat->phy_addr);
997 netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__,
1000 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
1004 if (IS_ERR_OR_NULL(phydev)) {
1005 netdev_err(priv->dev, "Could not attach to PHY\n");
1009 return PTR_ERR(phydev);
1012 /* Stop Advertising 1000BASE Capability if interface is not GMII */
1013 if ((interface == PHY_INTERFACE_MODE_MII) ||
1014 (interface == PHY_INTERFACE_MODE_RMII) ||
1015 (max_speed < 1000 && max_speed > 0))
1016 phy_set_max_speed(phydev, SPEED_100);
1019 * Half-duplex mode not supported with multiqueue
1020 * half-duplex can only works with single queue
1023 phy_remove_link_mode(phydev,
1024 ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1025 phy_remove_link_mode(phydev,
1026 ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1027 phy_remove_link_mode(phydev,
1028 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1032 * Broken HW is sometimes missing the pull-up resistor on the
1033 * MDIO line, which results in reads to non-existent devices returning
1034 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
1036 * Note: phydev->phy_id is the result of reading the UID PHY registers.
1038 if (!priv->plat->phy_node && phydev->phy_id == 0) {
1039 phy_disconnect(phydev);
1043 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
1044 * subsequent PHY polling, make sure we force a link transition if
1045 * we have a UP/DOWN/UP transition
1047 if (phydev->is_pseudo_fixed_link)
1048 phydev->irq = PHY_POLL;
1050 phy_attached_info(phydev);
1054 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1056 u32 rx_cnt = priv->plat->rx_queues_to_use;
1060 /* Display RX rings */
1061 for (queue = 0; queue < rx_cnt; queue++) {
1062 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1064 pr_info("\tRX Queue %u rings\n", queue);
1066 if (priv->extend_desc)
1067 head_rx = (void *)rx_q->dma_erx;
1069 head_rx = (void *)rx_q->dma_rx;
1071 /* Display RX ring */
1072 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1076 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1078 u32 tx_cnt = priv->plat->tx_queues_to_use;
1082 /* Display TX rings */
1083 for (queue = 0; queue < tx_cnt; queue++) {
1084 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1086 pr_info("\tTX Queue %d rings\n", queue);
1088 if (priv->extend_desc)
1089 head_tx = (void *)tx_q->dma_etx;
1091 head_tx = (void *)tx_q->dma_tx;
1093 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1097 static void stmmac_display_rings(struct stmmac_priv *priv)
1099 /* Display RX ring */
1100 stmmac_display_rx_rings(priv);
1102 /* Display TX ring */
1103 stmmac_display_tx_rings(priv);
1106 static int stmmac_set_bfsize(int mtu, int bufsize)
1110 if (mtu >= BUF_SIZE_4KiB)
1111 ret = BUF_SIZE_8KiB;
1112 else if (mtu >= BUF_SIZE_2KiB)
1113 ret = BUF_SIZE_4KiB;
1114 else if (mtu > DEFAULT_BUFSIZE)
1115 ret = BUF_SIZE_2KiB;
1117 ret = DEFAULT_BUFSIZE;
1123 * stmmac_clear_rx_descriptors - clear RX descriptors
1124 * @priv: driver private structure
1125 * @queue: RX queue index
1126 * Description: this function is called to clear the RX descriptors
1127 * in case of both basic and extended descriptors are used.
1129 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1131 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1134 /* Clear the RX descriptors */
1135 for (i = 0; i < DMA_RX_SIZE; i++)
1136 if (priv->extend_desc)
1137 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1138 priv->use_riwt, priv->mode,
1139 (i == DMA_RX_SIZE - 1));
1141 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1142 priv->use_riwt, priv->mode,
1143 (i == DMA_RX_SIZE - 1));
1147 * stmmac_clear_tx_descriptors - clear tx descriptors
1148 * @priv: driver private structure
1149 * @queue: TX queue index.
1150 * Description: this function is called to clear the TX descriptors
1151 * in case of both basic and extended descriptors are used.
1153 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1155 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1158 /* Clear the TX descriptors */
1159 for (i = 0; i < DMA_TX_SIZE; i++)
1160 if (priv->extend_desc)
1161 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1162 priv->mode, (i == DMA_TX_SIZE - 1));
1164 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1165 priv->mode, (i == DMA_TX_SIZE - 1));
1169 * stmmac_clear_descriptors - clear descriptors
1170 * @priv: driver private structure
1171 * Description: this function is called to clear the TX and RX descriptors
1172 * in case of both basic and extended descriptors are used.
1174 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1176 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1177 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1180 /* Clear the RX descriptors */
1181 for (queue = 0; queue < rx_queue_cnt; queue++)
1182 stmmac_clear_rx_descriptors(priv, queue);
1184 /* Clear the TX descriptors */
1185 for (queue = 0; queue < tx_queue_cnt; queue++)
1186 stmmac_clear_tx_descriptors(priv, queue);
1190 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1191 * @priv: driver private structure
1192 * @p: descriptor pointer
1193 * @i: descriptor index
1195 * @queue: RX queue index
1196 * Description: this function is called to allocate a receive buffer, perform
1197 * the DMA mapping and init the descriptor.
1199 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1200 int i, gfp_t flags, u32 queue)
1202 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1203 struct sk_buff *skb;
1205 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1207 netdev_err(priv->dev,
1208 "%s: Rx init fails; skb is NULL\n", __func__);
1211 rx_q->rx_skbuff[i] = skb;
1212 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1215 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1216 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1217 dev_kfree_skb_any(skb);
1221 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1223 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1224 stmmac_init_desc3(priv, p);
1230 * stmmac_free_rx_buffer - free RX dma buffers
1231 * @priv: private structure
1232 * @queue: RX queue index
1235 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1237 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1239 if (rx_q->rx_skbuff[i]) {
1240 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1241 priv->dma_buf_sz, DMA_FROM_DEVICE);
1242 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1244 rx_q->rx_skbuff[i] = NULL;
1248 * stmmac_free_tx_buffer - free RX dma buffers
1249 * @priv: private structure
1250 * @queue: RX queue index
1253 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1255 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1257 if (tx_q->tx_skbuff_dma[i].buf) {
1258 if (tx_q->tx_skbuff_dma[i].map_as_page)
1259 dma_unmap_page(priv->device,
1260 tx_q->tx_skbuff_dma[i].buf,
1261 tx_q->tx_skbuff_dma[i].len,
1264 dma_unmap_single(priv->device,
1265 tx_q->tx_skbuff_dma[i].buf,
1266 tx_q->tx_skbuff_dma[i].len,
1270 if (tx_q->tx_skbuff[i]) {
1271 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1272 tx_q->tx_skbuff[i] = NULL;
1273 tx_q->tx_skbuff_dma[i].buf = 0;
1274 tx_q->tx_skbuff_dma[i].map_as_page = false;
1279 * init_dma_rx_desc_rings - init the RX descriptor rings
1280 * @dev: net device structure
1282 * Description: this function initializes the DMA RX descriptors
1283 * and allocates the socket buffers. It supports the chained and ring
1286 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1288 struct stmmac_priv *priv = netdev_priv(dev);
1289 u32 rx_count = priv->plat->rx_queues_to_use;
1295 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1299 if (bfsize < BUF_SIZE_16KiB)
1300 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1302 priv->dma_buf_sz = bfsize;
1304 /* RX INITIALIZATION */
1305 netif_dbg(priv, probe, priv->dev,
1306 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1308 for (queue = 0; queue < rx_count; queue++) {
1309 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1311 netif_dbg(priv, probe, priv->dev,
1312 "(%s) dma_rx_phy=0x%08x\n", __func__,
1313 (u32)rx_q->dma_rx_phy);
1315 for (i = 0; i < DMA_RX_SIZE; i++) {
1318 if (priv->extend_desc)
1319 p = &((rx_q->dma_erx + i)->basic);
1321 p = rx_q->dma_rx + i;
1323 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1326 goto err_init_rx_buffers;
1328 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1329 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1330 (unsigned int)rx_q->rx_skbuff_dma[i]);
1334 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1336 stmmac_clear_rx_descriptors(priv, queue);
1338 /* Setup the chained descriptor addresses */
1339 if (priv->mode == STMMAC_CHAIN_MODE) {
1340 if (priv->extend_desc)
1341 stmmac_mode_init(priv, rx_q->dma_erx,
1342 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1344 stmmac_mode_init(priv, rx_q->dma_rx,
1345 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1353 err_init_rx_buffers:
1354 while (queue >= 0) {
1356 stmmac_free_rx_buffer(priv, queue, i);
1369 * init_dma_tx_desc_rings - init the TX descriptor rings
1370 * @dev: net device structure.
1371 * Description: this function initializes the DMA TX descriptors
1372 * and allocates the socket buffers. It supports the chained and ring
1375 static int init_dma_tx_desc_rings(struct net_device *dev)
1377 struct stmmac_priv *priv = netdev_priv(dev);
1378 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1382 for (queue = 0; queue < tx_queue_cnt; queue++) {
1383 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1385 netif_dbg(priv, probe, priv->dev,
1386 "(%s) dma_tx_phy=0x%08x\n", __func__,
1387 (u32)tx_q->dma_tx_phy);
1389 /* Setup the chained descriptor addresses */
1390 if (priv->mode == STMMAC_CHAIN_MODE) {
1391 if (priv->extend_desc)
1392 stmmac_mode_init(priv, tx_q->dma_etx,
1393 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1395 stmmac_mode_init(priv, tx_q->dma_tx,
1396 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1399 for (i = 0; i < DMA_TX_SIZE; i++) {
1401 if (priv->extend_desc)
1402 p = &((tx_q->dma_etx + i)->basic);
1404 p = tx_q->dma_tx + i;
1406 stmmac_clear_desc(priv, p);
1408 tx_q->tx_skbuff_dma[i].buf = 0;
1409 tx_q->tx_skbuff_dma[i].map_as_page = false;
1410 tx_q->tx_skbuff_dma[i].len = 0;
1411 tx_q->tx_skbuff_dma[i].last_segment = false;
1412 tx_q->tx_skbuff[i] = NULL;
1419 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1426 * init_dma_desc_rings - init the RX/TX descriptor rings
1427 * @dev: net device structure
1429 * Description: this function initializes the DMA RX/TX descriptors
1430 * and allocates the socket buffers. It supports the chained and ring
1433 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1435 struct stmmac_priv *priv = netdev_priv(dev);
1438 ret = init_dma_rx_desc_rings(dev, flags);
1442 ret = init_dma_tx_desc_rings(dev);
1444 stmmac_clear_descriptors(priv);
1446 if (netif_msg_hw(priv))
1447 stmmac_display_rings(priv);
1453 * dma_free_rx_skbufs - free RX dma buffers
1454 * @priv: private structure
1455 * @queue: RX queue index
1457 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1461 for (i = 0; i < DMA_RX_SIZE; i++)
1462 stmmac_free_rx_buffer(priv, queue, i);
1466 * dma_free_tx_skbufs - free TX dma buffers
1467 * @priv: private structure
1468 * @queue: TX queue index
1470 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1474 for (i = 0; i < DMA_TX_SIZE; i++)
1475 stmmac_free_tx_buffer(priv, queue, i);
1479 * free_dma_rx_desc_resources - free RX dma desc resources
1480 * @priv: private structure
1482 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1484 u32 rx_count = priv->plat->rx_queues_to_use;
1487 /* Free RX queue resources */
1488 for (queue = 0; queue < rx_count; queue++) {
1489 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1491 /* Release the DMA RX socket buffers */
1492 dma_free_rx_skbufs(priv, queue);
1494 /* Free DMA regions of consistent memory previously allocated */
1495 if (!priv->extend_desc)
1496 dma_free_coherent(priv->device,
1497 DMA_RX_SIZE * sizeof(struct dma_desc),
1498 rx_q->dma_rx, rx_q->dma_rx_phy);
1500 dma_free_coherent(priv->device, DMA_RX_SIZE *
1501 sizeof(struct dma_extended_desc),
1502 rx_q->dma_erx, rx_q->dma_rx_phy);
1504 kfree(rx_q->rx_skbuff_dma);
1505 kfree(rx_q->rx_skbuff);
1510 * free_dma_tx_desc_resources - free TX dma desc resources
1511 * @priv: private structure
1513 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1515 u32 tx_count = priv->plat->tx_queues_to_use;
1518 /* Free TX queue resources */
1519 for (queue = 0; queue < tx_count; queue++) {
1520 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1522 /* Release the DMA TX socket buffers */
1523 dma_free_tx_skbufs(priv, queue);
1525 /* Free DMA regions of consistent memory previously allocated */
1526 if (!priv->extend_desc)
1527 dma_free_coherent(priv->device,
1528 DMA_TX_SIZE * sizeof(struct dma_desc),
1529 tx_q->dma_tx, tx_q->dma_tx_phy);
1531 dma_free_coherent(priv->device, DMA_TX_SIZE *
1532 sizeof(struct dma_extended_desc),
1533 tx_q->dma_etx, tx_q->dma_tx_phy);
1535 kfree(tx_q->tx_skbuff_dma);
1536 kfree(tx_q->tx_skbuff);
1541 * alloc_dma_rx_desc_resources - alloc RX resources.
1542 * @priv: private structure
1543 * Description: according to which descriptor can be used (extend or basic)
1544 * this function allocates the resources for TX and RX paths. In case of
1545 * reception, for example, it pre-allocated the RX socket buffer in order to
1546 * allow zero-copy mechanism.
1548 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1550 u32 rx_count = priv->plat->rx_queues_to_use;
1554 /* RX queues buffers and DMA */
1555 for (queue = 0; queue < rx_count; queue++) {
1556 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1558 rx_q->queue_index = queue;
1559 rx_q->priv_data = priv;
1561 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1564 if (!rx_q->rx_skbuff_dma)
1567 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1568 sizeof(struct sk_buff *),
1570 if (!rx_q->rx_skbuff)
1573 if (priv->extend_desc) {
1574 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1575 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1582 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1583 DMA_RX_SIZE * sizeof(struct dma_desc),
1594 free_dma_rx_desc_resources(priv);
1600 * alloc_dma_tx_desc_resources - alloc TX resources.
1601 * @priv: private structure
1602 * Description: according to which descriptor can be used (extend or basic)
1603 * this function allocates the resources for TX and RX paths. In case of
1604 * reception, for example, it pre-allocated the RX socket buffer in order to
1605 * allow zero-copy mechanism.
1607 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1609 u32 tx_count = priv->plat->tx_queues_to_use;
1613 /* TX queues buffers and DMA */
1614 for (queue = 0; queue < tx_count; queue++) {
1615 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1617 tx_q->queue_index = queue;
1618 tx_q->priv_data = priv;
1620 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1621 sizeof(*tx_q->tx_skbuff_dma),
1623 if (!tx_q->tx_skbuff_dma)
1626 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1627 sizeof(struct sk_buff *),
1629 if (!tx_q->tx_skbuff)
1632 if (priv->extend_desc) {
1633 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1634 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1640 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1641 DMA_TX_SIZE * sizeof(struct dma_desc),
1652 free_dma_tx_desc_resources(priv);
1658 * alloc_dma_desc_resources - alloc TX/RX resources.
1659 * @priv: private structure
1660 * Description: according to which descriptor can be used (extend or basic)
1661 * this function allocates the resources for TX and RX paths. In case of
1662 * reception, for example, it pre-allocated the RX socket buffer in order to
1663 * allow zero-copy mechanism.
1665 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1668 int ret = alloc_dma_rx_desc_resources(priv);
1673 ret = alloc_dma_tx_desc_resources(priv);
1679 * free_dma_desc_resources - free dma desc resources
1680 * @priv: private structure
1682 static void free_dma_desc_resources(struct stmmac_priv *priv)
1684 /* Release the DMA RX socket buffers */
1685 free_dma_rx_desc_resources(priv);
1687 /* Release the DMA TX socket buffers */
1688 free_dma_tx_desc_resources(priv);
1692 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1693 * @priv: driver private structure
1694 * Description: It is used for enabling the rx queues in the MAC
1696 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1698 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1702 for (queue = 0; queue < rx_queues_count; queue++) {
1703 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1704 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1709 * stmmac_start_rx_dma - start RX DMA channel
1710 * @priv: driver private structure
1711 * @chan: RX channel index
1713 * This starts a RX DMA channel
1715 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1717 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1718 stmmac_start_rx(priv, priv->ioaddr, chan);
1722 * stmmac_start_tx_dma - start TX DMA channel
1723 * @priv: driver private structure
1724 * @chan: TX channel index
1726 * This starts a TX DMA channel
1728 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1730 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1731 stmmac_start_tx(priv, priv->ioaddr, chan);
1735 * stmmac_stop_rx_dma - stop RX DMA channel
1736 * @priv: driver private structure
1737 * @chan: RX channel index
1739 * This stops a RX DMA channel
1741 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1743 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1744 stmmac_stop_rx(priv, priv->ioaddr, chan);
1748 * stmmac_stop_tx_dma - stop TX DMA channel
1749 * @priv: driver private structure
1750 * @chan: TX channel index
1752 * This stops a TX DMA channel
1754 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1756 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1757 stmmac_stop_tx(priv, priv->ioaddr, chan);
1761 * stmmac_start_all_dma - start all RX and TX DMA channels
1762 * @priv: driver private structure
1764 * This starts all the RX and TX DMA channels
1766 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1768 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1769 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1772 for (chan = 0; chan < rx_channels_count; chan++)
1773 stmmac_start_rx_dma(priv, chan);
1775 for (chan = 0; chan < tx_channels_count; chan++)
1776 stmmac_start_tx_dma(priv, chan);
1780 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1781 * @priv: driver private structure
1783 * This stops the RX and TX DMA channels
1785 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1787 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1788 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1791 for (chan = 0; chan < rx_channels_count; chan++)
1792 stmmac_stop_rx_dma(priv, chan);
1794 for (chan = 0; chan < tx_channels_count; chan++)
1795 stmmac_stop_tx_dma(priv, chan);
1799 * stmmac_dma_operation_mode - HW DMA operation mode
1800 * @priv: driver private structure
1801 * Description: it is used for configuring the DMA operation mode register in
1802 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1804 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1806 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1807 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1808 int rxfifosz = priv->plat->rx_fifo_size;
1809 int txfifosz = priv->plat->tx_fifo_size;
1816 rxfifosz = priv->dma_cap.rx_fifo_size;
1818 txfifosz = priv->dma_cap.tx_fifo_size;
1820 /* Adjust for real per queue fifo size */
1821 rxfifosz /= rx_channels_count;
1822 txfifosz /= tx_channels_count;
1824 if (priv->plat->force_thresh_dma_mode) {
1827 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1829 * In case of GMAC, SF mode can be enabled
1830 * to perform the TX COE in HW. This depends on:
1831 * 1) TX COE if actually supported
1832 * 2) There is no bugged Jumbo frame support
1833 * that needs to not insert csum in the TDES.
1835 txmode = SF_DMA_MODE;
1836 rxmode = SF_DMA_MODE;
1837 priv->xstats.threshold = SF_DMA_MODE;
1840 rxmode = SF_DMA_MODE;
1843 /* configure all channels */
1844 for (chan = 0; chan < rx_channels_count; chan++) {
1845 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1847 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1849 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1853 for (chan = 0; chan < tx_channels_count; chan++) {
1854 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1856 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1862 * stmmac_tx_clean - to manage the transmission completion
1863 * @priv: driver private structure
1864 * @queue: TX queue index
1865 * Description: it reclaims the transmit resources after transmission completes.
1867 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1869 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1870 unsigned int bytes_compl = 0, pkts_compl = 0;
1871 unsigned int entry, count = 0;
1873 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1875 priv->xstats.tx_clean++;
1877 entry = tx_q->dirty_tx;
1878 while ((entry != tx_q->cur_tx) && (count < budget)) {
1879 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1883 if (priv->extend_desc)
1884 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1886 p = tx_q->dma_tx + entry;
1888 status = stmmac_tx_status(priv, &priv->dev->stats,
1889 &priv->xstats, p, priv->ioaddr);
1890 /* Check if the descriptor is owned by the DMA */
1891 if (unlikely(status & tx_dma_own))
1896 /* Make sure descriptor fields are read after reading
1901 /* Just consider the last segment and ...*/
1902 if (likely(!(status & tx_not_ls))) {
1903 /* ... verify the status error condition */
1904 if (unlikely(status & tx_err)) {
1905 priv->dev->stats.tx_errors++;
1907 priv->dev->stats.tx_packets++;
1908 priv->xstats.tx_pkt_n++;
1910 stmmac_get_tx_hwtstamp(priv, p, skb);
1913 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1914 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1915 dma_unmap_page(priv->device,
1916 tx_q->tx_skbuff_dma[entry].buf,
1917 tx_q->tx_skbuff_dma[entry].len,
1920 dma_unmap_single(priv->device,
1921 tx_q->tx_skbuff_dma[entry].buf,
1922 tx_q->tx_skbuff_dma[entry].len,
1924 tx_q->tx_skbuff_dma[entry].buf = 0;
1925 tx_q->tx_skbuff_dma[entry].len = 0;
1926 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1929 stmmac_clean_desc3(priv, tx_q, p);
1931 tx_q->tx_skbuff_dma[entry].last_segment = false;
1932 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1934 if (likely(skb != NULL)) {
1936 bytes_compl += skb->len;
1937 dev_consume_skb_any(skb);
1938 tx_q->tx_skbuff[entry] = NULL;
1941 stmmac_release_tx_desc(priv, p, priv->mode);
1943 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1945 tx_q->dirty_tx = entry;
1947 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1948 pkts_compl, bytes_compl);
1950 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1952 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1954 netif_dbg(priv, tx_done, priv->dev,
1955 "%s: restart transmit\n", __func__);
1956 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1959 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1960 stmmac_enable_eee_mode(priv);
1961 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1964 /* We still have pending packets, let's call for a new scheduling */
1965 if (tx_q->dirty_tx != tx_q->cur_tx)
1966 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1968 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1974 * stmmac_tx_err - to manage the tx error
1975 * @priv: driver private structure
1976 * @chan: channel index
1977 * Description: it cleans the descriptors and restarts the transmission
1978 * in case of transmission errors.
1980 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1982 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1985 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1987 stmmac_stop_tx_dma(priv, chan);
1988 dma_free_tx_skbufs(priv, chan);
1989 for (i = 0; i < DMA_TX_SIZE; i++)
1990 if (priv->extend_desc)
1991 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1992 priv->mode, (i == DMA_TX_SIZE - 1));
1994 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1995 priv->mode, (i == DMA_TX_SIZE - 1));
1999 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2000 stmmac_start_tx_dma(priv, chan);
2002 priv->dev->stats.tx_errors++;
2003 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2007 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2008 * @priv: driver private structure
2009 * @txmode: TX operating mode
2010 * @rxmode: RX operating mode
2011 * @chan: channel index
2012 * Description: it is used for configuring of the DMA operation mode in
2013 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2016 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2017 u32 rxmode, u32 chan)
2019 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2020 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2021 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2022 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2023 int rxfifosz = priv->plat->rx_fifo_size;
2024 int txfifosz = priv->plat->tx_fifo_size;
2027 rxfifosz = priv->dma_cap.rx_fifo_size;
2029 txfifosz = priv->dma_cap.tx_fifo_size;
2031 /* Adjust for real per queue fifo size */
2032 rxfifosz /= rx_channels_count;
2033 txfifosz /= tx_channels_count;
2035 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2036 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2039 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2043 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2044 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2045 if (ret && (ret != -EINVAL)) {
2046 stmmac_global_err(priv);
2053 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2055 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2056 &priv->xstats, chan);
2057 struct stmmac_channel *ch = &priv->channel[chan];
2059 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2060 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2061 napi_schedule_irqoff(&ch->rx_napi);
2064 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2065 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2066 napi_schedule_irqoff(&ch->tx_napi);
2073 * stmmac_dma_interrupt - DMA ISR
2074 * @priv: driver private structure
2075 * Description: this is the DMA ISR. It is called by the main ISR.
2076 * It calls the dwmac dma routine and schedule poll method in case of some
2079 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2081 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2082 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2083 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2084 tx_channel_count : rx_channel_count;
2086 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2088 /* Make sure we never check beyond our status buffer. */
2089 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2090 channels_to_check = ARRAY_SIZE(status);
2092 for (chan = 0; chan < channels_to_check; chan++)
2093 status[chan] = stmmac_napi_check(priv, chan);
2095 for (chan = 0; chan < tx_channel_count; chan++) {
2096 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2097 /* Try to bump up the dma threshold on this failure */
2098 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2101 if (priv->plat->force_thresh_dma_mode)
2102 stmmac_set_dma_operation_mode(priv,
2107 stmmac_set_dma_operation_mode(priv,
2111 priv->xstats.threshold = tc;
2113 } else if (unlikely(status[chan] == tx_hard_error)) {
2114 stmmac_tx_err(priv, chan);
2120 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2121 * @priv: driver private structure
2122 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2124 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2126 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2127 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2129 dwmac_mmc_intr_all_mask(priv->mmcaddr);
2131 if (priv->dma_cap.rmon) {
2132 dwmac_mmc_ctrl(priv->mmcaddr, mode);
2133 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2135 netdev_info(priv->dev, "No MAC Management Counters available\n");
2139 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2140 * @priv: driver private structure
2142 * new GMAC chip generations have a new register to indicate the
2143 * presence of the optional feature/functions.
2144 * This can be also used to override the value passed through the
2145 * platform and necessary for old MAC10/100 and GMAC chips.
2147 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2149 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2153 * stmmac_check_ether_addr - check if the MAC addr is valid
2154 * @priv: driver private structure
2156 * it is to verify if the MAC address is valid, in case of failures it
2157 * generates a random MAC address
2159 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2161 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2162 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2163 if (!is_valid_ether_addr(priv->dev->dev_addr))
2164 eth_hw_addr_random(priv->dev);
2165 netdev_info(priv->dev, "device MAC address %pM\n",
2166 priv->dev->dev_addr);
2171 * stmmac_init_dma_engine - DMA init.
2172 * @priv: driver private structure
2174 * It inits the DMA invoking the specific MAC/GMAC callback.
2175 * Some DMA parameters can be passed from the platform;
2176 * in case of these are not passed a default is kept for the MAC or GMAC.
2178 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2180 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2181 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2182 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2183 struct stmmac_rx_queue *rx_q;
2184 struct stmmac_tx_queue *tx_q;
2189 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2190 dev_err(priv->device, "Invalid DMA configuration\n");
2194 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2197 ret = stmmac_reset(priv, priv->ioaddr);
2199 dev_err(priv->device, "Failed to reset the dma\n");
2203 /* DMA Configuration */
2204 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2206 if (priv->plat->axi)
2207 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2209 /* DMA RX Channel Configuration */
2210 for (chan = 0; chan < rx_channels_count; chan++) {
2211 rx_q = &priv->rx_queue[chan];
2213 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2214 rx_q->dma_rx_phy, chan);
2216 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2217 (DMA_RX_SIZE * sizeof(struct dma_desc));
2218 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2219 rx_q->rx_tail_addr, chan);
2222 /* DMA TX Channel Configuration */
2223 for (chan = 0; chan < tx_channels_count; chan++) {
2224 tx_q = &priv->tx_queue[chan];
2226 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2227 tx_q->dma_tx_phy, chan);
2229 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2230 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2231 tx_q->tx_tail_addr, chan);
2234 /* DMA CSR Channel configuration */
2235 for (chan = 0; chan < dma_csr_ch; chan++)
2236 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2241 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2243 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2245 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2249 * stmmac_tx_timer - mitigation sw timer for tx.
2250 * @data: data pointer
2252 * This is the timer handler to directly invoke the stmmac_tx_clean.
2254 static void stmmac_tx_timer(struct timer_list *t)
2256 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2257 struct stmmac_priv *priv = tx_q->priv_data;
2258 struct stmmac_channel *ch;
2260 ch = &priv->channel[tx_q->queue_index];
2263 * If NAPI is already running we can miss some events. Let's rearm
2264 * the timer and try again.
2266 if (likely(napi_schedule_prep(&ch->tx_napi)))
2267 __napi_schedule(&ch->tx_napi);
2269 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2273 * stmmac_init_tx_coalesce - init tx mitigation options.
2274 * @priv: driver private structure
2276 * This inits the transmit coalesce parameters: i.e. timer rate,
2277 * timer handler and default threshold used for enabling the
2278 * interrupt on completion bit.
2280 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2282 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2285 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2286 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2288 for (chan = 0; chan < tx_channel_count; chan++) {
2289 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2291 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2295 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2297 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2298 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2301 /* set TX ring length */
2302 for (chan = 0; chan < tx_channels_count; chan++)
2303 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2304 (DMA_TX_SIZE - 1), chan);
2306 /* set RX ring length */
2307 for (chan = 0; chan < rx_channels_count; chan++)
2308 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2309 (DMA_RX_SIZE - 1), chan);
2313 * stmmac_set_tx_queue_weight - Set TX queue weight
2314 * @priv: driver private structure
2315 * Description: It is used for setting TX queues weight
2317 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2319 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2323 for (queue = 0; queue < tx_queues_count; queue++) {
2324 weight = priv->plat->tx_queues_cfg[queue].weight;
2325 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2330 * stmmac_configure_cbs - Configure CBS in TX queue
2331 * @priv: driver private structure
2332 * Description: It is used for configuring CBS in AVB TX queues
2334 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2336 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2340 /* queue 0 is reserved for legacy traffic */
2341 for (queue = 1; queue < tx_queues_count; queue++) {
2342 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2343 if (mode_to_use == MTL_QUEUE_DCB)
2346 stmmac_config_cbs(priv, priv->hw,
2347 priv->plat->tx_queues_cfg[queue].send_slope,
2348 priv->plat->tx_queues_cfg[queue].idle_slope,
2349 priv->plat->tx_queues_cfg[queue].high_credit,
2350 priv->plat->tx_queues_cfg[queue].low_credit,
2356 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2357 * @priv: driver private structure
2358 * Description: It is used for mapping RX queues to RX dma channels
2360 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2362 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2366 for (queue = 0; queue < rx_queues_count; queue++) {
2367 chan = priv->plat->rx_queues_cfg[queue].chan;
2368 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2373 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2374 * @priv: driver private structure
2375 * Description: It is used for configuring the RX Queue Priority
2377 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2379 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2383 for (queue = 0; queue < rx_queues_count; queue++) {
2384 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2387 prio = priv->plat->rx_queues_cfg[queue].prio;
2388 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2393 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2394 * @priv: driver private structure
2395 * Description: It is used for configuring the TX Queue Priority
2397 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2399 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2403 for (queue = 0; queue < tx_queues_count; queue++) {
2404 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2407 prio = priv->plat->tx_queues_cfg[queue].prio;
2408 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2413 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2414 * @priv: driver private structure
2415 * Description: It is used for configuring the RX queue routing
2417 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2419 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2423 for (queue = 0; queue < rx_queues_count; queue++) {
2424 /* no specific packet type routing specified for the queue */
2425 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2428 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2429 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2434 * stmmac_mtl_configuration - Configure MTL
2435 * @priv: driver private structure
2436 * Description: It is used for configurring MTL
2438 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2440 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2441 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2443 if (tx_queues_count > 1)
2444 stmmac_set_tx_queue_weight(priv);
2446 /* Configure MTL RX algorithms */
2447 if (rx_queues_count > 1)
2448 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2449 priv->plat->rx_sched_algorithm);
2451 /* Configure MTL TX algorithms */
2452 if (tx_queues_count > 1)
2453 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2454 priv->plat->tx_sched_algorithm);
2456 /* Configure CBS in AVB TX queues */
2457 if (tx_queues_count > 1)
2458 stmmac_configure_cbs(priv);
2460 /* Map RX MTL to DMA channels */
2461 stmmac_rx_queue_dma_chan_map(priv);
2463 /* Enable MAC RX Queues */
2464 stmmac_mac_enable_rx_queues(priv);
2466 /* Set RX priorities */
2467 if (rx_queues_count > 1)
2468 stmmac_mac_config_rx_queues_prio(priv);
2470 /* Set TX priorities */
2471 if (tx_queues_count > 1)
2472 stmmac_mac_config_tx_queues_prio(priv);
2474 /* Set RX routing */
2475 if (rx_queues_count > 1)
2476 stmmac_mac_config_rx_queues_routing(priv);
2479 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2481 if (priv->dma_cap.asp) {
2482 netdev_info(priv->dev, "Enabling Safety Features\n");
2483 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2485 netdev_info(priv->dev, "No Safety Features support found\n");
2490 * stmmac_hw_setup - setup mac in a usable state.
2491 * @dev : pointer to the device structure.
2493 * this is the main function to setup the HW in a usable state because the
2494 * dma engine is reset, the core registers are configured (e.g. AXI,
2495 * Checksum features, timers). The DMA is ready to start receiving and
2498 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2501 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2503 struct stmmac_priv *priv = netdev_priv(dev);
2504 u32 rx_cnt = priv->plat->rx_queues_to_use;
2505 u32 tx_cnt = priv->plat->tx_queues_to_use;
2509 /* DMA initialization and SW reset */
2510 ret = stmmac_init_dma_engine(priv);
2512 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2517 /* Copy the MAC addr into the HW */
2518 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2520 /* PS and related bits will be programmed according to the speed */
2521 if (priv->hw->pcs) {
2522 int speed = priv->plat->mac_port_sel_speed;
2524 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2525 (speed == SPEED_1000)) {
2526 priv->hw->ps = speed;
2528 dev_warn(priv->device, "invalid port speed\n");
2533 /* Initialize the MAC Core */
2534 stmmac_core_init(priv, priv->hw, dev);
2537 stmmac_mtl_configuration(priv);
2539 /* Initialize Safety Features */
2540 stmmac_safety_feat_configuration(priv);
2542 ret = stmmac_rx_ipc(priv, priv->hw);
2544 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2545 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2546 priv->hw->rx_csum = 0;
2549 /* Enable the MAC Rx/Tx */
2550 stmmac_mac_set(priv, priv->ioaddr, true);
2552 /* Set the HW DMA mode and the COE */
2553 stmmac_dma_operation_mode(priv);
2555 stmmac_mmc_setup(priv);
2558 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2560 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2562 ret = stmmac_init_ptp(priv);
2563 if (ret == -EOPNOTSUPP)
2564 netdev_warn(priv->dev, "PTP not supported by HW\n");
2566 netdev_warn(priv->dev, "PTP init failed\n");
2569 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2571 if (priv->use_riwt) {
2572 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MAX_DMA_RIWT, rx_cnt);
2574 priv->rx_riwt = MAX_DMA_RIWT;
2578 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2580 /* set TX and RX rings length */
2581 stmmac_set_rings_length(priv);
2585 for (chan = 0; chan < tx_cnt; chan++)
2586 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2589 /* Start the ball rolling... */
2590 stmmac_start_all_dma(priv);
2595 static void stmmac_hw_teardown(struct net_device *dev)
2597 struct stmmac_priv *priv = netdev_priv(dev);
2599 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2603 * stmmac_open - open entry point of the driver
2604 * @dev : pointer to the device structure.
2606 * This function is the open entry point of the driver.
2608 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2611 static int stmmac_open(struct net_device *dev)
2613 struct stmmac_priv *priv = netdev_priv(dev);
2617 stmmac_check_ether_addr(priv);
2619 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2620 priv->hw->pcs != STMMAC_PCS_TBI &&
2621 priv->hw->pcs != STMMAC_PCS_RTBI) {
2622 ret = stmmac_init_phy(dev);
2624 netdev_err(priv->dev,
2625 "%s: Cannot attach to PHY (error: %d)\n",
2631 /* Extra statistics */
2632 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2633 priv->xstats.threshold = tc;
2635 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2636 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2638 ret = alloc_dma_desc_resources(priv);
2640 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2642 goto dma_desc_error;
2645 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2647 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2652 ret = stmmac_hw_setup(dev, true);
2654 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2658 stmmac_init_tx_coalesce(priv);
2661 phy_start(dev->phydev);
2663 /* Request the IRQ lines */
2664 ret = request_irq(dev->irq, stmmac_interrupt,
2665 IRQF_SHARED, dev->name, dev);
2666 if (unlikely(ret < 0)) {
2667 netdev_err(priv->dev,
2668 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2669 __func__, dev->irq, ret);
2673 /* Request the Wake IRQ in case of another line is used for WoL */
2674 if (priv->wol_irq != dev->irq) {
2675 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2676 IRQF_SHARED, dev->name, dev);
2677 if (unlikely(ret < 0)) {
2678 netdev_err(priv->dev,
2679 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2680 __func__, priv->wol_irq, ret);
2685 /* Request the IRQ lines */
2686 if (priv->lpi_irq > 0) {
2687 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2689 if (unlikely(ret < 0)) {
2690 netdev_err(priv->dev,
2691 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2692 __func__, priv->lpi_irq, ret);
2697 stmmac_enable_all_queues(priv);
2698 stmmac_start_all_queues(priv);
2703 if (priv->wol_irq != dev->irq)
2704 free_irq(priv->wol_irq, dev);
2706 free_irq(dev->irq, dev);
2709 phy_stop(dev->phydev);
2711 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2712 del_timer_sync(&priv->tx_queue[chan].txtimer);
2714 stmmac_hw_teardown(dev);
2716 free_dma_desc_resources(priv);
2719 phy_disconnect(dev->phydev);
2725 * stmmac_release - close entry point of the driver
2726 * @dev : device pointer.
2728 * This is the stop entry point of the driver.
2730 static int stmmac_release(struct net_device *dev)
2732 struct stmmac_priv *priv = netdev_priv(dev);
2735 if (priv->eee_enabled)
2736 del_timer_sync(&priv->eee_ctrl_timer);
2738 /* Stop and disconnect the PHY */
2740 phy_stop(dev->phydev);
2741 phy_disconnect(dev->phydev);
2744 stmmac_stop_all_queues(priv);
2746 stmmac_disable_all_queues(priv);
2748 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2749 del_timer_sync(&priv->tx_queue[chan].txtimer);
2751 /* Free the IRQ lines */
2752 free_irq(dev->irq, dev);
2753 if (priv->wol_irq != dev->irq)
2754 free_irq(priv->wol_irq, dev);
2755 if (priv->lpi_irq > 0)
2756 free_irq(priv->lpi_irq, dev);
2758 /* Stop TX/RX DMA and clear the descriptors */
2759 stmmac_stop_all_dma(priv);
2761 /* Release and free the Rx/Tx resources */
2762 free_dma_desc_resources(priv);
2764 /* Disable the MAC Rx/Tx */
2765 stmmac_mac_set(priv, priv->ioaddr, false);
2767 netif_carrier_off(dev);
2769 stmmac_release_ptp(priv);
2775 * stmmac_tso_allocator - close entry point of the driver
2776 * @priv: driver private structure
2777 * @des: buffer start address
2778 * @total_len: total length to fill in descriptors
2779 * @last_segmant: condition for the last descriptor
2780 * @queue: TX queue index
2782 * This function fills descriptor and request new descriptors according to
2783 * buffer length to fill
2785 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
2786 int total_len, bool last_segment, u32 queue)
2788 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2789 struct dma_desc *desc;
2793 tmp_len = total_len;
2795 while (tmp_len > 0) {
2796 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2797 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2798 desc = tx_q->dma_tx + tx_q->cur_tx;
2800 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2801 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2802 TSO_MAX_BUFF_SIZE : tmp_len;
2804 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2806 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2809 tmp_len -= TSO_MAX_BUFF_SIZE;
2814 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2815 * @skb : the socket buffer
2816 * @dev : device pointer
2817 * Description: this is the transmit function that is called on TSO frames
2818 * (support available on GMAC4 and newer chips).
2819 * Diagram below show the ring programming in case of TSO frames:
2823 * | DES0 |---> buffer1 = L2/L3/L4 header
2824 * | DES1 |---> TCP Payload (can continue on next descr...)
2825 * | DES2 |---> buffer 1 and 2 len
2826 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2832 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2834 * | DES2 | --> buffer 1 and 2 len
2838 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2840 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2842 struct dma_desc *desc, *first, *mss_desc = NULL;
2843 struct stmmac_priv *priv = netdev_priv(dev);
2844 int nfrags = skb_shinfo(skb)->nr_frags;
2845 u32 queue = skb_get_queue_mapping(skb);
2846 unsigned int first_entry, des;
2847 struct stmmac_tx_queue *tx_q;
2848 int tmp_pay_len = 0;
2853 tx_q = &priv->tx_queue[queue];
2855 /* Compute header lengths */
2856 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2858 /* Desc availability based on threshold should be enough safe */
2859 if (unlikely(stmmac_tx_avail(priv, queue) <
2860 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2861 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2862 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2864 /* This is a hard error, log it. */
2865 netdev_err(priv->dev,
2866 "%s: Tx Ring full when queue awake\n",
2869 return NETDEV_TX_BUSY;
2872 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2874 mss = skb_shinfo(skb)->gso_size;
2876 /* set new MSS value if needed */
2877 if (mss != tx_q->mss) {
2878 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2879 stmmac_set_mss(priv, mss_desc, mss);
2881 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2882 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2885 if (netif_msg_tx_queued(priv)) {
2886 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2887 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2888 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2892 first_entry = tx_q->cur_tx;
2893 WARN_ON(tx_q->tx_skbuff[first_entry]);
2895 desc = tx_q->dma_tx + first_entry;
2898 /* first descriptor: fill Headers on Buf1 */
2899 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2901 if (dma_mapping_error(priv->device, des))
2904 tx_q->tx_skbuff_dma[first_entry].buf = des;
2905 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2907 first->des0 = cpu_to_le32(des);
2909 /* Fill start of payload in buff2 of first descriptor */
2911 first->des1 = cpu_to_le32(des + proto_hdr_len);
2913 /* If needed take extra descriptors to fill the remaining payload */
2914 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2916 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2918 /* Prepare fragments */
2919 for (i = 0; i < nfrags; i++) {
2920 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2922 des = skb_frag_dma_map(priv->device, frag, 0,
2923 skb_frag_size(frag),
2925 if (dma_mapping_error(priv->device, des))
2928 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2929 (i == nfrags - 1), queue);
2931 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2932 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2933 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2936 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2938 /* Only the last descriptor gets to point to the skb. */
2939 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2941 /* We've used all descriptors we need for this skb, however,
2942 * advance cur_tx so that it references a fresh descriptor.
2943 * ndo_start_xmit will fill this descriptor the next time it's
2944 * called and stmmac_tx_clean may clean up to this descriptor.
2946 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2948 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2949 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2951 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2954 dev->stats.tx_bytes += skb->len;
2955 priv->xstats.tx_tso_frames++;
2956 priv->xstats.tx_tso_nfrags += nfrags;
2958 /* Manage tx mitigation */
2959 tx_q->tx_count_frames += nfrags + 1;
2960 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
2961 stmmac_set_tx_ic(priv, desc);
2962 priv->xstats.tx_set_ic_bit++;
2963 tx_q->tx_count_frames = 0;
2965 stmmac_tx_timer_arm(priv, queue);
2968 skb_tx_timestamp(skb);
2970 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2971 priv->hwts_tx_en)) {
2972 /* declare that device is doing timestamping */
2973 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2974 stmmac_enable_tx_timestamp(priv, first);
2977 /* Complete the first descriptor before granting the DMA */
2978 stmmac_prepare_tso_tx_desc(priv, first, 1,
2981 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2982 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2984 /* If context desc is used to change MSS */
2986 /* Make sure that first descriptor has been completely
2987 * written, including its own bit. This is because MSS is
2988 * actually before first descriptor, so we need to make
2989 * sure that MSS's own bit is the last thing written.
2992 stmmac_set_tx_owner(priv, mss_desc);
2995 /* The own bit must be the latest setting done when prepare the
2996 * descriptor and then barrier is needed to make sure that
2997 * all is coherent before granting the DMA engine.
3001 if (netif_msg_pktdata(priv)) {
3002 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3003 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3004 tx_q->cur_tx, first, nfrags);
3006 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3008 pr_info(">>> frame to be transmitted: ");
3009 print_pkt(skb->data, skb_headlen(skb));
3012 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3014 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3015 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3017 return NETDEV_TX_OK;
3020 dev_err(priv->device, "Tx dma map failed\n");
3022 priv->dev->stats.tx_dropped++;
3023 return NETDEV_TX_OK;
3027 * stmmac_xmit - Tx entry point of the driver
3028 * @skb : the socket buffer
3029 * @dev : device pointer
3030 * Description : this is the tx entry point of the driver.
3031 * It programs the chain or the ring and supports oversized frames
3034 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3036 struct stmmac_priv *priv = netdev_priv(dev);
3037 unsigned int nopaged_len = skb_headlen(skb);
3038 int i, csum_insertion = 0, is_jumbo = 0;
3039 u32 queue = skb_get_queue_mapping(skb);
3040 int nfrags = skb_shinfo(skb)->nr_frags;
3042 unsigned int first_entry;
3043 struct dma_desc *desc, *first;
3044 struct stmmac_tx_queue *tx_q;
3045 unsigned int enh_desc;
3048 tx_q = &priv->tx_queue[queue];
3050 if (priv->tx_path_in_lpi_mode)
3051 stmmac_disable_eee_mode(priv);
3053 /* Manage oversized TCP frames for GMAC4 device */
3054 if (skb_is_gso(skb) && priv->tso) {
3055 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3057 * There is no way to determine the number of TSO
3058 * capable Queues. Let's use always the Queue 0
3059 * because if TSO is supported then at least this
3060 * one will be capable.
3062 skb_set_queue_mapping(skb, 0);
3064 return stmmac_tso_xmit(skb, dev);
3068 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3069 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3070 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3072 /* This is a hard error, log it. */
3073 netdev_err(priv->dev,
3074 "%s: Tx Ring full when queue awake\n",
3077 return NETDEV_TX_BUSY;
3080 entry = tx_q->cur_tx;
3081 first_entry = entry;
3082 WARN_ON(tx_q->tx_skbuff[first_entry]);
3084 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3086 if (likely(priv->extend_desc))
3087 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3089 desc = tx_q->dma_tx + entry;
3093 enh_desc = priv->plat->enh_desc;
3094 /* To program the descriptors according to the size of the frame */
3096 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3098 if (unlikely(is_jumbo)) {
3099 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3100 if (unlikely(entry < 0) && (entry != -EINVAL))
3104 for (i = 0; i < nfrags; i++) {
3105 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3106 int len = skb_frag_size(frag);
3107 bool last_segment = (i == (nfrags - 1));
3109 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3110 WARN_ON(tx_q->tx_skbuff[entry]);
3112 if (likely(priv->extend_desc))
3113 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3115 desc = tx_q->dma_tx + entry;
3117 des = skb_frag_dma_map(priv->device, frag, 0, len,
3119 if (dma_mapping_error(priv->device, des))
3120 goto dma_map_err; /* should reuse desc w/o issues */
3122 tx_q->tx_skbuff_dma[entry].buf = des;
3124 stmmac_set_desc_addr(priv, desc, des);
3126 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3127 tx_q->tx_skbuff_dma[entry].len = len;
3128 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3130 /* Prepare the descriptor and set the own bit too */
3131 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3132 priv->mode, 1, last_segment, skb->len);
3135 /* Only the last descriptor gets to point to the skb. */
3136 tx_q->tx_skbuff[entry] = skb;
3138 /* We've used all descriptors we need for this skb, however,
3139 * advance cur_tx so that it references a fresh descriptor.
3140 * ndo_start_xmit will fill this descriptor the next time it's
3141 * called and stmmac_tx_clean may clean up to this descriptor.
3143 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3144 tx_q->cur_tx = entry;
3146 if (netif_msg_pktdata(priv)) {
3149 netdev_dbg(priv->dev,
3150 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3151 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3152 entry, first, nfrags);
3154 if (priv->extend_desc)
3155 tx_head = (void *)tx_q->dma_etx;
3157 tx_head = (void *)tx_q->dma_tx;
3159 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3161 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3162 print_pkt(skb->data, skb->len);
3165 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3166 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3168 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3171 dev->stats.tx_bytes += skb->len;
3173 /* According to the coalesce parameter the IC bit for the latest
3174 * segment is reset and the timer re-started to clean the tx status.
3175 * This approach takes care about the fragments: desc is the first
3176 * element in case of no SG.
3178 tx_q->tx_count_frames += nfrags + 1;
3179 if (priv->tx_coal_frames <= tx_q->tx_count_frames) {
3180 stmmac_set_tx_ic(priv, desc);
3181 priv->xstats.tx_set_ic_bit++;
3182 tx_q->tx_count_frames = 0;
3184 stmmac_tx_timer_arm(priv, queue);
3187 skb_tx_timestamp(skb);
3189 /* Ready to fill the first descriptor and set the OWN bit w/o any
3190 * problems because all the descriptors are actually ready to be
3191 * passed to the DMA engine.
3193 if (likely(!is_jumbo)) {
3194 bool last_segment = (nfrags == 0);
3196 des = dma_map_single(priv->device, skb->data,
3197 nopaged_len, DMA_TO_DEVICE);
3198 if (dma_mapping_error(priv->device, des))
3201 tx_q->tx_skbuff_dma[first_entry].buf = des;
3203 stmmac_set_desc_addr(priv, first, des);
3205 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3206 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3208 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3209 priv->hwts_tx_en)) {
3210 /* declare that device is doing timestamping */
3211 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3212 stmmac_enable_tx_timestamp(priv, first);
3215 /* Prepare the first descriptor setting the OWN bit too */
3216 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3217 csum_insertion, priv->mode, 1, last_segment,
3220 stmmac_set_tx_owner(priv, first);
3223 /* The own bit must be the latest setting done when prepare the
3224 * descriptor and then barrier is needed to make sure that
3225 * all is coherent before granting the DMA engine.
3229 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3231 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3233 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3234 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3236 return NETDEV_TX_OK;
3239 netdev_err(priv->dev, "Tx DMA map failed\n");
3241 priv->dev->stats.tx_dropped++;
3242 return NETDEV_TX_OK;
3245 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3247 struct vlan_ethhdr *veth;
3251 veth = (struct vlan_ethhdr *)skb->data;
3252 vlan_proto = veth->h_vlan_proto;
3254 if ((vlan_proto == htons(ETH_P_8021Q) &&
3255 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3256 (vlan_proto == htons(ETH_P_8021AD) &&
3257 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3258 /* pop the vlan tag */
3259 vlanid = ntohs(veth->h_vlan_TCI);
3260 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3261 skb_pull(skb, VLAN_HLEN);
3262 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3267 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3269 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3276 * stmmac_rx_refill - refill used skb preallocated buffers
3277 * @priv: driver private structure
3278 * @queue: RX queue index
3279 * Description : this is to reallocate the skb for the reception process
3280 * that is based on zero-copy.
3282 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3284 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3285 int dirty = stmmac_rx_dirty(priv, queue);
3286 unsigned int entry = rx_q->dirty_rx;
3288 int bfsize = priv->dma_buf_sz;
3290 while (dirty-- > 0) {
3293 if (priv->extend_desc)
3294 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3296 p = rx_q->dma_rx + entry;
3298 if (likely(!rx_q->rx_skbuff[entry])) {
3299 struct sk_buff *skb;
3301 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3302 if (unlikely(!skb)) {
3303 /* so for a while no zero-copy! */
3304 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3305 if (unlikely(net_ratelimit()))
3306 dev_err(priv->device,
3307 "fail to alloc skb entry %d\n",
3312 rx_q->rx_skbuff[entry] = skb;
3313 rx_q->rx_skbuff_dma[entry] =
3314 dma_map_single(priv->device, skb->data, bfsize,
3316 if (dma_mapping_error(priv->device,
3317 rx_q->rx_skbuff_dma[entry])) {
3318 netdev_err(priv->dev, "Rx DMA map failed\n");
3323 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3324 stmmac_refill_desc3(priv, rx_q, p);
3326 if (rx_q->rx_zeroc_thresh > 0)
3327 rx_q->rx_zeroc_thresh--;
3329 netif_dbg(priv, rx_status, priv->dev,
3330 "refill entry #%d\n", entry);
3334 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3338 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3340 rx_q->dirty_rx = entry;
3344 * stmmac_rx - manage the receive process
3345 * @priv: driver private structure
3346 * @limit: napi bugget
3347 * @queue: RX queue index.
3348 * Description : this the function called by the napi poll method.
3349 * It gets all the frames inside the ring.
3351 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3353 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3354 struct stmmac_channel *ch = &priv->channel[queue];
3355 unsigned int entry = rx_q->cur_rx;
3356 int coe = priv->hw->rx_csum;
3357 unsigned int next_entry;
3358 unsigned int count = 0;
3361 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3363 if (netif_msg_rx_status(priv)) {
3366 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3367 if (priv->extend_desc)
3368 rx_head = (void *)rx_q->dma_erx;
3370 rx_head = (void *)rx_q->dma_rx;
3372 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3374 while (count < limit) {
3377 struct dma_desc *np;
3379 if (priv->extend_desc)
3380 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3382 p = rx_q->dma_rx + entry;
3384 /* read the status of the incoming frame */
3385 status = stmmac_rx_status(priv, &priv->dev->stats,
3387 /* check if managed by the DMA otherwise go ahead */
3388 if (unlikely(status & dma_own))
3393 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3394 next_entry = rx_q->cur_rx;
3396 if (priv->extend_desc)
3397 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3399 np = rx_q->dma_rx + next_entry;
3403 if (priv->extend_desc)
3404 stmmac_rx_extended_status(priv, &priv->dev->stats,
3405 &priv->xstats, rx_q->dma_erx + entry);
3406 if (unlikely(status == discard_frame)) {
3407 priv->dev->stats.rx_errors++;
3408 if (priv->hwts_rx_en && !priv->extend_desc) {
3409 /* DESC2 & DESC3 will be overwritten by device
3410 * with timestamp value, hence reinitialize
3411 * them in stmmac_rx_refill() function so that
3412 * device can reuse it.
3414 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3415 rx_q->rx_skbuff[entry] = NULL;
3416 dma_unmap_single(priv->device,
3417 rx_q->rx_skbuff_dma[entry],
3422 struct sk_buff *skb;
3426 stmmac_get_desc_addr(priv, p, &des);
3427 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3429 /* If frame length is greater than skb buffer size
3430 * (preallocated during init) then the packet is
3433 if (frame_len > priv->dma_buf_sz) {
3434 netdev_err(priv->dev,
3435 "len %d larger than size (%d)\n",
3436 frame_len, priv->dma_buf_sz);
3437 priv->dev->stats.rx_length_errors++;
3441 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3442 * Type frames (LLC/LLC-SNAP)
3444 * llc_snap is never checked in GMAC >= 4, so this ACS
3445 * feature is always disabled and packets need to be
3446 * stripped manually.
3448 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3449 unlikely(status != llc_snap))
3450 frame_len -= ETH_FCS_LEN;
3452 if (netif_msg_rx_status(priv)) {
3453 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3455 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3459 /* The zero-copy is always used for all the sizes
3460 * in case of GMAC4 because it needs
3461 * to refill the used descriptors, always.
3463 if (unlikely(!xmac &&
3464 ((frame_len < priv->rx_copybreak) ||
3465 stmmac_rx_threshold_count(rx_q)))) {
3466 skb = netdev_alloc_skb_ip_align(priv->dev,
3468 if (unlikely(!skb)) {
3469 if (net_ratelimit())
3470 dev_warn(priv->device,
3471 "packet dropped\n");
3472 priv->dev->stats.rx_dropped++;
3476 dma_sync_single_for_cpu(priv->device,
3480 skb_copy_to_linear_data(skb,
3482 rx_skbuff[entry]->data,
3485 skb_put(skb, frame_len);
3486 dma_sync_single_for_device(priv->device,
3491 skb = rx_q->rx_skbuff[entry];
3492 if (unlikely(!skb)) {
3493 netdev_err(priv->dev,
3494 "%s: Inconsistent Rx chain\n",
3496 priv->dev->stats.rx_dropped++;
3499 prefetch(skb->data - NET_IP_ALIGN);
3500 rx_q->rx_skbuff[entry] = NULL;
3501 rx_q->rx_zeroc_thresh++;
3503 skb_put(skb, frame_len);
3504 dma_unmap_single(priv->device,
3505 rx_q->rx_skbuff_dma[entry],
3510 if (netif_msg_pktdata(priv)) {
3511 netdev_dbg(priv->dev, "frame received (%dbytes)",
3513 print_pkt(skb->data, frame_len);
3516 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3518 stmmac_rx_vlan(priv->dev, skb);
3520 skb->protocol = eth_type_trans(skb, priv->dev);
3523 skb_checksum_none_assert(skb);
3525 skb->ip_summed = CHECKSUM_UNNECESSARY;
3527 napi_gro_receive(&ch->rx_napi, skb);
3529 priv->dev->stats.rx_packets++;
3530 priv->dev->stats.rx_bytes += frame_len;
3535 stmmac_rx_refill(priv, queue);
3537 priv->xstats.rx_pkt_n += count;
3542 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3544 struct stmmac_channel *ch =
3545 container_of(napi, struct stmmac_channel, rx_napi);
3546 struct stmmac_priv *priv = ch->priv_data;
3547 u32 chan = ch->index;
3550 priv->xstats.napi_poll++;
3552 work_done = stmmac_rx(priv, budget, chan);
3553 if (work_done < budget && napi_complete_done(napi, work_done))
3554 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3558 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3560 struct stmmac_channel *ch =
3561 container_of(napi, struct stmmac_channel, tx_napi);
3562 struct stmmac_priv *priv = ch->priv_data;
3563 struct stmmac_tx_queue *tx_q;
3564 u32 chan = ch->index;
3567 priv->xstats.napi_poll++;
3569 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3570 work_done = min(work_done, budget);
3572 if (work_done < budget && napi_complete_done(napi, work_done))
3573 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3575 /* Force transmission restart */
3576 tx_q = &priv->tx_queue[chan];
3577 if (tx_q->cur_tx != tx_q->dirty_tx) {
3578 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3579 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3588 * @dev : Pointer to net device structure
3589 * Description: this function is called when a packet transmission fails to
3590 * complete within a reasonable time. The driver will mark the error in the
3591 * netdev structure and arrange for the device to be reset to a sane state
3592 * in order to transmit a new packet.
3594 static void stmmac_tx_timeout(struct net_device *dev)
3596 struct stmmac_priv *priv = netdev_priv(dev);
3598 stmmac_global_err(priv);
3602 * stmmac_set_rx_mode - entry point for multicast addressing
3603 * @dev : pointer to the device structure
3605 * This function is a driver entry point which gets called by the kernel
3606 * whenever multicast addresses must be enabled/disabled.
3610 static void stmmac_set_rx_mode(struct net_device *dev)
3612 struct stmmac_priv *priv = netdev_priv(dev);
3614 stmmac_set_filter(priv, priv->hw, dev);
3618 * stmmac_change_mtu - entry point to change MTU size for the device.
3619 * @dev : device pointer.
3620 * @new_mtu : the new MTU size for the device.
3621 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3622 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3623 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3625 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3628 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3630 struct stmmac_priv *priv = netdev_priv(dev);
3632 if (netif_running(dev)) {
3633 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3639 netdev_update_features(dev);
3644 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3645 netdev_features_t features)
3647 struct stmmac_priv *priv = netdev_priv(dev);
3649 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3650 features &= ~NETIF_F_RXCSUM;
3652 if (!priv->plat->tx_coe)
3653 features &= ~NETIF_F_CSUM_MASK;
3655 /* Some GMAC devices have a bugged Jumbo frame support that
3656 * needs to have the Tx COE disabled for oversized frames
3657 * (due to limited buffer sizes). In this case we disable
3658 * the TX csum insertion in the TDES and not use SF.
3660 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3661 features &= ~NETIF_F_CSUM_MASK;
3663 /* Disable tso if asked by ethtool */
3664 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3665 if (features & NETIF_F_TSO)
3674 static int stmmac_set_features(struct net_device *netdev,
3675 netdev_features_t features)
3677 struct stmmac_priv *priv = netdev_priv(netdev);
3679 /* Keep the COE Type in case of csum is supporting */
3680 if (features & NETIF_F_RXCSUM)
3681 priv->hw->rx_csum = priv->plat->rx_coe;
3683 priv->hw->rx_csum = 0;
3684 /* No check needed because rx_coe has been set before and it will be
3685 * fixed in case of issue.
3687 stmmac_rx_ipc(priv, priv->hw);
3693 * stmmac_interrupt - main ISR
3694 * @irq: interrupt number.
3695 * @dev_id: to pass the net device pointer.
3696 * Description: this is the main driver interrupt service routine.
3698 * o DMA service routine (to manage incoming frame reception and transmission
3700 * o Core interrupts to manage: remote wake-up, management counter, LPI
3703 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3705 struct net_device *dev = (struct net_device *)dev_id;
3706 struct stmmac_priv *priv = netdev_priv(dev);
3707 u32 rx_cnt = priv->plat->rx_queues_to_use;
3708 u32 tx_cnt = priv->plat->tx_queues_to_use;
3713 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3714 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3717 pm_wakeup_event(priv->device, 0);
3719 if (unlikely(!dev)) {
3720 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3724 /* Check if adapter is up */
3725 if (test_bit(STMMAC_DOWN, &priv->state))
3727 /* Check if a fatal error happened */
3728 if (stmmac_safety_feat_interrupt(priv))
3731 /* To handle GMAC own interrupts */
3732 if ((priv->plat->has_gmac) || xmac) {
3733 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3736 if (unlikely(status)) {
3737 /* For LPI we need to save the tx status */
3738 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3739 priv->tx_path_in_lpi_mode = true;
3740 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3741 priv->tx_path_in_lpi_mode = false;
3744 for (queue = 0; queue < queues_count; queue++) {
3745 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3747 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3749 if (mtl_status != -EINVAL)
3750 status |= mtl_status;
3752 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3753 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3758 /* PCS link status */
3759 if (priv->hw->pcs) {
3760 if (priv->xstats.pcs_link)
3761 netif_carrier_on(dev);
3763 netif_carrier_off(dev);
3767 /* To handle DMA interrupts */
3768 stmmac_dma_interrupt(priv);
3773 #ifdef CONFIG_NET_POLL_CONTROLLER
3774 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3775 * to allow network I/O with interrupts disabled.
3777 static void stmmac_poll_controller(struct net_device *dev)
3779 disable_irq(dev->irq);
3780 stmmac_interrupt(dev->irq, dev);
3781 enable_irq(dev->irq);
3786 * stmmac_ioctl - Entry point for the Ioctl
3787 * @dev: Device pointer.
3788 * @rq: An IOCTL specefic structure, that can contain a pointer to
3789 * a proprietary structure used to pass information to the driver.
3790 * @cmd: IOCTL command
3792 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3794 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3796 int ret = -EOPNOTSUPP;
3798 if (!netif_running(dev))
3807 ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3810 ret = stmmac_hwtstamp_set(dev, rq);
3813 ret = stmmac_hwtstamp_get(dev, rq);
3822 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3825 struct stmmac_priv *priv = cb_priv;
3826 int ret = -EOPNOTSUPP;
3828 stmmac_disable_all_queues(priv);
3831 case TC_SETUP_CLSU32:
3832 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3833 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3839 stmmac_enable_all_queues(priv);
3843 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3844 struct tc_block_offload *f)
3846 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3849 switch (f->command) {
3851 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3852 priv, priv, f->extack);
3853 case TC_BLOCK_UNBIND:
3854 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3861 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3864 struct stmmac_priv *priv = netdev_priv(ndev);
3867 case TC_SETUP_BLOCK:
3868 return stmmac_setup_tc_block(priv, type_data);
3869 case TC_SETUP_QDISC_CBS:
3870 return stmmac_tc_setup_cbs(priv, priv, type_data);
3876 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3878 struct stmmac_priv *priv = netdev_priv(ndev);
3881 ret = eth_mac_addr(ndev, addr);
3885 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3890 #ifdef CONFIG_DEBUG_FS
3891 static struct dentry *stmmac_fs_dir;
3893 static void sysfs_display_ring(void *head, int size, int extend_desc,
3894 struct seq_file *seq)
3897 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3898 struct dma_desc *p = (struct dma_desc *)head;
3900 for (i = 0; i < size; i++) {
3902 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3903 i, (unsigned int)virt_to_phys(ep),
3904 le32_to_cpu(ep->basic.des0),
3905 le32_to_cpu(ep->basic.des1),
3906 le32_to_cpu(ep->basic.des2),
3907 le32_to_cpu(ep->basic.des3));
3910 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3911 i, (unsigned int)virt_to_phys(p),
3912 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3913 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3916 seq_printf(seq, "\n");
3920 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3922 struct net_device *dev = seq->private;
3923 struct stmmac_priv *priv = netdev_priv(dev);
3924 u32 rx_count = priv->plat->rx_queues_to_use;
3925 u32 tx_count = priv->plat->tx_queues_to_use;
3928 if ((dev->flags & IFF_UP) == 0)
3931 for (queue = 0; queue < rx_count; queue++) {
3932 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3934 seq_printf(seq, "RX Queue %d:\n", queue);
3936 if (priv->extend_desc) {
3937 seq_printf(seq, "Extended descriptor ring:\n");
3938 sysfs_display_ring((void *)rx_q->dma_erx,
3939 DMA_RX_SIZE, 1, seq);
3941 seq_printf(seq, "Descriptor ring:\n");
3942 sysfs_display_ring((void *)rx_q->dma_rx,
3943 DMA_RX_SIZE, 0, seq);
3947 for (queue = 0; queue < tx_count; queue++) {
3948 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3950 seq_printf(seq, "TX Queue %d:\n", queue);
3952 if (priv->extend_desc) {
3953 seq_printf(seq, "Extended descriptor ring:\n");
3954 sysfs_display_ring((void *)tx_q->dma_etx,
3955 DMA_TX_SIZE, 1, seq);
3957 seq_printf(seq, "Descriptor ring:\n");
3958 sysfs_display_ring((void *)tx_q->dma_tx,
3959 DMA_TX_SIZE, 0, seq);
3965 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3967 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3969 struct net_device *dev = seq->private;
3970 struct stmmac_priv *priv = netdev_priv(dev);
3972 if (!priv->hw_cap_support) {
3973 seq_printf(seq, "DMA HW features not supported\n");
3977 seq_printf(seq, "==============================\n");
3978 seq_printf(seq, "\tDMA HW features\n");
3979 seq_printf(seq, "==============================\n");
3981 seq_printf(seq, "\t10/100 Mbps: %s\n",
3982 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3983 seq_printf(seq, "\t1000 Mbps: %s\n",
3984 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3985 seq_printf(seq, "\tHalf duplex: %s\n",
3986 (priv->dma_cap.half_duplex) ? "Y" : "N");
3987 seq_printf(seq, "\tHash Filter: %s\n",
3988 (priv->dma_cap.hash_filter) ? "Y" : "N");
3989 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3990 (priv->dma_cap.multi_addr) ? "Y" : "N");
3991 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3992 (priv->dma_cap.pcs) ? "Y" : "N");
3993 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3994 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3995 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3996 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3997 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3998 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3999 seq_printf(seq, "\tRMON module: %s\n",
4000 (priv->dma_cap.rmon) ? "Y" : "N");
4001 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4002 (priv->dma_cap.time_stamp) ? "Y" : "N");
4003 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4004 (priv->dma_cap.atime_stamp) ? "Y" : "N");
4005 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4006 (priv->dma_cap.eee) ? "Y" : "N");
4007 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4008 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4009 (priv->dma_cap.tx_coe) ? "Y" : "N");
4010 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4011 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4012 (priv->dma_cap.rx_coe) ? "Y" : "N");
4014 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4015 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4016 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4017 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4019 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4020 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4021 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4022 priv->dma_cap.number_rx_channel);
4023 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4024 priv->dma_cap.number_tx_channel);
4025 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4026 (priv->dma_cap.enh_desc) ? "Y" : "N");
4030 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4032 static int stmmac_init_fs(struct net_device *dev)
4034 struct stmmac_priv *priv = netdev_priv(dev);
4036 /* Create per netdev entries */
4037 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4039 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
4040 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
4045 /* Entry to report DMA RX/TX rings */
4046 priv->dbgfs_rings_status =
4047 debugfs_create_file("descriptors_status", 0444,
4048 priv->dbgfs_dir, dev,
4049 &stmmac_rings_status_fops);
4051 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4052 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4053 debugfs_remove_recursive(priv->dbgfs_dir);
4058 /* Entry to report the DMA HW features */
4059 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4061 dev, &stmmac_dma_cap_fops);
4063 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4064 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4065 debugfs_remove_recursive(priv->dbgfs_dir);
4073 static void stmmac_exit_fs(struct net_device *dev)
4075 struct stmmac_priv *priv = netdev_priv(dev);
4077 debugfs_remove_recursive(priv->dbgfs_dir);
4079 #endif /* CONFIG_DEBUG_FS */
4081 static const struct net_device_ops stmmac_netdev_ops = {
4082 .ndo_open = stmmac_open,
4083 .ndo_start_xmit = stmmac_xmit,
4084 .ndo_stop = stmmac_release,
4085 .ndo_change_mtu = stmmac_change_mtu,
4086 .ndo_fix_features = stmmac_fix_features,
4087 .ndo_set_features = stmmac_set_features,
4088 .ndo_set_rx_mode = stmmac_set_rx_mode,
4089 .ndo_tx_timeout = stmmac_tx_timeout,
4090 .ndo_do_ioctl = stmmac_ioctl,
4091 .ndo_setup_tc = stmmac_setup_tc,
4092 #ifdef CONFIG_NET_POLL_CONTROLLER
4093 .ndo_poll_controller = stmmac_poll_controller,
4095 .ndo_set_mac_address = stmmac_set_mac_address,
4098 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4100 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4102 if (test_bit(STMMAC_DOWN, &priv->state))
4105 netdev_err(priv->dev, "Reset adapter.\n");
4108 netif_trans_update(priv->dev);
4109 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4110 usleep_range(1000, 2000);
4112 set_bit(STMMAC_DOWN, &priv->state);
4113 dev_close(priv->dev);
4114 dev_open(priv->dev, NULL);
4115 clear_bit(STMMAC_DOWN, &priv->state);
4116 clear_bit(STMMAC_RESETING, &priv->state);
4120 static void stmmac_service_task(struct work_struct *work)
4122 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4125 stmmac_reset_subtask(priv);
4126 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4130 * stmmac_hw_init - Init the MAC device
4131 * @priv: driver private structure
4132 * Description: this function is to configure the MAC device according to
4133 * some platform parameters or the HW capability register. It prepares the
4134 * driver to use either ring or chain modes and to setup either enhanced or
4135 * normal descriptors.
4137 static int stmmac_hw_init(struct stmmac_priv *priv)
4141 /* dwmac-sun8i only work in chain mode */
4142 if (priv->plat->has_sun8i)
4144 priv->chain_mode = chain_mode;
4146 /* Initialize HW Interface */
4147 ret = stmmac_hwif_init(priv);
4151 /* Get the HW capability (new GMAC newer than 3.50a) */
4152 priv->hw_cap_support = stmmac_get_hw_features(priv);
4153 if (priv->hw_cap_support) {
4154 dev_info(priv->device, "DMA HW capability register supported\n");
4156 /* We can override some gmac/dma configuration fields: e.g.
4157 * enh_desc, tx_coe (e.g. that are passed through the
4158 * platform) with the values from the HW capability
4159 * register (if supported).
4161 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4162 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4163 priv->hw->pmt = priv->plat->pmt;
4165 /* TXCOE doesn't work in thresh DMA mode */
4166 if (priv->plat->force_thresh_dma_mode)
4167 priv->plat->tx_coe = 0;
4169 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4171 /* In case of GMAC4 rx_coe is from HW cap register. */
4172 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4174 if (priv->dma_cap.rx_coe_type2)
4175 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4176 else if (priv->dma_cap.rx_coe_type1)
4177 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4180 dev_info(priv->device, "No HW DMA feature register supported\n");
4183 if (priv->plat->rx_coe) {
4184 priv->hw->rx_csum = priv->plat->rx_coe;
4185 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4186 if (priv->synopsys_id < DWMAC_CORE_4_00)
4187 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4189 if (priv->plat->tx_coe)
4190 dev_info(priv->device, "TX Checksum insertion supported\n");
4192 if (priv->plat->pmt) {
4193 dev_info(priv->device, "Wake-Up On Lan supported\n");
4194 device_set_wakeup_capable(priv->device, 1);
4197 if (priv->dma_cap.tsoen)
4198 dev_info(priv->device, "TSO supported\n");
4200 /* Run HW quirks, if any */
4201 if (priv->hwif_quirks) {
4202 ret = priv->hwif_quirks(priv);
4207 /* Rx Watchdog is available in the COREs newer than the 3.40.
4208 * In some case, for example on bugged HW this feature
4209 * has to be disable and this can be done by passing the
4210 * riwt_off field from the platform.
4212 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4213 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4215 dev_info(priv->device,
4216 "Enable RX Mitigation via HW Watchdog Timer\n");
4224 * @device: device pointer
4225 * @plat_dat: platform data pointer
4226 * @res: stmmac resource pointer
4227 * Description: this is the main probe function used to
4228 * call the alloc_etherdev, allocate the priv structure.
4230 * returns 0 on success, otherwise errno.
4232 int stmmac_dvr_probe(struct device *device,
4233 struct plat_stmmacenet_data *plat_dat,
4234 struct stmmac_resources *res)
4236 struct net_device *ndev = NULL;
4237 struct stmmac_priv *priv;
4241 ndev = alloc_etherdev_mqs(sizeof(struct stmmac_priv),
4247 SET_NETDEV_DEV(ndev, device);
4249 priv = netdev_priv(ndev);
4250 priv->device = device;
4253 stmmac_set_ethtool_ops(ndev);
4254 priv->pause = pause;
4255 priv->plat = plat_dat;
4256 priv->ioaddr = res->addr;
4257 priv->dev->base_addr = (unsigned long)res->addr;
4259 priv->dev->irq = res->irq;
4260 priv->wol_irq = res->wol_irq;
4261 priv->lpi_irq = res->lpi_irq;
4264 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4266 dev_set_drvdata(device, priv->dev);
4268 /* Verify driver arguments */
4269 stmmac_verify_args();
4271 /* Allocate workqueue */
4272 priv->wq = create_singlethread_workqueue("stmmac_wq");
4274 dev_err(priv->device, "failed to create workqueue\n");
4279 INIT_WORK(&priv->service_task, stmmac_service_task);
4281 /* Override with kernel parameters if supplied XXX CRS XXX
4282 * this needs to have multiple instances
4284 if ((phyaddr >= 0) && (phyaddr <= 31))
4285 priv->plat->phy_addr = phyaddr;
4287 if (priv->plat->stmmac_rst) {
4288 ret = reset_control_assert(priv->plat->stmmac_rst);
4289 reset_control_deassert(priv->plat->stmmac_rst);
4290 /* Some reset controllers have only reset callback instead of
4291 * assert + deassert callbacks pair.
4293 if (ret == -ENOTSUPP)
4294 reset_control_reset(priv->plat->stmmac_rst);
4297 /* Init MAC and get the capabilities */
4298 ret = stmmac_hw_init(priv);
4302 /* Configure real RX and TX queues */
4303 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4304 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4306 ndev->netdev_ops = &stmmac_netdev_ops;
4308 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4311 ret = stmmac_tc_init(priv, priv);
4313 ndev->hw_features |= NETIF_F_HW_TC;
4316 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4317 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4319 dev_info(priv->device, "TSO feature enabled\n");
4321 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4322 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4323 #ifdef STMMAC_VLAN_TAG_USED
4324 /* Both mac100 and gmac support receive VLAN tag detection */
4325 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4327 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4329 /* MTU range: 46 - hw-specific max */
4330 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4331 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4332 ndev->max_mtu = JUMBO_LEN;
4333 else if (priv->plat->has_xgmac)
4334 ndev->max_mtu = XGMAC_JUMBO_LEN;
4336 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4337 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4338 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4340 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4341 (priv->plat->maxmtu >= ndev->min_mtu))
4342 ndev->max_mtu = priv->plat->maxmtu;
4343 else if (priv->plat->maxmtu < ndev->min_mtu)
4344 dev_warn(priv->device,
4345 "%s: warning: maxmtu having invalid value (%d)\n",
4346 __func__, priv->plat->maxmtu);
4349 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4351 /* Setup channels NAPI */
4352 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4354 for (queue = 0; queue < maxq; queue++) {
4355 struct stmmac_channel *ch = &priv->channel[queue];
4357 ch->priv_data = priv;
4360 if (queue < priv->plat->rx_queues_to_use) {
4361 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4364 if (queue < priv->plat->tx_queues_to_use) {
4365 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4370 mutex_init(&priv->lock);
4372 /* If a specific clk_csr value is passed from the platform
4373 * this means that the CSR Clock Range selection cannot be
4374 * changed at run-time and it is fixed. Viceversa the driver'll try to
4375 * set the MDC clock dynamically according to the csr actual
4378 if (!priv->plat->clk_csr)
4379 stmmac_clk_csr_set(priv);
4381 priv->clk_csr = priv->plat->clk_csr;
4383 stmmac_check_pcs_mode(priv);
4385 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4386 priv->hw->pcs != STMMAC_PCS_TBI &&
4387 priv->hw->pcs != STMMAC_PCS_RTBI) {
4388 /* MDIO bus Registration */
4389 ret = stmmac_mdio_register(ndev);
4391 dev_err(priv->device,
4392 "%s: MDIO bus (id: %d) registration failed",
4393 __func__, priv->plat->bus_id);
4394 goto error_mdio_register;
4398 ret = register_netdev(ndev);
4400 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4402 goto error_netdev_register;
4405 #ifdef CONFIG_DEBUG_FS
4406 ret = stmmac_init_fs(ndev);
4408 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4414 error_netdev_register:
4415 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4416 priv->hw->pcs != STMMAC_PCS_TBI &&
4417 priv->hw->pcs != STMMAC_PCS_RTBI)
4418 stmmac_mdio_unregister(ndev);
4419 error_mdio_register:
4420 for (queue = 0; queue < maxq; queue++) {
4421 struct stmmac_channel *ch = &priv->channel[queue];
4423 if (queue < priv->plat->rx_queues_to_use)
4424 netif_napi_del(&ch->rx_napi);
4425 if (queue < priv->plat->tx_queues_to_use)
4426 netif_napi_del(&ch->tx_napi);
4429 destroy_workqueue(priv->wq);
4435 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4439 * @dev: device pointer
4440 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4441 * changes the link status, releases the DMA descriptor rings.
4443 int stmmac_dvr_remove(struct device *dev)
4445 struct net_device *ndev = dev_get_drvdata(dev);
4446 struct stmmac_priv *priv = netdev_priv(ndev);
4448 netdev_info(priv->dev, "%s: removing driver", __func__);
4450 #ifdef CONFIG_DEBUG_FS
4451 stmmac_exit_fs(ndev);
4453 stmmac_stop_all_dma(priv);
4455 stmmac_mac_set(priv, priv->ioaddr, false);
4456 netif_carrier_off(ndev);
4457 unregister_netdev(ndev);
4458 if (priv->plat->stmmac_rst)
4459 reset_control_assert(priv->plat->stmmac_rst);
4460 clk_disable_unprepare(priv->plat->pclk);
4461 clk_disable_unprepare(priv->plat->stmmac_clk);
4462 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4463 priv->hw->pcs != STMMAC_PCS_TBI &&
4464 priv->hw->pcs != STMMAC_PCS_RTBI)
4465 stmmac_mdio_unregister(ndev);
4466 destroy_workqueue(priv->wq);
4467 mutex_destroy(&priv->lock);
4472 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4475 * stmmac_suspend - suspend callback
4476 * @dev: device pointer
4477 * Description: this is the function to suspend the device and it is called
4478 * by the platform driver to stop the network queue, release the resources,
4479 * program the PMT register (for WoL), clean and release driver resources.
4481 int stmmac_suspend(struct device *dev)
4483 struct net_device *ndev = dev_get_drvdata(dev);
4484 struct stmmac_priv *priv = netdev_priv(ndev);
4486 if (!ndev || !netif_running(ndev))
4490 phy_stop(ndev->phydev);
4492 mutex_lock(&priv->lock);
4494 netif_device_detach(ndev);
4495 stmmac_stop_all_queues(priv);
4497 stmmac_disable_all_queues(priv);
4499 /* Stop TX/RX DMA */
4500 stmmac_stop_all_dma(priv);
4502 /* Enable Power down mode by programming the PMT regs */
4503 if (device_may_wakeup(priv->device)) {
4504 stmmac_pmt(priv, priv->hw, priv->wolopts);
4507 stmmac_mac_set(priv, priv->ioaddr, false);
4508 pinctrl_pm_select_sleep_state(priv->device);
4509 /* Disable clock in case of PWM is off */
4510 clk_disable(priv->plat->pclk);
4511 clk_disable(priv->plat->stmmac_clk);
4513 mutex_unlock(&priv->lock);
4515 priv->oldlink = false;
4516 priv->speed = SPEED_UNKNOWN;
4517 priv->oldduplex = DUPLEX_UNKNOWN;
4520 EXPORT_SYMBOL_GPL(stmmac_suspend);
4523 * stmmac_reset_queues_param - reset queue parameters
4524 * @dev: device pointer
4526 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4528 u32 rx_cnt = priv->plat->rx_queues_to_use;
4529 u32 tx_cnt = priv->plat->tx_queues_to_use;
4532 for (queue = 0; queue < rx_cnt; queue++) {
4533 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4539 for (queue = 0; queue < tx_cnt; queue++) {
4540 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4549 * stmmac_resume - resume callback
4550 * @dev: device pointer
4551 * Description: when resume this function is invoked to setup the DMA and CORE
4552 * in a usable state.
4554 int stmmac_resume(struct device *dev)
4556 struct net_device *ndev = dev_get_drvdata(dev);
4557 struct stmmac_priv *priv = netdev_priv(ndev);
4559 if (!netif_running(ndev))
4562 /* Power Down bit, into the PM register, is cleared
4563 * automatically as soon as a magic packet or a Wake-up frame
4564 * is received. Anyway, it's better to manually clear
4565 * this bit because it can generate problems while resuming
4566 * from another devices (e.g. serial console).
4568 if (device_may_wakeup(priv->device)) {
4569 mutex_lock(&priv->lock);
4570 stmmac_pmt(priv, priv->hw, 0);
4571 mutex_unlock(&priv->lock);
4574 pinctrl_pm_select_default_state(priv->device);
4575 /* enable the clk previously disabled */
4576 clk_enable(priv->plat->stmmac_clk);
4577 clk_enable(priv->plat->pclk);
4578 /* reset the phy so that it's ready */
4580 stmmac_mdio_reset(priv->mii);
4583 netif_device_attach(ndev);
4585 mutex_lock(&priv->lock);
4587 stmmac_reset_queues_param(priv);
4589 stmmac_clear_descriptors(priv);
4591 stmmac_hw_setup(ndev, false);
4592 stmmac_init_tx_coalesce(priv);
4593 stmmac_set_rx_mode(ndev);
4595 stmmac_enable_all_queues(priv);
4597 stmmac_start_all_queues(priv);
4599 mutex_unlock(&priv->lock);
4602 phy_start(ndev->phydev);
4606 EXPORT_SYMBOL_GPL(stmmac_resume);
4609 static int __init stmmac_cmdline_opt(char *str)
4615 while ((opt = strsep(&str, ",")) != NULL) {
4616 if (!strncmp(opt, "debug:", 6)) {
4617 if (kstrtoint(opt + 6, 0, &debug))
4619 } else if (!strncmp(opt, "phyaddr:", 8)) {
4620 if (kstrtoint(opt + 8, 0, &phyaddr))
4622 } else if (!strncmp(opt, "buf_sz:", 7)) {
4623 if (kstrtoint(opt + 7, 0, &buf_sz))
4625 } else if (!strncmp(opt, "tc:", 3)) {
4626 if (kstrtoint(opt + 3, 0, &tc))
4628 } else if (!strncmp(opt, "watchdog:", 9)) {
4629 if (kstrtoint(opt + 9, 0, &watchdog))
4631 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4632 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4634 } else if (!strncmp(opt, "pause:", 6)) {
4635 if (kstrtoint(opt + 6, 0, &pause))
4637 } else if (!strncmp(opt, "eee_timer:", 10)) {
4638 if (kstrtoint(opt + 10, 0, &eee_timer))
4640 } else if (!strncmp(opt, "chain_mode:", 11)) {
4641 if (kstrtoint(opt + 11, 0, &chain_mode))
4648 pr_err("%s: ERROR broken module parameter conversion", __func__);
4652 __setup("stmmaceth=", stmmac_cmdline_opt);
4655 static int __init stmmac_init(void)
4657 #ifdef CONFIG_DEBUG_FS
4658 /* Create debugfs main directory if it doesn't exist yet */
4659 if (!stmmac_fs_dir) {
4660 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4662 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4663 pr_err("ERROR %s, debugfs create directory failed\n",
4664 STMMAC_RESOURCE_NAME);
4674 static void __exit stmmac_exit(void)
4676 #ifdef CONFIG_DEBUG_FS
4677 debugfs_remove_recursive(stmmac_fs_dir);
4681 module_init(stmmac_init)
4682 module_exit(stmmac_exit)
4684 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4685 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4686 MODULE_LICENSE("GPL");