drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 /**
   2  * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   3  *
   4  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   5  *
   6  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/stmmac.h>
  20 #include <linux/bitops.h>
  21 #include <linux/clk.h>
  22 #include <linux/phy.h>
  23 #include <linux/of_net.h>
  24 #include <linux/gpio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/delay.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include "stmmac_platform.h"
  36
  37 struct rk_priv_data;
  38 struct rk_gmac_ops {
  39         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  40                              int tx_delay, int rx_delay);
  41         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  42         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  43         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  44         void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
  45 };
  46
  47 struct rk_priv_data {
  48         struct platform_device *pdev;
  49         int phy_iface;
  50         struct regulator *regulator;
  51         bool suspended;
  52         const struct rk_gmac_ops *ops;
  53
  54         bool clk_enabled;
  55         bool clock_input;
  56         bool integrated_phy;
  57
  58         struct clk *clk_mac;
  59         struct clk *gmac_clkin;
  60         struct clk *mac_clk_rx;
  61         struct clk *mac_clk_tx;
  62         struct clk *clk_mac_ref;
  63         struct clk *clk_mac_refout;
  64         struct clk *aclk_mac;
  65         struct clk *pclk_mac;
  66         struct clk *clk_phy;
  67
  68         struct reset_control *phy_reset;
  69
  70         int tx_delay;
  71         int rx_delay;
  72
  73         struct regmap *grf;
  74 };
  75
  76 #define HIWORD_UPDATE(val, mask, shift) \
  77                 ((val) << (shift) | (mask) << ((shift) + 16))
  78
  79 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  80 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  81
  82 #define DELAY_ENABLE(soc, tx, rx) \
  83         (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
  84          ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
  85
  86 #define RK3128_GRF_MAC_CON0     0x0168
  87 #define RK3128_GRF_MAC_CON1     0x016c
  88
  89 /* RK3128_GRF_MAC_CON0 */
  90 #define RK3128_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(14)
  91 #define RK3128_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(14)
  92 #define RK3128_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(15)
  93 #define RK3128_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(15)
  94 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
  95 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
  96
  97 /* RK3128_GRF_MAC_CON1 */
  98 #define RK3128_GMAC_PHY_INTF_SEL_RGMII  \
  99                 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
 100 #define RK3128_GMAC_PHY_INTF_SEL_RMII   \
 101                 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
 102 #define RK3128_GMAC_FLOW_CTRL          GRF_BIT(9)
 103 #define RK3128_GMAC_FLOW_CTRL_CLR      GRF_CLR_BIT(9)
 104 #define RK3128_GMAC_SPEED_10M          GRF_CLR_BIT(10)
 105 #define RK3128_GMAC_SPEED_100M         GRF_BIT(10)
 106 #define RK3128_GMAC_RMII_CLK_25M       GRF_BIT(11)
 107 #define RK3128_GMAC_RMII_CLK_2_5M      GRF_CLR_BIT(11)
 108 #define RK3128_GMAC_CLK_125M           (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 109 #define RK3128_GMAC_CLK_25M            (GRF_BIT(12) | GRF_BIT(13))
 110 #define RK3128_GMAC_CLK_2_5M           (GRF_CLR_BIT(12) | GRF_BIT(13))
 111 #define RK3128_GMAC_RMII_MODE          GRF_BIT(14)
 112 #define RK3128_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(14)
 113
 114 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
 115                                 int tx_delay, int rx_delay)
 116 {
 117         struct device *dev = &bsp_priv->pdev->dev;
 118
 119         if (IS_ERR(bsp_priv->grf)) {
 120                 dev_err(dev, "Missing rockchip,grf property\n");
 121                 return;
 122         }
 123
 124         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 125                      RK3128_GMAC_PHY_INTF_SEL_RGMII |
 126                      RK3128_GMAC_RMII_MODE_CLR);
 127         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
 128                      DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
 129                      RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
 130                      RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
 131 }
 132
 133 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
 134 {
 135         struct device *dev = &bsp_priv->pdev->dev;
 136
 137         if (IS_ERR(bsp_priv->grf)) {
 138                 dev_err(dev, "Missing rockchip,grf property\n");
 139                 return;
 140         }
 141
 142         regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 143                      RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
 144 }
 145
 146 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 147 {
 148         struct device *dev = &bsp_priv->pdev->dev;
 149
 150         if (IS_ERR(bsp_priv->grf)) {
 151                 dev_err(dev, "Missing rockchip,grf property\n");
 152                 return;
 153         }
 154
 155         if (speed == 10)
 156                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 157                              RK3128_GMAC_CLK_2_5M);
 158         else if (speed == 100)
 159                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 160                              RK3128_GMAC_CLK_25M);
 161         else if (speed == 1000)
 162                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 163                              RK3128_GMAC_CLK_125M);
 164         else
 165                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 166 }
 167
 168 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 169 {
 170         struct device *dev = &bsp_priv->pdev->dev;
 171
 172         if (IS_ERR(bsp_priv->grf)) {
 173                 dev_err(dev, "Missing rockchip,grf property\n");
 174                 return;
 175         }
 176
 177         if (speed == 10) {
 178                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 179                              RK3128_GMAC_RMII_CLK_2_5M |
 180                              RK3128_GMAC_SPEED_10M);
 181         } else if (speed == 100) {
 182                 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
 183                              RK3128_GMAC_RMII_CLK_25M |
 184                              RK3128_GMAC_SPEED_100M);
 185         } else {
 186                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 187         }
 188 }
 189
 190 static const struct rk_gmac_ops rk3128_ops = {
 191         .set_to_rgmii = rk3128_set_to_rgmii,
 192         .set_to_rmii = rk3128_set_to_rmii,
 193         .set_rgmii_speed = rk3128_set_rgmii_speed,
 194         .set_rmii_speed = rk3128_set_rmii_speed,
 195 };
 196
 197 #define RK3228_GRF_MAC_CON0     0x0900
 198 #define RK3228_GRF_MAC_CON1     0x0904
 199
 200 #define RK3228_GRF_CON_MUX      0x50
 201
 202 /* RK3228_GRF_MAC_CON0 */
 203 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 204 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 205
 206 /* RK3228_GRF_MAC_CON1 */
 207 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
 208                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 209 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
 210                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 211 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
 212 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 213 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 214 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
 215 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
 216 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 217 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
 218 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
 219 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
 220 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
 221 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
 222 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 223 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 224 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 225 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 226
 227 /* RK3228_GRF_COM_MUX */
 228 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY  GRF_BIT(15)
 229
 230 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 231                                 int tx_delay, int rx_delay)
 232 {
 233         struct device *dev = &bsp_priv->pdev->dev;
 234
 235         if (IS_ERR(bsp_priv->grf)) {
 236                 dev_err(dev, "Missing rockchip,grf property\n");
 237                 return;
 238         }
 239
 240         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 241                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 242                      RK3228_GMAC_RMII_MODE_CLR |
 243                      DELAY_ENABLE(RK3228, tx_delay, rx_delay));
 244
 245         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 246                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 247                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 248 }
 249
 250 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 251 {
 252         struct device *dev = &bsp_priv->pdev->dev;
 253
 254         if (IS_ERR(bsp_priv->grf)) {
 255                 dev_err(dev, "Missing rockchip,grf property\n");
 256                 return;
 257         }
 258
 259         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 260                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 261                      RK3228_GMAC_RMII_MODE);
 262
 263         /* set MAC to RMII mode */
 264         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 265 }
 266
 267 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 268 {
 269         struct device *dev = &bsp_priv->pdev->dev;
 270
 271         if (IS_ERR(bsp_priv->grf)) {
 272                 dev_err(dev, "Missing rockchip,grf property\n");
 273                 return;
 274         }
 275
 276         if (speed == 10)
 277                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 278                              RK3228_GMAC_CLK_2_5M);
 279         else if (speed == 100)
 280                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 281                              RK3228_GMAC_CLK_25M);
 282         else if (speed == 1000)
 283                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 284                              RK3228_GMAC_CLK_125M);
 285         else
 286                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 287 }
 288
 289 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 290 {
 291         struct device *dev = &bsp_priv->pdev->dev;
 292
 293         if (IS_ERR(bsp_priv->grf)) {
 294                 dev_err(dev, "Missing rockchip,grf property\n");
 295                 return;
 296         }
 297
 298         if (speed == 10)
 299                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 300                              RK3228_GMAC_RMII_CLK_2_5M |
 301                              RK3228_GMAC_SPEED_10M);
 302         else if (speed == 100)
 303                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 304                              RK3228_GMAC_RMII_CLK_25M |
 305                              RK3228_GMAC_SPEED_100M);
 306         else
 307                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 308 }
 309
 310 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
 311 {
 312         regmap_write(priv->grf, RK3228_GRF_CON_MUX,
 313                      RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
 314 }
 315
 316 static const struct rk_gmac_ops rk3228_ops = {
 317         .set_to_rgmii = rk3228_set_to_rgmii,
 318         .set_to_rmii = rk3228_set_to_rmii,
 319         .set_rgmii_speed = rk3228_set_rgmii_speed,
 320         .set_rmii_speed = rk3228_set_rmii_speed,
 321         .integrated_phy_powerup =  rk3228_integrated_phy_powerup,
 322 };
 323
 324 #define RK3288_GRF_SOC_CON1     0x0248
 325 #define RK3288_GRF_SOC_CON3     0x0250
 326
 327 /*RK3288_GRF_SOC_CON1*/
 328 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 329                                          GRF_CLR_BIT(8))
 330 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 331                                          GRF_BIT(8))
 332 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 333 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 334 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 335 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 336 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 337 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 338 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 339 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 340 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 341 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 342 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 343
 344 /*RK3288_GRF_SOC_CON3*/
 345 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 346 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 347 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 348 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 349 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 350 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 351
 352 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 353                                 int tx_delay, int rx_delay)
 354 {
 355         struct device *dev = &bsp_priv->pdev->dev;
 356
 357         if (IS_ERR(bsp_priv->grf)) {
 358                 dev_err(dev, "Missing rockchip,grf property\n");
 359                 return;
 360         }
 361
 362         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 363                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 364                      RK3288_GMAC_RMII_MODE_CLR);
 365         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 366                      DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
 367                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 368                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 369 }
 370
 371 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 372 {
 373         struct device *dev = &bsp_priv->pdev->dev;
 374
 375         if (IS_ERR(bsp_priv->grf)) {
 376                 dev_err(dev, "Missing rockchip,grf property\n");
 377                 return;
 378         }
 379
 380         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 381                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 382 }
 383
 384 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 385 {
 386         struct device *dev = &bsp_priv->pdev->dev;
 387
 388         if (IS_ERR(bsp_priv->grf)) {
 389                 dev_err(dev, "Missing rockchip,grf property\n");
 390                 return;
 391         }
 392
 393         if (speed == 10)
 394                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 395                              RK3288_GMAC_CLK_2_5M);
 396         else if (speed == 100)
 397                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 398                              RK3288_GMAC_CLK_25M);
 399         else if (speed == 1000)
 400                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 401                              RK3288_GMAC_CLK_125M);
 402         else
 403                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 404 }
 405
 406 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 407 {
 408         struct device *dev = &bsp_priv->pdev->dev;
 409
 410         if (IS_ERR(bsp_priv->grf)) {
 411                 dev_err(dev, "Missing rockchip,grf property\n");
 412                 return;
 413         }
 414
 415         if (speed == 10) {
 416                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 417                              RK3288_GMAC_RMII_CLK_2_5M |
 418                              RK3288_GMAC_SPEED_10M);
 419         } else if (speed == 100) {
 420                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 421                              RK3288_GMAC_RMII_CLK_25M |
 422                              RK3288_GMAC_SPEED_100M);
 423         } else {
 424                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 425         }
 426 }
 427
 428 static const struct rk_gmac_ops rk3288_ops = {
 429         .set_to_rgmii = rk3288_set_to_rgmii,
 430         .set_to_rmii = rk3288_set_to_rmii,
 431         .set_rgmii_speed = rk3288_set_rgmii_speed,
 432         .set_rmii_speed = rk3288_set_rmii_speed,
 433 };
 434
 435 #define RK3328_GRF_MAC_CON0     0x0900
 436 #define RK3328_GRF_MAC_CON1     0x0904
 437 #define RK3328_GRF_MAC_CON2     0x0908
 438 #define RK3328_GRF_MACPHY_CON1  0xb04
 439
 440 /* RK3328_GRF_MAC_CON0 */
 441 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 442 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 443
 444 /* RK3328_GRF_MAC_CON1 */
 445 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 446                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 447 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 448                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 449 #define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 450 #define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 451 #define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 452 #define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 453 #define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 454 #define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 455 #define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 456 #define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 457 #define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 458 #define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 459 #define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 460 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 461 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 462 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 463 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 464
 465 /* RK3328_GRF_MACPHY_CON1 */
 466 #define RK3328_MACPHY_RMII_MODE         GRF_BIT(9)
 467
 468 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 469                                 int tx_delay, int rx_delay)
 470 {
 471         struct device *dev = &bsp_priv->pdev->dev;
 472
 473         if (IS_ERR(bsp_priv->grf)) {
 474                 dev_err(dev, "Missing rockchip,grf property\n");
 475                 return;
 476         }
 477
 478         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 479                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 480                      RK3328_GMAC_RMII_MODE_CLR |
 481                      RK3328_GMAC_RXCLK_DLY_ENABLE |
 482                      RK3328_GMAC_TXCLK_DLY_ENABLE);
 483
 484         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 485                      RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 486                      RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 487 }
 488
 489 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 490 {
 491         struct device *dev = &bsp_priv->pdev->dev;
 492         unsigned int reg;
 493
 494         if (IS_ERR(bsp_priv->grf)) {
 495                 dev_err(dev, "Missing rockchip,grf property\n");
 496                 return;
 497         }
 498
 499         reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 500                   RK3328_GRF_MAC_CON1;
 501
 502         regmap_write(bsp_priv->grf, reg,
 503                      RK3328_GMAC_PHY_INTF_SEL_RMII |
 504                      RK3328_GMAC_RMII_MODE);
 505 }
 506
 507 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 508 {
 509         struct device *dev = &bsp_priv->pdev->dev;
 510
 511         if (IS_ERR(bsp_priv->grf)) {
 512                 dev_err(dev, "Missing rockchip,grf property\n");
 513                 return;
 514         }
 515
 516         if (speed == 10)
 517                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 518                              RK3328_GMAC_CLK_2_5M);
 519         else if (speed == 100)
 520                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 521                              RK3328_GMAC_CLK_25M);
 522         else if (speed == 1000)
 523                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 524                              RK3328_GMAC_CLK_125M);
 525         else
 526                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 527 }
 528
 529 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 530 {
 531         struct device *dev = &bsp_priv->pdev->dev;
 532         unsigned int reg;
 533
 534         if (IS_ERR(bsp_priv->grf)) {
 535                 dev_err(dev, "Missing rockchip,grf property\n");
 536                 return;
 537         }
 538
 539         reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
 540                   RK3328_GRF_MAC_CON1;
 541
 542         if (speed == 10)
 543                 regmap_write(bsp_priv->grf, reg,
 544                              RK3328_GMAC_RMII_CLK_2_5M |
 545                              RK3328_GMAC_SPEED_10M);
 546         else if (speed == 100)
 547                 regmap_write(bsp_priv->grf, reg,
 548                              RK3328_GMAC_RMII_CLK_25M |
 549                              RK3328_GMAC_SPEED_100M);
 550         else
 551                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 552 }
 553
 554 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
 555 {
 556         regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
 557                      RK3328_MACPHY_RMII_MODE);
 558 }
 559
 560 static const struct rk_gmac_ops rk3328_ops = {
 561         .set_to_rgmii = rk3328_set_to_rgmii,
 562         .set_to_rmii = rk3328_set_to_rmii,
 563         .set_rgmii_speed = rk3328_set_rgmii_speed,
 564         .set_rmii_speed = rk3328_set_rmii_speed,
 565         .integrated_phy_powerup =  rk3328_integrated_phy_powerup,
 566 };
 567
 568 #define RK3366_GRF_SOC_CON6     0x0418
 569 #define RK3366_GRF_SOC_CON7     0x041c
 570
 571 /* RK3366_GRF_SOC_CON6 */
 572 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 573                                          GRF_CLR_BIT(11))
 574 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 575                                          GRF_BIT(11))
 576 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 577 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 578 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 579 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 580 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 581 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 582 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 583 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 584 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 585 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 586 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 587
 588 /* RK3366_GRF_SOC_CON7 */
 589 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 590 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 591 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 592 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 593 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 594 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 595
 596 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 597                                 int tx_delay, int rx_delay)
 598 {
 599         struct device *dev = &bsp_priv->pdev->dev;
 600
 601         if (IS_ERR(bsp_priv->grf)) {
 602                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 603                 return;
 604         }
 605
 606         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 607                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 608                      RK3366_GMAC_RMII_MODE_CLR);
 609         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 610                      DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
 611                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 612                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 613 }
 614
 615 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 616 {
 617         struct device *dev = &bsp_priv->pdev->dev;
 618
 619         if (IS_ERR(bsp_priv->grf)) {
 620                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 621                 return;
 622         }
 623
 624         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 625                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 626 }
 627
 628 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 629 {
 630         struct device *dev = &bsp_priv->pdev->dev;
 631
 632         if (IS_ERR(bsp_priv->grf)) {
 633                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 634                 return;
 635         }
 636
 637         if (speed == 10)
 638                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 639                              RK3366_GMAC_CLK_2_5M);
 640         else if (speed == 100)
 641                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 642                              RK3366_GMAC_CLK_25M);
 643         else if (speed == 1000)
 644                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 645                              RK3366_GMAC_CLK_125M);
 646         else
 647                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 648 }
 649
 650 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 651 {
 652         struct device *dev = &bsp_priv->pdev->dev;
 653
 654         if (IS_ERR(bsp_priv->grf)) {
 655                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 656                 return;
 657         }
 658
 659         if (speed == 10) {
 660                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 661                              RK3366_GMAC_RMII_CLK_2_5M |
 662                              RK3366_GMAC_SPEED_10M);
 663         } else if (speed == 100) {
 664                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 665                              RK3366_GMAC_RMII_CLK_25M |
 666                              RK3366_GMAC_SPEED_100M);
 667         } else {
 668                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 669         }
 670 }
 671
 672 static const struct rk_gmac_ops rk3366_ops = {
 673         .set_to_rgmii = rk3366_set_to_rgmii,
 674         .set_to_rmii = rk3366_set_to_rmii,
 675         .set_rgmii_speed = rk3366_set_rgmii_speed,
 676         .set_rmii_speed = rk3366_set_rmii_speed,
 677 };
 678
 679 #define RK3368_GRF_SOC_CON15    0x043c
 680 #define RK3368_GRF_SOC_CON16    0x0440
 681
 682 /* RK3368_GRF_SOC_CON15 */
 683 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 684                                          GRF_CLR_BIT(11))
 685 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 686                                          GRF_BIT(11))
 687 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 688 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 689 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 690 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 691 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 692 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 693 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 694 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 695 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 696 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 697 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 698
 699 /* RK3368_GRF_SOC_CON16 */
 700 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 701 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 702 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 703 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 704 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 705 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 706
 707 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 708                                 int tx_delay, int rx_delay)
 709 {
 710         struct device *dev = &bsp_priv->pdev->dev;
 711
 712         if (IS_ERR(bsp_priv->grf)) {
 713                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 714                 return;
 715         }
 716
 717         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 718                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 719                      RK3368_GMAC_RMII_MODE_CLR);
 720         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 721                      DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
 722                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 723                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 724 }
 725
 726 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 727 {
 728         struct device *dev = &bsp_priv->pdev->dev;
 729
 730         if (IS_ERR(bsp_priv->grf)) {
 731                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 732                 return;
 733         }
 734
 735         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 736                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 737 }
 738
 739 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 740 {
 741         struct device *dev = &bsp_priv->pdev->dev;
 742
 743         if (IS_ERR(bsp_priv->grf)) {
 744                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 745                 return;
 746         }
 747
 748         if (speed == 10)
 749                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 750                              RK3368_GMAC_CLK_2_5M);
 751         else if (speed == 100)
 752                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 753                              RK3368_GMAC_CLK_25M);
 754         else if (speed == 1000)
 755                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 756                              RK3368_GMAC_CLK_125M);
 757         else
 758                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 759 }
 760
 761 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 762 {
 763         struct device *dev = &bsp_priv->pdev->dev;
 764
 765         if (IS_ERR(bsp_priv->grf)) {
 766                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 767                 return;
 768         }
 769
 770         if (speed == 10) {
 771                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 772                              RK3368_GMAC_RMII_CLK_2_5M |
 773                              RK3368_GMAC_SPEED_10M);
 774         } else if (speed == 100) {
 775                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 776                              RK3368_GMAC_RMII_CLK_25M |
 777                              RK3368_GMAC_SPEED_100M);
 778         } else {
 779                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 780         }
 781 }
 782
 783 static const struct rk_gmac_ops rk3368_ops = {
 784         .set_to_rgmii = rk3368_set_to_rgmii,
 785         .set_to_rmii = rk3368_set_to_rmii,
 786         .set_rgmii_speed = rk3368_set_rgmii_speed,
 787         .set_rmii_speed = rk3368_set_rmii_speed,
 788 };
 789
 790 #define RK3399_GRF_SOC_CON5     0xc214
 791 #define RK3399_GRF_SOC_CON6     0xc218
 792
 793 /* RK3399_GRF_SOC_CON5 */
 794 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 795                                          GRF_CLR_BIT(11))
 796 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 797                                          GRF_BIT(11))
 798 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 799 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 800 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 801 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 802 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 803 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 804 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 805 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 806 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 807 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 808 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 809
 810 /* RK3399_GRF_SOC_CON6 */
 811 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 812 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 813 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 814 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 815 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 816 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 817
 818 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 819                                 int tx_delay, int rx_delay)
 820 {
 821         struct device *dev = &bsp_priv->pdev->dev;
 822
 823         if (IS_ERR(bsp_priv->grf)) {
 824                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 825                 return;
 826         }
 827
 828         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 829                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 830                      RK3399_GMAC_RMII_MODE_CLR);
 831         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 832                      DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
 833                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 834                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 835 }
 836
 837 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 838 {
 839         struct device *dev = &bsp_priv->pdev->dev;
 840
 841         if (IS_ERR(bsp_priv->grf)) {
 842                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 843                 return;
 844         }
 845
 846         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 847                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 848 }
 849
 850 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 851 {
 852         struct device *dev = &bsp_priv->pdev->dev;
 853
 854         if (IS_ERR(bsp_priv->grf)) {
 855                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 856                 return;
 857         }
 858
 859         if (speed == 10)
 860                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 861                              RK3399_GMAC_CLK_2_5M);
 862         else if (speed == 100)
 863                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 864                              RK3399_GMAC_CLK_25M);
 865         else if (speed == 1000)
 866                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 867                              RK3399_GMAC_CLK_125M);
 868         else
 869                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 870 }
 871
 872 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 873 {
 874         struct device *dev = &bsp_priv->pdev->dev;
 875
 876         if (IS_ERR(bsp_priv->grf)) {
 877                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 878                 return;
 879         }
 880
 881         if (speed == 10) {
 882                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 883                              RK3399_GMAC_RMII_CLK_2_5M |
 884                              RK3399_GMAC_SPEED_10M);
 885         } else if (speed == 100) {
 886                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 887                              RK3399_GMAC_RMII_CLK_25M |
 888                              RK3399_GMAC_SPEED_100M);
 889         } else {
 890                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 891         }
 892 }
 893
 894 static const struct rk_gmac_ops rk3399_ops = {
 895         .set_to_rgmii = rk3399_set_to_rgmii,
 896         .set_to_rmii = rk3399_set_to_rmii,
 897         .set_rgmii_speed = rk3399_set_rgmii_speed,
 898         .set_rmii_speed = rk3399_set_rmii_speed,
 899 };
 900
 901 #define RV1108_GRF_GMAC_CON0            0X0900
 902
 903 /* RV1108_GRF_GMAC_CON0 */
 904 #define RV1108_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
 905                                         GRF_BIT(6))
 906 #define RV1108_GMAC_FLOW_CTRL           GRF_BIT(3)
 907 #define RV1108_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 908 #define RV1108_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 909 #define RV1108_GMAC_SPEED_100M          GRF_BIT(2)
 910 #define RV1108_GMAC_RMII_CLK_25M        GRF_BIT(7)
 911 #define RV1108_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 912
 913 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
 914 {
 915         struct device *dev = &bsp_priv->pdev->dev;
 916
 917         if (IS_ERR(bsp_priv->grf)) {
 918                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 919                 return;
 920         }
 921
 922         regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
 923                      RV1108_GMAC_PHY_INTF_SEL_RMII);
 924 }
 925
 926 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 927 {
 928         struct device *dev = &bsp_priv->pdev->dev;
 929
 930         if (IS_ERR(bsp_priv->grf)) {
 931                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 932                 return;
 933         }
 934
 935         if (speed == 10) {
 936                 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
 937                              RV1108_GMAC_RMII_CLK_2_5M |
 938                              RV1108_GMAC_SPEED_10M);
 939         } else if (speed == 100) {
 940                 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
 941                              RV1108_GMAC_RMII_CLK_25M |
 942                              RV1108_GMAC_SPEED_100M);
 943         } else {
 944                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 945         }
 946 }
 947
 948 static const struct rk_gmac_ops rv1108_ops = {
 949         .set_to_rmii = rv1108_set_to_rmii,
 950         .set_rmii_speed = rv1108_set_rmii_speed,
 951 };
 952
 953 #define RK_GRF_MACPHY_CON0              0xb00
 954 #define RK_GRF_MACPHY_CON1              0xb04
 955 #define RK_GRF_MACPHY_CON2              0xb08
 956 #define RK_GRF_MACPHY_CON3              0xb0c
 957
 958 #define RK_MACPHY_ENABLE                GRF_BIT(0)
 959 #define RK_MACPHY_DISABLE               GRF_CLR_BIT(0)
 960 #define RK_MACPHY_CFG_CLK_50M           GRF_BIT(14)
 961 #define RK_GMAC2PHY_RMII_MODE           (GRF_BIT(6) | GRF_CLR_BIT(7))
 962 #define RK_GRF_CON2_MACPHY_ID           HIWORD_UPDATE(0x1234, 0xffff, 0)
 963 #define RK_GRF_CON3_MACPHY_ID           HIWORD_UPDATE(0x35, 0x3f, 0)
 964
 965 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
 966 {
 967         if (priv->ops->integrated_phy_powerup)
 968                 priv->ops->integrated_phy_powerup(priv);
 969
 970         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
 971         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
 972
 973         regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
 974         regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
 975
 976         if (priv->phy_reset) {
 977                 /* PHY needs to be disabled before trying to reset it */
 978                 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
 979                 if (priv->phy_reset)
 980                         reset_control_assert(priv->phy_reset);
 981                 usleep_range(10, 20);
 982                 if (priv->phy_reset)
 983                         reset_control_deassert(priv->phy_reset);
 984                 usleep_range(10, 20);
 985                 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
 986                 msleep(30);
 987         }
 988 }
 989
 990 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
 991 {
 992         regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
 993         if (priv->phy_reset)
 994                 reset_control_assert(priv->phy_reset);
 995 }
 996
 997 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
 998 {
 999         struct rk_priv_data *bsp_priv = plat->bsp_priv;
1000         struct device *dev = &bsp_priv->pdev->dev;
1001         int ret;
1002
1003         bsp_priv->clk_enabled = false;
1004
1005         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1006         if (IS_ERR(bsp_priv->mac_clk_rx))
1007                 dev_err(dev, "cannot get clock %s\n",
1008                         "mac_clk_rx");
1009
1010         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1011         if (IS_ERR(bsp_priv->mac_clk_tx))
1012                 dev_err(dev, "cannot get clock %s\n",
1013                         "mac_clk_tx");
1014
1015         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1016         if (IS_ERR(bsp_priv->aclk_mac))
1017                 dev_err(dev, "cannot get clock %s\n",
1018                         "aclk_mac");
1019
1020         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1021         if (IS_ERR(bsp_priv->pclk_mac))
1022                 dev_err(dev, "cannot get clock %s\n",
1023                         "pclk_mac");
1024
1025         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1026         if (IS_ERR(bsp_priv->clk_mac))
1027                 dev_err(dev, "cannot get clock %s\n",
1028                         "stmmaceth");
1029
1030         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1031                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1032                 if (IS_ERR(bsp_priv->clk_mac_ref))
1033                         dev_err(dev, "cannot get clock %s\n",
1034                                 "clk_mac_ref");
1035
1036                 if (!bsp_priv->clock_input) {
1037                         bsp_priv->clk_mac_refout =
1038                                 devm_clk_get(dev, "clk_mac_refout");
1039                         if (IS_ERR(bsp_priv->clk_mac_refout))
1040                                 dev_err(dev, "cannot get clock %s\n",
1041                                         "clk_mac_refout");
1042                 }
1043         }
1044
1045         if (bsp_priv->clock_input) {
1046                 dev_info(dev, "clock input from PHY\n");
1047         } else {
1048                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1049                         clk_set_rate(bsp_priv->clk_mac, 50000000);
1050         }
1051
1052         if (plat->phy_node && bsp_priv->integrated_phy) {
1053                 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1054                 if (IS_ERR(bsp_priv->clk_phy)) {
1055                         ret = PTR_ERR(bsp_priv->clk_phy);
1056                         dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1057                         return -EINVAL;
1058                 }
1059                 clk_set_rate(bsp_priv->clk_phy, 50000000);
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1066 {
1067         int phy_iface = bsp_priv->phy_iface;
1068
1069         if (enable) {
1070                 if (!bsp_priv->clk_enabled) {
1071                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1072                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
1073                                         clk_prepare_enable(
1074                                                 bsp_priv->mac_clk_rx);
1075
1076                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
1077                                         clk_prepare_enable(
1078                                                 bsp_priv->clk_mac_ref);
1079
1080                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
1081                                         clk_prepare_enable(
1082                                                 bsp_priv->clk_mac_refout);
1083                         }
1084
1085                         if (!IS_ERR(bsp_priv->clk_phy))
1086                                 clk_prepare_enable(bsp_priv->clk_phy);
1087
1088                         if (!IS_ERR(bsp_priv->aclk_mac))
1089                                 clk_prepare_enable(bsp_priv->aclk_mac);
1090
1091                         if (!IS_ERR(bsp_priv->pclk_mac))
1092                                 clk_prepare_enable(bsp_priv->pclk_mac);
1093
1094                         if (!IS_ERR(bsp_priv->mac_clk_tx))
1095                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
1096
1097                         /**
1098                          * if (!IS_ERR(bsp_priv->clk_mac))
1099                          *      clk_prepare_enable(bsp_priv->clk_mac);
1100                          */
1101                         mdelay(5);
1102                         bsp_priv->clk_enabled = true;
1103                 }
1104         } else {
1105                 if (bsp_priv->clk_enabled) {
1106                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1107                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
1108                                         clk_disable_unprepare(
1109                                                 bsp_priv->mac_clk_rx);
1110
1111                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
1112                                         clk_disable_unprepare(
1113                                                 bsp_priv->clk_mac_ref);
1114
1115                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
1116                                         clk_disable_unprepare(
1117                                                 bsp_priv->clk_mac_refout);
1118                         }
1119
1120                         if (!IS_ERR(bsp_priv->clk_phy))
1121                                 clk_disable_unprepare(bsp_priv->clk_phy);
1122
1123                         if (!IS_ERR(bsp_priv->aclk_mac))
1124                                 clk_disable_unprepare(bsp_priv->aclk_mac);
1125
1126                         if (!IS_ERR(bsp_priv->pclk_mac))
1127                                 clk_disable_unprepare(bsp_priv->pclk_mac);
1128
1129                         if (!IS_ERR(bsp_priv->mac_clk_tx))
1130                                 clk_disable_unprepare(bsp_priv->mac_clk_tx);
1131                         /**
1132                          * if (!IS_ERR(bsp_priv->clk_mac))
1133                          *      clk_disable_unprepare(bsp_priv->clk_mac);
1134                          */
1135                         bsp_priv->clk_enabled = false;
1136                 }
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1143 {
1144         struct regulator *ldo = bsp_priv->regulator;
1145         int ret;
1146         struct device *dev = &bsp_priv->pdev->dev;
1147
1148         if (!ldo) {
1149                 dev_err(dev, "no regulator found\n");
1150                 return -1;
1151         }
1152
1153         if (enable) {
1154                 ret = regulator_enable(ldo);
1155                 if (ret)
1156                         dev_err(dev, "fail to enable phy-supply\n");
1157         } else {
1158                 ret = regulator_disable(ldo);
1159                 if (ret)
1160                         dev_err(dev, "fail to disable phy-supply\n");
1161         }
1162
1163         return 0;
1164 }
1165
1166 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1167                                           struct plat_stmmacenet_data *plat,
1168                                           const struct rk_gmac_ops *ops)
1169 {
1170         struct rk_priv_data *bsp_priv;
1171         struct device *dev = &pdev->dev;
1172         int ret;
1173         const char *strings = NULL;
1174         int value;
1175
1176         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1177         if (!bsp_priv)
1178                 return ERR_PTR(-ENOMEM);
1179
1180         bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
1181         bsp_priv->ops = ops;
1182
1183         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
1184         if (IS_ERR(bsp_priv->regulator)) {
1185                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
1186                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
1187                         return ERR_PTR(-EPROBE_DEFER);
1188                 }
1189                 dev_err(dev, "no regulator found\n");
1190                 bsp_priv->regulator = NULL;
1191         }
1192
1193         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1194         if (ret) {
1195                 dev_err(dev, "Can not read property: clock_in_out.\n");
1196                 bsp_priv->clock_input = true;
1197         } else {
1198                 dev_info(dev, "clock input or output? (%s).\n",
1199                          strings);
1200                 if (!strcmp(strings, "input"))
1201                         bsp_priv->clock_input = true;
1202                 else
1203                         bsp_priv->clock_input = false;
1204         }
1205
1206         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1207         if (ret) {
1208                 bsp_priv->tx_delay = 0x30;
1209                 dev_err(dev, "Can not read property: tx_delay.");
1210                 dev_err(dev, "set tx_delay to 0x%x\n",
1211                         bsp_priv->tx_delay);
1212         } else {
1213                 dev_info(dev, "TX delay(0x%x).\n", value);
1214                 bsp_priv->tx_delay = value;
1215         }
1216
1217         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1218         if (ret) {
1219                 bsp_priv->rx_delay = 0x10;
1220                 dev_err(dev, "Can not read property: rx_delay.");
1221                 dev_err(dev, "set rx_delay to 0x%x\n",
1222                         bsp_priv->rx_delay);
1223         } else {
1224                 dev_info(dev, "RX delay(0x%x).\n", value);
1225                 bsp_priv->rx_delay = value;
1226         }
1227
1228         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1229                                                         "rockchip,grf");
1230
1231         if (plat->phy_node) {
1232                 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1233                                                                  "phy-is-integrated");
1234                 if (bsp_priv->integrated_phy) {
1235                         bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1236                         if (IS_ERR(bsp_priv->phy_reset)) {
1237                                 dev_err(&pdev->dev, "No PHY reset control found.\n");
1238                                 bsp_priv->phy_reset = NULL;
1239                         }
1240                 }
1241         }
1242         dev_info(dev, "integrated PHY? (%s).\n",
1243                  bsp_priv->integrated_phy ? "yes" : "no");
1244
1245         bsp_priv->pdev = pdev;
1246
1247         return bsp_priv;
1248 }
1249
1250 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1251 {
1252         int ret;
1253         struct device *dev = &bsp_priv->pdev->dev;
1254
1255         ret = gmac_clk_enable(bsp_priv, true);
1256         if (ret)
1257                 return ret;
1258
1259         /*rmii or rgmii*/
1260         switch (bsp_priv->phy_iface) {
1261         case PHY_INTERFACE_MODE_RGMII:
1262                 dev_info(dev, "init for RGMII\n");
1263                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1264                                             bsp_priv->rx_delay);
1265                 break;
1266         case PHY_INTERFACE_MODE_RGMII_ID:
1267                 dev_info(dev, "init for RGMII_ID\n");
1268                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1269                 break;
1270         case PHY_INTERFACE_MODE_RGMII_RXID:
1271                 dev_info(dev, "init for RGMII_RXID\n");
1272                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1273                 break;
1274         case PHY_INTERFACE_MODE_RGMII_TXID:
1275                 dev_info(dev, "init for RGMII_TXID\n");
1276                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1277                 break;
1278         case PHY_INTERFACE_MODE_RMII:
1279                 dev_info(dev, "init for RMII\n");
1280                 bsp_priv->ops->set_to_rmii(bsp_priv);
1281                 break;
1282         default:
1283                 dev_err(dev, "NO interface defined!\n");
1284         }
1285
1286         ret = phy_power_on(bsp_priv, true);
1287         if (ret)
1288                 return ret;
1289
1290         pm_runtime_enable(dev);
1291         pm_runtime_get_sync(dev);
1292
1293         if (bsp_priv->integrated_phy)
1294                 rk_gmac_integrated_phy_powerup(bsp_priv);
1295
1296         return 0;
1297 }
1298
1299 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1300 {
1301         struct device *dev = &gmac->pdev->dev;
1302
1303         if (gmac->integrated_phy)
1304                 rk_gmac_integrated_phy_powerdown(gmac);
1305
1306         pm_runtime_put_sync(dev);
1307         pm_runtime_disable(dev);
1308
1309         phy_power_on(gmac, false);
1310         gmac_clk_enable(gmac, false);
1311 }
1312
1313 static void rk_fix_speed(void *priv, unsigned int speed)
1314 {
1315         struct rk_priv_data *bsp_priv = priv;
1316         struct device *dev = &bsp_priv->pdev->dev;
1317
1318         switch (bsp_priv->phy_iface) {
1319         case PHY_INTERFACE_MODE_RGMII:
1320         case PHY_INTERFACE_MODE_RGMII_ID:
1321         case PHY_INTERFACE_MODE_RGMII_RXID:
1322         case PHY_INTERFACE_MODE_RGMII_TXID:
1323                 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1324                 break;
1325         case PHY_INTERFACE_MODE_RMII:
1326                 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1327                 break;
1328         default:
1329                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1330         }
1331 }
1332
1333 static int rk_gmac_probe(struct platform_device *pdev)
1334 {
1335         struct plat_stmmacenet_data *plat_dat;
1336         struct stmmac_resources stmmac_res;
1337         const struct rk_gmac_ops *data;
1338         int ret;
1339
1340         data = of_device_get_match_data(&pdev->dev);
1341         if (!data) {
1342                 dev_err(&pdev->dev, "no of match data provided\n");
1343                 return -EINVAL;
1344         }
1345
1346         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1347         if (ret)
1348                 return ret;
1349
1350         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1351         if (IS_ERR(plat_dat))
1352                 return PTR_ERR(plat_dat);
1353
1354         plat_dat->has_gmac = true;
1355         plat_dat->fix_mac_speed = rk_fix_speed;
1356
1357         plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1358         if (IS_ERR(plat_dat->bsp_priv)) {
1359                 ret = PTR_ERR(plat_dat->bsp_priv);
1360                 goto err_remove_config_dt;
1361         }
1362
1363         ret = rk_gmac_clk_init(plat_dat);
1364         if (ret)
1365                 return ret;
1366
1367         ret = rk_gmac_powerup(plat_dat->bsp_priv);
1368         if (ret)
1369                 goto err_remove_config_dt;
1370
1371         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1372         if (ret)
1373                 goto err_gmac_powerdown;
1374
1375         return 0;
1376
1377 err_gmac_powerdown:
1378         rk_gmac_powerdown(plat_dat->bsp_priv);
1379 err_remove_config_dt:
1380         stmmac_remove_config_dt(pdev, plat_dat);
1381
1382         return ret;
1383 }
1384
1385 static int rk_gmac_remove(struct platform_device *pdev)
1386 {
1387         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1388         int ret = stmmac_dvr_remove(&pdev->dev);
1389
1390         rk_gmac_powerdown(bsp_priv);
1391
1392         return ret;
1393 }
1394
1395 #ifdef CONFIG_PM_SLEEP
1396 static int rk_gmac_suspend(struct device *dev)
1397 {
1398         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1399         int ret = stmmac_suspend(dev);
1400
1401         /* Keep the PHY up if we use Wake-on-Lan. */
1402         if (!device_may_wakeup(dev)) {
1403                 rk_gmac_powerdown(bsp_priv);
1404                 bsp_priv->suspended = true;
1405         }
1406
1407         return ret;
1408 }
1409
1410 static int rk_gmac_resume(struct device *dev)
1411 {
1412         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1413
1414         /* The PHY was up for Wake-on-Lan. */
1415         if (bsp_priv->suspended) {
1416                 rk_gmac_powerup(bsp_priv);
1417                 bsp_priv->suspended = false;
1418         }
1419
1420         return stmmac_resume(dev);
1421 }
1422 #endif /* CONFIG_PM_SLEEP */
1423
1424 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1425
1426 static const struct of_device_id rk_gmac_dwmac_match[] = {
1427         { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1428         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1429         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1430         { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1431         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1432         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1433         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1434         { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1435         { }
1436 };
1437 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1438
1439 static struct platform_driver rk_gmac_dwmac_driver = {
1440         .probe  = rk_gmac_probe,
1441         .remove = rk_gmac_remove,
1442         .driver = {
1443                 .name           = "rk_gmac-dwmac",
1444                 .pm             = &rk_gmac_pm_ops,
1445                 .of_match_table = rk_gmac_dwmac_match,
1446         },
1447 };
1448 module_platform_driver(rk_gmac_dwmac_driver);
1449
1450 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1451 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1452 MODULE_LICENSE("GPL");