1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/stmmac.h>
31 #include <linux/phy.h>
32 #include <linux/module.h>
33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
41 /* Synopsys Core versions */
42 #define DWMAC_CORE_3_40 0x34
43 #define DWMAC_CORE_3_50 0x35
44 #define DWMAC_CORE_4_00 0x40
45 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
47 #define DMA_TX_SIZE 512
48 #define DMA_RX_SIZE 512
49 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
51 #undef FRAME_FILTER_DEBUG
52 /* #define FRAME_FILTER_DEBUG */
54 /* Extra statistic and debug information exposed by ethtool */
55 struct stmmac_extra_stats {
57 unsigned long tx_underflow ____cacheline_aligned;
58 unsigned long tx_carrier;
59 unsigned long tx_losscarrier;
60 unsigned long vlan_tag;
61 unsigned long tx_deferred;
62 unsigned long tx_vlan;
63 unsigned long tx_jabber;
64 unsigned long tx_frame_flushed;
65 unsigned long tx_payload_error;
66 unsigned long tx_ip_header_error;
68 unsigned long rx_desc;
69 unsigned long sa_filter_fail;
70 unsigned long overflow_error;
71 unsigned long ipc_csum_error;
72 unsigned long rx_collision;
74 unsigned long dribbling_bit;
75 unsigned long rx_length;
77 unsigned long rx_multicast;
78 unsigned long rx_gmac_overflow;
79 unsigned long rx_watchdog;
80 unsigned long da_rx_filter_fail;
81 unsigned long sa_rx_filter_fail;
82 unsigned long rx_missed_cntr;
83 unsigned long rx_overflow_cntr;
84 unsigned long rx_vlan;
85 /* Tx/Rx IRQ error info */
86 unsigned long tx_undeflow_irq;
87 unsigned long tx_process_stopped_irq;
88 unsigned long tx_jabber_irq;
89 unsigned long rx_overflow_irq;
90 unsigned long rx_buf_unav_irq;
91 unsigned long rx_process_stopped_irq;
92 unsigned long rx_watchdog_irq;
93 unsigned long tx_early_irq;
94 unsigned long fatal_bus_error_irq;
95 /* Tx/Rx IRQ Events */
96 unsigned long rx_early_irq;
97 unsigned long threshold;
98 unsigned long tx_pkt_n;
99 unsigned long rx_pkt_n;
100 unsigned long normal_irq_n;
101 unsigned long rx_normal_irq_n;
102 unsigned long napi_poll;
103 unsigned long tx_normal_irq_n;
104 unsigned long tx_clean;
105 unsigned long tx_set_ic_bit;
106 unsigned long irq_receive_pmt_irq_n;
108 unsigned long mmc_tx_irq_n;
109 unsigned long mmc_rx_irq_n;
110 unsigned long mmc_rx_csum_offload_irq_n;
112 unsigned long irq_tx_path_in_lpi_mode_n;
113 unsigned long irq_tx_path_exit_lpi_mode_n;
114 unsigned long irq_rx_path_in_lpi_mode_n;
115 unsigned long irq_rx_path_exit_lpi_mode_n;
116 unsigned long phy_eee_wakeup_error_n;
117 /* Extended RDES status */
118 unsigned long ip_hdr_err;
119 unsigned long ip_payload_err;
120 unsigned long ip_csum_bypassed;
121 unsigned long ipv4_pkt_rcvd;
122 unsigned long ipv6_pkt_rcvd;
123 unsigned long rx_msg_type_ext_no_ptp;
124 unsigned long rx_msg_type_sync;
125 unsigned long rx_msg_type_follow_up;
126 unsigned long rx_msg_type_delay_req;
127 unsigned long rx_msg_type_delay_resp;
128 unsigned long rx_msg_type_pdelay_req;
129 unsigned long rx_msg_type_pdelay_resp;
130 unsigned long rx_msg_type_pdelay_follow_up;
131 unsigned long ptp_frame_type;
132 unsigned long ptp_ver;
133 unsigned long timestamp_dropped;
134 unsigned long av_pkt_rcvd;
135 unsigned long av_tagged_pkt_rcvd;
136 unsigned long vlan_tag_priority_val;
137 unsigned long l3_filter_match;
138 unsigned long l4_filter_match;
139 unsigned long l3_l4_filter_no_match;
141 unsigned long irq_pcs_ane_n;
142 unsigned long irq_pcs_link_n;
143 unsigned long irq_rgmii_n;
144 unsigned long pcs_link;
145 unsigned long pcs_duplex;
146 unsigned long pcs_speed;
148 unsigned long mtl_tx_status_fifo_full;
149 unsigned long mtl_tx_fifo_not_empty;
150 unsigned long mmtl_fifo_ctrl;
151 unsigned long mtl_tx_fifo_read_ctrl_write;
152 unsigned long mtl_tx_fifo_read_ctrl_wait;
153 unsigned long mtl_tx_fifo_read_ctrl_read;
154 unsigned long mtl_tx_fifo_read_ctrl_idle;
155 unsigned long mac_tx_in_pause;
156 unsigned long mac_tx_frame_ctrl_xfer;
157 unsigned long mac_tx_frame_ctrl_idle;
158 unsigned long mac_tx_frame_ctrl_wait;
159 unsigned long mac_tx_frame_ctrl_pause;
160 unsigned long mac_gmii_tx_proto_engine;
161 unsigned long mtl_rx_fifo_fill_level_full;
162 unsigned long mtl_rx_fifo_fill_above_thresh;
163 unsigned long mtl_rx_fifo_fill_below_thresh;
164 unsigned long mtl_rx_fifo_fill_level_empty;
165 unsigned long mtl_rx_fifo_read_ctrl_flush;
166 unsigned long mtl_rx_fifo_read_ctrl_read_data;
167 unsigned long mtl_rx_fifo_read_ctrl_status;
168 unsigned long mtl_rx_fifo_read_ctrl_idle;
169 unsigned long mtl_rx_fifo_ctrl_active;
170 unsigned long mac_rx_frame_ctrl_fifo;
171 unsigned long mac_gmii_rx_proto_engine;
174 /* CSR Frequency Access Defines*/
175 #define CSR_F_35M 35000000
176 #define CSR_F_60M 60000000
177 #define CSR_F_100M 100000000
178 #define CSR_F_150M 150000000
179 #define CSR_F_250M 250000000
180 #define CSR_F_300M 300000000
182 #define MAC_CSR_H_FRQ_MASK 0x20
184 #define HASH_TABLE_SIZE 64
185 #define PAUSE_TIME 0xffff
187 /* Flow Control defines */
191 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
194 #define STMMAC_PCS_RGMII (1 << 0)
195 #define STMMAC_PCS_SGMII (1 << 1)
196 #define STMMAC_PCS_TBI (1 << 2)
197 #define STMMAC_PCS_RTBI (1 << 3)
199 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
201 /* DAM HW feature register fields */
202 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
203 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
204 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
205 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
206 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
207 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
208 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
209 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
210 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
211 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
212 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
213 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
214 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
215 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
216 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
217 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
218 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
219 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
220 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
221 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
222 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
223 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
224 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
225 /* Timestamping with Internal System Time */
226 #define DMA_HW_FEAT_INTTSEN 0x02000000
227 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
228 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
229 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
230 #define DEFAULT_DMA_PBL 8
232 /* Max/Min RI Watchdog Timer count value */
233 #define MAX_DMA_RIWT 0xff
234 #define MIN_DMA_RIWT 0x20
235 /* Tx coalesce parameters */
236 #define STMMAC_COAL_TX_TIMER 40000
237 #define STMMAC_MAX_COAL_TX_TICK 100000
238 #define STMMAC_TX_MAX_FRAMES 256
239 #define STMMAC_TX_FRAMES 64
242 enum rx_frame_status {
252 enum tx_frame_status {
259 enum dma_irq_status {
261 tx_hard_error_bump_tc = 0x2,
266 /* EEE and LPI defines */
267 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
268 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
269 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
270 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
272 #define CORE_PCS_ANE_COMPLETE (1 << 5)
273 #define CORE_PCS_LINK_STATUS (1 << 6)
274 #define CORE_RGMII_IRQ (1 << 7)
275 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
277 /* Physical Coding Sublayer */
281 unsigned int lp_pause;
282 unsigned int lp_duplex;
285 #define STMMAC_PCS_PAUSE 1
286 #define STMMAC_PCS_ASYM_PAUSE 2
288 /* DMA HW capabilities */
289 struct dma_features {
290 unsigned int mbps_10_100;
291 unsigned int mbps_1000;
292 unsigned int half_duplex;
293 unsigned int hash_filter;
294 unsigned int multi_addr;
296 unsigned int sma_mdio;
297 unsigned int pmt_remote_wake_up;
298 unsigned int pmt_magic_frame;
301 unsigned int time_stamp;
303 unsigned int atime_stamp;
304 /* 802.3az - Energy-Efficient Ethernet (EEE) */
311 unsigned int rx_coe_type1;
312 unsigned int rx_coe_type2;
313 unsigned int rxfifo_over_2048;
314 /* TX and RX number of channels */
315 unsigned int number_rx_channel;
316 unsigned int number_tx_channel;
317 /* Alternate (enhanced) DESC mode */
318 unsigned int enh_desc;
321 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
322 #define BUF_SIZE_16KiB 16384
323 #define BUF_SIZE_8KiB 8192
324 #define BUF_SIZE_4KiB 4096
325 #define BUF_SIZE_2KiB 2048
327 /* Power Down and WOL */
328 #define PMT_NOT_SUPPORTED 0
329 #define PMT_SUPPORTED 1
331 /* Common MAC defines */
332 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
333 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
334 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
336 /* Default LPI timers */
337 #define STMMAC_DEFAULT_LIT_LS 0x3E8
338 #define STMMAC_DEFAULT_TWT_LS 0x1E
340 #define STMMAC_CHAIN_MODE 0x1
341 #define STMMAC_RING_MODE 0x2
343 #define JUMBO_LEN 9000
345 /* Descriptors helpers */
346 struct stmmac_desc_ops {
347 /* DMA RX descriptor ring initialization */
348 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
350 /* DMA TX descriptor ring initialization */
351 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
353 /* Invoked by the xmit function to prepare the tx descriptor */
354 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
355 bool csum_flag, int mode, bool tx_own,
357 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
358 int len2, bool tx_own, bool ls,
359 unsigned int tcphdrlen,
360 unsigned int tcppayloadlen);
361 /* Set/get the owner of the descriptor */
362 void (*set_tx_owner) (struct dma_desc *p);
363 int (*get_tx_owner) (struct dma_desc *p);
364 /* Clean the tx descriptor as soon as the tx irq is received */
365 void (*release_tx_desc) (struct dma_desc *p, int mode);
366 /* Clear interrupt on tx frame completion. When this bit is
367 * set an interrupt happens as soon as the frame is transmitted */
368 void (*set_tx_ic)(struct dma_desc *p);
369 /* Last tx segment reports the transmit status */
370 int (*get_tx_ls) (struct dma_desc *p);
371 /* Return the transmit status looking at the TDES1 */
372 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
373 struct dma_desc *p, void __iomem *ioaddr);
374 /* Get the buffer size from the descriptor */
375 int (*get_tx_len) (struct dma_desc *p);
376 /* Handle extra events on specific interrupts hw dependent */
377 void (*set_rx_owner) (struct dma_desc *p);
378 /* Get the receive frame size */
379 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
380 /* Return the reception status looking at the RDES1 */
381 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
383 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
384 struct dma_extended_desc *p);
385 /* Set tx timestamp enable bit */
386 void (*enable_tx_timestamp) (struct dma_desc *p);
387 /* get tx timestamp status */
388 int (*get_tx_timestamp_status) (struct dma_desc *p);
389 /* get timestamp value */
390 u64(*get_timestamp) (void *desc, u32 ats);
391 /* get rx timestamp status */
392 int (*get_rx_timestamp_status) (void *desc, u32 ats);
394 void (*display_ring)(void *head, unsigned int size, bool rx);
395 /* set MSS via context descriptor */
396 void (*set_mss)(struct dma_desc *p, unsigned int mss);
399 extern const struct stmmac_desc_ops enh_desc_ops;
400 extern const struct stmmac_desc_ops ndesc_ops;
402 /* Specific DMA helpers */
403 struct stmmac_dma_ops {
404 /* DMA core initialization */
405 int (*reset)(void __iomem *ioaddr);
406 void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
407 int aal, u32 dma_tx, u32 dma_rx, int atds);
408 /* Configure the AXI Bus Mode Register */
409 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
410 /* Dump DMA registers */
411 void (*dump_regs) (void __iomem *ioaddr);
412 /* Set tx/rx threshold in the csr6 register
413 * An invalid value enables the store-and-forward mode */
414 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
416 /* To track extra statistic (if supported) */
417 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
418 void __iomem *ioaddr);
419 void (*enable_dma_transmission) (void __iomem *ioaddr);
420 void (*enable_dma_irq) (void __iomem *ioaddr);
421 void (*disable_dma_irq) (void __iomem *ioaddr);
422 void (*start_tx) (void __iomem *ioaddr);
423 void (*stop_tx) (void __iomem *ioaddr);
424 void (*start_rx) (void __iomem *ioaddr);
425 void (*stop_rx) (void __iomem *ioaddr);
426 int (*dma_interrupt) (void __iomem *ioaddr,
427 struct stmmac_extra_stats *x);
428 /* If supported then get the optional core features */
429 void (*get_hw_feature)(void __iomem *ioaddr,
430 struct dma_features *dma_cap);
431 /* Program the HW RX Watchdog */
432 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
433 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
434 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
435 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
436 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
437 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
440 struct mac_device_info;
442 /* Helpers to program the MAC core */
444 /* MAC core initialization */
445 void (*core_init)(struct mac_device_info *hw, int mtu);
446 /* Enable and verify that the IPC module is supported */
447 int (*rx_ipc)(struct mac_device_info *hw);
448 /* Dump MAC registers */
449 void (*dump_regs)(struct mac_device_info *hw);
450 /* Handle extra events on specific interrupts hw dependent */
451 int (*host_irq_status)(struct mac_device_info *hw,
452 struct stmmac_extra_stats *x);
453 /* Multicast filter setting */
454 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
455 /* Flow control setting */
456 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
457 unsigned int fc, unsigned int pause_time);
458 /* Set power management mode (e.g. magic frame) */
459 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
460 /* Set/Get Unicast MAC addresses */
461 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
463 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
465 void (*set_eee_mode)(struct mac_device_info *hw);
466 void (*reset_eee_mode)(struct mac_device_info *hw);
467 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
468 void (*set_eee_pls)(struct mac_device_info *hw, int link);
469 void (*ctrl_ane)(struct mac_device_info *hw, bool restart);
470 void (*get_adv)(struct mac_device_info *hw, struct rgmii_adv *adv);
471 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
474 /* PTP and HW Timer helpers */
475 struct stmmac_hwtimestamp {
476 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
477 u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
478 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
479 int (*config_addend) (void __iomem *ioaddr, u32 addend);
480 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
482 u64(*get_systime) (void __iomem *ioaddr);
485 extern const struct stmmac_hwtimestamp stmmac_ptp;
486 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
495 unsigned int addr; /* MII Address */
496 unsigned int data; /* MII Data */
499 /* Helpers to manage the descriptors for chain and ring modes */
500 struct stmmac_mode_ops {
501 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
502 unsigned int extend_desc);
503 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
504 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
505 int (*set_16kib_bfsize)(int mtu);
506 void (*init_desc3)(struct dma_desc *p);
507 void (*refill_desc3) (void *priv, struct dma_desc *p);
508 void (*clean_desc3) (void *priv, struct dma_desc *p);
511 struct mac_device_info {
512 const struct stmmac_ops *mac;
513 const struct stmmac_desc_ops *desc;
514 const struct stmmac_dma_ops *dma;
515 const struct stmmac_mode_ops *mode;
516 const struct stmmac_hwtimestamp *ptp;
517 struct mii_regs mii; /* MII register Addresses */
518 struct mac_link link;
519 void __iomem *pcsr; /* vpointer to device CSRs */
520 int multicast_filter_bins;
521 int unicast_filter_entries;
523 unsigned int rx_csum;
526 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
527 int perfect_uc_entries,
529 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
530 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
531 int perfect_uc_entries, int *synopsys_id);
533 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
534 unsigned int high, unsigned int low);
535 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
536 unsigned int high, unsigned int low);
537 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
539 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
540 unsigned int high, unsigned int low);
541 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
542 unsigned int high, unsigned int low);
543 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
545 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
546 extern const struct stmmac_mode_ops ring_mode_ops;
547 extern const struct stmmac_mode_ops chain_mode_ops;
550 * stmmac_get_synopsys_id - return the SYINID.
551 * @priv: driver private structure
552 * Description: this simple function is to decode and return the SYINID
553 * starting from the HW core register.
555 static inline u32 stmmac_get_synopsys_id(u32 hwid)
557 /* Check Synopsys Id (not available on old chips) */
559 u32 uid = ((hwid & 0x0000ff00) >> 8);
560 u32 synid = (hwid & 0x000000ff);
562 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
569 #endif /* __COMMON_H__ */