drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  56         [EDSR]          = 0x0000,
  57         [EDMR]          = 0x0400,
  58         [EDTRR]         = 0x0408,
  59         [EDRRR]         = 0x0410,
  60         [EESR]          = 0x0428,
  61         [EESIPR]        = 0x0430,
  62         [TDLAR]         = 0x0010,
  63         [TDFAR]         = 0x0014,
  64         [TDFXR]         = 0x0018,
  65         [TDFFR]         = 0x001c,
  66         [RDLAR]         = 0x0030,
  67         [RDFAR]         = 0x0034,
  68         [RDFXR]         = 0x0038,
  69         [RDFFR]         = 0x003c,
  70         [TRSCER]        = 0x0438,
  71         [RMFCR]         = 0x0440,
  72         [TFTR]          = 0x0448,
  73         [FDR]           = 0x0450,
  74         [RMCR]          = 0x0458,
  75         [RPADIR]        = 0x0460,
  76         [FCFTR]         = 0x0468,
  77         [CSMR]          = 0x04E4,
  78
  79         [ECMR]          = 0x0500,
  80         [ECSR]          = 0x0510,
  81         [ECSIPR]        = 0x0518,
  82         [PIR]           = 0x0520,
  83         [PSR]           = 0x0528,
  84         [PIPR]          = 0x052c,
  85         [RFLR]          = 0x0508,
  86         [APR]           = 0x0554,
  87         [MPR]           = 0x0558,
  88         [PFTCR]         = 0x055c,
  89         [PFRCR]         = 0x0560,
  90         [TPAUSER]       = 0x0564,
  91         [GECMR]         = 0x05b0,
  92         [BCULR]         = 0x05b4,
  93         [MAHR]          = 0x05c0,
  94         [MALR]          = 0x05c8,
  95         [TROCR]         = 0x0700,
  96         [CDCR]          = 0x0708,
  97         [LCCR]          = 0x0710,
  98         [CEFCR]         = 0x0740,
  99         [FRECR]         = 0x0748,
 100         [TSFRCR]        = 0x0750,
 101         [TLFRCR]        = 0x0758,
 102         [RFCR]          = 0x0760,
 103         [CERCR]         = 0x0768,
 104         [CEECR]         = 0x0770,
 105         [MAFCR]         = 0x0778,
 106         [RMII_MII]      = 0x0790,
 107
 108         [ARSTR]         = 0x0000,
 109         [TSU_CTRST]     = 0x0004,
 110         [TSU_FWEN0]     = 0x0010,
 111         [TSU_FWEN1]     = 0x0014,
 112         [TSU_FCM]       = 0x0018,
 113         [TSU_BSYSL0]    = 0x0020,
 114         [TSU_BSYSL1]    = 0x0024,
 115         [TSU_PRISL0]    = 0x0028,
 116         [TSU_PRISL1]    = 0x002c,
 117         [TSU_FWSL0]     = 0x0030,
 118         [TSU_FWSL1]     = 0x0034,
 119         [TSU_FWSLC]     = 0x0038,
 120         [TSU_QTAG0]     = 0x0040,
 121         [TSU_QTAG1]     = 0x0044,
 122         [TSU_FWSR]      = 0x0050,
 123         [TSU_FWINMK]    = 0x0054,
 124         [TSU_ADQT0]     = 0x0048,
 125         [TSU_ADQT1]     = 0x004c,
 126         [TSU_VTAG0]     = 0x0058,
 127         [TSU_VTAG1]     = 0x005c,
 128         [TSU_ADSBSY]    = 0x0060,
 129         [TSU_TEN]       = 0x0064,
 130         [TSU_POST1]     = 0x0070,
 131         [TSU_POST2]     = 0x0074,
 132         [TSU_POST3]     = 0x0078,
 133         [TSU_POST4]     = 0x007c,
 134         [TSU_ADRH0]     = 0x0100,
 135         [TSU_ADRL0]     = 0x0104,
 136         [TSU_ADRH31]    = 0x01f8,
 137         [TSU_ADRL31]    = 0x01fc,
 138
 139         [TXNLCR0]       = 0x0080,
 140         [TXALCR0]       = 0x0084,
 141         [RXNLCR0]       = 0x0088,
 142         [RXALCR0]       = 0x008c,
 143         [FWNLCR0]       = 0x0090,
 144         [FWALCR0]       = 0x0094,
 145         [TXNLCR1]       = 0x00a0,
 146         [TXALCR1]       = 0x00a0,
 147         [RXNLCR1]       = 0x00a8,
 148         [RXALCR1]       = 0x00ac,
 149         [FWNLCR1]       = 0x00b0,
 150         [FWALCR1]       = 0x00b4,
 151 };
 152
 153 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 154         [EDSR]          = 0x0000,
 155         [EDMR]          = 0x0400,
 156         [EDTRR]         = 0x0408,
 157         [EDRRR]         = 0x0410,
 158         [EESR]          = 0x0428,
 159         [EESIPR]        = 0x0430,
 160         [TDLAR]         = 0x0010,
 161         [TDFAR]         = 0x0014,
 162         [TDFXR]         = 0x0018,
 163         [TDFFR]         = 0x001c,
 164         [RDLAR]         = 0x0030,
 165         [RDFAR]         = 0x0034,
 166         [RDFXR]         = 0x0038,
 167         [RDFFR]         = 0x003c,
 168         [TRSCER]        = 0x0438,
 169         [RMFCR]         = 0x0440,
 170         [TFTR]          = 0x0448,
 171         [FDR]           = 0x0450,
 172         [RMCR]          = 0x0458,
 173         [RPADIR]        = 0x0460,
 174         [FCFTR]         = 0x0468,
 175         [CSMR]          = 0x04E4,
 176
 177         [ECMR]          = 0x0500,
 178         [RFLR]          = 0x0508,
 179         [ECSR]          = 0x0510,
 180         [ECSIPR]        = 0x0518,
 181         [PIR]           = 0x0520,
 182         [APR]           = 0x0554,
 183         [MPR]           = 0x0558,
 184         [PFTCR]         = 0x055c,
 185         [PFRCR]         = 0x0560,
 186         [TPAUSER]       = 0x0564,
 187         [MAHR]          = 0x05c0,
 188         [MALR]          = 0x05c8,
 189         [CEFCR]         = 0x0740,
 190         [FRECR]         = 0x0748,
 191         [TSFRCR]        = 0x0750,
 192         [TLFRCR]        = 0x0758,
 193         [RFCR]          = 0x0760,
 194         [MAFCR]         = 0x0778,
 195
 196         [ARSTR]         = 0x0000,
 197         [TSU_CTRST]     = 0x0004,
 198         [TSU_VTAG0]     = 0x0058,
 199         [TSU_ADSBSY]    = 0x0060,
 200         [TSU_TEN]       = 0x0064,
 201         [TSU_ADRH0]     = 0x0100,
 202         [TSU_ADRL0]     = 0x0104,
 203         [TSU_ADRH31]    = 0x01f8,
 204         [TSU_ADRL31]    = 0x01fc,
 205
 206         [TXNLCR0]       = 0x0080,
 207         [TXALCR0]       = 0x0084,
 208         [RXNLCR0]       = 0x0088,
 209         [RXALCR0]       = 0x008C,
 210 };
 211
 212 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 213         [ECMR]          = 0x0300,
 214         [RFLR]          = 0x0308,
 215         [ECSR]          = 0x0310,
 216         [ECSIPR]        = 0x0318,
 217         [PIR]           = 0x0320,
 218         [PSR]           = 0x0328,
 219         [RDMLR]         = 0x0340,
 220         [IPGR]          = 0x0350,
 221         [APR]           = 0x0354,
 222         [MPR]           = 0x0358,
 223         [RFCF]          = 0x0360,
 224         [TPAUSER]       = 0x0364,
 225         [TPAUSECR]      = 0x0368,
 226         [MAHR]          = 0x03c0,
 227         [MALR]          = 0x03c8,
 228         [TROCR]         = 0x03d0,
 229         [CDCR]          = 0x03d4,
 230         [LCCR]          = 0x03d8,
 231         [CNDCR]         = 0x03dc,
 232         [CEFCR]         = 0x03e4,
 233         [FRECR]         = 0x03e8,
 234         [TSFRCR]        = 0x03ec,
 235         [TLFRCR]        = 0x03f0,
 236         [RFCR]          = 0x03f4,
 237         [MAFCR]         = 0x03f8,
 238
 239         [EDMR]          = 0x0200,
 240         [EDTRR]         = 0x0208,
 241         [EDRRR]         = 0x0210,
 242         [TDLAR]         = 0x0218,
 243         [RDLAR]         = 0x0220,
 244         [EESR]          = 0x0228,
 245         [EESIPR]        = 0x0230,
 246         [TRSCER]        = 0x0238,
 247         [RMFCR]         = 0x0240,
 248         [TFTR]          = 0x0248,
 249         [FDR]           = 0x0250,
 250         [RMCR]          = 0x0258,
 251         [TFUCR]         = 0x0264,
 252         [RFOCR]         = 0x0268,
 253         [RMIIMODE]      = 0x026c,
 254         [FCFTR]         = 0x0270,
 255         [TRIMD]         = 0x027c,
 256 };
 257
 258 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 259         [ECMR]          = 0x0100,
 260         [RFLR]          = 0x0108,
 261         [ECSR]          = 0x0110,
 262         [ECSIPR]        = 0x0118,
 263         [PIR]           = 0x0120,
 264         [PSR]           = 0x0128,
 265         [RDMLR]         = 0x0140,
 266         [IPGR]          = 0x0150,
 267         [APR]           = 0x0154,
 268         [MPR]           = 0x0158,
 269         [TPAUSER]       = 0x0164,
 270         [RFCF]          = 0x0160,
 271         [TPAUSECR]      = 0x0168,
 272         [BCFRR]         = 0x016c,
 273         [MAHR]          = 0x01c0,
 274         [MALR]          = 0x01c8,
 275         [TROCR]         = 0x01d0,
 276         [CDCR]          = 0x01d4,
 277         [LCCR]          = 0x01d8,
 278         [CNDCR]         = 0x01dc,
 279         [CEFCR]         = 0x01e4,
 280         [FRECR]         = 0x01e8,
 281         [TSFRCR]        = 0x01ec,
 282         [TLFRCR]        = 0x01f0,
 283         [RFCR]          = 0x01f4,
 284         [MAFCR]         = 0x01f8,
 285         [RTRATE]        = 0x01fc,
 286
 287         [EDMR]          = 0x0000,
 288         [EDTRR]         = 0x0008,
 289         [EDRRR]         = 0x0010,
 290         [TDLAR]         = 0x0018,
 291         [RDLAR]         = 0x0020,
 292         [EESR]          = 0x0028,
 293         [EESIPR]        = 0x0030,
 294         [TRSCER]        = 0x0038,
 295         [RMFCR]         = 0x0040,
 296         [TFTR]          = 0x0048,
 297         [FDR]           = 0x0050,
 298         [RMCR]          = 0x0058,
 299         [TFUCR]         = 0x0064,
 300         [RFOCR]         = 0x0068,
 301         [FCFTR]         = 0x0070,
 302         [RPADIR]        = 0x0078,
 303         [TRIMD]         = 0x007c,
 304         [RBWAR]         = 0x00c8,
 305         [RDFAR]         = 0x00cc,
 306         [TBRAR]         = 0x00d4,
 307         [TDFAR]         = 0x00d8,
 308 };
 309
 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 311         [EDMR]          = 0x0000,
 312         [EDTRR]         = 0x0004,
 313         [EDRRR]         = 0x0008,
 314         [TDLAR]         = 0x000c,
 315         [RDLAR]         = 0x0010,
 316         [EESR]          = 0x0014,
 317         [EESIPR]        = 0x0018,
 318         [TRSCER]        = 0x001c,
 319         [RMFCR]         = 0x0020,
 320         [TFTR]          = 0x0024,
 321         [FDR]           = 0x0028,
 322         [RMCR]          = 0x002c,
 323         [EDOCR]         = 0x0030,
 324         [FCFTR]         = 0x0034,
 325         [RPADIR]        = 0x0038,
 326         [TRIMD]         = 0x003c,
 327         [RBWAR]         = 0x0040,
 328         [RDFAR]         = 0x0044,
 329         [TBRAR]         = 0x004c,
 330         [TDFAR]         = 0x0050,
 331
 332         [ECMR]          = 0x0160,
 333         [ECSR]          = 0x0164,
 334         [ECSIPR]        = 0x0168,
 335         [PIR]           = 0x016c,
 336         [MAHR]          = 0x0170,
 337         [MALR]          = 0x0174,
 338         [RFLR]          = 0x0178,
 339         [PSR]           = 0x017c,
 340         [TROCR]         = 0x0180,
 341         [CDCR]          = 0x0184,
 342         [LCCR]          = 0x0188,
 343         [CNDCR]         = 0x018c,
 344         [CEFCR]         = 0x0194,
 345         [FRECR]         = 0x0198,
 346         [TSFRCR]        = 0x019c,
 347         [TLFRCR]        = 0x01a0,
 348         [RFCR]          = 0x01a4,
 349         [MAFCR]         = 0x01a8,
 350         [IPGR]          = 0x01b4,
 351         [APR]           = 0x01b8,
 352         [MPR]           = 0x01bc,
 353         [TPAUSER]       = 0x01c4,
 354         [BCFR]          = 0x01cc,
 355
 356         [ARSTR]         = 0x0000,
 357         [TSU_CTRST]     = 0x0004,
 358         [TSU_FWEN0]     = 0x0010,
 359         [TSU_FWEN1]     = 0x0014,
 360         [TSU_FCM]       = 0x0018,
 361         [TSU_BSYSL0]    = 0x0020,
 362         [TSU_BSYSL1]    = 0x0024,
 363         [TSU_PRISL0]    = 0x0028,
 364         [TSU_PRISL1]    = 0x002c,
 365         [TSU_FWSL0]     = 0x0030,
 366         [TSU_FWSL1]     = 0x0034,
 367         [TSU_FWSLC]     = 0x0038,
 368         [TSU_QTAGM0]    = 0x0040,
 369         [TSU_QTAGM1]    = 0x0044,
 370         [TSU_ADQT0]     = 0x0048,
 371         [TSU_ADQT1]     = 0x004c,
 372         [TSU_FWSR]      = 0x0050,
 373         [TSU_FWINMK]    = 0x0054,
 374         [TSU_ADSBSY]    = 0x0060,
 375         [TSU_TEN]       = 0x0064,
 376         [TSU_POST1]     = 0x0070,
 377         [TSU_POST2]     = 0x0074,
 378         [TSU_POST3]     = 0x0078,
 379         [TSU_POST4]     = 0x007c,
 380
 381         [TXNLCR0]       = 0x0080,
 382         [TXALCR0]       = 0x0084,
 383         [RXNLCR0]       = 0x0088,
 384         [RXALCR0]       = 0x008c,
 385         [FWNLCR0]       = 0x0090,
 386         [FWALCR0]       = 0x0094,
 387         [TXNLCR1]       = 0x00a0,
 388         [TXALCR1]       = 0x00a0,
 389         [RXNLCR1]       = 0x00a8,
 390         [RXALCR1]       = 0x00ac,
 391         [FWNLCR1]       = 0x00b0,
 392         [FWALCR1]       = 0x00b4,
 393
 394         [TSU_ADRH0]     = 0x0100,
 395         [TSU_ADRL0]     = 0x0104,
 396         [TSU_ADRL31]    = 0x01fc,
 397 };
 398
 399 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 401
 402 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 403 {
 404         return mdp->reg_offset == sh_eth_offset_gigabit;
 405 }
 406
 407 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 408 {
 409         return mdp->reg_offset == sh_eth_offset_fast_rz;
 410 }
 411
 412 static void sh_eth_select_mii(struct net_device *ndev)
 413 {
 414         u32 value = 0x0;
 415         struct sh_eth_private *mdp = netdev_priv(ndev);
 416
 417         switch (mdp->phy_interface) {
 418         case PHY_INTERFACE_MODE_GMII:
 419                 value = 0x2;
 420                 break;
 421         case PHY_INTERFACE_MODE_MII:
 422                 value = 0x1;
 423                 break;
 424         case PHY_INTERFACE_MODE_RMII:
 425                 value = 0x0;
 426                 break;
 427         default:
 428                 netdev_warn(ndev,
 429                             "PHY interface mode was not setup. Set to MII.\n");
 430                 value = 0x1;
 431                 break;
 432         }
 433
 434         sh_eth_write(ndev, value, RMII_MII);
 435 }
 436
 437 static void sh_eth_set_duplex(struct net_device *ndev)
 438 {
 439         struct sh_eth_private *mdp = netdev_priv(ndev);
 440
 441         if (mdp->duplex) /* Full */
 442                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 443         else            /* Half */
 444                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 445 }
 446
 447 /* There is CPU dependent code */
 448 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 449 {
 450         struct sh_eth_private *mdp = netdev_priv(ndev);
 451
 452         switch (mdp->speed) {
 453         case 10: /* 10BASE */
 454                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 455                 break;
 456         case 100:/* 100BASE */
 457                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 458                 break;
 459         default:
 460                 break;
 461         }
 462 }
 463
 464 /* R8A7778/9 */
 465 static struct sh_eth_cpu_data r8a777x_data = {
 466         .set_duplex     = sh_eth_set_duplex,
 467         .set_rate       = sh_eth_set_rate_r8a777x,
 468
 469         .register_type  = SH_ETH_REG_FAST_RCAR,
 470
 471         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 472         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 473         .eesipr_value   = 0x01ff009f,
 474
 475         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 476         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 477                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 478                           EESR_ECI,
 479         .fdr_value      = 0x00000f0f,
 480
 481         .apr            = 1,
 482         .mpr            = 1,
 483         .tpauser        = 1,
 484         .hw_swap        = 1,
 485 };
 486
 487 /* R8A7790/1 */
 488 static struct sh_eth_cpu_data r8a779x_data = {
 489         .set_duplex     = sh_eth_set_duplex,
 490         .set_rate       = sh_eth_set_rate_r8a777x,
 491
 492         .register_type  = SH_ETH_REG_FAST_RCAR,
 493
 494         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 495         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 496         .eesipr_value   = 0x01ff009f,
 497
 498         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 499         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 500                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 501                           EESR_ECI,
 502         .fdr_value      = 0x00000f0f,
 503
 504         .trscer_err_mask = DESC_I_RINT8,
 505
 506         .apr            = 1,
 507         .mpr            = 1,
 508         .tpauser        = 1,
 509         .hw_swap        = 1,
 510         .rmiimode       = 1,
 511 };
 512
 513 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 514 {
 515         struct sh_eth_private *mdp = netdev_priv(ndev);
 516
 517         switch (mdp->speed) {
 518         case 10: /* 10BASE */
 519                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 520                 break;
 521         case 100:/* 100BASE */
 522                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 523                 break;
 524         default:
 525                 break;
 526         }
 527 }
 528
 529 /* SH7724 */
 530 static struct sh_eth_cpu_data sh7724_data = {
 531         .set_duplex     = sh_eth_set_duplex,
 532         .set_rate       = sh_eth_set_rate_sh7724,
 533
 534         .register_type  = SH_ETH_REG_FAST_SH4,
 535
 536         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 537         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 538         .eesipr_value   = 0x01ff009f,
 539
 540         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 541         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 542                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 543                           EESR_ECI,
 544
 545         .apr            = 1,
 546         .mpr            = 1,
 547         .tpauser        = 1,
 548         .hw_swap        = 1,
 549         .rpadir         = 1,
 550         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 551 };
 552
 553 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 554 {
 555         struct sh_eth_private *mdp = netdev_priv(ndev);
 556
 557         switch (mdp->speed) {
 558         case 10: /* 10BASE */
 559                 sh_eth_write(ndev, 0, RTRATE);
 560                 break;
 561         case 100:/* 100BASE */
 562                 sh_eth_write(ndev, 1, RTRATE);
 563                 break;
 564         default:
 565                 break;
 566         }
 567 }
 568
 569 /* SH7757 */
 570 static struct sh_eth_cpu_data sh7757_data = {
 571         .set_duplex     = sh_eth_set_duplex,
 572         .set_rate       = sh_eth_set_rate_sh7757,
 573
 574         .register_type  = SH_ETH_REG_FAST_SH4,
 575
 576         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 577
 578         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 579         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 580                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 581                           EESR_ECI,
 582
 583         .irq_flags      = IRQF_SHARED,
 584         .apr            = 1,
 585         .mpr            = 1,
 586         .tpauser        = 1,
 587         .hw_swap        = 1,
 588         .no_ade         = 1,
 589         .rpadir         = 1,
 590         .rpadir_value   = 2 << 16,
 591 };
 592
 593 #define SH_GIGA_ETH_BASE        0xfee00000UL
 594 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 595 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 596 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 597 {
 598         int i;
 599         u32 mahr[2], malr[2];
 600
 601         /* save MAHR and MALR */
 602         for (i = 0; i < 2; i++) {
 603                 malr[i] = ioread32((void *)GIGA_MALR(i));
 604                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 605         }
 606
 607         /* reset device */
 608         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 609         mdelay(1);
 610
 611         /* restore MAHR and MALR */
 612         for (i = 0; i < 2; i++) {
 613                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 614                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 615         }
 616 }
 617
 618 static void sh_eth_set_rate_giga(struct net_device *ndev)
 619 {
 620         struct sh_eth_private *mdp = netdev_priv(ndev);
 621
 622         switch (mdp->speed) {
 623         case 10: /* 10BASE */
 624                 sh_eth_write(ndev, 0x00000000, GECMR);
 625                 break;
 626         case 100:/* 100BASE */
 627                 sh_eth_write(ndev, 0x00000010, GECMR);
 628                 break;
 629         case 1000: /* 1000BASE */
 630                 sh_eth_write(ndev, 0x00000020, GECMR);
 631                 break;
 632         default:
 633                 break;
 634         }
 635 }
 636
 637 /* SH7757(GETHERC) */
 638 static struct sh_eth_cpu_data sh7757_data_giga = {
 639         .chip_reset     = sh_eth_chip_reset_giga,
 640         .set_duplex     = sh_eth_set_duplex,
 641         .set_rate       = sh_eth_set_rate_giga,
 642
 643         .register_type  = SH_ETH_REG_GIGABIT,
 644
 645         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 646         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 647         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 648
 649         .tx_check       = EESR_TC1 | EESR_FTC,
 650         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 651                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 652                           EESR_TDE | EESR_ECI,
 653         .fdr_value      = 0x0000072f,
 654
 655         .irq_flags      = IRQF_SHARED,
 656         .apr            = 1,
 657         .mpr            = 1,
 658         .tpauser        = 1,
 659         .bculr          = 1,
 660         .hw_swap        = 1,
 661         .rpadir         = 1,
 662         .rpadir_value   = 2 << 16,
 663         .no_trimd       = 1,
 664         .no_ade         = 1,
 665         .tsu            = 1,
 666 };
 667
 668 static void sh_eth_chip_reset(struct net_device *ndev)
 669 {
 670         struct sh_eth_private *mdp = netdev_priv(ndev);
 671
 672         /* reset device */
 673         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 674         mdelay(1);
 675 }
 676
 677 static void sh_eth_set_rate_gether(struct net_device *ndev)
 678 {
 679         struct sh_eth_private *mdp = netdev_priv(ndev);
 680
 681         switch (mdp->speed) {
 682         case 10: /* 10BASE */
 683                 sh_eth_write(ndev, GECMR_10, GECMR);
 684                 break;
 685         case 100:/* 100BASE */
 686                 sh_eth_write(ndev, GECMR_100, GECMR);
 687                 break;
 688         case 1000: /* 1000BASE */
 689                 sh_eth_write(ndev, GECMR_1000, GECMR);
 690                 break;
 691         default:
 692                 break;
 693         }
 694 }
 695
 696 /* SH7734 */
 697 static struct sh_eth_cpu_data sh7734_data = {
 698         .chip_reset     = sh_eth_chip_reset,
 699         .set_duplex     = sh_eth_set_duplex,
 700         .set_rate       = sh_eth_set_rate_gether,
 701
 702         .register_type  = SH_ETH_REG_GIGABIT,
 703
 704         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 705         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 706         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 707
 708         .tx_check       = EESR_TC1 | EESR_FTC,
 709         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 710                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 711                           EESR_TDE | EESR_ECI,
 712
 713         .apr            = 1,
 714         .mpr            = 1,
 715         .tpauser        = 1,
 716         .bculr          = 1,
 717         .hw_swap        = 1,
 718         .no_trimd       = 1,
 719         .no_ade         = 1,
 720         .tsu            = 1,
 721         .hw_crc         = 1,
 722         .select_mii     = 1,
 723 };
 724
 725 /* SH7763 */
 726 static struct sh_eth_cpu_data sh7763_data = {
 727         .chip_reset     = sh_eth_chip_reset,
 728         .set_duplex     = sh_eth_set_duplex,
 729         .set_rate       = sh_eth_set_rate_gether,
 730
 731         .register_type  = SH_ETH_REG_GIGABIT,
 732
 733         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 734         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 735         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 736
 737         .tx_check       = EESR_TC1 | EESR_FTC,
 738         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 739                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 740                           EESR_ECI,
 741
 742         .apr            = 1,
 743         .mpr            = 1,
 744         .tpauser        = 1,
 745         .bculr          = 1,
 746         .hw_swap        = 1,
 747         .no_trimd       = 1,
 748         .no_ade         = 1,
 749         .tsu            = 1,
 750         .irq_flags      = IRQF_SHARED,
 751 };
 752
 753 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 754 {
 755         struct sh_eth_private *mdp = netdev_priv(ndev);
 756
 757         /* reset device */
 758         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 759         mdelay(1);
 760
 761         sh_eth_select_mii(ndev);
 762 }
 763
 764 /* R8A7740 */
 765 static struct sh_eth_cpu_data r8a7740_data = {
 766         .chip_reset     = sh_eth_chip_reset_r8a7740,
 767         .set_duplex     = sh_eth_set_duplex,
 768         .set_rate       = sh_eth_set_rate_gether,
 769
 770         .register_type  = SH_ETH_REG_GIGABIT,
 771
 772         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 773         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 774         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 775
 776         .tx_check       = EESR_TC1 | EESR_FTC,
 777         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 778                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 779                           EESR_TDE | EESR_ECI,
 780         .fdr_value      = 0x0000070f,
 781
 782         .apr            = 1,
 783         .mpr            = 1,
 784         .tpauser        = 1,
 785         .bculr          = 1,
 786         .hw_swap        = 1,
 787         .rpadir         = 1,
 788         .rpadir_value   = 2 << 16,
 789         .no_trimd       = 1,
 790         .no_ade         = 1,
 791         .tsu            = 1,
 792         .select_mii     = 1,
 793         .shift_rd0      = 1,
 794 };
 795
 796 /* R7S72100 */
 797 static struct sh_eth_cpu_data r7s72100_data = {
 798         .chip_reset     = sh_eth_chip_reset,
 799         .set_duplex     = sh_eth_set_duplex,
 800
 801         .register_type  = SH_ETH_REG_FAST_RZ,
 802
 803         .ecsr_value     = ECSR_ICD,
 804         .ecsipr_value   = ECSIPR_ICDIP,
 805         .eesipr_value   = 0xff7f009f,
 806
 807         .tx_check       = EESR_TC1 | EESR_FTC,
 808         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 809                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 810                           EESR_TDE | EESR_ECI,
 811         .fdr_value      = 0x0000070f,
 812
 813         .no_psr         = 1,
 814         .apr            = 1,
 815         .mpr            = 1,
 816         .tpauser        = 1,
 817         .hw_swap        = 1,
 818         .rpadir         = 1,
 819         .rpadir_value   = 2 << 16,
 820         .no_trimd       = 1,
 821         .no_ade         = 1,
 822         .hw_crc         = 1,
 823         .tsu            = 1,
 824         .shift_rd0      = 1,
 825 };
 826
 827 static struct sh_eth_cpu_data sh7619_data = {
 828         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 829
 830         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 831
 832         .apr            = 1,
 833         .mpr            = 1,
 834         .tpauser        = 1,
 835         .hw_swap        = 1,
 836 };
 837
 838 static struct sh_eth_cpu_data sh771x_data = {
 839         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 840
 841         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 842         .tsu            = 1,
 843 };
 844
 845 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 846 {
 847         if (!cd->ecsr_value)
 848                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 849
 850         if (!cd->ecsipr_value)
 851                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 852
 853         if (!cd->fcftr_value)
 854                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 855                                   DEFAULT_FIFO_F_D_RFD;
 856
 857         if (!cd->fdr_value)
 858                 cd->fdr_value = DEFAULT_FDR_INIT;
 859
 860         if (!cd->tx_check)
 861                 cd->tx_check = DEFAULT_TX_CHECK;
 862
 863         if (!cd->eesr_err_check)
 864                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 865
 866         if (!cd->trscer_err_mask)
 867                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 868 }
 869
 870 static int sh_eth_check_reset(struct net_device *ndev)
 871 {
 872         int ret = 0;
 873         int cnt = 100;
 874
 875         while (cnt > 0) {
 876                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 877                         break;
 878                 mdelay(1);
 879                 cnt--;
 880         }
 881         if (cnt <= 0) {
 882                 netdev_err(ndev, "Device reset failed\n");
 883                 ret = -ETIMEDOUT;
 884         }
 885         return ret;
 886 }
 887
 888 static int sh_eth_reset(struct net_device *ndev)
 889 {
 890         struct sh_eth_private *mdp = netdev_priv(ndev);
 891         int ret = 0;
 892
 893         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 894                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 895                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 896                              EDMR);
 897
 898                 ret = sh_eth_check_reset(ndev);
 899                 if (ret)
 900                         return ret;
 901
 902                 /* Table Init */
 903                 sh_eth_write(ndev, 0x0, TDLAR);
 904                 sh_eth_write(ndev, 0x0, TDFAR);
 905                 sh_eth_write(ndev, 0x0, TDFXR);
 906                 sh_eth_write(ndev, 0x0, TDFFR);
 907                 sh_eth_write(ndev, 0x0, RDLAR);
 908                 sh_eth_write(ndev, 0x0, RDFAR);
 909                 sh_eth_write(ndev, 0x0, RDFXR);
 910                 sh_eth_write(ndev, 0x0, RDFFR);
 911
 912                 /* Reset HW CRC register */
 913                 if (mdp->cd->hw_crc)
 914                         sh_eth_write(ndev, 0x0, CSMR);
 915
 916                 /* Select MII mode */
 917                 if (mdp->cd->select_mii)
 918                         sh_eth_select_mii(ndev);
 919         } else {
 920                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 921                              EDMR);
 922                 mdelay(3);
 923                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 924                              EDMR);
 925         }
 926
 927         return ret;
 928 }
 929
 930 static void sh_eth_set_receive_align(struct sk_buff *skb)
 931 {
 932         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 933
 934         if (reserve)
 935                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 936 }
 937
 938
 939 /* CPU <-> EDMAC endian convert */
 940 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 941 {
 942         switch (mdp->edmac_endian) {
 943         case EDMAC_LITTLE_ENDIAN:
 944                 return cpu_to_le32(x);
 945         case EDMAC_BIG_ENDIAN:
 946                 return cpu_to_be32(x);
 947         }
 948         return x;
 949 }
 950
 951 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 952 {
 953         switch (mdp->edmac_endian) {
 954         case EDMAC_LITTLE_ENDIAN:
 955                 return le32_to_cpu(x);
 956         case EDMAC_BIG_ENDIAN:
 957                 return be32_to_cpu(x);
 958         }
 959         return x;
 960 }
 961
 962 /* Program the hardware MAC address from dev->dev_addr. */
 963 static void update_mac_address(struct net_device *ndev)
 964 {
 965         sh_eth_write(ndev,
 966                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 967                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 968         sh_eth_write(ndev,
 969                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 970 }
 971
 972 /* Get MAC address from SuperH MAC address register
 973  *
 974  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 975  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 976  * When you want use this device, you must set MAC address in bootloader.
 977  *
 978  */
 979 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 980 {
 981         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 982                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 983         } else {
 984                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 985                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 986                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 987                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 988                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 989                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 990         }
 991 }
 992
 993 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 994 {
 995         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
 996                 return EDTRR_TRNS_GETHER;
 997         else
 998                 return EDTRR_TRNS_ETHER;
 999 }
1000
1001 struct bb_info {
1002         void (*set_gate)(void *addr);
1003         struct mdiobb_ctrl ctrl;
1004         void *addr;
1005         u32 mmd_msk;/* MMD */
1006         u32 mdo_msk;
1007         u32 mdi_msk;
1008         u32 mdc_msk;
1009 };
1010
1011 /* PHY bit set */
1012 static void bb_set(void *addr, u32 msk)
1013 {
1014         iowrite32(ioread32(addr) | msk, addr);
1015 }
1016
1017 /* PHY bit clear */
1018 static void bb_clr(void *addr, u32 msk)
1019 {
1020         iowrite32((ioread32(addr) & ~msk), addr);
1021 }
1022
1023 /* PHY bit read */
1024 static int bb_read(void *addr, u32 msk)
1025 {
1026         return (ioread32(addr) & msk) != 0;
1027 }
1028
1029 /* Data I/O pin control */
1030 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1031 {
1032         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1033
1034         if (bitbang->set_gate)
1035                 bitbang->set_gate(bitbang->addr);
1036
1037         if (bit)
1038                 bb_set(bitbang->addr, bitbang->mmd_msk);
1039         else
1040                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1041 }
1042
1043 /* Set bit data*/
1044 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1045 {
1046         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1047
1048         if (bitbang->set_gate)
1049                 bitbang->set_gate(bitbang->addr);
1050
1051         if (bit)
1052                 bb_set(bitbang->addr, bitbang->mdo_msk);
1053         else
1054                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1055 }
1056
1057 /* Get bit data*/
1058 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1059 {
1060         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1061
1062         if (bitbang->set_gate)
1063                 bitbang->set_gate(bitbang->addr);
1064
1065         return bb_read(bitbang->addr, bitbang->mdi_msk);
1066 }
1067
1068 /* MDC pin control */
1069 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1070 {
1071         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1072
1073         if (bitbang->set_gate)
1074                 bitbang->set_gate(bitbang->addr);
1075
1076         if (bit)
1077                 bb_set(bitbang->addr, bitbang->mdc_msk);
1078         else
1079                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1080 }
1081
1082 /* mdio bus control struct */
1083 static struct mdiobb_ops bb_ops = {
1084         .owner = THIS_MODULE,
1085         .set_mdc = sh_mdc_ctrl,
1086         .set_mdio_dir = sh_mmd_ctrl,
1087         .set_mdio_data = sh_set_mdio,
1088         .get_mdio_data = sh_get_mdio,
1089 };
1090
1091 /* free skb and descriptor buffer */
1092 static void sh_eth_ring_free(struct net_device *ndev)
1093 {
1094         struct sh_eth_private *mdp = netdev_priv(ndev);
1095         int i;
1096
1097         /* Free Rx skb ringbuffer */
1098         if (mdp->rx_skbuff) {
1099                 for (i = 0; i < mdp->num_rx_ring; i++)
1100                         dev_kfree_skb(mdp->rx_skbuff[i]);
1101         }
1102         kfree(mdp->rx_skbuff);
1103         mdp->rx_skbuff = NULL;
1104
1105         /* Free Tx skb ringbuffer */
1106         if (mdp->tx_skbuff) {
1107                 for (i = 0; i < mdp->num_tx_ring; i++)
1108                         dev_kfree_skb(mdp->tx_skbuff[i]);
1109         }
1110         kfree(mdp->tx_skbuff);
1111         mdp->tx_skbuff = NULL;
1112 }
1113
1114 /* format skb and descriptor buffer */
1115 static void sh_eth_ring_format(struct net_device *ndev)
1116 {
1117         struct sh_eth_private *mdp = netdev_priv(ndev);
1118         int i;
1119         struct sk_buff *skb;
1120         struct sh_eth_rxdesc *rxdesc = NULL;
1121         struct sh_eth_txdesc *txdesc = NULL;
1122         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1123         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1124         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1125         dma_addr_t dma_addr;
1126
1127         mdp->cur_rx = 0;
1128         mdp->cur_tx = 0;
1129         mdp->dirty_rx = 0;
1130         mdp->dirty_tx = 0;
1131
1132         memset(mdp->rx_ring, 0, rx_ringsize);
1133
1134         /* build Rx ring buffer */
1135         for (i = 0; i < mdp->num_rx_ring; i++) {
1136                 /* skb */
1137                 mdp->rx_skbuff[i] = NULL;
1138                 skb = netdev_alloc_skb(ndev, skbuff_size);
1139                 if (skb == NULL)
1140                         break;
1141                 sh_eth_set_receive_align(skb);
1142
1143                 /* RX descriptor */
1144                 rxdesc = &mdp->rx_ring[i];
1145                 /* The size of the buffer is a multiple of 16 bytes. */
1146                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1147                 dma_addr = dma_map_single(&ndev->dev, skb->data,
1148                                           rxdesc->buffer_length,
1149                                           DMA_FROM_DEVICE);
1150                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1151                         kfree_skb(skb);
1152                         break;
1153                 }
1154                 mdp->rx_skbuff[i] = skb;
1155                 rxdesc->addr = dma_addr;
1156                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1157
1158                 /* Rx descriptor address set */
1159                 if (i == 0) {
1160                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1161                         if (sh_eth_is_gether(mdp) ||
1162                             sh_eth_is_rz_fast_ether(mdp))
1163                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1164                 }
1165         }
1166
1167         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1168
1169         /* Mark the last entry as wrapping the ring. */
1170         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1171
1172         memset(mdp->tx_ring, 0, tx_ringsize);
1173
1174         /* build Tx ring buffer */
1175         for (i = 0; i < mdp->num_tx_ring; i++) {
1176                 mdp->tx_skbuff[i] = NULL;
1177                 txdesc = &mdp->tx_ring[i];
1178                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1179                 txdesc->buffer_length = 0;
1180                 if (i == 0) {
1181                         /* Tx descriptor address set */
1182                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1183                         if (sh_eth_is_gether(mdp) ||
1184                             sh_eth_is_rz_fast_ether(mdp))
1185                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1186                 }
1187         }
1188
1189         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1190 }
1191
1192 /* Get skb and descriptor buffer */
1193 static int sh_eth_ring_init(struct net_device *ndev)
1194 {
1195         struct sh_eth_private *mdp = netdev_priv(ndev);
1196         int rx_ringsize, tx_ringsize, ret = 0;
1197
1198         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1199          * card needs room to do 8 byte alignment, +2 so we can reserve
1200          * the first 2 bytes, and +16 gets room for the status word from the
1201          * card.
1202          */
1203         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1204                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1205         if (mdp->cd->rpadir)
1206                 mdp->rx_buf_sz += NET_IP_ALIGN;
1207
1208         /* Allocate RX and TX skb rings */
1209         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1210                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1211         if (!mdp->rx_skbuff) {
1212                 ret = -ENOMEM;
1213                 return ret;
1214         }
1215
1216         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1217                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1218         if (!mdp->tx_skbuff) {
1219                 ret = -ENOMEM;
1220                 goto skb_ring_free;
1221         }
1222
1223         /* Allocate all Rx descriptors. */
1224         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1225         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1226                                           GFP_KERNEL);
1227         if (!mdp->rx_ring) {
1228                 ret = -ENOMEM;
1229                 goto desc_ring_free;
1230         }
1231
1232         mdp->dirty_rx = 0;
1233
1234         /* Allocate all Tx descriptors. */
1235         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1236         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1237                                           GFP_KERNEL);
1238         if (!mdp->tx_ring) {
1239                 ret = -ENOMEM;
1240                 goto desc_ring_free;
1241         }
1242         return ret;
1243
1244 desc_ring_free:
1245         /* free DMA buffer */
1246         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1247
1248 skb_ring_free:
1249         /* Free Rx and Tx skb ring buffer */
1250         sh_eth_ring_free(ndev);
1251         mdp->tx_ring = NULL;
1252         mdp->rx_ring = NULL;
1253
1254         return ret;
1255 }
1256
1257 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1258 {
1259         int ringsize;
1260
1261         if (mdp->rx_ring) {
1262                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1263                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1264                                   mdp->rx_desc_dma);
1265                 mdp->rx_ring = NULL;
1266         }
1267
1268         if (mdp->tx_ring) {
1269                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1270                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1271                                   mdp->tx_desc_dma);
1272                 mdp->tx_ring = NULL;
1273         }
1274 }
1275
1276 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1277 {
1278         int ret = 0;
1279         struct sh_eth_private *mdp = netdev_priv(ndev);
1280         u32 val;
1281
1282         /* Soft Reset */
1283         ret = sh_eth_reset(ndev);
1284         if (ret)
1285                 return ret;
1286
1287         if (mdp->cd->rmiimode)
1288                 sh_eth_write(ndev, 0x1, RMIIMODE);
1289
1290         /* Descriptor format */
1291         sh_eth_ring_format(ndev);
1292         if (mdp->cd->rpadir)
1293                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1294
1295         /* all sh_eth int mask */
1296         sh_eth_write(ndev, 0, EESIPR);
1297
1298 #if defined(__LITTLE_ENDIAN)
1299         if (mdp->cd->hw_swap)
1300                 sh_eth_write(ndev, EDMR_EL, EDMR);
1301         else
1302 #endif
1303                 sh_eth_write(ndev, 0, EDMR);
1304
1305         /* FIFO size set */
1306         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1307         sh_eth_write(ndev, 0, TFTR);
1308
1309         /* Frame recv control (enable multiple-packets per rx irq) */
1310         sh_eth_write(ndev, RMCR_RNC, RMCR);
1311
1312         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1313
1314         if (mdp->cd->bculr)
1315                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1316
1317         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1318
1319         if (!mdp->cd->no_trimd)
1320                 sh_eth_write(ndev, 0, TRIMD);
1321
1322         /* Recv frame limit set register */
1323         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1324                      RFLR);
1325
1326         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1327         if (start) {
1328                 mdp->irq_enabled = true;
1329                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1330         }
1331
1332         /* PAUSE Prohibition */
1333         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1334                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1335
1336         sh_eth_write(ndev, val, ECMR);
1337
1338         if (mdp->cd->set_rate)
1339                 mdp->cd->set_rate(ndev);
1340
1341         /* E-MAC Status Register clear */
1342         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1343
1344         /* E-MAC Interrupt Enable register */
1345         if (start)
1346                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1347
1348         /* Set MAC address */
1349         update_mac_address(ndev);
1350
1351         /* mask reset */
1352         if (mdp->cd->apr)
1353                 sh_eth_write(ndev, APR_AP, APR);
1354         if (mdp->cd->mpr)
1355                 sh_eth_write(ndev, MPR_MP, MPR);
1356         if (mdp->cd->tpauser)
1357                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1358
1359         if (start) {
1360                 /* Setting the Rx mode will start the Rx process. */
1361                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1362
1363                 netif_start_queue(ndev);
1364         }
1365
1366         return ret;
1367 }
1368
1369 static void sh_eth_dev_exit(struct net_device *ndev)
1370 {
1371         struct sh_eth_private *mdp = netdev_priv(ndev);
1372         int i;
1373
1374         /* Deactivate all TX descriptors, so DMA should stop at next
1375          * packet boundary if it's currently running
1376          */
1377         for (i = 0; i < mdp->num_tx_ring; i++)
1378                 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1379
1380         /* Disable TX FIFO egress to MAC */
1381         sh_eth_rcv_snd_disable(ndev);
1382
1383         /* Stop RX DMA at next packet boundary */
1384         sh_eth_write(ndev, 0, EDRRR);
1385
1386         /* Aside from TX DMA, we can't tell when the hardware is
1387          * really stopped, so we need to reset to make sure.
1388          * Before doing that, wait for long enough to *probably*
1389          * finish transmitting the last packet and poll stats.
1390          */
1391         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1392         sh_eth_get_stats(ndev);
1393         sh_eth_reset(ndev);
1394
1395         /* Set MAC address again */
1396         update_mac_address(ndev);
1397 }
1398
1399 /* free Tx skb function */
1400 static int sh_eth_txfree(struct net_device *ndev)
1401 {
1402         struct sh_eth_private *mdp = netdev_priv(ndev);
1403         struct sh_eth_txdesc *txdesc;
1404         int free_num = 0;
1405         int entry = 0;
1406
1407         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1408                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1409                 txdesc = &mdp->tx_ring[entry];
1410                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1411                         break;
1412                 /* TACT bit must be checked before all the following reads */
1413                 rmb();
1414                 /* Free the original skb. */
1415                 if (mdp->tx_skbuff[entry]) {
1416                         dma_unmap_single(&ndev->dev, txdesc->addr,
1417                                          txdesc->buffer_length, DMA_TO_DEVICE);
1418                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1419                         mdp->tx_skbuff[entry] = NULL;
1420                         free_num++;
1421                 }
1422                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1423                 if (entry >= mdp->num_tx_ring - 1)
1424                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1425
1426                 ndev->stats.tx_packets++;
1427                 ndev->stats.tx_bytes += txdesc->buffer_length;
1428         }
1429         return free_num;
1430 }
1431
1432 /* Packet receive function */
1433 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1434 {
1435         struct sh_eth_private *mdp = netdev_priv(ndev);
1436         struct sh_eth_rxdesc *rxdesc;
1437
1438         int entry = mdp->cur_rx % mdp->num_rx_ring;
1439         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1440         int limit;
1441         struct sk_buff *skb;
1442         u16 pkt_len = 0;
1443         u32 desc_status;
1444         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1445         dma_addr_t dma_addr;
1446
1447         boguscnt = min(boguscnt, *quota);
1448         limit = boguscnt;
1449         rxdesc = &mdp->rx_ring[entry];
1450         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1451                 /* RACT bit must be checked before all the following reads */
1452                 rmb();
1453                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1454                 pkt_len = rxdesc->frame_length;
1455
1456                 if (--boguscnt < 0)
1457                         break;
1458
1459                 if (!(desc_status & RDFEND))
1460                         ndev->stats.rx_length_errors++;
1461
1462                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1463                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1464                  * bit 0. However, in case of the R8A7740 and R7S72100
1465                  * the RFS bits are from bit 25 to bit 16. So, the
1466                  * driver needs right shifting by 16.
1467                  */
1468                 if (mdp->cd->shift_rd0)
1469                         desc_status >>= 16;
1470
1471                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1472                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1473                         ndev->stats.rx_errors++;
1474                         if (desc_status & RD_RFS1)
1475                                 ndev->stats.rx_crc_errors++;
1476                         if (desc_status & RD_RFS2)
1477                                 ndev->stats.rx_frame_errors++;
1478                         if (desc_status & RD_RFS3)
1479                                 ndev->stats.rx_length_errors++;
1480                         if (desc_status & RD_RFS4)
1481                                 ndev->stats.rx_length_errors++;
1482                         if (desc_status & RD_RFS6)
1483                                 ndev->stats.rx_missed_errors++;
1484                         if (desc_status & RD_RFS10)
1485                                 ndev->stats.rx_over_errors++;
1486                 } else {
1487                         if (!mdp->cd->hw_swap)
1488                                 sh_eth_soft_swap(
1489                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1490                                         pkt_len + 2);
1491                         skb = mdp->rx_skbuff[entry];
1492                         mdp->rx_skbuff[entry] = NULL;
1493                         if (mdp->cd->rpadir)
1494                                 skb_reserve(skb, NET_IP_ALIGN);
1495                         dma_unmap_single(&ndev->dev, rxdesc->addr,
1496                                          ALIGN(mdp->rx_buf_sz, 16),
1497                                          DMA_FROM_DEVICE);
1498                         skb_put(skb, pkt_len);
1499                         skb->protocol = eth_type_trans(skb, ndev);
1500                         netif_receive_skb(skb);
1501                         ndev->stats.rx_packets++;
1502                         ndev->stats.rx_bytes += pkt_len;
1503                 }
1504                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1505                 rxdesc = &mdp->rx_ring[entry];
1506         }
1507
1508         /* Refill the Rx ring buffers. */
1509         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1510                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1511                 rxdesc = &mdp->rx_ring[entry];
1512                 /* The size of the buffer is 16 byte boundary. */
1513                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1514
1515                 if (mdp->rx_skbuff[entry] == NULL) {
1516                         skb = netdev_alloc_skb(ndev, skbuff_size);
1517                         if (skb == NULL)
1518                                 break;  /* Better luck next round. */
1519                         sh_eth_set_receive_align(skb);
1520                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1521                                                   rxdesc->buffer_length,
1522                                                   DMA_FROM_DEVICE);
1523                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1524                                 kfree_skb(skb);
1525                                 break;
1526                         }
1527                         mdp->rx_skbuff[entry] = skb;
1528
1529                         skb_checksum_none_assert(skb);
1530                         rxdesc->addr = dma_addr;
1531                 }
1532                 wmb(); /* RACT bit must be set after all the above writes */
1533                 if (entry >= mdp->num_rx_ring - 1)
1534                         rxdesc->status |=
1535                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1536                 else
1537                         rxdesc->status |=
1538                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1539         }
1540
1541         /* Restart Rx engine if stopped. */
1542         /* If we don't need to check status, don't. -KDU */
1543         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1544                 /* fix the values for the next receiving if RDE is set */
1545                 if (intr_status & EESR_RDE && mdp->reg_offset[RDFAR] != 0) {
1546                         u32 count = (sh_eth_read(ndev, RDFAR) -
1547                                      sh_eth_read(ndev, RDLAR)) >> 4;
1548
1549                         mdp->cur_rx = count;
1550                         mdp->dirty_rx = count;
1551                 }
1552                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1553         }
1554
1555         *quota -= limit - boguscnt - 1;
1556
1557         return *quota <= 0;
1558 }
1559
1560 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1561 {
1562         /* disable tx and rx */
1563         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1564                 ~(ECMR_RE | ECMR_TE), ECMR);
1565 }
1566
1567 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1568 {
1569         /* enable tx and rx */
1570         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1571                 (ECMR_RE | ECMR_TE), ECMR);
1572 }
1573
1574 /* error control function */
1575 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1576 {
1577         struct sh_eth_private *mdp = netdev_priv(ndev);
1578         u32 felic_stat;
1579         u32 link_stat;
1580         u32 mask;
1581
1582         if (intr_status & EESR_ECI) {
1583                 felic_stat = sh_eth_read(ndev, ECSR);
1584                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1585                 if (felic_stat & ECSR_ICD)
1586                         ndev->stats.tx_carrier_errors++;
1587                 if (felic_stat & ECSR_LCHNG) {
1588                         /* Link Changed */
1589                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1590                                 goto ignore_link;
1591                         } else {
1592                                 link_stat = (sh_eth_read(ndev, PSR));
1593                                 if (mdp->ether_link_active_low)
1594                                         link_stat = ~link_stat;
1595                         }
1596                         if (!(link_stat & PHY_ST_LINK)) {
1597                                 sh_eth_rcv_snd_disable(ndev);
1598                         } else {
1599                                 /* Link Up */
1600                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1601                                                    ~DMAC_M_ECI, EESIPR);
1602                                 /* clear int */
1603                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1604                                              ECSR);
1605                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1606                                                    DMAC_M_ECI, EESIPR);
1607                                 /* enable tx and rx */
1608                                 sh_eth_rcv_snd_enable(ndev);
1609                         }
1610                 }
1611         }
1612
1613 ignore_link:
1614         if (intr_status & EESR_TWB) {
1615                 /* Unused write back interrupt */
1616                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1617                         ndev->stats.tx_aborted_errors++;
1618                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1619                 }
1620         }
1621
1622         if (intr_status & EESR_RABT) {
1623                 /* Receive Abort int */
1624                 if (intr_status & EESR_RFRMER) {
1625                         /* Receive Frame Overflow int */
1626                         ndev->stats.rx_frame_errors++;
1627                 }
1628         }
1629
1630         if (intr_status & EESR_TDE) {
1631                 /* Transmit Descriptor Empty int */
1632                 ndev->stats.tx_fifo_errors++;
1633                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1634         }
1635
1636         if (intr_status & EESR_TFE) {
1637                 /* FIFO under flow */
1638                 ndev->stats.tx_fifo_errors++;
1639                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1640         }
1641
1642         if (intr_status & EESR_RDE) {
1643                 /* Receive Descriptor Empty int */
1644                 ndev->stats.rx_over_errors++;
1645         }
1646
1647         if (intr_status & EESR_RFE) {
1648                 /* Receive FIFO Overflow int */
1649                 ndev->stats.rx_fifo_errors++;
1650         }
1651
1652         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1653                 /* Address Error */
1654                 ndev->stats.tx_fifo_errors++;
1655                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1656         }
1657
1658         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1659         if (mdp->cd->no_ade)
1660                 mask &= ~EESR_ADE;
1661         if (intr_status & mask) {
1662                 /* Tx error */
1663                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1664
1665                 /* dmesg */
1666                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1667                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1668                            (u32)ndev->state, edtrr);
1669                 /* dirty buffer free */
1670                 sh_eth_txfree(ndev);
1671
1672                 /* SH7712 BUG */
1673                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1674                         /* tx dma start */
1675                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1676                 }
1677                 /* wakeup */
1678                 netif_wake_queue(ndev);
1679         }
1680 }
1681
1682 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1683 {
1684         struct net_device *ndev = netdev;
1685         struct sh_eth_private *mdp = netdev_priv(ndev);
1686         struct sh_eth_cpu_data *cd = mdp->cd;
1687         irqreturn_t ret = IRQ_NONE;
1688         u32 intr_status, intr_enable;
1689
1690         spin_lock(&mdp->lock);
1691
1692         /* Get interrupt status */
1693         intr_status = sh_eth_read(ndev, EESR);
1694         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1695          * enabled since it's the one that  comes thru regardless of the mask,
1696          * and we need to fully handle it in sh_eth_error() in order to quench
1697          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1698          */
1699         intr_enable = sh_eth_read(ndev, EESIPR);
1700         intr_status &= intr_enable | DMAC_M_ECI;
1701         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1702                 ret = IRQ_HANDLED;
1703         else
1704                 goto out;
1705
1706         if (!likely(mdp->irq_enabled)) {
1707                 sh_eth_write(ndev, 0, EESIPR);
1708                 goto out;
1709         }
1710
1711         if (intr_status & EESR_RX_CHECK) {
1712                 if (napi_schedule_prep(&mdp->napi)) {
1713                         /* Mask Rx interrupts */
1714                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1715                                      EESIPR);
1716                         __napi_schedule(&mdp->napi);
1717                 } else {
1718                         netdev_warn(ndev,
1719                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1720                                     intr_status, intr_enable);
1721                 }
1722         }
1723
1724         /* Tx Check */
1725         if (intr_status & cd->tx_check) {
1726                 /* Clear Tx interrupts */
1727                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1728
1729                 sh_eth_txfree(ndev);
1730                 netif_wake_queue(ndev);
1731         }
1732
1733         if (intr_status & cd->eesr_err_check) {
1734                 /* Clear error interrupts */
1735                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1736
1737                 sh_eth_error(ndev, intr_status);
1738         }
1739
1740 out:
1741         spin_unlock(&mdp->lock);
1742
1743         return ret;
1744 }
1745
1746 static int sh_eth_poll(struct napi_struct *napi, int budget)
1747 {
1748         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1749                                                   napi);
1750         struct net_device *ndev = napi->dev;
1751         int quota = budget;
1752         u32 intr_status;
1753
1754         for (;;) {
1755                 intr_status = sh_eth_read(ndev, EESR);
1756                 if (!(intr_status & EESR_RX_CHECK))
1757                         break;
1758                 /* Clear Rx interrupts */
1759                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1760
1761                 if (sh_eth_rx(ndev, intr_status, &quota))
1762                         goto out;
1763         }
1764
1765         napi_complete(napi);
1766
1767         /* Reenable Rx interrupts */
1768         if (mdp->irq_enabled)
1769                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1770 out:
1771         return budget - quota;
1772 }
1773
1774 /* PHY state control function */
1775 static void sh_eth_adjust_link(struct net_device *ndev)
1776 {
1777         struct sh_eth_private *mdp = netdev_priv(ndev);
1778         struct phy_device *phydev = mdp->phydev;
1779         int new_state = 0;
1780
1781         if (phydev->link) {
1782                 if (phydev->duplex != mdp->duplex) {
1783                         new_state = 1;
1784                         mdp->duplex = phydev->duplex;
1785                         if (mdp->cd->set_duplex)
1786                                 mdp->cd->set_duplex(ndev);
1787                 }
1788
1789                 if (phydev->speed != mdp->speed) {
1790                         new_state = 1;
1791                         mdp->speed = phydev->speed;
1792                         if (mdp->cd->set_rate)
1793                                 mdp->cd->set_rate(ndev);
1794                 }
1795                 if (!mdp->link) {
1796                         sh_eth_write(ndev,
1797                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1798                                      ECMR);
1799                         new_state = 1;
1800                         mdp->link = phydev->link;
1801                         if (mdp->cd->no_psr || mdp->no_ether_link)
1802                                 sh_eth_rcv_snd_enable(ndev);
1803                 }
1804         } else if (mdp->link) {
1805                 new_state = 1;
1806                 mdp->link = 0;
1807                 mdp->speed = 0;
1808                 mdp->duplex = -1;
1809                 if (mdp->cd->no_psr || mdp->no_ether_link)
1810                         sh_eth_rcv_snd_disable(ndev);
1811         }
1812
1813         if (new_state && netif_msg_link(mdp))
1814                 phy_print_status(phydev);
1815 }
1816
1817 /* PHY init function */
1818 static int sh_eth_phy_init(struct net_device *ndev)
1819 {
1820         struct device_node *np = ndev->dev.parent->of_node;
1821         struct sh_eth_private *mdp = netdev_priv(ndev);
1822         struct phy_device *phydev = NULL;
1823
1824         mdp->link = 0;
1825         mdp->speed = 0;
1826         mdp->duplex = -1;
1827
1828         /* Try connect to PHY */
1829         if (np) {
1830                 struct device_node *pn;
1831
1832                 pn = of_parse_phandle(np, "phy-handle", 0);
1833                 phydev = of_phy_connect(ndev, pn,
1834                                         sh_eth_adjust_link, 0,
1835                                         mdp->phy_interface);
1836
1837                 if (!phydev)
1838                         phydev = ERR_PTR(-ENOENT);
1839         } else {
1840                 char phy_id[MII_BUS_ID_SIZE + 3];
1841
1842                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1843                          mdp->mii_bus->id, mdp->phy_id);
1844
1845                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1846                                      mdp->phy_interface);
1847         }
1848
1849         if (IS_ERR(phydev)) {
1850                 netdev_err(ndev, "failed to connect PHY\n");
1851                 return PTR_ERR(phydev);
1852         }
1853
1854         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1855                     phydev->addr, phydev->irq, phydev->drv->name);
1856
1857         mdp->phydev = phydev;
1858
1859         return 0;
1860 }
1861
1862 /* PHY control start function */
1863 static int sh_eth_phy_start(struct net_device *ndev)
1864 {
1865         struct sh_eth_private *mdp = netdev_priv(ndev);
1866         int ret;
1867
1868         ret = sh_eth_phy_init(ndev);
1869         if (ret)
1870                 return ret;
1871
1872         phy_start(mdp->phydev);
1873
1874         return 0;
1875 }
1876
1877 static int sh_eth_get_settings(struct net_device *ndev,
1878                                struct ethtool_cmd *ecmd)
1879 {
1880         struct sh_eth_private *mdp = netdev_priv(ndev);
1881         unsigned long flags;
1882         int ret;
1883
1884         if (!mdp->phydev)
1885                 return -ENODEV;
1886
1887         spin_lock_irqsave(&mdp->lock, flags);
1888         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1889         spin_unlock_irqrestore(&mdp->lock, flags);
1890
1891         return ret;
1892 }
1893
1894 static int sh_eth_set_settings(struct net_device *ndev,
1895                                struct ethtool_cmd *ecmd)
1896 {
1897         struct sh_eth_private *mdp = netdev_priv(ndev);
1898         unsigned long flags;
1899         int ret;
1900
1901         if (!mdp->phydev)
1902                 return -ENODEV;
1903
1904         spin_lock_irqsave(&mdp->lock, flags);
1905
1906         /* disable tx and rx */
1907         sh_eth_rcv_snd_disable(ndev);
1908
1909         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1910         if (ret)
1911                 goto error_exit;
1912
1913         if (ecmd->duplex == DUPLEX_FULL)
1914                 mdp->duplex = 1;
1915         else
1916                 mdp->duplex = 0;
1917
1918         if (mdp->cd->set_duplex)
1919                 mdp->cd->set_duplex(ndev);
1920
1921 error_exit:
1922         mdelay(1);
1923
1924         /* enable tx and rx */
1925         sh_eth_rcv_snd_enable(ndev);
1926
1927         spin_unlock_irqrestore(&mdp->lock, flags);
1928
1929         return ret;
1930 }
1931
1932 static int sh_eth_nway_reset(struct net_device *ndev)
1933 {
1934         struct sh_eth_private *mdp = netdev_priv(ndev);
1935         unsigned long flags;
1936         int ret;
1937
1938         if (!mdp->phydev)
1939                 return -ENODEV;
1940
1941         spin_lock_irqsave(&mdp->lock, flags);
1942         ret = phy_start_aneg(mdp->phydev);
1943         spin_unlock_irqrestore(&mdp->lock, flags);
1944
1945         return ret;
1946 }
1947
1948 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1949 {
1950         struct sh_eth_private *mdp = netdev_priv(ndev);
1951         return mdp->msg_enable;
1952 }
1953
1954 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1955 {
1956         struct sh_eth_private *mdp = netdev_priv(ndev);
1957         mdp->msg_enable = value;
1958 }
1959
1960 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1961         "rx_current", "tx_current",
1962         "rx_dirty", "tx_dirty",
1963 };
1964 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1965
1966 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1967 {
1968         switch (sset) {
1969         case ETH_SS_STATS:
1970                 return SH_ETH_STATS_LEN;
1971         default:
1972                 return -EOPNOTSUPP;
1973         }
1974 }
1975
1976 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1977                                      struct ethtool_stats *stats, u64 *data)
1978 {
1979         struct sh_eth_private *mdp = netdev_priv(ndev);
1980         int i = 0;
1981
1982         /* device-specific stats */
1983         data[i++] = mdp->cur_rx;
1984         data[i++] = mdp->cur_tx;
1985         data[i++] = mdp->dirty_rx;
1986         data[i++] = mdp->dirty_tx;
1987 }
1988
1989 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1990 {
1991         switch (stringset) {
1992         case ETH_SS_STATS:
1993                 memcpy(data, *sh_eth_gstrings_stats,
1994                        sizeof(sh_eth_gstrings_stats));
1995                 break;
1996         }
1997 }
1998
1999 static void sh_eth_get_ringparam(struct net_device *ndev,
2000                                  struct ethtool_ringparam *ring)
2001 {
2002         struct sh_eth_private *mdp = netdev_priv(ndev);
2003
2004         ring->rx_max_pending = RX_RING_MAX;
2005         ring->tx_max_pending = TX_RING_MAX;
2006         ring->rx_pending = mdp->num_rx_ring;
2007         ring->tx_pending = mdp->num_tx_ring;
2008 }
2009
2010 static int sh_eth_set_ringparam(struct net_device *ndev,
2011                                 struct ethtool_ringparam *ring)
2012 {
2013         struct sh_eth_private *mdp = netdev_priv(ndev);
2014         int ret;
2015
2016         if (ring->tx_pending > TX_RING_MAX ||
2017             ring->rx_pending > RX_RING_MAX ||
2018             ring->tx_pending < TX_RING_MIN ||
2019             ring->rx_pending < RX_RING_MIN)
2020                 return -EINVAL;
2021         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2022                 return -EINVAL;
2023
2024         if (netif_running(ndev)) {
2025                 netif_device_detach(ndev);
2026                 netif_tx_disable(ndev);
2027
2028                 /* Serialise with the interrupt handler and NAPI, then
2029                  * disable interrupts.  We have to clear the
2030                  * irq_enabled flag first to ensure that interrupts
2031                  * won't be re-enabled.
2032                  */
2033                 mdp->irq_enabled = false;
2034                 synchronize_irq(ndev->irq);
2035                 napi_synchronize(&mdp->napi);
2036                 sh_eth_write(ndev, 0x0000, EESIPR);
2037
2038                 sh_eth_dev_exit(ndev);
2039
2040                 /* Free all the skbuffs in the Rx queue. */
2041                 sh_eth_ring_free(ndev);
2042                 /* Free DMA buffer */
2043                 sh_eth_free_dma_buffer(mdp);
2044         }
2045
2046         /* Set new parameters */
2047         mdp->num_rx_ring = ring->rx_pending;
2048         mdp->num_tx_ring = ring->tx_pending;
2049
2050         if (netif_running(ndev)) {
2051                 ret = sh_eth_ring_init(ndev);
2052                 if (ret < 0) {
2053                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2054                                    __func__);
2055                         return ret;
2056                 }
2057                 ret = sh_eth_dev_init(ndev, false);
2058                 if (ret < 0) {
2059                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2060                                    __func__);
2061                         return ret;
2062                 }
2063
2064                 mdp->irq_enabled = true;
2065                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2066                 /* Setting the Rx mode will start the Rx process. */
2067                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2068                 netif_device_attach(ndev);
2069         }
2070
2071         return 0;
2072 }
2073
2074 static const struct ethtool_ops sh_eth_ethtool_ops = {
2075         .get_settings   = sh_eth_get_settings,
2076         .set_settings   = sh_eth_set_settings,
2077         .nway_reset     = sh_eth_nway_reset,
2078         .get_msglevel   = sh_eth_get_msglevel,
2079         .set_msglevel   = sh_eth_set_msglevel,
2080         .get_link       = ethtool_op_get_link,
2081         .get_strings    = sh_eth_get_strings,
2082         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2083         .get_sset_count     = sh_eth_get_sset_count,
2084         .get_ringparam  = sh_eth_get_ringparam,
2085         .set_ringparam  = sh_eth_set_ringparam,
2086 };
2087
2088 /* network device open function */
2089 static int sh_eth_open(struct net_device *ndev)
2090 {
2091         int ret = 0;
2092         struct sh_eth_private *mdp = netdev_priv(ndev);
2093
2094         pm_runtime_get_sync(&mdp->pdev->dev);
2095
2096         napi_enable(&mdp->napi);
2097
2098         ret = request_irq(ndev->irq, sh_eth_interrupt,
2099                           mdp->cd->irq_flags, ndev->name, ndev);
2100         if (ret) {
2101                 netdev_err(ndev, "Can not assign IRQ number\n");
2102                 goto out_napi_off;
2103         }
2104
2105         /* Descriptor set */
2106         ret = sh_eth_ring_init(ndev);
2107         if (ret)
2108                 goto out_free_irq;
2109
2110         /* device init */
2111         ret = sh_eth_dev_init(ndev, true);
2112         if (ret)
2113                 goto out_free_irq;
2114
2115         /* PHY control start*/
2116         ret = sh_eth_phy_start(ndev);
2117         if (ret)
2118                 goto out_free_irq;
2119
2120         mdp->is_opened = 1;
2121
2122         return ret;
2123
2124 out_free_irq:
2125         free_irq(ndev->irq, ndev);
2126 out_napi_off:
2127         napi_disable(&mdp->napi);
2128         pm_runtime_put_sync(&mdp->pdev->dev);
2129         return ret;
2130 }
2131
2132 /* Timeout function */
2133 static void sh_eth_tx_timeout(struct net_device *ndev)
2134 {
2135         struct sh_eth_private *mdp = netdev_priv(ndev);
2136         struct sh_eth_rxdesc *rxdesc;
2137         int i;
2138
2139         netif_stop_queue(ndev);
2140
2141         netif_err(mdp, timer, ndev,
2142                   "transmit timed out, status %8.8x, resetting...\n",
2143                   sh_eth_read(ndev, EESR));
2144
2145         /* tx_errors count up */
2146         ndev->stats.tx_errors++;
2147
2148         /* Free all the skbuffs in the Rx queue. */
2149         for (i = 0; i < mdp->num_rx_ring; i++) {
2150                 rxdesc = &mdp->rx_ring[i];
2151                 rxdesc->status = 0;
2152                 rxdesc->addr = 0xBADF00D0;
2153                 dev_kfree_skb(mdp->rx_skbuff[i]);
2154                 mdp->rx_skbuff[i] = NULL;
2155         }
2156         for (i = 0; i < mdp->num_tx_ring; i++) {
2157                 dev_kfree_skb(mdp->tx_skbuff[i]);
2158                 mdp->tx_skbuff[i] = NULL;
2159         }
2160
2161         /* device init */
2162         sh_eth_dev_init(ndev, true);
2163 }
2164
2165 /* Packet transmit function */
2166 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2167 {
2168         struct sh_eth_private *mdp = netdev_priv(ndev);
2169         struct sh_eth_txdesc *txdesc;
2170         u32 entry;
2171         unsigned long flags;
2172
2173         spin_lock_irqsave(&mdp->lock, flags);
2174         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2175                 if (!sh_eth_txfree(ndev)) {
2176                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2177                         netif_stop_queue(ndev);
2178                         spin_unlock_irqrestore(&mdp->lock, flags);
2179                         return NETDEV_TX_BUSY;
2180                 }
2181         }
2182         spin_unlock_irqrestore(&mdp->lock, flags);
2183
2184         if (skb_put_padto(skb, ETH_ZLEN))
2185                 return NETDEV_TX_OK;
2186
2187         entry = mdp->cur_tx % mdp->num_tx_ring;
2188         mdp->tx_skbuff[entry] = skb;
2189         txdesc = &mdp->tx_ring[entry];
2190         /* soft swap. */
2191         if (!mdp->cd->hw_swap)
2192                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2193                                  skb->len + 2);
2194         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2195                                       DMA_TO_DEVICE);
2196         if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2197                 kfree_skb(skb);
2198                 return NETDEV_TX_OK;
2199         }
2200         txdesc->buffer_length = skb->len;
2201
2202         wmb(); /* TACT bit must be set after all the above writes */
2203         if (entry >= mdp->num_tx_ring - 1)
2204                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2205         else
2206                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2207
2208         mdp->cur_tx++;
2209
2210         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2211                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2212
2213         return NETDEV_TX_OK;
2214 }
2215
2216 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2217 {
2218         struct sh_eth_private *mdp = netdev_priv(ndev);
2219
2220         if (sh_eth_is_rz_fast_ether(mdp))
2221                 return &ndev->stats;
2222
2223         if (!mdp->is_opened)
2224                 return &ndev->stats;
2225
2226         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2227         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
2228         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2229         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
2230         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2231         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
2232
2233         if (sh_eth_is_gether(mdp)) {
2234                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2235                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
2236                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2237                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
2238         } else {
2239                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2240                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
2241         }
2242
2243         return &ndev->stats;
2244 }
2245
2246 /* device close function */
2247 static int sh_eth_close(struct net_device *ndev)
2248 {
2249         struct sh_eth_private *mdp = netdev_priv(ndev);
2250
2251         netif_stop_queue(ndev);
2252
2253         /* Serialise with the interrupt handler and NAPI, then disable
2254          * interrupts.  We have to clear the irq_enabled flag first to
2255          * ensure that interrupts won't be re-enabled.
2256          */
2257         mdp->irq_enabled = false;
2258         synchronize_irq(ndev->irq);
2259         napi_disable(&mdp->napi);
2260         sh_eth_write(ndev, 0x0000, EESIPR);
2261
2262         sh_eth_dev_exit(ndev);
2263
2264         /* PHY Disconnect */
2265         if (mdp->phydev) {
2266                 phy_stop(mdp->phydev);
2267                 phy_disconnect(mdp->phydev);
2268                 mdp->phydev = NULL;
2269         }
2270
2271         free_irq(ndev->irq, ndev);
2272
2273         /* Free all the skbuffs in the Rx queue. */
2274         sh_eth_ring_free(ndev);
2275
2276         /* free DMA buffer */
2277         sh_eth_free_dma_buffer(mdp);
2278
2279         pm_runtime_put_sync(&mdp->pdev->dev);
2280
2281         mdp->is_opened = 0;
2282
2283         return 0;
2284 }
2285
2286 /* ioctl to device function */
2287 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2288 {
2289         struct sh_eth_private *mdp = netdev_priv(ndev);
2290         struct phy_device *phydev = mdp->phydev;
2291
2292         if (!netif_running(ndev))
2293                 return -EINVAL;
2294
2295         if (!phydev)
2296                 return -ENODEV;
2297
2298         return phy_mii_ioctl(phydev, rq, cmd);
2299 }
2300
2301 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2302 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2303                                             int entry)
2304 {
2305         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2306 }
2307
2308 static u32 sh_eth_tsu_get_post_mask(int entry)
2309 {
2310         return 0x0f << (28 - ((entry % 8) * 4));
2311 }
2312
2313 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2314 {
2315         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2316 }
2317
2318 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2319                                              int entry)
2320 {
2321         struct sh_eth_private *mdp = netdev_priv(ndev);
2322         u32 tmp;
2323         void *reg_offset;
2324
2325         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2326         tmp = ioread32(reg_offset);
2327         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2328 }
2329
2330 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2331                                               int entry)
2332 {
2333         struct sh_eth_private *mdp = netdev_priv(ndev);
2334         u32 post_mask, ref_mask, tmp;
2335         void *reg_offset;
2336
2337         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2338         post_mask = sh_eth_tsu_get_post_mask(entry);
2339         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2340
2341         tmp = ioread32(reg_offset);
2342         iowrite32(tmp & ~post_mask, reg_offset);
2343
2344         /* If other port enables, the function returns "true" */
2345         return tmp & ref_mask;
2346 }
2347
2348 static int sh_eth_tsu_busy(struct net_device *ndev)
2349 {
2350         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2351         struct sh_eth_private *mdp = netdev_priv(ndev);
2352
2353         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2354                 udelay(10);
2355                 timeout--;
2356                 if (timeout <= 0) {
2357                         netdev_err(ndev, "%s: timeout\n", __func__);
2358                         return -ETIMEDOUT;
2359                 }
2360         }
2361
2362         return 0;
2363 }
2364
2365 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2366                                   const u8 *addr)
2367 {
2368         u32 val;
2369
2370         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2371         iowrite32(val, reg);
2372         if (sh_eth_tsu_busy(ndev) < 0)
2373                 return -EBUSY;
2374
2375         val = addr[4] << 8 | addr[5];
2376         iowrite32(val, reg + 4);
2377         if (sh_eth_tsu_busy(ndev) < 0)
2378                 return -EBUSY;
2379
2380         return 0;
2381 }
2382
2383 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2384 {
2385         u32 val;
2386
2387         val = ioread32(reg);
2388         addr[0] = (val >> 24) & 0xff;
2389         addr[1] = (val >> 16) & 0xff;
2390         addr[2] = (val >> 8) & 0xff;
2391         addr[3] = val & 0xff;
2392         val = ioread32(reg + 4);
2393         addr[4] = (val >> 8) & 0xff;
2394         addr[5] = val & 0xff;
2395 }
2396
2397
2398 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2399 {
2400         struct sh_eth_private *mdp = netdev_priv(ndev);
2401         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2402         int i;
2403         u8 c_addr[ETH_ALEN];
2404
2405         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2406                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2407                 if (ether_addr_equal(addr, c_addr))
2408                         return i;
2409         }
2410
2411         return -ENOENT;
2412 }
2413
2414 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2415 {
2416         u8 blank[ETH_ALEN];
2417         int entry;
2418
2419         memset(blank, 0, sizeof(blank));
2420         entry = sh_eth_tsu_find_entry(ndev, blank);
2421         return (entry < 0) ? -ENOMEM : entry;
2422 }
2423
2424 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2425                                               int entry)
2426 {
2427         struct sh_eth_private *mdp = netdev_priv(ndev);
2428         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2429         int ret;
2430         u8 blank[ETH_ALEN];
2431
2432         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2433                          ~(1 << (31 - entry)), TSU_TEN);
2434
2435         memset(blank, 0, sizeof(blank));
2436         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2437         if (ret < 0)
2438                 return ret;
2439         return 0;
2440 }
2441
2442 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2443 {
2444         struct sh_eth_private *mdp = netdev_priv(ndev);
2445         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2446         int i, ret;
2447
2448         if (!mdp->cd->tsu)
2449                 return 0;
2450
2451         i = sh_eth_tsu_find_entry(ndev, addr);
2452         if (i < 0) {
2453                 /* No entry found, create one */
2454                 i = sh_eth_tsu_find_empty(ndev);
2455                 if (i < 0)
2456                         return -ENOMEM;
2457                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2458                 if (ret < 0)
2459                         return ret;
2460
2461                 /* Enable the entry */
2462                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2463                                  (1 << (31 - i)), TSU_TEN);
2464         }
2465
2466         /* Entry found or created, enable POST */
2467         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2468
2469         return 0;
2470 }
2471
2472 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2473 {
2474         struct sh_eth_private *mdp = netdev_priv(ndev);
2475         int i, ret;
2476
2477         if (!mdp->cd->tsu)
2478                 return 0;
2479
2480         i = sh_eth_tsu_find_entry(ndev, addr);
2481         if (i) {
2482                 /* Entry found */
2483                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2484                         goto done;
2485
2486                 /* Disable the entry if both ports was disabled */
2487                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2488                 if (ret < 0)
2489                         return ret;
2490         }
2491 done:
2492         return 0;
2493 }
2494
2495 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2496 {
2497         struct sh_eth_private *mdp = netdev_priv(ndev);
2498         int i, ret;
2499
2500         if (!mdp->cd->tsu)
2501                 return 0;
2502
2503         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2504                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2505                         continue;
2506
2507                 /* Disable the entry if both ports was disabled */
2508                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2509                 if (ret < 0)
2510                         return ret;
2511         }
2512
2513         return 0;
2514 }
2515
2516 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2517 {
2518         struct sh_eth_private *mdp = netdev_priv(ndev);
2519         u8 addr[ETH_ALEN];
2520         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2521         int i;
2522
2523         if (!mdp->cd->tsu)
2524                 return;
2525
2526         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2527                 sh_eth_tsu_read_entry(reg_offset, addr);
2528                 if (is_multicast_ether_addr(addr))
2529                         sh_eth_tsu_del_entry(ndev, addr);
2530         }
2531 }
2532
2533 /* Update promiscuous flag and multicast filter */
2534 static void sh_eth_set_rx_mode(struct net_device *ndev)
2535 {
2536         struct sh_eth_private *mdp = netdev_priv(ndev);
2537         u32 ecmr_bits;
2538         int mcast_all = 0;
2539         unsigned long flags;
2540
2541         spin_lock_irqsave(&mdp->lock, flags);
2542         /* Initial condition is MCT = 1, PRM = 0.
2543          * Depending on ndev->flags, set PRM or clear MCT
2544          */
2545         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2546         if (mdp->cd->tsu)
2547                 ecmr_bits |= ECMR_MCT;
2548
2549         if (!(ndev->flags & IFF_MULTICAST)) {
2550                 sh_eth_tsu_purge_mcast(ndev);
2551                 mcast_all = 1;
2552         }
2553         if (ndev->flags & IFF_ALLMULTI) {
2554                 sh_eth_tsu_purge_mcast(ndev);
2555                 ecmr_bits &= ~ECMR_MCT;
2556                 mcast_all = 1;
2557         }
2558
2559         if (ndev->flags & IFF_PROMISC) {
2560                 sh_eth_tsu_purge_all(ndev);
2561                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2562         } else if (mdp->cd->tsu) {
2563                 struct netdev_hw_addr *ha;
2564                 netdev_for_each_mc_addr(ha, ndev) {
2565                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2566                                 continue;
2567
2568                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2569                                 if (!mcast_all) {
2570                                         sh_eth_tsu_purge_mcast(ndev);
2571                                         ecmr_bits &= ~ECMR_MCT;
2572                                         mcast_all = 1;
2573                                 }
2574                         }
2575                 }
2576         }
2577
2578         /* update the ethernet mode */
2579         sh_eth_write(ndev, ecmr_bits, ECMR);
2580
2581         spin_unlock_irqrestore(&mdp->lock, flags);
2582 }
2583
2584 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2585 {
2586         if (!mdp->port)
2587                 return TSU_VTAG0;
2588         else
2589                 return TSU_VTAG1;
2590 }
2591
2592 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2593                                   __be16 proto, u16 vid)
2594 {
2595         struct sh_eth_private *mdp = netdev_priv(ndev);
2596         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2597
2598         if (unlikely(!mdp->cd->tsu))
2599                 return -EPERM;
2600
2601         /* No filtering if vid = 0 */
2602         if (!vid)
2603                 return 0;
2604
2605         mdp->vlan_num_ids++;
2606
2607         /* The controller has one VLAN tag HW filter. So, if the filter is
2608          * already enabled, the driver disables it and the filte
2609          */
2610         if (mdp->vlan_num_ids > 1) {
2611                 /* disable VLAN filter */
2612                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2613                 return 0;
2614         }
2615
2616         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2617                          vtag_reg_index);
2618
2619         return 0;
2620 }
2621
2622 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2623                                    __be16 proto, u16 vid)
2624 {
2625         struct sh_eth_private *mdp = netdev_priv(ndev);
2626         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2627
2628         if (unlikely(!mdp->cd->tsu))
2629                 return -EPERM;
2630
2631         /* No filtering if vid = 0 */
2632         if (!vid)
2633                 return 0;
2634
2635         mdp->vlan_num_ids--;
2636         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2637
2638         return 0;
2639 }
2640
2641 /* SuperH's TSU register init function */
2642 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2643 {
2644         if (sh_eth_is_rz_fast_ether(mdp)) {
2645                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2646                 return;
2647         }
2648
2649         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2650         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2651         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2652         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2653         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2654         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2655         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2656         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2657         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2658         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2659         if (sh_eth_is_gether(mdp)) {
2660                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2661                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2662         } else {
2663                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2664                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2665         }
2666         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2667         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2668         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2669         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2670         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2671         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2672         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2673 }
2674
2675 /* MDIO bus release function */
2676 static int sh_mdio_release(struct sh_eth_private *mdp)
2677 {
2678         /* unregister mdio bus */
2679         mdiobus_unregister(mdp->mii_bus);
2680
2681         /* free bitbang info */
2682         free_mdio_bitbang(mdp->mii_bus);
2683
2684         return 0;
2685 }
2686
2687 /* MDIO bus init function */
2688 static int sh_mdio_init(struct sh_eth_private *mdp,
2689                         struct sh_eth_plat_data *pd)
2690 {
2691         int ret, i;
2692         struct bb_info *bitbang;
2693         struct platform_device *pdev = mdp->pdev;
2694         struct device *dev = &mdp->pdev->dev;
2695
2696         /* create bit control struct for PHY */
2697         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2698         if (!bitbang)
2699                 return -ENOMEM;
2700
2701         /* bitbang init */
2702         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2703         bitbang->set_gate = pd->set_mdio_gate;
2704         bitbang->mdi_msk = PIR_MDI;
2705         bitbang->mdo_msk = PIR_MDO;
2706         bitbang->mmd_msk = PIR_MMD;
2707         bitbang->mdc_msk = PIR_MDC;
2708         bitbang->ctrl.ops = &bb_ops;
2709
2710         /* MII controller setting */
2711         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2712         if (!mdp->mii_bus)
2713                 return -ENOMEM;
2714
2715         /* Hook up MII support for ethtool */
2716         mdp->mii_bus->name = "sh_mii";
2717         mdp->mii_bus->parent = dev;
2718         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2719                  pdev->name, pdev->id);
2720
2721         /* PHY IRQ */
2722         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2723                                                GFP_KERNEL);
2724         if (!mdp->mii_bus->irq) {
2725                 ret = -ENOMEM;
2726                 goto out_free_bus;
2727         }
2728
2729         /* register MDIO bus */
2730         if (dev->of_node) {
2731                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2732         } else {
2733                 for (i = 0; i < PHY_MAX_ADDR; i++)
2734                         mdp->mii_bus->irq[i] = PHY_POLL;
2735                 if (pd->phy_irq > 0)
2736                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2737
2738                 ret = mdiobus_register(mdp->mii_bus);
2739         }
2740
2741         if (ret)
2742                 goto out_free_bus;
2743
2744         return 0;
2745
2746 out_free_bus:
2747         free_mdio_bitbang(mdp->mii_bus);
2748         return ret;
2749 }
2750
2751 static const u16 *sh_eth_get_register_offset(int register_type)
2752 {
2753         const u16 *reg_offset = NULL;
2754
2755         switch (register_type) {
2756         case SH_ETH_REG_GIGABIT:
2757                 reg_offset = sh_eth_offset_gigabit;
2758                 break;
2759         case SH_ETH_REG_FAST_RZ:
2760                 reg_offset = sh_eth_offset_fast_rz;
2761                 break;
2762         case SH_ETH_REG_FAST_RCAR:
2763                 reg_offset = sh_eth_offset_fast_rcar;
2764                 break;
2765         case SH_ETH_REG_FAST_SH4:
2766                 reg_offset = sh_eth_offset_fast_sh4;
2767                 break;
2768         case SH_ETH_REG_FAST_SH3_SH2:
2769                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2770                 break;
2771         default:
2772                 break;
2773         }
2774
2775         return reg_offset;
2776 }
2777
2778 static const struct net_device_ops sh_eth_netdev_ops = {
2779         .ndo_open               = sh_eth_open,
2780         .ndo_stop               = sh_eth_close,
2781         .ndo_start_xmit         = sh_eth_start_xmit,
2782         .ndo_get_stats          = sh_eth_get_stats,
2783         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2784         .ndo_tx_timeout         = sh_eth_tx_timeout,
2785         .ndo_do_ioctl           = sh_eth_do_ioctl,
2786         .ndo_validate_addr      = eth_validate_addr,
2787         .ndo_set_mac_address    = eth_mac_addr,
2788         .ndo_change_mtu         = eth_change_mtu,
2789 };
2790
2791 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2792         .ndo_open               = sh_eth_open,
2793         .ndo_stop               = sh_eth_close,
2794         .ndo_start_xmit         = sh_eth_start_xmit,
2795         .ndo_get_stats          = sh_eth_get_stats,
2796         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2797         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2798         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2799         .ndo_tx_timeout         = sh_eth_tx_timeout,
2800         .ndo_do_ioctl           = sh_eth_do_ioctl,
2801         .ndo_validate_addr      = eth_validate_addr,
2802         .ndo_set_mac_address    = eth_mac_addr,
2803         .ndo_change_mtu         = eth_change_mtu,
2804 };
2805
2806 #ifdef CONFIG_OF
2807 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2808 {
2809         struct device_node *np = dev->of_node;
2810         struct sh_eth_plat_data *pdata;
2811         const char *mac_addr;
2812
2813         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2814         if (!pdata)
2815                 return NULL;
2816
2817         pdata->phy_interface = of_get_phy_mode(np);
2818
2819         mac_addr = of_get_mac_address(np);
2820         if (mac_addr)
2821                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2822
2823         pdata->no_ether_link =
2824                 of_property_read_bool(np, "renesas,no-ether-link");
2825         pdata->ether_link_active_low =
2826                 of_property_read_bool(np, "renesas,ether-link-active-low");
2827
2828         return pdata;
2829 }
2830
2831 static const struct of_device_id sh_eth_match_table[] = {
2832         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2833         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2834         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2835         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2836         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2837         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2838         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2839         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2840         { }
2841 };
2842 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2843 #else
2844 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2845 {
2846         return NULL;
2847 }
2848 #endif
2849
2850 static int sh_eth_drv_probe(struct platform_device *pdev)
2851 {
2852         int ret, devno = 0;
2853         struct resource *res;
2854         struct net_device *ndev = NULL;
2855         struct sh_eth_private *mdp = NULL;
2856         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2857         const struct platform_device_id *id = platform_get_device_id(pdev);
2858
2859         /* get base addr */
2860         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2861
2862         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2863         if (!ndev)
2864                 return -ENOMEM;
2865
2866         pm_runtime_enable(&pdev->dev);
2867         pm_runtime_get_sync(&pdev->dev);
2868
2869         devno = pdev->id;
2870         if (devno < 0)
2871                 devno = 0;
2872
2873         ndev->dma = -1;
2874         ret = platform_get_irq(pdev, 0);
2875         if (ret < 0) {
2876                 ret = -ENODEV;
2877                 goto out_release;
2878         }
2879         ndev->irq = ret;
2880
2881         SET_NETDEV_DEV(ndev, &pdev->dev);
2882
2883         mdp = netdev_priv(ndev);
2884         mdp->num_tx_ring = TX_RING_SIZE;
2885         mdp->num_rx_ring = RX_RING_SIZE;
2886         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2887         if (IS_ERR(mdp->addr)) {
2888                 ret = PTR_ERR(mdp->addr);
2889                 goto out_release;
2890         }
2891
2892         ndev->base_addr = res->start;
2893
2894         spin_lock_init(&mdp->lock);
2895         mdp->pdev = pdev;
2896
2897         if (pdev->dev.of_node)
2898                 pd = sh_eth_parse_dt(&pdev->dev);
2899         if (!pd) {
2900                 dev_err(&pdev->dev, "no platform data\n");
2901                 ret = -EINVAL;
2902                 goto out_release;
2903         }
2904
2905         /* get PHY ID */
2906         mdp->phy_id = pd->phy;
2907         mdp->phy_interface = pd->phy_interface;
2908         /* EDMAC endian */
2909         mdp->edmac_endian = pd->edmac_endian;
2910         mdp->no_ether_link = pd->no_ether_link;
2911         mdp->ether_link_active_low = pd->ether_link_active_low;
2912
2913         /* set cpu data */
2914         if (id) {
2915                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2916         } else  {
2917                 const struct of_device_id *match;
2918
2919                 match = of_match_device(of_match_ptr(sh_eth_match_table),
2920                                         &pdev->dev);
2921                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2922         }
2923         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2924         if (!mdp->reg_offset) {
2925                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2926                         mdp->cd->register_type);
2927                 ret = -EINVAL;
2928                 goto out_release;
2929         }
2930         sh_eth_set_default_cpu_data(mdp->cd);
2931
2932         /* set function */
2933         if (mdp->cd->tsu)
2934                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2935         else
2936                 ndev->netdev_ops = &sh_eth_netdev_ops;
2937         ndev->ethtool_ops = &sh_eth_ethtool_ops;
2938         ndev->watchdog_timeo = TX_TIMEOUT;
2939
2940         /* debug message level */
2941         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2942
2943         /* read and set MAC address */
2944         read_mac_address(ndev, pd->mac_addr);
2945         if (!is_valid_ether_addr(ndev->dev_addr)) {
2946                 dev_warn(&pdev->dev,
2947                          "no valid MAC address supplied, using a random one.\n");
2948                 eth_hw_addr_random(ndev);
2949         }
2950
2951         /* ioremap the TSU registers */
2952         if (mdp->cd->tsu) {
2953                 struct resource *rtsu;
2954                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2955                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2956                 if (IS_ERR(mdp->tsu_addr)) {
2957                         ret = PTR_ERR(mdp->tsu_addr);
2958                         goto out_release;
2959                 }
2960                 mdp->port = devno % 2;
2961                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2962         }
2963
2964         /* initialize first or needed device */
2965         if (!devno || pd->needs_init) {
2966                 if (mdp->cd->chip_reset)
2967                         mdp->cd->chip_reset(ndev);
2968
2969                 if (mdp->cd->tsu) {
2970                         /* TSU init (Init only)*/
2971                         sh_eth_tsu_init(mdp);
2972                 }
2973         }
2974
2975         if (mdp->cd->rmiimode)
2976                 sh_eth_write(ndev, 0x1, RMIIMODE);
2977
2978         /* MDIO bus init */
2979         ret = sh_mdio_init(mdp, pd);
2980         if (ret) {
2981                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2982                 goto out_release;
2983         }
2984
2985         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2986
2987         /* network device register */
2988         ret = register_netdev(ndev);
2989         if (ret)
2990                 goto out_napi_del;
2991
2992         /* print device information */
2993         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2994                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2995
2996         pm_runtime_put(&pdev->dev);
2997         platform_set_drvdata(pdev, ndev);
2998
2999         return ret;
3000
3001 out_napi_del:
3002         netif_napi_del(&mdp->napi);
3003         sh_mdio_release(mdp);
3004
3005 out_release:
3006         /* net_dev free */
3007         if (ndev)
3008                 free_netdev(ndev);
3009
3010         pm_runtime_put(&pdev->dev);
3011         pm_runtime_disable(&pdev->dev);
3012         return ret;
3013 }
3014
3015 static int sh_eth_drv_remove(struct platform_device *pdev)
3016 {
3017         struct net_device *ndev = platform_get_drvdata(pdev);
3018         struct sh_eth_private *mdp = netdev_priv(ndev);
3019
3020         unregister_netdev(ndev);
3021         netif_napi_del(&mdp->napi);
3022         sh_mdio_release(mdp);
3023         pm_runtime_disable(&pdev->dev);
3024         free_netdev(ndev);
3025
3026         return 0;
3027 }
3028
3029 #ifdef CONFIG_PM
3030 #ifdef CONFIG_PM_SLEEP
3031 static int sh_eth_suspend(struct device *dev)
3032 {
3033         struct net_device *ndev = dev_get_drvdata(dev);
3034         int ret = 0;
3035
3036         if (netif_running(ndev)) {
3037                 netif_device_detach(ndev);
3038                 ret = sh_eth_close(ndev);
3039         }
3040
3041         return ret;
3042 }
3043
3044 static int sh_eth_resume(struct device *dev)
3045 {
3046         struct net_device *ndev = dev_get_drvdata(dev);
3047         int ret = 0;
3048
3049         if (netif_running(ndev)) {
3050                 ret = sh_eth_open(ndev);
3051                 if (ret < 0)
3052                         return ret;
3053                 netif_device_attach(ndev);
3054         }
3055
3056         return ret;
3057 }
3058 #endif
3059
3060 static int sh_eth_runtime_nop(struct device *dev)
3061 {
3062         /* Runtime PM callback shared between ->runtime_suspend()
3063          * and ->runtime_resume(). Simply returns success.
3064          *
3065          * This driver re-initializes all registers after
3066          * pm_runtime_get_sync() anyway so there is no need
3067          * to save and restore registers here.
3068          */
3069         return 0;
3070 }
3071
3072 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3073         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3074         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3075 };
3076 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3077 #else
3078 #define SH_ETH_PM_OPS NULL
3079 #endif
3080
3081 static struct platform_device_id sh_eth_id_table[] = {
3082         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3083         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3084         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3085         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3086         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3087         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3088         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3089         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3090         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3091         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3092         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3093         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3094         { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3095         { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3096         { }
3097 };
3098 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3099
3100 static struct platform_driver sh_eth_driver = {
3101         .probe = sh_eth_drv_probe,
3102         .remove = sh_eth_drv_remove,
3103         .id_table = sh_eth_id_table,
3104         .driver = {
3105                    .name = CARDNAME,
3106                    .pm = SH_ETH_PM_OPS,
3107                    .of_match_table = of_match_ptr(sh_eth_match_table),
3108         },
3109 };
3110
3111 module_platform_driver(sh_eth_driver);
3112
3113 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3114 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3115 MODULE_LICENSE("GPL v2");